Memory device and read-write test method thereof

Abstract

A read-write test method is performed by a test apparatus on a memory device. The read-write test method includes: entering the memory device into a test mode; writing test data bytes into a memory module of the memory device via a parallel transmission path by a mode register of the memory device in one time; reading out stored data bytes corresponding to the test data bytes from the memory module via the parallel transmission path in one time; and comparing the stored data bytes with the test data bytes to generate a comparison result. The memory device can detect whether the memory module has normal read-write function through the comparison result by a parallel read-write operation and an internal comparison mechanism without relying on a sequence data transmission path conforming to a JEDEC specification, thereby improving test efficiency.

Description

Technical Field

[0001] This disclosure relates to a memory device and a method for testing its read and write operations, and more particularly to a dynamic random access memory and a method for testing its read and write operations in a test mode. Background Technology

[0002] Existing memory devices typically perform read and write operations through a sequential data transmission output path and a burst data transmission mechanism conforming to JEDEC specifications. This data transmission mechanism is designed to support the memory device in normal high-speed operating environments and requires multiple clock cycles with corresponding write and read latency and burst lengths to ensure data transmission accuracy.

[0003] However, in memory testing, pre-packaging testing, or other low-speed testing environments, the test equipment used to test memory devices usually does not have high-speed data transmission capabilities. This means that memory devices still need to follow the data transmission mechanism specified by JEDEC when operating at low speeds, which results in a significant increase in test time.

[0004] How to effectively shorten the time required for memory read / write testing in low-speed testing environments to improve testing efficiency is an important issue that needs to be addressed by those skilled in the art. Summary of the Invention

[0005] This disclosure provides a read / write test method. The read / write test method is performed by a test device on a memory device. The memory device includes a memory module and a mode buffer. The read / write test method includes: entering a test mode for the memory device via a write instruction to the mode buffer; in the test mode, writing test data bytes to the memory module in one go via a parallel transmission path using the mode buffer; reading the corresponding stored data bytes from the memory module in one go via a read instruction to the mode buffer via the parallel transmission path; and comparing the stored data bytes and the test data bytes to generate a comparison result. The comparison result represents whether the memory area of ​​the memory module has normal read / write functionality.

[0006] In some embodiments, the read / write test method further includes: setting a plurality of test operation buffers within the pattern buffer; storing a plurality of preset data corresponding to the plurality of test operation buffers; generating a command / address combination after receiving a write instruction from the pattern buffer; and setting one of the plurality of preset data as the test data byte according to the command of the command / address combination through the pattern buffer.

[0007] In some embodiments, the address of the command / address combination corresponds to a memory region of the memory library in the memory module.

[0008] In some embodiments, the memory device further includes a JEDEC-compliant sequential data transmission path for transmitting data and a data strobe signal, and in the test mode, the data and the data strobe signal are not written to the memory module via the sequential data transmission path.

[0009] In some embodiments, in the normal mode after the test mode ends, the data and the data strobe signal are written into the memory module via the sequence data transmission path.

[0010] In some embodiments, the test device further includes a comparator, and the read / write test method further includes: generating the comparison result through the comparator and outputting the comparison result to the test device.

[0011] In some embodiments, the test mode refers to the memory device operating in an environment with a data transfer rate of less than or equal to 533 Mbps.

[0012] In some embodiments, the read / write test method further includes: in the test mode, using parallel data access operations triggered by the mode buffer to directly write and read data from the memory module, instead of using a sequential data transmission mechanism conforming to the JEDEC specification, in order to avoid the write latency, read latency, and multiple clock cycles corresponding to the burst length required by the sequential data transmission mechanism, thereby reducing the test time.

[0013] This disclosure provides a memory device. The memory device is coupled to a test apparatus and includes a memory module, a controller, a mode buffer, and a comparator. Control circuitry is coupled to the memory module. The control circuitry receives a mode buffer write command from the test apparatus to put the memory device into a test mode; and receives a mode buffer read command from the test apparatus. The mode buffer is coupled to the memory module and the control circuitry. In response to the control circuitry receiving a mode buffer write command, the mode buffer writes a test data byte to the memory module in a single operation via a parallel transmission path. The comparator is coupled to the mode buffer and receives, in response to the control circuitry receiving a mode buffer read command, a stored data byte corresponding to the test data byte in a single operation from the memory module via a parallel transmission path; and compares the stored data byte with the test data byte to generate a comparison result. The comparison result represents whether a memory region of the memory module has normal read / write functionality.

[0014] In some embodiments, the pattern buffer is provided with a plurality of test operation buffers, which are used to store a plurality of preset data; the control circuit is further used to generate a command / address combination after receiving a write instruction from the pattern buffer; and the pattern buffer is further used to receive a command from the command / address combination to set one of the plurality of preset data as the test data byte.

[0015] In some embodiments, the address of the command / address combination corresponds to a memory region of the memory library in the memory module.

[0016] In some embodiments, the memory device further includes a JEDEC-compliant sequential data transmission path for transmitting data and a data strobe signal, and in the test mode, the data and the data strobe signal are not written to the memory module via the sequential data transmission path.

[0017] In some embodiments, in the normal mode after the test mode ends, the data and the data strobe signal are written into the memory module via the sequence data transmission path.

[0018] In some embodiments, the test mode refers to the memory device operating in an environment with a data transfer rate of less than or equal to 533 Mbps.

[0019] In some embodiments, the comparator is further used to output the comparison result to the test device.

[0020] In summary, the memory device and its read / write test method provided in this disclosure can perform read / write tests on memory modules through parallel read / write operations and internal comparison mechanisms, without relying on a sequential data transmission path conforming to JEDEC specifications. Therefore, the memory device in this disclosure can significantly reduce test time during read / write testing, thereby improving test efficiency. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the architecture of a test system according to an embodiment of this disclosure.

[0022] Figure 2 This is a schematic diagram of the architecture of a test system according to an embodiment of this disclosure.

[0023] Figure 3 This is a flowchart of a read / write test method according to an embodiment of this disclosure. Detailed Implementation

[0024] The embodiments of this disclosure will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same or similar elements or method flows.

[0025] This disclosure discloses a test system for testing whether a memory device has normal read and write capabilities. The test system includes at least a test device for sending test commands and a memory device under test. The memory device under test may be Dynamic Random Access Memory (DRAM).

[0026] When testing the read / write capabilities of the memory device, the test equipment typically only has low data write and read speeds, placing the entire test system in a low-speed test environment with a transmission rate of 533 Mbps or less. In this low-speed environment, if the memory device still follows the sequential and burst data transmission mechanisms of the JEDEC specification designed for high-speed normal operation for data writing and reading, the slower write and read speeds of the test equipment will lead to a relative increase in the write latency, read latency, and the number of clock cycles corresponding to the burst length required by the sequential data transmission mechanism, thus prolonging the overall test time.

[0027] To address this, the test system disclosed in this document proposes a parallel data access architecture suitable for the aforementioned low-speed test mode. This architecture allows test data writing and reading to be directly triggered and completed by the mode buffer built into the memory device, without performing sequential data transmission operations conforming to JEDEC specifications. This avoids the write latency, read latency, and multiple clock cycles corresponding to the burst length originally required by the aforementioned transmission mechanism, effectively shortening the overall test time.

[0028] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the system architecture of a test system SYS100 according to an embodiment of this disclosure. The test system SYS100 includes a test device TD100 and a memory device M100.

[0029] The test equipment TD100 is coupled to the memory device M100. The test equipment TD100 can perform read and write tests on the memory device M100 during the memory testing phase, the pre-packaging testing phase, or other low-speed testing environments to confirm whether the memory cells in the memory device M100 have normal read and write capabilities.

[0030] like Figure 1 As shown, the memory device M100 can be a dynamic random access memory or other memory device with a configurable mode cache. For example... Figure 1As shown, the memory device M100 may include a memory module M110, a control circuit M120, a mode buffer M130, a comparator M140, an input / output gate circuit M150, a sequence receiving circuit M160, and a sequence-to-parallel conversion circuit M170.

[0031] The memory module M110 can be composed of multiple memory cells and can be divided into multiple memory banks or multiple memory regions according to the actual design.

[0032] The control circuit M120 can receive control signals from the test equipment TD100 or any external control terminal, and control each circuit module of the memory device M100. Figure 1 In this embodiment, the control circuit M120 can receive the mode buffer write instruction MRW and the mode buffer read instruction MRR, and then generate a command / address combination. The command information CMD of the command / address combination is used to control the mode buffer M130, and the address control information ADDR of the command / address combination is used to control the memory module M110.

[0033] It is worth noting that the command information CMD and address control information ADDR in this disclosure document refer to control information used to indicate test operations, test data selection, or test procedures, and do not belong to memory operation commands that conform to the JEDEC specification.

[0034] The pattern buffer M130 is coupled to the memory module M110 and the control circuit M120. The pattern buffer M130 is a buffer module located within the memory device M100, used to store data related to test patterns. The pattern buffer M130 is responsive to a pattern buffer write instruction (MRW) and a pattern buffer read instruction (MRR). In one embodiment, multiple test operation buffers may be internally configured within the pattern buffer M130, and each test operation buffer can be used to pre-store multiple sets of preset test data.

[0035] Comparator M140 is used to receive and compare two sets of data contents and obtain a comparison result CMP_RS to determine whether the memory area of ​​the corresponding memory module M110 has normal read and write functions. Furthermore, comparator M140 can report the comparison result CMP_RS to the test equipment TD100.

[0036] exist Figure 1 In one embodiment, one of the data received by comparator M140 is the test data byte T_DA passed from pattern buffer M130 to memory module M110, while the second data received by comparator M140 is the stored data byte S_DA stored in memory module M110.

[0037] The input / output gate circuit M150 is electrically connected to the data read / write terminals of the memory module M110. The input / output gate circuit M150 is connected to the mode buffer M130, comparator M140, and sequence-to-parallel converter circuit M170 via a multi-bit internal data path. In different operating modes of the memory device M100, the input / output gate circuit M150 can selectively transmit multiple bits of data in parallel via the multi-bit internal data path.

[0038] It is worth mentioning that the multi-bit data transmission path can have a fixed data width, and can transmit 8 bits, 16 bits, 32 bits, or any number of data bits at a time. This disclosure does not limit this. In some embodiments, the effective data width of the multi-bit data transmission path in this disclosure can be configurable or maskable. For example, it can enable only a portion of the data bits to accommodate different memory module architectures, test resolutions, or test time requirements.

[0039] The sequence receiving circuit M160 and the sequence-to-parallel conversion circuit M170 are used to support sequence data transmission paths conforming to JEDEC specifications. The sequence receiving circuit M160 transmits data DQ and data strobe signal DQS in sequence form. The sequence-to-parallel conversion circuit M170 is used to convert the data between sequence and parallel formats.

[0040] In the test mode of memory device M100, input / output gate circuit M150 prevents data DQ and data strobe signal DQS from being written into memory module M110 via the sequence data transmission path formed by sequence receiving circuit M160 and sequence-to-parallel conversion circuit M170.

[0041] In the normal operation mode of the end test mode of the memory device M100, the input / output gate circuit M150 will cause the data DQ and the data strobe signal DQS to be written to the memory module M110 via the sequence data transmission path, without receiving the data transmitted by the mode buffer M130, and without transmitting the data to the comparator M140.

[0042] Please refer to the following at the same time Figure 1 , Figure 2 , Figure 2 This is a schematic diagram of the architecture of a test system SYS200 according to an embodiment of this disclosure. (Comparison) Figure 1 , Figure 2 It can be seen that, Figure 2 The SYS200 testing system is compatible with Figure 1The test system SYS100. Test equipment TD100 can correspond to test equipment TD200. The memory module M110, control circuit M120, mode buffer M130, comparator M140, input / output gate circuit M150, sequence receiving circuit M160 and sequence-to-parallel conversion circuit M170 in memory device M100 can correspond to the memory module M210, control circuit M220, mode buffer M230, comparator M240, input / output gate circuit M250, sequence receiving circuit M260 and sequence-to-parallel conversion circuit M270 in memory device M200.

[0043] Figure 2 Relative examples Figure 1 The difference in the embodiments is that, Figure 2 The internal configuration of the memory device M200 was further revealed.

[0044] The memory module M210 includes a memory bank M211, a sensing amplifier M212, and an address decoding circuit M213.

[0045] The test equipment TD200 can communicate with the memory device M200 via the control circuit M220 to execute specific memory libraries for the memory module M110 (e.g., Figure 2 Read and write tests of memory library M211 or specific memory regions.

[0046] The address decoding circuit M213 is used to select a memory region in the memory bank M211 based on the address control information ADDR generated by the control circuit M220. The sensing amplifier M212 is used to perform data read and write operations on the selected memory region.

[0047] At Figure 2 In some embodiments, the pattern buffer M230 may contain a plurality of test operation buffers (e.g., test operation buffers TOPO231, TOPO232 and TOPO233).

[0048] Each test operation buffer stores different preset data. When the control circuit M220 receives the mode buffer write instruction MRW sent by the test device TD200, the control circuit M220 generates a command / address combination. The command information CMD in the command / address combination is used to specify the test operation buffer to be selected, so as to set one of the multiple preset data as the test data byte T_DA. Combined with the address control information ADDR in the command / address combination, the test data byte (preset data) can be written into the specified memory area of ​​the memory bank M211.

[0049] It should be noted that, in Figure 2 In this embodiment, the test data byte T_DA is provided by the test operation buffers TOPO231, TOPO232, and TOPO233 within the pattern buffer M230. However, this disclosure is not limited thereto. In some embodiments, the test data byte T_DA may also be first loaded by the test device TD100 into the temporary storage circuit, buffer circuit, or other internal storage unit within the memory device M100, and then the pattern buffer M230 triggers the corresponding parallel write and read operations. In short, the test data byte T_DA may be built-in or loaded externally.

[0050] In the test mode of the memory device M200, the pattern buffer M230 can transmit the preset data set as the test data byte T_DA via the parallel transmission path ( Figure 2 Multiple transmission lines of the location are written at once to the memory area specified by the address control information ADDR.

[0051] Since the above write operation is performed via a parallel transmission path, the memory device M200 does not use the JEDEC-compliant sequential data transmission path for data writing, nor does it need to execute the JEDEC-compliant sequential data transmission mechanism. Therefore, it avoids the write latency, read latency, and clock cycles corresponding to the burst length required by the data transmission mechanism, thereby reducing test time.

[0052] After the write operation, when the control circuit M220 receives the mode buffer read instruction MRR, the control sense amplifier M212 reads data from the memory region specified by the address control information ADDR and transmits the read stored data byte S_DA to the comparator M240 via a parallel path. The comparator M240 compares the stored data byte S_DA with the test data byte T_DA previously provided by the test operation buffer and generates a comparison result CMP_RS.

[0053] exist Figure 2 In the embodiment, the comparison result CMP_RS can represent whether the corresponding memory area in the memory bank M211 has normal read and write functions, and can be sent back to the test equipment TD200 for subsequent fault analysis, yield statistics or repair strategy judgment.

[0054] Please refer to the following at the same time Figure 1 , Figure 3 , Figure 3This is a flowchart of a read / write test method 300 according to an embodiment of this disclosure. In this embodiment, the test device TD100 in the test system SYS100 can perform the read / write test method 300 on the memory device M100 to determine whether the memory area of ​​the memory module M110 of the memory device M100 has normal read / write functionality.

[0055] In step S310, the test system SYS100 can write the instruction MRW through the mode buffer to enable the memory device M100 to enter the test mode.

[0056] In the test mode, the input / output gate circuit M150 will shut down or bypass the sequence data transmission path conforming to the JEDEC specification, so that subsequent test data does not need to be processed by the sequence receiving circuit M160 and the sequence-to-parallel conversion circuit M170.

[0057] In step S320, the test system SYS100 can, in test mode, enable the mode buffer M130 to write the test data byte T_DA into the memory module M110 in one go through the parallel transmission path.

[0058] Specifically, the pattern buffer M130 has multiple test operation buffers inside, and each test operation buffer can pre-store different test data patterns, such as all logic "1", all logic "0", checkerboard data or other data content suitable for testing.

[0059] The control circuit M120 can generate a command / address combination (i.e., command information CMD and address control information ADDR) according to the mode buffer write instruction MRW. The command information CMD is used to specify the test operation buffer to be selected, while the address control information ADDR is used to specify the memory bank or memory region in the memory module M110.

[0060] After receiving the command information CMD, the mode buffer M130 can set the corresponding preset data as the test data byte T_DA, and write the test data byte to the memory area specified by the address control information ADDR in one go through the parallel transmission path.

[0061] It is worth mentioning that the parallel transmission path can be a multi-bit data transmission path, and the amount of data that can be transmitted at one time can be 8 bits, 16 bits, 32 bits or any number of bits.

[0062] Furthermore, since the write operation on the test data byte T_DA is performed directly on the memory module M110 via a parallel data access path, it does not require the sequential data transfer mechanism specified in the JEDEC standard.

[0063] In step S330, the test system SYS100 can read the stored data byte S_DA corresponding to the test data byte T_DA from the memory module M110 in one go through the mode buffer read instruction MRR via the parallel transmission path.

[0064] Specifically, after receiving the mode buffer read instruction MRR, the control circuit M120 of the test system SYS100 controls the mode buffer M130 to read the stored data byte S_DA corresponding to the test data byte T_DA from the corresponding write address of the memory module M110 through the aforementioned parallel transmission path.

[0065] In step S340, the test system SYS100 can compare the stored data byte S_DA with the test data byte T_DA through comparator M140 to generate a comparison result CMP_RS.

[0066] In some embodiments, the comparison result CMP_RS can be transmitted to the test device TD100 via comparator M140 for recording, analysis or use in subsequent memory repair processes.

[0067] By executing read / write test method 300, the test system SYS100 can not only perform tests on the overall memory module M110, but also further perform read / write tests on the memory library or more subdivided memory regions within the memory module M110, so that the test results correspond to more precise memory regions, thereby improving test efficiency and memory repair accuracy.

[0068] Incidentally, in other areas not shown... Figures 1 to 3 In the embodiments described, the "comparator" can be located not only in the memory device but also in the test equipment. Furthermore, the data width of the test data byte T_DA and the actual implementation of the parallel transmission path can be adjusted according to actual needs without affecting the core spirit of the technology disclosed herein.

[0069] In summary, the memory device and its read / write test method provided in this disclosure can perform read / write tests on memory modules through parallel read / write operations and internal comparison mechanisms, without relying on a sequential data transmission path conforming to JEDEC specifications. Therefore, the memory device in this disclosure can significantly reduce test time during read / write testing, thereby improving test efficiency.

[0070] The above are merely preferred embodiments of this disclosure. Various modifications and equivalent changes can be made to this disclosure without departing from its scope or spirit. In summary, all modifications and equivalent changes to this disclosure made within the scope of the following claims are within the scope of this disclosure.

[0071] [Symbol Explanation] SYS100, SYS200: Test systems TD100, TD200: Test equipment M100, M200: Memory devices M110, M210: Memory modules M120, M220: Control circuit M130, M230: Mode Buffer M140, M240: Comparators M150, M250: Input / output gate control circuit M160, M260: Sequence receiving circuit M170, M270: Sequence to Parallel Conversion Circuit TOPO231, TOPO232, TOPO233: Test Operation Buffer M211: Memory library M212: Sensing Amplifier M213: Address Decoding Circuit MRW: Pattern Buffer Write Instruction MRR: Mode Buffer Read Instruction ADDR: Address control information CMD: Command Information T_DA: Test data bytes S_DA: Storage data bytes CMP_RS: Comparison Results DQ: Data DQS: Data strobe signal 300: Read / Write Test Method S310, S320, S330, S340: Steps.

Claims

1. A read / write test method, performed by a test device on a memory device, characterized in that, The memory device includes a memory module and a pattern cache, and the read / write test method includes: The memory device is put into test mode by writing instructions to the mode buffer; In the test mode, the mode buffer writes the test data bytes into the memory module at once via a parallel transmission path; The storage data byte corresponding to the test data byte is read from the memory module in one go via the parallel transmission path by reading the instruction from the pattern buffer. as well as The stored data bytes and the test data bytes are compared to generate a comparison result. The comparison result is used to represent whether the memory region of the memory module has normal read and write functions.

2. The read / write test method according to claim 1, characterized in that, The read / write test method further includes: Multiple test operation buffers are set within the pattern buffer; The multiple test operation buffers store multiple sets of preset data. Upon receiving the write instruction to the pattern buffer, a command / address combination is generated; as well as The pattern buffer sets one of the multiple preset data into the test data byte according to the command / address combination.

3. The read / write test method according to claim 2, characterized in that, One address of the command / address combination is used to correspond to a memory region of the memory library in the memory module.

4. The read / write test method according to claim 1, characterized in that, The memory device further includes a sequential data transmission path conforming to the JEDEC standard for transmitting data and data strobe signals, and in the test mode, the data and the data strobe signals are not written to the memory module via the sequential data transmission path.

5. The read / write test method according to claim 4, characterized in that, In the normal mode after the test mode ends, the data and the data strobe signal are written to the memory module via the sequence data transmission path.

6. The read / write test method according to claim 1, characterized in that, The testing device further includes a comparator, and the read / write testing method further includes: The comparator generates the comparison result and outputs the comparison result to the test device.

7. The read / write test method according to claim 1, characterized in that, The test mode refers to the memory device operating in an environment with a data transfer rate of less than or equal to 533 Mbps.

8. The read / write test method according to claim 1, characterized in that, The read / write test method further includes: In the test mode, the memory module is directly written to and read from using parallel data access operations triggered by the mode buffer, instead of using the sequential data transmission mechanism that conforms to the JEDEC standard. This avoids the write latency, read latency, and multiple clock cycles corresponding to the burst length required by the sequential data transmission mechanism, thereby reducing the test time.

9. A memory device coupled to a test apparatus, characterized in that, The memory device includes: Memory module; A control circuit, coupled to the memory module, is used to: The test device receives a mode buffer write instruction, causing the memory device to enter test mode. as well as Receive a read instruction from the pattern buffer from the test device; A pattern buffer, coupled to the memory module and the control circuit, is used to write test data bytes into the memory module at once via a parallel transmission path in response to the control circuit receiving a write command from the pattern buffer. as well as The comparator, coupled to the pattern buffer, is used to: In response to the control circuit receiving the mode buffer read instruction, the stored data bits corresponding to the test data bits are received from the memory module at once via the parallel transmission path; as well as The stored data bytes and the test data bytes are compared to generate a comparison result. The comparison result is used to represent whether the memory region of the memory module has normal read and write functions.

10. The memory device according to claim 9, characterized in that, The pattern buffer is equipped with multiple test operation buffers, which are used to store multiple preset data entries. The control circuit is further configured to generate a command / address combination after receiving the write instruction to the mode buffer; as well as The pattern buffer is further configured to receive the command / address combination command to set one of the plurality of preset data as the test data byte.

11. The memory device according to claim 10, characterized in that, The address of the command / address combination corresponds to the memory region of the memory library in the memory module.

12. The memory device according to claim 9, characterized in that, The memory device further includes a sequential data transmission path conforming to the JEDEC standard for transmitting data and data strobe signals, and in the test mode, the data and the data strobe signals are not written to the memory module via the sequential data transmission path.

13. The memory device according to claim 12, characterized in that, In the normal mode after the test mode ends, the data and the data strobe signal are written to the memory module via the sequence data transmission path.

14. The memory device according to claim 9, characterized in that, The test mode refers to the memory device operating in an environment with a data transfer rate of less than or equal to 533 Mbps.

15. The memory device according to claim 9, characterized in that, The comparator is further used to output the comparison result to the test device.

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