Tqv chip srma fault dynamic positioning method and system

Abstract

The application discloses a TQV chip SRAM fault dynamic positioning method and system, wherein the method comprises the following steps: based on preset chip hardware parameters, all SRAM modules are configured as detection groups including several subgroups through a resource constraint cost function; actual data and expected data are executed bit-by-bit exclusive or operation on each SRAM module, and an error flag is marked for the detection group of the SRAM module with a fault; according to the marking condition of the error flag, a clock gate-off instruction is executed on the detection group without the error flag to skip the scanning period, and a scanning chain through switching instruction is executed to keep the scanning chain continuously through; the fault scanning operation is continuously executed on each subgroup in the detection group with the error flag; and based on the preconfigured static address mapping table, the address of the fault SRAM module is determined according to the judgment result of the fault scanning operation. The application effectively improves the detection efficiency, shortens the detection time, optimizes the hardware resources, and improves the positioning accuracy.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit testing technology, and in particular to a method and system for dynamic fault location of TQV chip SRAM. Background Technology

[0002] TQV chips (Technology Qualification Vehicles) are a set of test structures specifically designed to verify, monitor, and optimize wafer manufacturing process capabilities. TQV chips integrate a large-scale SRAM (Static Random Access Memory) array and are key test objects for process yield verification and reliability assessment.

[0003] Locating faulty SRAM is a key task in TQV chip testing. Traditional serial scanning methods for SRAM fault location have scanning times that increase linearly with array size and complexity, while parallel testing methods have inherent drawbacks such as high hardware resource overhead and poor scalability. In addition, the current binary search method used for fault location cannot adapt to different array sizes and is constrained by hardware resources, resulting in low resource utilization. The detection process requires a complete scan of fault-free groups, leading to significant clock cycle waste, especially in low-fault-rate scenarios.

[0004] In summary, existing SRAM fault location methods struggle to balance testing efficiency, hardware overhead, and location accuracy, making them unsuitable for increasingly demanding testing tasks. Summary of the Invention

[0005] In order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a method and system for dynamic fault location of TQV chip SRAM, which has the advantages of effectively utilizing hardware resources and improving testing efficiency.

[0006] The objective of this invention is achieved through the following technical solution: According to a first aspect of the present disclosure, a method for dynamic fault location of a TQV chip SRAM is provided, comprising: Based on the preset chip hardware parameters, all SRAM modules are configured into detection groups including several subgroups through a resource constraint cost function to construct a tree-structured comparison array; Perform a bitwise XOR operation between the actual data and the expected data for each SRAM module, and mark the detection group of faulty SRAM modules with an error flag; Based on the error flag marking status, a clock gating shutdown instruction is executed on the detection group without an error flag to skip the scan cycle and a scan chain pass-through switching instruction is executed to keep the scan chain continuously connected. Continue performing fault scanning operations on each subgroup within the detection group that has an error flag; The address of the faulty SRAM module is determined based on the pre-configured static address mapping table and the judgment results of the fault scan operation.

[0007] In some exemplary implementations, the chip hardware parameters include the total number of SRAM modules, the maximum number of available parallel comparator groups per level, the preset maximum number of layers, and the underlying switching threshold.

[0008] In some exemplary embodiments, configuring all SRAM modules into a detection group comprising several subgroups using a resource constraint cost function specifically includes: The number of candidate groups M is determined according to a predetermined grouping rule, which is configured as follows: M∈{2,4,8,16,…,min(C,N)}, where C is the maximum number of available parallel comparator groups in a single stage, and N is the total number of SRAM modules; For each candidate group number M, the theoretical minimum number of strata is determined according to the stratification calculation formula, where the stratification calculation formula is L. M =log M N , where L M This represents the theoretical minimum number of layers. For each candidate group number M, the proportion of error-free groups is estimated based on a preset failure rate, and the comprehensive cost is calculated according to the cost function; The comprehensive cost of all candidate group numbers M is traversed, and the candidate group number M with the minimum comprehensive cost is taken as the final number of detection groups.

[0009] In some exemplary embodiments, the step of estimating the proportion of error-free groups for each candidate group number M based on a preset failure rate specifically includes: The number of SARM modules in a single group is determined according to a first calculation formula, which is: , of which S M This refers to the number of SARM modules in a single group; The probability of error-free grouping is determined according to the second calculation formula, which is: Where P0 is the probability of error-free grouping and p is the preset failure rate; The estimated skip rate is determined according to the third calculation formula, which is η. M ≈P0, where η M To estimate the skip rate; The estimated effective scanning period is determined according to the fourth calculation formula, which is: T scan (M)=N(1−η M ), where T scan (M) represents the estimated effective scan period.

[0010] In some exemplary embodiments, the cost function is: Cost(M) = α⋅L M +β⋅T scan (M)+γ⋅M, where Cost(M) is the overall cost, α is the layer number weight, β is the scan cycle weight, and γ is the hardware overhead weight.

[0011] In some exemplary implementations, when the number of SARM modules in a detection group is less than or equal to the underlying switching threshold S0, the grouping process is switched to a binary search method.

[0012] In some exemplary embodiments, when the clock gating shutdown instruction is executed on the detection group without error flag, a skip enable signal is generated based on the absence of error flag, and the clock gating shutdown instruction is executed based on the skip enable signal to skip the scan cycle of the corresponding group.

[0013] In some exemplary embodiments, when executing the scan chain pass-through switching instruction to keep the scan chain continuously connected, the input is switched through a multiplexer to keep the scan chain continuously connected.

[0014] In some exemplary embodiments, when determining the address of the faulty SRAM module based on the judgment result of the fault scan operation, a skip mask is also configured to filter invalid scan segments.

[0015] According to a second aspect of the present disclosure, a TQV chip SRAM fault dynamic location system is provided, comprising: The grouping construction unit is used to configure all SRAM modules into detection groups including several subgroups based on preset chip hardware parameters and through a resource constraint cost function, so as to construct a tree-like comparison array; The operation identification unit is used to perform a bitwise XOR operation between the actual data and the expected data for each SRAM module, and to mark the detection group of faulty SRAM modules with an error flag. The scan skip unit is used to execute a clock gating shutdown instruction to skip the scan cycle and a scan chain pass-through switching instruction to keep the scan chain continuously connected, based on the marking status of the error flags. The fault scanning unit is used to continue performing fault scanning operations on each subgroup in the detection group with error identification; The fault location unit is used to determine the address of the faulty SRAM module based on the pre-configured static address mapping table and the judgment result of the fault scan operation.

[0016] In summary, compared with the prior art, the present invention has the following beneficial effects: This invention provides a method and system for dynamic fault location of SRAM in a TQV chip. The method includes: configuring all SRAM modules into detection groups comprising several subgroups based on preset chip hardware parameters and using a resource constraint cost function to construct a tree-structured comparison array; performing a bitwise XOR operation between the actual data and the expected data for each SRAM module, and marking the detection groups containing faulty SRAM modules with error flags; based on the marking status of the error flags, executing a clock gating shutdown instruction to skip the scan cycle and executing a scan chain pass-through switching instruction to maintain continuous scan chain operation for detection groups without error flags; continuing to perform fault scanning operations on each subgroup in the detection groups with error flags; and determining the address of the faulty SRAM module based on a pre-configured static address mapping table and the judgment result of the fault scanning operation. By constructing a tree-structured comparison array, the scanning cycle is skipped for detection groups without error flags, allowing only detection groups with error flags to continue scanning. This effectively reduces the scanning and detection workload, thereby improving detection efficiency and shortening detection time. At the same time, the group comparison method can effectively reduce dynamic power consumption and reduce the use of comparators, optimizing hardware resources and effectively balancing resource overhead and test speed. Furthermore, combined with a static address mapping table, the location of faulty SRAM modules can be accurately located, improving positioning accuracy. Attached Figure Description

[0017] Figure 1 This is a flowchart of the method for dynamic fault location of TQV chip SRAM in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] like Figure 1 As shown, an embodiment of the present invention provides a method for dynamic fault location of a TQV chip SRAM, comprising: S100: Based on preset chip hardware parameters, all SRAM modules are configured into detection groups including several subgroups through a resource constraint cost function to construct a tree-like comparison array.

[0020] Specifically, the chip hardware parameters include the total number of SRAM modules, the maximum number of available parallel comparator groups per level, the preset maximum number of layers, and the underlying switching threshold.

[0021] The specific steps of configuring all SRAM modules into detection groups comprising several sub-groups using the resource constraint cost function include: S101. Determine the number of candidate groups M according to the predetermined grouping rules, wherein the grouping rules are configured as: M∈{2,4,8,16,…,min(C,N)}, where C is the maximum number of available parallel comparator groups in a single stage, and N is the total number of SRAM modules.

[0022] Typically, to ensure hardware regularity and facilitate circuit implementation, the number of candidate groups M is taken as an integer power of 2. Integer powers of 2 are treated as a set, and min(C,N) is used as the boundary of the set. The maximum number of parallel comparator groups available in a single stage, C, is the upper limit of hardware resources, usually taking values ​​such as 4, 8, 16, etc. min(C,N) means taking the minimum value between C and N. For example, when C is 4 and N is 512, M∈{2,4}.

[0023] S102. For each candidate group number M, determine the theoretical minimum number of strata according to the stratification calculation formula, wherein the stratification calculation formula is L. M =log M N , where L M The theoretical minimum number of layers; the preset maximum number of layers L is usually taken as 2~4 based on engineering experience, and the theoretical minimum number of layers L M The optimal value is within the range of L. The minimum number of layers required to recursively split the N SARM modules into M groups during this process is the theoretical minimum number of layers.

[0024] S103. For each candidate group number M, estimate the proportion of error-free groups based on the preset failure rate, and calculate the comprehensive cost according to the cost function.

[0025] Specifically, the proportion of error-free groups estimated for each candidate group number M based on a preset failure rate includes: S1031. Determine the number of SARM modules in a single group according to the first calculation formula, wherein the first calculation formula is: , of which S M The number of SARM modules in a single group, N, M, L M The value is determined based on the values ​​and calculation results from the preceding steps.

[0026] S1032. Determine the probability of error-free grouping according to the second calculation formula, where the second calculation formula is: Where P0 is the probability of error-free grouping and p is the preset failure rate; the failure rate p is determined based on engineering experience or historical data statistics, for example, it can be set to 0.01.

[0027] S1033. Determine the estimated skip rate according to the third calculation formula, wherein the third calculation formula is η. M≈P0, where η M To estimate the skip rate.

[0028] S1034. Determine the estimated effective scanning period according to the fourth calculation formula, wherein the fourth calculation formula is: T scan (M)=N(1−η M ), where T scan (M) represents the estimated effective scan period.

[0029] Furthermore, the cost function is: Cost(M) = α⋅L M +β⋅T scan (M)+γ⋅M, where Cost(M) is the overall cost, α is the layer number weight, β is the scan cycle weight, and γ is the hardware overhead weight; α⋅L M Used to penalize excessive layers in order to reduce timing delays and control complexity, β⋅T scan (M) is used to penalize excessively long effective scan cycles to prevent slow testing speeds, while γ⋅M is used to penalize excessively large numbers of hardware comparators, thereby saving resource overhead.

[0030] S104. Iterate through the comprehensive cost of all candidate group numbers M and use the candidate group number M with the minimum comprehensive cost as the final number of detection groups.

[0031] Taking a specific example, the total number of SRAM modules N is set to 512, the maximum number of available parallel comparator groups in a single stage C is 4, and the failure rate p is 0.01. At this time, the number of candidate groups M ∈ {2,4}. When M=2, L M =log M N =9,T scan (M) ≈512×(1−0.73)=138, Cost≈1×9+0.5×138+0.2×2=78.4; When M=4, L M =log M N =5,T scan (M) ≈512×(1−0.99)=5.12, Cost≈1×5+0.5×5.12+0.2×4=8.36; It is evident that the overall cost is minimized when M=4, therefore the number of detection groups is determined to be 4.

[0032] Furthermore, it also includes S105, when the number of SARM modules in the detection group is less than or equal to the underlying switching threshold S0, switching to the binary method for group processing; where S0 can be set to values ​​such as 32 or 64, etc. By setting the forced binary method, both coarse positioning speed and fine positioning accuracy can be taken into account.

[0033] S200: Perform a bitwise XOR operation between the actual data and the expected data for each SRAM module, and mark the detection group of faulty SRAM modules with an error flag.

[0034] Specifically, for example: each SRAM module stores a data bit as the actual value, denoted as R[i]. During testing, a corresponding expected data bit is generated, such as previously written known data, denoted as E[i]. During the comparison at the detection group level, each SRAM module performs a bitwise XOR operation between the actual data and the expected data. When the actual data and the expected data are the same, the result is 0; when they are different, the result is 1. If the results are different, it indicates that there is a fault. At this time, the detection group with the fault can be marked with an error flag.

[0035] S300. Based on the marking status of the error flag, execute a clock gating shutdown instruction to skip the scan cycle and execute a scan chain pass-through switching instruction to keep the scan chain continuously connected for the detection group without an error flag.

[0036] In actual operation, error flags of lower-level subgroups can be aggregated by upper-level nodes to generate a group error-free flag G. OK When G OK When G is 1, it means that the detection group is error-free and can be skipped. OK When the value is 0, it indicates that the detection group has a fault and the subsequent group comparison process needs to be executed. At the same time, a skip enable signal SKIP can be generated based on the error-free flag of the group. When SKIP is 1, the skip operation can be performed, and when SKIP is 0, a full scan is performed on the corresponding detection group.

[0037] In this embodiment, when executing a clock-gated shutdown instruction for a detection group without an error flag, a skip enable signal is generated based on the absence of an error flag, and the clock-gated shutdown instruction is executed based on the skip enable signal to skip the scan cycle of the corresponding group. When executing a scan chain pass-through switching instruction to keep the scan chain continuously connected, the input is switched through a multiplexer to keep the scan chain continuously connected.

[0038] Specifically: when there is no error flag G in the grouping... OK When the value is 1, the clock gating shuts off the clock of the group scan unit, stops the flip-flop from toggling to reduce power consumption, and at the same time, the scan chain is switched to the upper-level input via the MUX (multiplexer), so that the scan chain is continuously connected without interrupting the shift link; thus, while skipping the scan cycle, the integrity of the scan chain and the fault location accuracy are guaranteed.

[0039] S400. Continue to perform fault scanning operation on each subgroup in the detection group with error identification. During the fault scanning operation, the aforementioned skip operation can also be used.

[0040] S500 determines the address of the faulty SRAM module based on the pre-configured static address mapping table and the judgment result of the fault scan operation.

[0041] Specifically, when determining the address of the faulty SRAM module based on the judgment result of the fault scan operation, a skip mask is also configured to filter invalid scan segments.

[0042] The following is an example to illustrate this: In this example, the total number of SRAM modules is 512, the configured static address range is 0 to 511, the data bit width is 8 bits, the maximum number of layers L=2, the maximum number of available comparator groups per level C=4, and the bottom layer switching threshold S0=32.

[0043] S100, Input chip hardware parameters: Total number of SRAM modules N is 512, maximum number of available parallel comparator groups in a single level C is 4, maximum number of layers L=2, calculate the number of detection groups M=4, that is, the top layer is divided into 4 detection groups A, B, C, D, each group contains 128 SRAM modules, with address ranges of 0~127, 128~255, 256~383, 384~511 respectively; while the size of the bottom layer sub-groups is equal to the switching threshold S0=32, keeping M=4 groups.

[0044] S200. First, initialize the SRAM modules by writing custom test data to all SRAM modules and resetting the fault scan chain. Set all 512 initial values ​​to 0 and reset the skip mask register, with an initial value of 0000. Then, perform a bitwise XOR operation between the actual data and the expected data of each SRAM module to generate a cell error flag. The result is: Group A, 128 SRAM modules: all cell error flags are 0; Group B contains 128 SRAM modules: including 2 faulty cells with a cell error flag of 1; Group C contains 128 SRAM modules: including 1 faulty cell with the cell error flag set to 1; Group D, 128 SRAM modules: all cell error flags are 0.

[0045] S300: Aggregate the unit error flags of the four detection groups to generate an error-free flag G. OK Among them, G in Group A and Group D OK =1, Group B and Group C G OK=0; At this time, status code 1001 is generated, and the skip mask register is updated to 1001; Groups A and D disable the subsequent group comparison logic, while groups B and C enter the next layer comparison.

[0046] S400, further subdividing group B into B1, B2, B3, and B4, each group containing 32 SRAM modules, and group C into C1, C2, C3, and C4, each group containing 32 SRAM modules, the fault scan operation determines that B1, B4, C1, C2, and C4 are fault-free, and their G... OK =1, SKIP=1; B2, B3, C3 are faulty, and their G... OK =0, SKIP=0; At this time, update the skip mask register, mark B2, B3, and C3 as valid scan segments. Specifically, the initial value of the skip mask registers for groups B and C is 0000. Since groups B1, B4, C1, C2, and C4 are error-free, the skip mask register for group B is updated to 1001, and the skip mask register for group C is updated to 1101.

[0047] Understandably, the system configures a hierarchical skip mask register with a bit width consistent with the current layer's group size M. Each bit corresponds to one group, with 1 indicating skipping the scan and 0 indicating performing the scan. After the top-level group comparison is complete, the error-free flag G of the top-level group is set. OK The data is directly mapped and written to the top-level skip mask register. Only for erroneous groups with a top-level mask of 0, the lower-level sub-group comparison is further performed. The error-free flag of the lower-level sub-group is directly mapped and written to the corresponding lower-level skip mask register. After the mask of each layer is updated, it is uniformly output to the clock gating and scan chain pass-through MUX to control whether the scan cycle is skipped or executed normally.

[0048] After the above processing, the skipped groups are A, B1, B4, C1, C2, C4, and D, totaling 416 scan cycles. The clock gating of these skipped groups is turned off and the scan chain is straight through. The effective scan segments include B2, B3, and C3, totaling 96 scan cycles. These groups require a complete shift output fault scan operation.

[0049] S500. Finally, the address of the faulty SRAM module is determined by combining the static address mapping table. The fault scan operation is performed sequentially in the 32-bit B2 segment, the 32-bit B3 segment, and the 32-bit C3 segment. The fault location is the 5th bit of the B2 segment, the 12th bit of the B3 segment, and the 8th bit of the C3 segment. The judgment result is: The starting address of segment B2 is 160. The 5th bit of the scan result is 1, which indicates a fault point with a fault address of 165. The starting address of segment B3 is 192, and the 12th bit scan result is 1, which indicates a fault point with a fault address of 204. The starting address of segment C3 is 320. The 8th bit of the scan result is 1, which indicates a fault point with a fault address of 328.

[0050] Therefore, the final output addresses of the faulty SRAM modules are 165, 204, and 328.

[0051] A second aspect of this invention provides a TQV chip SRAM fault dynamic location system, comprising: a group construction unit, configured to configure all SRAM modules into detection groups including several sub-groups based on preset chip hardware parameters and a resource constraint cost function, to construct a tree-like comparison array; an operation identification unit, configured to perform a bitwise XOR operation between actual data and expected data for each SRAM module, and to mark the detection group with faulty SRAM modules with error flags; a scan skip unit, configured to execute a clock gating shutdown instruction to skip the scan cycle and a scan chain pass-through switching instruction to maintain the continuous operation of the scan chain for detection groups without error flags, based on the marking status of the error flags; a fault scanning unit, configured to continue performing fault scanning operations on each sub-group in the detection group with error flags; and a fault location unit, configured to determine the address of the faulty SRAM module based on a pre-configured static address mapping table and the judgment result of the fault scanning operation.

[0052] This invention constructs a tree-structured comparison array to skip the scan cycle for detection groups without error flags, achieving a skip rate of 50%–90%. This allows scanning to continue only for detection groups with error flags, effectively reducing the scanning workload and thus improving detection efficiency and shortening detection time, significantly outperforming traditional serial scanning and fixed binary search methods. Furthermore, the group comparison method effectively reduces dynamic power consumption and comparator usage, optimizing hardware resources and effectively balancing resource overhead and test speed. Combined with a static address mapping table, it can accurately locate the faulty SRAM module, improving positioning accuracy.

[0053] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention. These are all equivalent modifications and improvements made to the above embodiments based on the essential technology of the present invention, and all of these fall within the protection scope of the present invention.

Claims

1. A method for dynamic fault location of SRAM in a TQV chip, characterized in that, include: Based on the preset chip hardware parameters, all SRAM modules are configured into detection groups including several subgroups through a resource constraint cost function to construct a tree-structured comparison array; Perform a bitwise XOR operation between the actual data and the expected data for each SRAM module, and mark the detection group of faulty SRAM modules with an error flag; Based on the error flag marking status, a clock gating shutdown instruction is executed on the detection group without an error flag to skip the scan cycle and a scan chain pass-through switching instruction is executed to keep the scan chain continuously connected. Continue performing fault scanning operations on each subgroup within the detection group that has an error flag; The address of the faulty SRAM module is determined based on the pre-configured static address mapping table and the judgment results of the fault scan operation.

2. The TQV chip SRAM fault dynamic location method according to claim 1, characterized in that, The chip hardware parameters include the total number of SRAM modules, the maximum number of available parallel comparator groups per level, the preset maximum number of layers, and the underlying switching threshold.

3. The TQV chip SRAM fault dynamic location method according to claim 2, characterized in that, The specific steps of configuring all SRAM modules into detection groups comprising several sub-groups using the resource constraint cost function include: The number of candidate groups M is determined according to a predetermined grouping rule, which is configured as follows: M∈{2,4,8,16,…,min(C,N)}, where C is the maximum number of available parallel comparator groups in a single stage, and N is the total number of SRAM modules; For each candidate group number M, the theoretical minimum number of strata is determined according to the stratification calculation formula, where the stratification calculation formula is L. M =log M N , where L M This represents the theoretical minimum number of layers. For each candidate group number M, the proportion of error-free groups is estimated based on a preset failure rate, and the comprehensive cost is calculated according to the cost function; The comprehensive cost of all candidate group numbers M is traversed, and the candidate group number M with the minimum comprehensive cost is taken as the final number of detection groups.

4. The TQV chip SRAM fault dynamic location method according to claim 3, characterized in that, The specific steps of estimating the proportion of error-free groups for each candidate group number M based on a preset failure rate include: The number of SARM modules in a single group is determined according to a first calculation formula, which is: , of which S M This refers to the number of SARM modules in a single group; The probability of error-free grouping is determined according to the second calculation formula, which is: Where P0 is the probability of error-free grouping and p is the preset failure rate; The estimated skip rate is determined according to the third calculation formula, which is η. M ≈P0, where η M To estimate the skip rate; The estimated effective scanning period is determined according to the fourth calculation formula, which is: T scan (M)=N(1−η M ), where T scan (M) represents the estimated effective scan period.

5. The TQV chip SRAM fault dynamic location method according to claim 4, characterized in that, The cost function is: Cost(M) = α⋅L M +β⋅T scan (M)+γ⋅M, where Cost(M) is the overall cost, α is the layer number weight, β is the scan cycle weight, and γ is the hardware overhead weight.

6. The TQV chip SRAM fault dynamic location method according to claim 3, characterized in that, When the number of SARM modules in the detection group is less than or equal to the underlying switching threshold S0, the grouping process is switched to binary search.

7. The TQV chip SRAM fault dynamic location method according to claim 1, characterized in that, When executing the clock gating shutdown instruction on the detection group without error flag, a skip enable signal is generated based on the absence of error flag, and the clock gating shutdown instruction is executed based on the skip enable signal to skip the scan cycle of the corresponding group.

8. The TQV chip SRAM fault dynamic location method according to claim 1 or 7, characterized in that, When executing the scan chain pass-through switching command to keep the scan chain continuously connected, the input is switched through a multiplexer to keep the scan chain continuously connected.

9. The TQV chip SRAM fault dynamic location method according to claim 1, characterized in that, When determining the address of the faulty SRAM module based on the judgment result of the fault scan operation, a skip mask is also configured to filter invalid scan segments.

10. A dynamic fault location system for TQV chip SRAM, characterized in that, include: The grouping construction unit is used to configure all SRAM modules into detection groups including several subgroups based on preset chip hardware parameters and through a resource constraint cost function, so as to construct a tree-like comparison array; The operation identification unit is used to perform a bitwise XOR operation between the actual data and the expected data for each SRAM module, and to mark the detection group of faulty SRAM modules with an error flag. The scan skip unit is used to execute a clock gating shutdown instruction to skip the scan cycle and a scan chain pass-through switching instruction to keep the scan chain continuously connected, based on the marking status of the error flags. The fault scanning unit is used to continue performing fault scanning operations on each subgroup in the detection group with error identification; The fault location unit is used to determine the address of the faulty SRAM module based on the pre-configured static address mapping table and the judgment result of the fault scan operation.

Images