Circuit board structure and inductor structure of magnetic element

Abstract

The application relates to a circuit board structure and an inductance structure of a magnetic element, wherein a plurality of layers of the PCB boards are arranged in a laminated mode, and a magnetic core is arranged at a corresponding position on the plurality of layers of the PCB boards; a twisted wire includes a plurality of wires; each wire is provided with a via hole on each layer of the PCB boards; each wire is extended from a first layer of the PCB boards to a last layer of the PCB boards through the corresponding via hole in a preset direction around the magnetic core in a preset order of the plurality of layers of the PCB boards; the plurality of wires are twisted on the plurality of layers of the PCB boards; and the positions of the via holes corresponding to the wires on the PCB boards are related to the phase span gradient of the magnetic core. The plurality of wires are connected in parallel through the via holes on the plurality of layers of the PCB boards, so that the current is uniformly distributed among the layers, the circulating current is effectively inhibited, and the performance of the magnetic element is further improved.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a circuit board structure and an inductor structure for a magnetic element. Background Technology

[0002] Magnetic components are core components of power electronics technology, typically consisting of windings and magnetic cores. They mainly include transformers and inductors, and are used for functions such as energy storage, energy conversion, and electrical isolation. With the increasingly widespread application of planar magnetic components in power electronics, PCB windings are widely used due to their inherent insulation and high production efficiency.

[0003] Currently, in related technologies, planar magnetic components typically have multiple layers of traces connected in parallel due to the limited current-carrying capacity of single-layer PCB windings. Specifically, each layer of traces is in a different magnetic field strength, resulting in different AC impedances between the layers. The layer with lower impedance carries a larger current, while the layer with higher impedance carries a smaller current, leading to uneven current distribution and severe circulating current, which further affects the performance of the magnetic components. Summary of the Invention

[0004] Therefore, it is necessary to provide a circuit board structure and an inductor structure for magnetic components to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a circuit board structure for a magnetic component. The circuit board structure includes a multilayer PCB board, a magnetic core, and stranded traces. The multilayer PCB boards are stacked, and the magnetic core is disposed at corresponding positions on the multilayer PCB boards. The stranded traces include multiple traces. Each trace has a corresponding via on each layer of the PCB board. Each trace, in a predetermined order of the multilayer PCB boards, winds around the magnetic core in a predetermined direction, extending from the first layer of the PCB board through the corresponding via to the last layer of the PCB board. The multiple traces are stranded on the multilayer PCB boards. The position of the via corresponding to each trace on the PCB board is related to the phase span gradient of the magnetic core.

[0006] In one embodiment, the number of turns of the stranded trace is a first quantity, and the number of layers of the multilayer PCB board is a second quantity; the second quantity is an integer multiple of the first quantity, and is greater than one.

[0007] In one embodiment, there is a phase span gradient in the region surrounded by magnetic lines of force around the magnetic core on each PCB layer; the phase span for each via corresponding to each trace on each PCB layer is: Ø=2πN / L; where N is a first quantity, L is a second quantity, and Ø is the phase span.

[0008] In one embodiment, the magnetic core includes a core center post and two core side posts; the second number is twice the first number; the stranded traces include two traces; the vias in each layer of the PCB are opened in the area around the core center post that is not surrounded by magnetic lines of force; and the vias in two adjacent layers of the PCB are on both sides of the core center post.

[0009] In one embodiment, the vias of each layer of the PCB are located in the area around the magnetic core pillar that is not surrounded by magnetic lines of force, except at the center position.

[0010] In one embodiment, the stranded traces include a first trace and a second trace; in each layer of the PCB board, the area corresponding to the first trace and the area corresponding to the second trace do not overlap and are staggered.

[0011] Secondly, this application also provides an inductor structure, the inductor structure comprising a circuit board structure of two magnetic elements as described in the first aspect; the circuit board structure comprising a magnetic core, two PCB layers and a stranded trace; the stranded trace comprising a first trace and a second trace; the magnetic core comprising a core center post and two core side posts.

[0012] In one embodiment, the first trace is composed of a first long trace, a first short trace, a first via trace, and a first transition trace; the second trace is composed of a second long trace, a second short trace, a second via trace, and a second transition trace; the first long trace, the second long trace, and the second transition trace are disposed on a first layer PCB board; the first short trace, the first transition trace, and the second short trace are disposed on a second layer PCB board.

[0013] In one embodiment, the first long trace and the second long trace have the same dimensions; the first short trace and the second short trace have the same dimensions; the first transition trace and the second transition trace have the same dimensions; and the first via trace and the second via trace have the same dimensions.

[0014] In one embodiment, the centerline of the first transition line and the second transition line coincides with the centerline of the region around the magnetic core pillar that is not surrounded by magnetic field lines.

[0015] The aforementioned magnetic component's circuit board structure and inductor structure include a circuit board structure comprising a multilayer PCB board, a magnetic core, and stranded traces. The multilayer PCB boards are stacked, with the magnetic core positioned at corresponding locations on each board. The stranded traces consist of multiple traces, each with a corresponding via on each PCB layer. Each trace, following a predetermined sequence on the multilayer PCB boards, winds around the magnetic core in a predetermined direction, extending from the first PCB layer through its corresponding via to the last PCB layer. The multiple traces are stranded on the multilayer PCB boards. The position of the via on the PCB board corresponding to each trace is related to the phase span of the magnetic core. The stranding and connection of multiple traces on the multilayer PCB boards through vias achieves interlayer current equalization, effectively suppressing circulating current and further improving the performance of the magnetic component. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the circuit board structure of the magnetic element in one embodiment;

[0017] Figure 2 This is a schematic diagram of the phase span gradient of an E-shaped magnetic core in one embodiment;

[0018] Figure 3 This is a schematic diagram of the phase span gradient of the magnetic core in one embodiment;

[0019] Figure 4 This is a schematic diagram of the magnetic elements of an E-shaped magnetic core in one embodiment;

[0020] Figure 5 This is a schematic diagram of a magnetic element of an E-shaped magnetic core with vias at arbitrary positions in one embodiment.

[0021] Figure 6 This is a schematic diagram of a magnetic component on a four-layer PCB board with three turns of trace in one embodiment;

[0022] Figure 7 This is a schematic diagram of a magnetic component on a six-layer PCB board with three turns of trace in one embodiment;

[0023] Figure 8 This is a schematic diagram of the inductor structure in one embodiment;

[0024] Figure 9 This is a schematic diagram of the first and second traces in one embodiment;

[0025] Figure 10 This is a schematic diagram of a split resonant inductor in one embodiment;

[0026] Figure 11 This is a schematic diagram illustrating the superposition of the differential-mode magnetomotive forces of the resonant inductors in one embodiment;

[0027] Figure 12This is a schematic diagram illustrating the mutual cancellation of common-mode magnetomotive forces of resonant inductors in one embodiment;

[0028] Figure 13 This is a perspective view of a finite element simulation model in one embodiment;

[0029] Figure 14 This is a side view of a finite element simulation model in one embodiment;

[0030] Figure 15 An exploded view of a finite element simulation model in one embodiment;

[0031] Figure 16 This is an external current source excitation circuit used in the simulation of one embodiment;

[0032] Figure 17 The current waveforms of four traces obtained from simulation in one embodiment are shown.

[0033] Figure 18 The loss waveforms of four traces obtained from simulation in one embodiment are shown.

[0034] Figure 19 The following is a simulation of the current waveforms of four traces obtained for a specific technology in one embodiment;

[0035] Figure 20 This is a simulation of the loss waveforms of four traces obtained for a related technology in one embodiment. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0038] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0039] Magnetic components are core components of power electronics technology, typically consisting of windings and magnetic cores. They mainly include transformers and inductors, and are used for functions such as energy storage, energy conversion, and electrical isolation. With the increasingly widespread application of planar magnetic components in the field of power electronics, planar design helps to reduce the size of magnetic components. At the same time, PCB windings are widely used due to their advantages such as built-in insulation, frame, and high production efficiency.

[0040] Currently, planar magnetic components in related technologies have limited current-carrying capacity in a single-layer PCB winding, requiring inter-layer or inter-board parallel connections. This means their windings are typically multiple layers of traces directly connected in parallel. For example, in a transformer, the primary and secondary windings have opposite magnetomotive forces. By alternating the primary and secondary windings, the magnetic field strength of each winding can be made approximately equal, thus achieving current sharing in the parallel branches and reducing losses. However, in planar inductors, since there is no magnetomotive force opposite to the inductor winding, the traces on each layer are in different magnetic field strengths, resulting in different AC impedances between the layers. This leads to inconsistent magnetic flux across the traces; the layer with lower impedance carries more current, and the layer with higher impedance carries less current, resulting in uneven current distribution and severe circulating currents, further affecting the performance of the magnetic component.

[0041] In one embodiment, such as Figure 1 As shown, a circuit board structure for a magnetic component is provided, wherein the circuit board structure includes a multilayer PCB board 100, a magnetic core 200, and stranded traces 300.

[0042] A PCB, or Printed Circuit Board, is an electronic interconnect carrier that uses an insulating substrate as a support and forms predetermined traces, pads, vias, and electrical connection structures on its surface through pattern transfer and electrochemical processes. In this embodiment, the PCB has a multi-layer structure. Specifically, the multi-layer PCB 100 can be a 4-layer, 6-layer, or 8-layer PCB, etc. This embodiment does not impose a specific limitation on the number of layers of the multi-layer PCB 100, only requiring compliance with usage requirements. The multi-layer PCB 100 is stacked; for example, a 4-layer PCB is stacked from top to bottom as follows: first layer, second layer, third layer, and fourth layer. Magnetic cores 200 are provided at corresponding positions on the multi-layer PCB 100. Specifically, a portion of the magnetic core is provided at the same position on each PCB layer, thus forming a complete magnetic core 200 from the partial magnetic cores of the multi-layer PCB 100. The "same position" refers to the position where the vertical projection of each PCB layer is the same. In this embodiment, the magnetic core 200 can be any type of magnetic core. This embodiment does not make specific limitations. For example, the magnetic core 200 can be an E-shaped magnetic core, or a PQ or EQ magnetic core.

[0043] The stranded trace 300 includes multiple traces. For example, the stranded trace 300 may include 2 traces, 4 traces, 7 traces, etc. This embodiment does not specifically limit the number of stranded traces.

[0044] Each of the aforementioned traces has a corresponding via on each layer of the PCB board. Taking a multilayer PCB board with four layers as an example, the stranded trace 300 includes four traces. For the first trace, a via is provided between the first and second PCB layers, between the second and third PCB layers, and between the third and fourth PCB layers. For the second trace, a via is provided between the first and second PCB layers, between the second and third PCB layers, and between the third and fourth PCB layers. For the third trace, a via is provided between the first and second PCB layers, between the second and third PCB layers, and between the third and fourth PCB layers. For the fourth trace, a via is provided between the first and second PCB layers, between the second and third PCB layers, and between the third and fourth PCB layers.

[0045] Each trace, following a preset order of the multilayer PCBs, winds around the magnetic core in a preset direction, extending from the first PCB layer through the corresponding via to the last PCB layer. The preset order of the multilayer PCBs 100 can be a top-to-bottom arrangement within the entire circuit board structure, a bottom-to-top arrangement, or even a random arrangement. This embodiment does not specifically limit the preset order. For example, taking a 4-layer PCB, the preset order can be the first, second, third, and fourth PCB layers; or it can be the same. The preset direction can be clockwise or counterclockwise; this embodiment does not specifically limit it.

[0046] Taking a multilayer PCB board 100 as a 4-layer PCB board and a stranded trace 300 including 4 traces as an example, for the first trace, the first trace starts from the entry point of the circuit board structure for the first trace. The first trace is laid clockwise on the first PCB board to the via between the first and second PCB boards. After passing through the via, the first trace is laid clockwise on the second PCB board to the via between the second and third PCB boards. After passing through the via, the first trace is laid clockwise on the third PCB board to the via between the third and fourth PCB boards. After passing through the via, the first trace is laid clockwise on the fourth PCB board to the exit point of the circuit board structure for the first trace. For the second trace, the second trace starts from the entry point of the circuit board structure. On the first PCB layer, the second trace is laid clockwise to the via between the first and second PCB layers. After passing through the via, the second trace is laid clockwise on the second PCB layer to the via between the second and third PCB layers. After passing through the via, the second trace is laid clockwise on the third PCB layer to the via between the third and fourth PCB layers. After passing through the via, the second trace is laid clockwise on the fourth PCB layer to the exit point of the circuit board structure. For the third trace, the third trace starts from the entry point of the circuit board structure. On the first PCB layer, the third trace is laid clockwise to the via between the first and second PCB layers. After passing through the via, the third trace is laid clockwise on the second PCB layer to the via between the second and third PCB layers. After passing through the via, the third trace is laid clockwise on the third PCB layer to the via between the third and fourth PCB layers. After passing through the via, the third trace is laid clockwise on the fourth PCB layer to the exit point of the circuit board structure. For the fourth trace, the fourth trace starts from the entry point of the circuit board structure. On the first PCB layer, the fourth trace is laid clockwise to the via between the first and second PCB layers. After passing through the via, the fourth trace is laid clockwise on the second PCB layer to the via between the second and third PCB layers. After passing through the via, the fourth trace is laid clockwise on the third PCB layer to the via between the third and fourth PCB layers. After passing through the via, the fourth trace is laid clockwise on the fourth PCB layer to the exit point of the circuit board structure.The areas corresponding to the four traces on each PCB layer do not overlap.

[0047] Based on the way each trace is set on the multi-layer PCB, multiple traces can be twisted together on the multi-layer PCB.

[0048] The position of the via corresponding to each trace on the PCB is related to the phase span gradient of the magnetic core, thereby optimizing the uniformity of magnetic field coupling. For example... Figure 2 As shown, a schematic diagram of the phase span gradient of an E-shaped magnetic core is provided; as Figure 3 As shown, a schematic diagram of the phase span gradient of a magnetic core is provided. A phase span gradient exists in the region surrounding the magnetic core 200 that is enclosed by magnetic field lines, while no phase span gradient exists in the region surrounding the magnetic core 200 that is not enclosed by magnetic field lines. These magnetic field lines are also known as magnetic field lines. Figure 2 As shown, in this PCB layer, the input terminal is located between the middle and left pillars of the magnetic core. Starting from the input terminal, the area between the middle and left pillars is surrounded by magnetic field lines. Therefore, a phase span gradient exists in the region between the middle and left pillars, with a gradient magnitude of 0 starting from the input terminal and ranging from 0 to π. The area above the middle pillar is not surrounded by magnetic field lines, therefore, there is no phase span gradient in the area above the middle pillar, and the phase span in this area is π. The area between the middle and right pillars is surrounded by magnetic field lines, therefore, there is a phase span gradient between the middle and right pillars, with a gradient magnitude starting from π and ranging from π to 2π. The area below the middle pillar is not surrounded by magnetic field lines, therefore, there is no phase span gradient in the area below the middle pillar, and the phase span in this area is 0 or 2π. Figure 3 As shown, the magnetic core of the ferrite pot is completely surrounded by magnetic field lines, therefore, there is a phase gradient in the circumference of the magnetic core. The gradient magnitude starts from 0 at the input end and ranges from 0 to 2π. Specifically, the vias on each PCB layer are set according to the input position of the corresponding trace and the phase gradient.

[0049] Taking a multilayer PCB board 100 as a 4-layer PCB board and a stranded trace 300 including 4 traces as an example, for the first trace, the via position of the first trace between the first and second PCB boards is determined by the circuit board structure based on the starting position of the first trace's entry point and the phase span gradient of the magnetic core on the first PCB board; the via position of the first trace between the second and third PCB boards is determined by the entry position of the first trace on the second PCB board and the phase span gradient of the magnetic core on the second PCB board, where the entry position of the first trace on the second PCB board is also the via position of the first trace between the first and second PCB boards; the via position of the first trace between the third and fourth PCB boards is determined by the entry position of the first trace on the third PCB board and the phase span gradient of the magnetic core on the third PCB board, where the entry position of the first trace on the third PCB board is also the via position of the first trace between the second and third PCB boards. The method for determining the vias corresponding to the second, third, and fourth traces is the same as that for the first trace, and will not be repeated here.

[0050] This embodiment of the circuit board structure includes a multilayer PCB board, a magnetic core, and stranded traces. The multilayer PCB boards are stacked, and the magnetic core is positioned at corresponding locations on each multilayer PCB board. The stranded traces consist of multiple traces, each with a corresponding via on each PCB layer. Each trace, following a predetermined sequence on the multilayer PCB boards, winds around the magnetic core in a predetermined direction, extending from the first PCB layer through its corresponding via to the last PCB layer. The multiple traces are stranded on the multilayer PCB boards. The position of the via on the PCB board corresponding to each trace is related to the phase span of the magnetic core. The stranding and connection of multiple traces on the multilayer PCB boards through vias achieves interlayer current equalization, effectively suppresses circulating current, and further improves the performance of the magnetic components.

[0051] In one embodiment, taking the twisted trace 300 as an example, the twisted trace 300 includes a first trace 310 and a second trace 320. The first trace 310 and the second trace 320 form a twisted pair structure in the entire circuit board structure, thereby realizing interlayer current equalization and effectively suppressing circulating current.

[0052] Based on the vias on each PCB layer for the first trace 310, the first trace 310 starts from the entry point of the circuit board structure for the first trace 310, and extends along the first direction around the magnetic core 200 in a preset order of the multilayer PCB 100, from the first PCB layer through the vias to the last PCB layer. The preset order of the multilayer PCB 100 can be a top-to-bottom arrangement in the entire circuit board structure, a bottom-to-top arrangement, or a random arrangement. This embodiment does not specifically limit the preset order. For example, taking a 4-layer PCB board, the preset order can be the first, second, third, and fourth PCB layers; or it can be the same as above. The first direction can be clockwise or counterclockwise; this embodiment does not specifically limit it. Understandably, the via positions for the first trace 310 need to be determined sequentially according to a preset order and a first direction. Taking the preset order as the first PCB layer, second PCB layer, third PCB layer, and fourth PCB layer as an example, firstly, based on the circuit board structure, the phase span gradient of the first PCB layer is found along the first direction from the starting position of the first trace 310. The via position is then determined on the first PCB layer, and a via connecting the first and second PCB layers is created at this position. The position of this via on the second PCB layer is the entry position of the first trace 310 on the second PCB layer. The phase span gradient of the second PCB board is found in the first direction, and the via position is determined on the second PCB board. A via connecting the second and third PCB boards is opened at the via position. The position of the via on the third PCB board is the entry position of the first trace 310 on the third PCB board. Based on the entry position of the first trace 310 on the third PCB board, the phase span gradient of the third PCB board is found in the first direction, and the via position is determined on the third PCB board. A via connecting the third and fourth PCB boards is opened at the via position. The position of the via on the fourth PCB board is the entry position of the first trace 310 on the fourth PCB board. It is understood that, depending on the actual number of connected layers, the via can be a through hole, buried via, or blind via. It can also be filled with copper or other metal, as long as the corresponding PCB layer is connected. This embodiment does not make specific limitations. Preferably, for ease of processing, all vias can be set as through holes.For the first trace 310, starting from the entry point of the circuit board structure for the first trace 310, the first trace 310 is laid in the first direction on the first PCB board to the via corresponding to the first PCB board and the second PCB board. After passing through the via, the first trace 310 is laid in the first direction on the second PCB board to the via corresponding to the second PCB board and the third PCB board. After passing through the via, the first trace 310 is laid in the first direction on the third PCB board to the via corresponding to the third PCB board and the fourth PCB board. After passing through the via, the first trace 310 is laid in the first direction on the fourth PCB board to the exit point of the circuit board structure for the first trace 310.

[0053] Based on the vias on each PCB layer for the second trace 320, the second trace 320 starts from the entry point of the circuit board structure for the second trace 320, and extends along the first direction around the magnetic core 200 in the preset order of the multilayer PCB 100, from the last PCB layer through the vias to the first PCB layer. The preset order and first direction of the multilayer PCB 100 are the same as those for the first trace 310, and will not be repeated here. Understandably, the via positions for the second trace 320 need to be determined sequentially according to a preset order and the first direction. Taking the preset order as the first PCB layer, second PCB layer, third PCB layer, and fourth PCB layer as an example, firstly, based on the circuit board structure, the phase span gradient of the fourth PCB layer is found in the first direction from the starting position of the second trace 320. The via position is then determined on the fourth PCB layer, and a via connecting the fourth and third PCB layers is created at this position. The position of this via on the third PCB layer is the entry position of the second trace 320 on the third PCB layer. Based on the entry position of the second trace 320 on the third PCB layer... The phase span gradient of the third PCB board is located in the first direction. A via location is then determined on the third PCB board, and a via connecting the third and second PCB boards is created at that location. The position of this via on the second PCB board is the entry point of the second trace 320 on the second PCB board. Based on the entry point of the second trace 320 on the second PCB board, the phase span gradient of the second PCB board is located in the first direction. A via location is then determined on the second PCB board, and a via connecting the second and first PCB boards is created at that location. The position of this via on the first PCB board is the entry point of the second trace 320 on the first PCB board. It is understood that, for the actual number of connected layers, the via can be a through-hole, buried via, or blind via, as long as it ensures the connectivity of the corresponding PCB layers. This embodiment does not impose specific limitations. Preferably, for ease of processing, all vias can be set as through-holes.For the second trace 320, starting from the entry point of the second trace 320 on the circuit board structure, the second trace 320 is laid in the first direction on the fourth PCB board to the via connecting the fourth PCB board and the third PCB board. After passing through the via, the second trace 320 is laid in the first direction on the third PCB board to the via connecting the third PCB board and the second PCB board. After passing through the via, the second trace 320 is laid in the first direction on the second PCB board to the via connecting the second PCB board and the first PCB board. After passing through the via, the second trace 320 is laid in the first direction on the first PCB board to the exit point of the circuit board structure for the second trace 320.

[0054] In this embodiment, the first trace 310 and the second trace 320 are connected in parallel via a via, allowing the magnetic field distribution and flux linkage experienced by the two traces within the core window to spatially interleave and compensate for each other. This effectively counteracts the self-inductance and impedance imbalance caused by the different AC impedances of the interlayer traces. Simultaneously, the via position is correlated with the core phase span gradient, optimizing interlayer electrical connectivity and magnetic field coupling uniformity. As a result, the equivalent impedance of the two parallel branches tends to be consistent, achieving uniform current distribution between layers. Furthermore, the reverse path characteristics of the twisted-pair structure cancel out parasitic circulating currents, effectively suppressing circulating currents and improving the overall performance of the magnetic component.

[0055] In one embodiment, the number of turns of the stranded trace is a first quantity, and the number of layers of the multilayer PCB board is a second quantity. The second quantity is an integer multiple of the first quantity, and greater than one. The stranded trace includes multiple traces. Since multiple traces need to achieve a stranded structure, each trace has the same number of turns. The number of turns is the number of times the trace wraps around the magnetic core; one turn of the trace around the magnetic core is one loop. The number of layers of the multilayer PCB board is the second quantity. In this embodiment, the second quantity is an integer multiple of the first quantity, that is, the number of layers of the PCB board is an integer multiple of the number of turns of the trace. This ensures that the arrangement of the stranded traces in the stacked structure has strict periodicity and symmetry. Each loop of trace is completely mapped to the corresponding PCB layer group, avoiding uneven distribution caused by a mismatch between the number of layers and the number of turns, preventing parallel branches from being squeezed into the same wiring interval, and obtaining a distribution result that meets the phase span gradient requirements. Here, the integer multiple is two times, three times, etc., and this embodiment does not make a specific limitation.

[0056] This embodiment uses the number of turns to represent the number of times the circuit has been wound and provides a periodic reference. Integer multiples define mathematical constraints and ensure the periodicity and symmetry of the arrangement. This ensures that each turn of the trace is uniformly and completely mapped to the corresponding PCB layer group, avoiding local magnetic field distortion or parasitic parameter mutations caused by the mismatch between the number of layers and the number of turns. This makes the equivalent flux linkage, self-inductance and AC impedance of each parallel branch highly consistent, eliminates impedance imbalance caused by radial position differences, and achieves uniform distribution of interlayer current.

[0057] In one embodiment, please refer to Figure 2 as well as Figure 3 There is a phase gradient in the area surrounded by magnetic lines of force around the magnetic core on each PCB layer.

[0058] The phase span for each via on each PCB layer is: Ø=2πN / L; where N is the first quantity, L is the second quantity, Ø is the phase span, and 2π is the phase span of a complete turn of the trace.

[0059] Specifically, taking a 4-layer PCB board and 2-turn traces as an example, the stranded traces include a first trace and a second trace. The phase span of the first trace on each PCB layer is: 2π × 2 / 4 = π. The circuit board structure is designed so that the starting position of the first trace's entry point is the position with a phase span of 0 on the first PCB layer. First, starting from the position with a phase span of 0 on the first PCB layer, the phase span gradient of the first PCB layer is searched along the first direction to determine the position with a phase span of π. A via is then created at this position, connecting the first and second PCB layers. The position of this via on the second PCB layer is the entry point of the first trace on the second PCB layer. Then, starting from the entry point on the second PCB layer with a phase span of 0, the phase span gradient of the second PCB layer is searched along the first direction to determine the position with a phase span of π. In the second-layer PCB, at a position with a phase span of π, a via is made connecting the second and third-layer PCBs. The position of this via on the third-layer PCB is the entry point of the first trace on the third-layer PCB. With the phase span of the entry point on the third-layer PCB as 0, the phase span gradient of the third-layer PCB is searched along the first direction to determine the position in the third-layer PCB with a phase span of π. At this position, a via is made connecting the third and fourth-layer PCBs. The position of this via on the fourth-layer PCB is the entry point of the first trace on the fourth-layer PCB.

[0060] The phase span of the second trace on each PCB layer is: 2π × 2 / 4 = π. The circuit board structure is designed so that the starting position of the second trace's entry point is the location with a phase span of 0 on the fourth PCB layer. First, starting from the location with a phase span of 0 on the fourth PCB layer, the phase span gradient of the fourth PCB layer is searched along the first direction to determine the location with a phase span of π. A via is then created at this location, connecting the fourth and third PCB layers. The position of this via on the third PCB layer is the entry point of the second trace on the third PCB layer. Starting from the entry point on the third PCB layer with a phase span of 0, the phase span gradient of the third PCB layer is searched along the first direction to determine the... In a three-layer PCB board, at a position with a phase span of π, a via is made connecting the third and second PCB boards. The position of this via on the second PCB board is the entry point of the second trace on the second PCB board. With the phase span of the entry point on the second PCB board as 0, the phase span gradient of the second PCB board is searched along the first direction to determine the position in the second PCB board with a phase span of π. At this position, a via is made connecting the second and first PCB boards. The position of this via on the first PCB board is the entry point of the second trace on the first PCB board.

[0061] This embodiment specifies the via locations for the traces and distributes the traces at equal angles across the PCB layers based on the number of coil turns and PCB layers. Simultaneously, the via locations avoid areas of abrupt magnetic field changes to force equalization of the equivalent impedance. Each parallel branch achieves spatial averaging across regions with varying radial magnetic field strengths, effectively offsetting localized self-inductance and impedance imbalances caused by differences in inner and outer layer positions. This ensures that each layer's branches bear equal current, achieving interlayer current sharing. Furthermore, it significantly reduces and balances the parasitic loop area, causing parasitic circulating currents between adjacent layers to cancel each other out, effectively suppressing circulating currents and improving the overall performance of the magnetic components.

[0062] In one embodiment, such as Figure 4 As shown, the magnetic core includes a central core post and two side core posts, namely a left core post and a right core post. That is, the magnetic core can be an E-shaped core. The second quantity is twice the first quantity, meaning the number of layers in a multilayer PCB is twice the number of turns of the stranded traces. The stranded traces include a first trace and a second trace. For example, when the stranded trace has 2 turns, the multilayer PCB has 4 layers; when the stranded trace has 4 turns, the multilayer PCB has 8 layers. Vias in each PCB layer are located in the area around the central core post that is not surrounded by magnetic lines of force; and the vias of adjacent PCB layers are on both sides of the central core post. Figure 2As shown, the E-shaped magnetic core's input terminal is located between the middle column and the left column of the core. The middle column and the left column are surrounded by magnetic field lines, with a phase span gradient of 0-π. The area above the middle column is not surrounded by magnetic field lines, and the phase span of this area is π. The middle column and the right column are surrounded by magnetic field lines, with a phase span gradient of π-2π. The area below the middle column is not surrounded by magnetic field lines, and the phase span of this area is 0 or 2π.

[0063] For the first trace 310, firstly, starting from the position where the phase span is 0 in the first PCB board, the phase span gradient of the first PCB board is searched along the first direction to determine the position where the phase span is π in the first PCB board, which is the upper region of the magnetic core pillar. Since the phase span in this region is all π, the via connecting the first and second PCB boards can be placed at any position in the upper region of the magnetic core pillar. The position of this via on the second PCB board is the entry position of the first trace 310 on the second PCB board. Starting from the entry position on the second PCB board with a phase span of 0, the phase span gradient of the second PCB board is searched along the first direction to determine the position where the phase span is π in the second PCB board, which is the lower region of the magnetic core pillar. Since the phase span in this region is all π, the via connecting the second and third PCB boards can be placed at any position in the lower region of the magnetic core pillar. The location of the via on the third PCB layer is the entry point of the first trace 310 on the third PCB layer. Using the phase span of the entry point on the third PCB layer as 0, the phase span gradient of the third PCB layer is searched along the first direction to determine the location of the phase span π on the third PCB layer, which is the upper region of the magnetic core pillar. Since the phase span in this region is all π, the via connecting the third and fourth PCB layers can be placed at any location in the upper region of the magnetic core pillar. The location of the via on the fourth PCB layer is the entry point of the first trace 310 on the fourth PCB layer.

[0064] For the second trace 320, firstly, starting from the position where the phase span is 0 on the fourth PCB board, the phase span gradient of the fourth PCB board is searched along the first direction to determine the position where the phase span is π on the fourth PCB board, which is the upper region of the magnetic core pillar. Since the phase span in this region is all π, the via connecting the fourth and third PCB boards can be placed at any position in the upper region of the magnetic core pillar. The position of this via on the third PCB board is the entry position of the second trace 320 on the third PCB board. Then, starting from the entry position on the third PCB board with a phase span of 0, the phase span gradient of the third PCB board is searched along the first direction to determine the position where the phase span is π on the third PCB board, which is the lower region of the magnetic core pillar. Since the phase span in this region is all π, the via connecting the third and second PCB boards can be placed at any position in the lower region of the magnetic core pillar. The location of the via on the second PCB layer is the entry point of the second trace 320 on the second PCB layer. Using the phase span of the entry point on the second PCB layer as 0, the phase span gradient of the second PCB layer is searched along the first direction to determine the location of the phase span π on the second PCB layer, which is the upper region of the magnetic core pillar. Since the phase span in this region is all π, the via connecting the second and first PCB layers can be placed at any location in the upper region of the magnetic core pillar. The location of the via on the first PCB layer is the entry point of the second trace 320 on the first PCB layer.

[0065] Based on the above, for the first trace 310, the vias connecting the first and second PCB boards are located in the upper region of the magnetic core pillar, the vias connecting the second and third PCB boards are located in the lower region of the magnetic core pillar, and the vias connecting the third and fourth PCB boards are located in the upper region of the magnetic core pillar. For the second trace 320, the vias connecting the fourth and third PCB boards can be located in the upper region of the magnetic core pillar, the vias connecting the third and second PCB boards can be located in the lower region of the magnetic core pillar, and the vias connecting the second and first PCB boards can be located in the upper region of the magnetic core pillar.

[0066] In this embodiment, vias are precisely positioned near the magnetic core in areas not surrounded by magnetic field lines to avoid cutting into the main magnetic circuit, thus effectively reducing local impedance disturbances. Simultaneously, vias on adjacent PCB layers are alternately arranged on both sides of the magnetic core, forming a strict geometric symmetry and spatially staggered topology. This allows the spatial positions of parallel branches in the magnetic field to compensate for each other, effectively homogenizing the equivalent magnetic flux experienced by the traces on each layer. This fundamentally eliminates impedance imbalance caused by longitudinal differences between inner and outer layers, achieving uniform current distribution between layers. The longitudinal difference is also the difference in the Z-direction. The alternating distribution of vias on both sides of adjacent layers causes interlayer parasitic circulating currents to cancel each other out, achieving interlayer current equalization and circulating current suppression.

[0067] In one embodiment, the vias of each PCB layer are located in the area around the magnetic core pillar that is not surrounded by magnetic lines of force, except for the center position.

[0068] The vias connecting the first and second PCB layers are located on the upper side of the magnetic core pillar, with their center position being the center of the upper side of the magnetic core pillar area. Figure 4 As shown, the via can be placed at the geometric midpoint in the X direction, offset to the left or to the right by a preset distance. The preset distance can be set based on actual usage requirements.

[0069] The vias connecting the second and third PCB layers are located in the area below the core pillar, with their center position being the center of the area below the core pillar. Figure 4 As shown, the via can be placed at the geometric midpoint in the X direction, offset to the left or to the right by a preset distance. The preset distance can be set based on actual usage requirements.

[0070] The vias connecting the third and fourth PCB layers are located on the upper side of the magnetic core pillar, with their center position being the center of the upper side of the magnetic core pillar area. Figure 4 As shown, the via can be placed at the geometric midpoint in the X direction, offset to the left or to the right by a preset distance. The preset distance can be set based on actual usage requirements.

[0071] By further defining the via positions, this embodiment can make the equivalent impedances of the first trace 310 and the second trace 320 more consistent, thereby achieving uniform distribution of interlayer current.

[0072] In one embodiment, in each PCB layer, the area corresponding to the first trace 310 and the area corresponding to the second trace 320 do not overlap and are staggered. For example... Figure 4As shown, in the first PCB layer, the first trace 310 wraps around the left half of the magnetic core pillar, and the second trace 320 wraps around the right half of the magnetic core pillar, and they do not overlap; in the second PCB layer, the first trace 310 wraps around the right half of the magnetic core pillar, and the second trace 320 wraps around the left half of the magnetic core pillar, and they do not overlap; in the third PCB layer, the first trace 310 wraps around the left half of the magnetic core pillar, and the second trace 320 wraps around the right half of the magnetic core pillar, and they do not overlap; in the fourth PCB layer, the first trace 310 wraps around the right half of the magnetic core pillar, and the second trace 320 wraps around the left half of the magnetic core pillar, and they do not overlap.

[0073] In this embodiment, the first trace 310 and the second trace 320 are staggered in each PCB layer to achieve interlayer current uniformity and effectively suppress circulating current.

[0074] In one specific embodiment, taking an inductor as the magnetic element and an E-shaped magnetic core as an example, two turns of stranded traces are arranged on a four-layer PCB board, with each turn of stranded trace consisting of two PCB boards on average. The magnetic field lines of the E-shaped magnetic core are parallel to the XZ plane, because the traces in the Y direction are surrounded by magnetic field lines, i.e., surrounded by a magnetic circuit. The magnetic field strength within the core window varies significantly along the Z-axis, resulting in a large difference in AC impedance between the traces in the Y direction. In this case, if the traces of the first and second PCB boards are connected in parallel to form the first turn, and the traces of the third and fourth PCB boards are connected in parallel to form the second turn, then a large amount of commutation will occur between the first and second PCB boards, as well as between the third and fourth PCB boards.

[0075] like Figure 5 As shown, this embodiment adopts Figure 5 The wiring diagram shown depicts a first trace 310 (blue solid line in the Y direction) and a second trace 320 (red dashed line in the Y direction). The first and second traces 310 and 320 are staggered on both sides of the magnetic core pillar. The first and second traces 310 and 320 in the X direction are not surrounded by magnetic field lines, resulting in minimal difference in interlayer magnetic field strength. Therefore, vias between the first and second PCB layers, between the second and third PCB layers, and between the third and fourth PCB layers can move arbitrarily along the X-axis. Figure 4 As shown, since the interlayer temperatures cannot be completely uniform, the impedance between traces in the Z direction may differ. To further improve current sharing, the midpoint position in the X direction can be determined first, and the vias can be set at the midpoint offset to the left or right by a preset distance. Simultaneously, to reduce the difficulty of PCB manufacturing, all vias can be made into through-holes. Typically, the copper plating on the walls of through-holes is 1 oz. To improve the current carrying capacity of the vias, copper can be filled into them.

[0076] In this embodiment, the via location is specifically determined by the following formula: Ø = 2πN / L; where N is the number of turns of the stranded trace, L is the number of layers in the multilayer PCB board, and Ø is the phase span. The phase span is the phase span from the current PCB layer's entry point to the via, and 2π is the phase span of a complete turn of the trace. Figure 2 As shown, in this PCB layer, the input terminal is located between the middle column and the left column of the magnetic core. Starting from the input terminal, the area between the middle column and the left column is surrounded by magnetic field lines. Therefore, there is a phase span gradient in the region between the middle column and the left column, with the gradient magnitude starting from 0 at the input terminal and ranging from 0 to π. The area above the middle column is not surrounded by magnetic field lines, so there is no phase span gradient in the area above the middle column, and the phase span in this area is π. The area between the middle column and the right column is surrounded by magnetic field lines, so there is a phase span gradient between the middle column and the right column, with the gradient magnitude starting from π and ranging from π to 2π. The area below the middle column is not surrounded by magnetic field lines, so there is no phase span gradient in the area below the middle column, and the phase span in this area is 0 or 2π.

[0077] like Figure 4 As shown, when N=2 and L=4, Ø=π, therefore the vias on the corresponding PCB layer can be placed at any position within the Ø=π or Ø=2π region. For example... Figure 6 As shown, when N=3 and L=4, Ø=1.5π. In this case, vias must be placed between the middle and left pillars of the core, and between the middle and right pillars of the core. This results in parallel branches being squeezed into the same wiring interval across all layers, increasing the current density. For example... Figure 7 As shown, for a 3-turn stranded trace, it should be arranged on a 6-layer PCB board. That is, for an E-shaped magnetic core, the number of layers on the PCB board should be twice the number of stranded traces to achieve better results.

[0078] The above explanation uses an E-shaped magnetic core as an example. It's understandable that, based on the E-shaped core, the central cylinder of the core is circular. In this case, the magnetic field lines are still parallel to the XZ plane, and the phase gradient remains as shown. Figure 2 As shown.

[0079] In one embodiment, such as Figure 8As shown, an inductor structure is provided, wherein the inductor structure includes a circuit board structure of two magnetic elements. The circuit board structure of the magnetic elements is the structure described in the above embodiment. The circuit board structure of the magnetic elements includes a magnetic core, two PCB layers, and a stranded trace, the stranded trace including a first trace and a second trace; the magnetic core includes a central core post and two side core posts; the two side core posts include a left core post and a right core post. That is, the magnetic core can be an E-shaped magnetic core. Since both circuit board structures of the two magnetic elements use E-shaped magnetic cores, the same E-shaped magnetic core can be used for both magnetic elements, thereby reducing the size and loss of the magnetic core. In actual use, the excitation voltages on the common-mode paths of the two magnetic element circuit board structures are equal in magnitude and opposite in direction, thus canceling out their respective common-mode excitations.

[0080] Since the circuit board structures of the two magnetic components are identical, differing only in the direction of current, the following embodiments will be described using the circuit board structure of any one magnetic component as an example.

[0081] The stranded traces in the circuit board structure of the magnetic component include a first trace 310 and a second trace 320, such as... Figure 9 As shown, yellow represents the first trace 310; red represents the second trace 320. The first trace 310 consists of a first long trace 311, a first short trace 312, a first via trace 313, and a first transition trace 314; the second trace 320 consists of a second long trace 321, a second short trace 322, a second via trace 323, and a second transition trace 324.

[0082] For the first trace 310, starting from the entry point of the circuit board structure for the first trace 310, on the first PCB board, a first long trace 311 is laid to the vias of the first PCB board and the second PCB board, and a first via trace 313 passes through the via. On the second PCB board, a first transition trace 314 and a first short trace 312 are laid to the exit point of the circuit board structure for the first trace 310.

[0083] For the second trace 320, starting from the entry point of the second trace 320 in the circuit board structure, on the second PCB board, a second short trace 322 is laid to the vias of the first PCB board and the second PCB board. A second via trace 323 passes through the via. On the first PCB board, a second transition trace 324 and a second long trace 321 are laid to the location of the second trace 320 in the circuit board structure.

[0084] Based on the above, the first long trace 311, the second long trace 321, and the second transition trace 324 are disposed on the first layer of the PCB board. The first short trace 312, the first transition trace 314, and the second short trace 322 are disposed on the second layer of the PCB board.

[0085] In this embodiment, the first trace 310 and the second trace 320 are staggered across two PCB layers, forming a spatially symmetrical path. This further ensures that the magnetic field environments of the first trace 310 and the second trace 320 are consistent, guaranteeing uniform equivalent impedance and thus achieving overall current sharing. The first trace 310 and the second trace 320 are positioned in a symmetrical magnetic circuit, ensuring that the AC impedance of each trace is the same, effectively suppressing circulating current.

[0086] In one embodiment, the first long trace 311 and the second long trace 321 have the same dimensions; that is, the length of the first long trace 311 in the Y direction and the width in the X direction are the same as the length of the second long trace 321 in the Y direction and the width in the X direction. The first short trace 312 and the second short trace 322 have the same dimensions; that is, the length of the first short trace 312 in the Y direction and the width in the X direction are the same as the length of the second short trace 322 in the Y direction and the width in the X direction. The first transition line 314 and the second transition line 324 have the same dimensions; that is, the length of the first transition line 314 in the Y direction and the width in the X direction are the same as the length of the second transition line 324 in the Y direction and the width in the X direction. The first via trace 313 and the second via trace 323 have the same dimensions. That is, the length of the first via trace 313 in the Y direction, the width in the X direction, and the height in the Z direction are the same as the length of the second via trace 323 in the Y direction, the width in the X direction, and the height in the Z direction.

[0087] In this embodiment, all parts of the first trace 310 and the second trace 320 are identical, thereby making the resistance, distributed inductance and parasitic capacitance parameters of the first trace 310 and the second trace 320 highly consistent, further improving the current sharing characteristics and better suppressing circulating current.

[0088] In one embodiment, the centerlines of the first transition line 314 and the second transition line 324 coincide with the centerline of the region surrounding the magnetic core pillar that is not surrounded by magnetic field lines. Specifically, the centerline of the first transition line 314 is a straight line parallel to the Y direction passing through the midpoint of its X-direction width; the centerline of the second transition line 324 is a straight line parallel to the Y direction passing through the midpoint of its X-direction width. The centerline of the region surrounding the magnetic core pillar that is not surrounded by magnetic field lines is a straight line parallel to the Y direction passing through the midpoint of the magnetic core pillar's X-direction width. The centerlines of the first transition line 314, the second transition line 324, and the region surrounding the magnetic core pillar that is not surrounded by magnetic field lines coincide, meaning their projections in the Z-direction coincide.

[0089] This embodiment uses the centerline as a geometric alignment reference parameter to eliminate the magnetic flux difference in the X direction between the first transition line 314 and the second transition line 324, thereby improving the current sharing performance, thermal stability and overall efficiency of the magnetic components.

[0090] In one specific embodiment, a resonant inductor with an E-shaped magnetic core is used as an example for illustration. In phase-shifted full-bridge and LLC converters, the resonant inductor is used to facilitate soft switching. To avoid increasing common-mode noise, a single resonant inductor is typically split into two sub-inductors with the same inductance value, each connected to one of the two primary leads of the transformer, such as... Figure 10 As shown. During operation, the excitation voltages of the two sub-inductors L1 and L2 on the common-mode path are equal in magnitude and opposite in direction, thus canceling out their respective common-mode excitations. The two sub-inductors of the resonant inductor are also the circuit board structure of the two magnetic elements of the inductor structure. Integrating the two sub-inductors into the same magnetic core can reduce the size and loss of the magnetic core. Figure 11 as well as Figure 12 As shown, sub-inductor L1 is composed of coil 1, and sub-inductor L2 is composed of coil 2. The differential mode current of the two coils is excited in the same direction, and the common mode current is excited in opposite directions, which can prevent the magnetic core from overheating under the excitation of the common mode current.

[0091] More specifically, the resonant inductor has a peak current of 28A, a frequency of 100kHz, and an inductance of 3μH. That is, each sub-inductor has a capacity of 1.5μH. Two PEI43 ferrite cores are connected in parallel, with each sub-inductor having one turn. The air gap between the three magnetic pillars of the E-shaped core is 0.4mm. The resonant inductor is fabricated using a 4-layer PCB, with each layer having a copper thickness of 3oz. Each sub-inductor uses 2 layers of PCB for wiring, as shown below. Figure 8 As shown, the two sub-inductors are located on both sides of the magnetic core. Therefore, the vias for the two sub-inductors can be arranged on both sides of the magnetic core in the Y direction, and the traces do not need to avoid each other. Furthermore, the vias on the same side are basically at the same potential, so there is no need to consider safety distances; functional insulation is sufficient.

[0092] To verify the effectiveness of the aforementioned resonant inductor, a structure was constructed as follows: Figure 13 , Figure 14 as well as Figure 15 The 3D finite element simulation model is shown. Blue and green traces constitute the first sub-inductor, while yellow and red traces constitute the second sub-inductor. The twisted traces of the two sub-inductors are mirror-symmetrically connected vias and zigzag patterns. The copper plug vias have dimensions of 1.0mm in length, 4.0mm in width, and 1.3mm in height, where 1.3mm represents the PCB thickness. Within the height constraints, a significant portion of the core window height is retained to prevent magnetic flux dissipation through the air gap via eddy currents in the windings. The copper plating of the first sub-inductor is narrower than that of the second sub-inductor to further minimize magnetic flux dissipation in the air gap. The simulation model is established as follows... Figure 16 The external current source excitation circuit shown yields the following result: Figure 17 as well as Figure 18 The waveform shown Figure 17 The four waveforms in blue, green, yellow, and red represent the current of the four traces, respectively. Figure 18 The four waveforms in blue, green, yellow, and red represent the losses of the four traces, respectively. Based on this waveform, the current in each parallel branch of the resonant inductor is almost completely evenly distributed, and the losses are also uniformly distributed, totaling 2.6W.

[0093] For ease of comparison, a simulation was performed on the resonant inductor constructed using the direct parallel connection of interlayer copper in PCBs in related technologies, and the results are as follows: Figure 19 as well as Figure 20 waveform, Figure 19 The four waveforms in blue, green, yellow, and red represent the current of the four traces, respectively. Figure 20 The four waveforms—blue, green, yellow, and red—represent the losses of the four traces, respectively. Based on these waveforms, the current and losses in the parallel branch of the resonant inductor are uneven, which can easily lead to excessive local temperature rise.

[0094] This embodiment is based on the complete theory of PCB trace twisted parallel connection, enabling traces between different layers of the PCB to be twisted parallel through vias. This effectively suppresses circulating current between parallel branches, reduces winding losses, and thus achieves interlayer current sharing, not limited to winding and magnetic circuit structures. Twisting is achieved using a small number of copper-filled vias, eliminating the need for numerous buried or blind vias, reducing via losses and lowering the PCB manufacturing difficulty.

[0095] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A circuit board structure for a magnetic element, characterized in that, The circuit board structure includes a multi-layer PCB board, a magnetic core, and stranded traces. The PCB boards are stacked in multiple layers, and magnetic cores are provided at corresponding positions on the multiple PCB boards. The stranded trace includes multiple traces; each trace has a corresponding via on each layer of the PCB board; each trace, in a preset order of the multiple PCB boards, winds around the magnetic core in a preset direction, extending from the first layer of the PCB board through the corresponding via to the last layer of the PCB board; the multiple traces are stranded on the multiple PCB boards. The position of the via corresponding to each of the aforementioned traces on the PCB board is related to the phase span gradient of the magnetic core.

2. The circuit board structure according to claim 1, characterized in that, The number of turns of the stranded trace is the first quantity, and the number of layers of the multilayer PCB board is the second quantity; The second quantity is an integer multiple of the first quantity, and is greater than one.

3. The circuit board structure according to claim 2, characterized in that, There is a phase span gradient in the region surrounded by magnetic lines of force around the magnetic core on each layer of the PCB board. The phase span of the via for each trace on each layer of the PCB is: Ø=2πN / L; Where N is the first quantity, L is the second quantity, and Ø is the phase span.

4. The circuit board structure according to claim 3, characterized in that, The magnetic core includes a central core post and two side core posts; the second quantity is twice the first quantity; the stranded wiring includes two wirings; The vias in each layer of the PCB are located in the area around the magnetic core pillar that is not surrounded by magnetic lines of force; and the vias in two adjacent layers of the PCB are located on both sides of the magnetic core pillar.

5. The circuit board structure according to claim 4, characterized in that, The vias of each layer of the PCB are located in the area around the magnetic core pillar that is not surrounded by magnetic lines of force, except for the center position.

6. The circuit board structure according to claim 4, characterized in that, The stranded wiring includes a first wiring and a second wiring; In each layer of the PCB board, the area corresponding to the first trace does not overlap with the area corresponding to the second trace, and they are staggered.

7. An inductor structure, characterized in that, The inductor structure includes two circuit board structures of the magnetic elements described in claims 1-6; the circuit board structure includes a magnetic core, two PCB boards and a stranded trace; the stranded trace includes a first trace and a second trace; the magnetic core includes a core center post and two core side posts.

8. The inductor structure according to claim 7, characterized in that, The first trace consists of a first long trace, a first short trace, a first via trace, and a first transition trace. The second trace consists of a second long trace, a second short trace, a second via trace, and a second transition trace. The first long trace, the second long trace, and the second transition trace are disposed on the first layer of the PCB board; The first short trace, the first transition trace, and the second short trace are disposed on the second layer of the PCB board.

9. The inductor structure according to claim 8, characterized in that, The first long trace and the second long trace have the same dimensions; The first short trace and the second short trace have the same dimensions; The first transition line and the second transition line have the same dimensions; The first via trace has the same dimensions as the second via trace.

10. The inductor structure according to claim 9, characterized in that, The centerlines of the first transition line and the second transition line coincide with the centerline of the region around the magnetic core pillar that is not surrounded by magnetic field lines.

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