Dual redundant thermal protection system

Abstract

The application provides a double-redundancy thermal protection system, comprising: an ultrasonic chip; the ultrasonic chip comprises an ultrasonic transceiving array, a digital control module, an on-chip temperature sensor and an over-temperature protection unit; the ultrasonic transceiving array comprises a plurality of ultrasonic transceiving elements, and is used for driving a transducer array element to emit ultrasonic waves and receive echo signals; the on-chip temperature sensor is used for outputting a temperature signal associated with a real-time temperature of the chip; the over-temperature protection unit is used for acquiring a threshold signal associated with a temperature threshold, continuously comparing the temperature signal with the threshold signal, and outputting a first over-temperature signal when the temperature signal is greater than the threshold signal; and the digital control module is used for controlling the ultrasonic transceiving array to perform a cooling work according to the first over-temperature signal. The application can realize over-temperature protection of an ultrasonic probe, thereby avoiding the risk of burning human tissues.

Description

Technical Field

[0001] This invention relates to ultrasonic chips, and more specifically, to a dual-redundancy thermal protection system. Background Technology

[0002] Complementary Metal Oxide Semiconductor (CMOS) technology, as a core technology in the semiconductor field, is widely used in integrated circuit manufacturing and many other areas. It can integrate a large number of transistors onto a small chip, continuously developing in accordance with Moore's Law, and driving the evolution of semiconductors towards miniaturization and high performance.

[0003] The working principle of an ultrasonic transducer is based on the direct and inverse piezoelectric effects of piezoelectric materials. It achieves efficient transmission and reception of ultrasonic signals through the periodic vibration of the piezoelectric layer. When the ultrasonic transducer acts as a transmitter, it essentially converts electrical signals into mechanical vibration energy. Under the action of a driving voltage, the piezoelectric layer deforms due to the inverse piezoelectric effect, radiating ultrasonic waves into the medium. When acting as a receiver, it becomes a sensor that captures mechanical vibration energy. External ultrasonic waves cause the piezoelectric layer to vibrate, converting the acoustic signal into an electrical signal through the direct piezoelectric effect for subsequent processing.

[0004] In ultrasound chips, the CMOS integrated circuit at the transmitting end precisely controls the excitation signal of the ultrasound transducer. For example, it can generate electrical pulse signals with specific frequencies, pulse widths, and amplitudes to drive the ultrasound transducer to emit ultrasonic waves. In some medical ultrasound diagnostic devices, the CMOS integrated circuit optimizes the emitted waveform, improving the emission efficiency and directivity of the ultrasound waves, thereby enhancing the resolution and clarity of the imaging. At the receiving end, the CMOS integrated circuit is responsible for receiving the echo signals received by the ultrasound transducer and performing preprocessing such as pre-amplification and filtering. CMOS integrated circuits can integrate high-performance, low-noise amplifiers to reduce noise interference in the received signal, while simultaneously processing echo signals of different frequencies and amplitudes quickly and accurately, providing high-quality data for subsequent signal processing and image reconstruction.

[0005] Ultrasonic probes come into direct contact with human tissue during operation, and the chip circuitry and transducer generate heat. If this heat accumulates and causes the probe surface temperature to become excessively high, there is a risk of burning human tissue; therefore, an effective thermal protection mechanism is essential. Currently, most common temperature protection schemes rely on a single temperature sensor combined with a control circuit. When the sensor detects a temperature exceeding a preset threshold, the system cuts off the power or stops energy output. Temperature sensors based on resistance thermometers (RTDs) cannot be integrated into the chip, thus they are not close enough to the probe chip and cannot accurately measure its temperature. System-level thermal protection has a long activation time, and if the system malfunctions, the entire thermal protection system faces the serious safety hazard of losing its protective function.

[0006] With advancements in chip manufacturing processes and increasing power density, the accuracy, reliability, and interference immunity of over-temperature protection have become paramount. In practical applications, thermal protection signals are susceptible to power supply noise or signal crosstalk. If directly used as the trigger condition for system reset, it may lead to unnecessary system restarts, affecting stable operation. Therefore, effectively suppressing false triggering by interference signals while accurately identifying actual over-temperature conditions has become a crucial issue in chip design. Summary of the Invention

[0007] In view of the problems in the prior art, the purpose of this invention is to provide a dual-redundancy thermal protection system.

[0008] The dual-redundancy thermal protection system for an ultrasonic probe chip provided by the present invention comprises: an ultrasonic chip; the ultrasonic chip includes an ultrasonic transceiver array, a digital control module, an on-chip temperature sensor, and an over-temperature protection unit. The ultrasonic transceiver array includes multiple ultrasonic transceiver elements, used to drive the transducer elements to emit ultrasonic waves and receive echo signals. The on-chip temperature sensor is used to output a temperature signal that is correlated with the real-time temperature of the chip. The over-temperature protection unit is used to acquire a threshold signal associated with a temperature threshold, continuously compare the temperature signal with the threshold signal, and output a first over-temperature signal when the temperature signal is greater than the threshold signal. The digital control module is used to control the ultrasonic transceiver array to perform cooling operations based on the first over-temperature signal.

[0009] Preferably, it also includes a host system; The host system is electrically connected to the on-chip temperature sensor and the digital control module, and is used to acquire the temperature signal in real time, continuously compare the temperature signal with the threshold signal, and output the second over-temperature signal when the temperature signal is greater than the threshold signal. The digital control module is used to receive the second over-temperature signal and control the ultrasonic transceiver array to perform cooling operation according to the second over-temperature signal.

[0010] Preferably, the digital control module controls the ultrasonic transceiver array to perform cooling operations based on the first over-temperature signal or the second over-temperature signal, including: Set the on-chip temperature sensor to normally open and turn off the over-temperature protection unit; The over-temperature protection unit is activated, enabling it to continuously detect over-temperature conditions. When the first over-temperature signal is detected or the second over-temperature signal is received, the ultrasonic chip is controlled to reset, and the over-temperature protection unit automatically shuts down after reset.

[0011] Preferably, the threshold signal is pre-stored in a storage unit on the ultrasound chip, or sent to the ultrasound chip via the host system.

[0012] Preferably, the on-chip temperature sensor includes a first PTAT current generation unit, a CTAT current generation unit, a resistor network, and a weighted linearization unit; The first PTAT current generation unit is used to generate a first positive temperature coefficient current; The CTAT current generation unit is used to generate negative temperature coefficient current; The resistor network is used to generate a positive temperature coefficient voltage based on the first positive temperature coefficient current and to generate a negative temperature coefficient voltage based on the negative temperature coefficient current. The weighted linearization unit is used to generate a temperature signal that is linearly related to temperature by weighting and summing the positive temperature coefficient voltage and the negative temperature coefficient voltage to cancel out their respective nonlinearities.

[0013] Preferably, the on-chip temperature sensor includes: The first current mirror unit includes transistor PM1, transistor PM2 and transistor PM3, wherein the sources of transistors PM1, PM2 and PM3 are all connected to the power supply terminal and their gates are connected to each other. Operational amplifier A2 has its non-inverting input connected to one end of resistor R2 and the drain of transistor PM1, its inverting input connected to the drain of transistor PM2, and its output connected to the gate of each transistor in the first current mirror unit. The other end of resistor R2 is grounded. The first bipolar transistor pair includes transistor Q1 and transistor Q2. The base and collector of transistor Q1 are grounded, and the emitter is connected to the drain of transistor PM2. The base and collector of transistor Q2 are grounded, and the emitter is connected to one end of resistor R1. Operational amplifier A1 has its non-inverting input connected to one end of resistor R3, its inverting input connected to the drain of transistor PM3 and the other end of resistor R1, and its output connected to the Vout port. The resistor network includes resistors R3 and R4. One end of resistor R3 is connected to the drain of transistor PM2, and the other end is connected to the Vout port. One end of resistor R4 is connected to the inverting input of operational amplifier A1, and the other end is connected to the output Vout port.

[0014] Preferably, the on-chip temperature sensor includes: The first current mirror unit includes transistors PM1, PM2, PM3, and PM4. The sources of transistors PM1, PM2, PM3, and PM4 are all connected to the power supply terminal, and their gates are connected to each other. Operational amplifier A2 has its non-inverting input connected to one end of resistor R2 and the drain of transistor PM1, its inverting input connected to the drain of transistor PM2, and its output connected to the gate of each transistor in the first current mirror unit. The other end of resistor R2 is grounded. The first bipolar transistor pair includes transistor Q1 and transistor Q2. The base and collector of transistor Q1 are grounded, and the emitter is connected to the drain of transistor PM2. The base and collector of transistor Q2 are grounded, and the emitter is connected to one end of resistor R1. Operational amplifier A1 has its non-inverting input connected to one end of resistor R3, and its inverting input connected to the drain of transistor PM3 and the other end of resistor R1. A resistor network, including resistors R3, R4, and R... trim_os and resistance R trim_slope One end of resistor R3 is connected to the drain of transistor PM2, and the other end is connected to resistor R. trim_slope One end of the resistor R4 is connected to the inverting input of the operational amplifier A1, and the other end is connected to the resistor R. trim_slope One end of the resistor R trim_slope The other end and the output terminal of the operational amplifier A1 are connected to the resistor R. trim_os One end; The second current mirror unit includes a transistor PM5 and a second PTAT current generation unit. The second PTAT current generation unit is used to generate a second positive temperature coefficient current. The transistor PM5 is used to replicate the second positive temperature coefficient current. The source of the transistor PM5 is connected to the power supply terminal, and the drains of the transistor PM5 and the transistor PM4 are connected to the resistor R. trim_os At the other end, and the resistor R trim_os The other end is connected to the Vout port.

[0015] Preferably, the operational amplifier A2 is used to control the first current mirror unit through negative feedback, so that the drain voltages of transistor PM1 and transistor PM2 are equal, thereby replicating the negative temperature coefficient current I. CTAT ; The first bipolar transistor pair is used to apply the generated emitter-junction voltage difference across the resistor R1 to form a first positive temperature coefficient current IPTAT; The operational amplifier A1 is used to superimpose the negative temperature coefficient current and the first positive temperature coefficient current through negative feedback, and output a temperature signal that is linearly related to the temperature. The temperature signal is output through the Vout port.

[0016] Preferably, the over-temperature protection unit includes transistor PM6, transistor PM7, transistor NM1, transistor NM2, resistor R5, digital-to-analog converter, and comparator; The transistor PM6 is used to replicate negative temperature coefficient current; The transistor PM7 is used to replicate the second positive temperature coefficient current; the sources of the transistors PM6 and PM7 are connected to the power supply terminal, and their drains are connected to the drain of the transistor NM1. The gates of transistors NM1 and NM2 are connected to form a third current mirror unit, and the sources of transistors NM1 and NM2 are grounded; the gate of transistor NM1 is connected to its drain. One output port of the digital-to-analog converter is connected to one end of resistor R5 and the inverting input of the comparator to set the over-temperature protection threshold. The other output port is connected to the drain of transistor NM2 to set the output current ratio of the third current mirror unit. The other end of resistor R5 is grounded. The Vout port is connected to the non-inverting input of the comparator, and the output of the comparator is used to output the first over-temperature signal.

[0017] Preferably, the second PTAT current generating unit includes: The second PTAT current generation unit includes: The fourth current mirror unit includes transistor PM8 and transistor PM9. The sources of transistors PM8, PM9 and PM5 are all connected to the power supply terminal, and their gates are connected to each other. Operational amplifier A5 has its inverting input connected to one end of resistor R6 and the drain of transistor PM9, its non-inverting input connected to the drain of transistor PM8, and its output connected to the gates of transistors PM8 and PM9. The second bipolar transistor pair includes transistor Q3 and transistor Q4. The base and collector of transistor Q3 are grounded, and the emitter is connected to the drain of transistor PM8. The base and collector of transistor Q4 are grounded, and the emitter is connected to the other end of resistor R6.

[0018] Compared with the prior art, the present invention has the following beneficial effects: This invention establishes a dual redundancy system by integrating an on-chip temperature sensor and an over-temperature protection unit into the chip as primary protection, and a secondary protection system that reads the temperature electrical signal from the host system. The on-chip protection can independently monitor the comparison between the temperature electrical signal and the threshold electrical signal, and directly trigger the ultrasound transceiver array to stop working after the temperature exceeds the limit, without relying on an external system. The host system synchronously acquires the temperature electrical signal and makes a secondary judgment, forming a redundancy check. This solves the problems of delayed response and single-point failure of traditional single-system protection, ensuring that when ultrasound probes (such as interventional cardiac probes and wearable patch probes) are in direct contact with human tissue, even if any protection link is abnormal, the risk of burns caused by excessive temperature can still be avoided through the other link. This invention's temperature sensor achieves linear temperature and voltage response by weighted summation of positive and negative temperature coefficient currents. It is equipped with a dual fine-tuning structure, with an offset fine-tuning resistor compensating for chip offset errors, making the temperature sensing voltage offset close to 0V. The slope fine-tuning resistor compensates for the current weighting ratio deviation, ensuring stable temperature and voltage slopes. This solves the problems of traditional RTD sensors being unable to be integrated and having large temperature measurement deviations, ensuring accurate triggering of over-temperature protection thresholds and avoiding false or missed protection due to inaccurate temperature measurement. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort. Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram illustrating the application scenario of the ultrasound chip in intracardiac ultrasound imaging in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the ultrasonic probe in an embodiment of the present invention; Figure 3 This is a schematic diagram of the ultrasonic chip in a wearable ultrasound application scenario according to an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the application scenario of the ultrasound chip in a brain-computer interface according to an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the application scenario of the ultrasound chip in a neuromodulation system according to an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the working principle of the ultrasonic chip in an embodiment of the present invention; Figure 7 This is a schematic diagram of a dual-redundancy thermal protection system for an ultrasonic probe chip in an embodiment of the present invention; Figure 8 This is a circuit diagram of the temperature sensor in an embodiment of the present invention; Figure 9 This is a circuit diagram of the temperature sensor in a modified embodiment of the present invention; Figure 10 This is a circuit diagram of the over-temperature protection unit in an embodiment of the present invention; Figure 11 This is a circuit diagram of the second PTAT current generation unit in an embodiment of the present invention; Figure 12 This is a working logic diagram of the digital control module in an embodiment of the present invention; Figure 13 This is a logic diagram of temperature coefficient weighting in an embodiment of the present invention; and Figure 14 This is a logic diagram for fine-tuning the temperature sensing output voltage in an embodiment of the present invention. Detailed Implementation

[0020] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0021] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0023] The technical solutions of the present invention and how they solve the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0024] Figure 1 This is a schematic diagram illustrating the application scenario of the ultrasound chip in intracardiac ultrasound imaging according to an embodiment of the present invention, such as... Figure 1 As shown, during intracardiac ultrasound, a transceiver probe 100 is placed inside the heart via a blood vessel to perform real-time, high-quality imaging or hemodynamic measurements of the heart and adjacent tissues. It is primarily used in interventional cardiac procedures such as atrial fibrillation radiofrequency ablation, mitral valve repair, left atrial appendage closure, and closure of atrial septal defects and patent foramen ovale. It enables real-time monitoring of catheter position and surgical outcomes, assessment of cardiac structure and function, guidance of surgical procedures, and reduction of surgical risks. The probe 100 has a diameter of approximately 3-10F (1-3.3 mm) and is integrated into the tip of the interventional catheter 200, inserted into the heart chamber via a vascular pathway (such as the femoral vein). The probe 100 typically operates at a frequency of 5-20 MHz, offering extremely high resolution, but with limited penetration depth, covering only local structures within the heart chambers. Given that the heart rate is approximately 60-100 beats per minute and the valve opening and closing cycle is only a few hundred milliseconds, a high imaging frame rate, such as a real-time three-dimensional imaging rate of 50 volumes / s, is required.

[0025] Figure 2 This is a schematic diagram of the ultrasonic probe in an embodiment of the present invention, as shown below. Figure 2 As shown, the ultrasound probe 100 adopts a cylindrical package, balancing structural strength and clinical operational flexibility. The probe shell provides sealed protection for the core components, isolating them from interference from body fluids and the external environment, while its smooth, curved surface design adapts to the grip requirements in clinical settings, facilitating rapid cleaning and disinfection. The ultrasound chip 101 integrates a high-density transducer array, enabling precise transmission and echo reception of high-frequency ultrasound signals. Its compact array layout effectively improves the lateral resolution of the image, providing hardware support for imaging fine tissue structures such as blood vessel walls and digestive tract mucosa. The chip is electrically connected to the underlying PCB circuit board 102 via flip-chip bonding, ensuring low signal transmission loss and high response speed. The weak echo signals acquired by the ultrasound chip can be transmitted to peripheral devices via flexible cables.

[0026] Figure 3 This is a schematic diagram of the ultrasonic chip in a wearable ultrasound application scenario according to an embodiment of the present invention, such as... Figure 3As shown, when the ultrasound chip in this embodiment of the invention is applied to wearable scenarios, the battery-powered ultrasound imaging patch can achieve long-term, non-invasive, and real-time health monitoring. For example, when the ultrasound imaging patch 300 is attached to the chest, the PMUT transducer array continuously monitors the structure and function of the heart. Combined with long-term battery power, it provides continuous home monitoring for patients with hypertension and heart failure, replacing the traditional "regular ultrasound visits to the hospital" model and assisting doctors in adjusting treatment plans in a timely manner. When attached to the abdomen, it monitors liver fatty infiltration (judged through ultrasound echo characteristics) and acoustic changes in the pancreas, helping patients with diabetes and fatty liver track disease progression. Combined with the signal processing capabilities of the ultrasound ASIC, it analyzes data in real time and provides risk feedback. Data is automatically collected and wirelessly transmitted to a mobile phone, replacing the traditional "queueing at the hospital for ultrasound" model.

[0027] Figure 4 This is a schematic diagram illustrating the application scenario of the ultrasound chip in a brain-computer interface according to an embodiment of the present invention, such as... Figure 4 As shown, ultrasound chips are paving a completely new hardware path for brain-computer interface (BCI) technology. BCIs aim to establish direct communication between the brain and external devices, and ultrasound modules, with their completely non-invasive nature, high spatiotemporal resolution, and excellent skull penetration capabilities, are becoming one of the core components in this field. Previously, accurately decoding brain activities such as vision almost always required large magnetic resonance imaging (MRI) devices, while invasive electrodes required craniotomy for implantation. The ultrasound module 400 in this embodiment of the invention achieves sub-millimeter-level vascular imaging across the entire brain by replacing the entire skull, fundamentally addressing the two key requirements of BCIs: covering the widely distributed thought network of the brain and possessing sufficiently fine resolution. This overcomes the bottlenecks of signal ambiguity and limited spatial resolution in traditional non-invasive techniques such as electroencephalography (EEG). Its working principle is based on the close coupling between nerves and blood vessels: when neurons are active, they trigger an increase in local blood flow. The ultrasound module 400 emits ultrasound waves into the brain, using the scattered echoes from microbubbles or red blood cells flowing in the blood vessels to capture minute changes in blood flow caused by neural activity in brain tissue. These ultra-fine blood flow and blood volume maps are then converted into resolvable neural activity information, which can then be used to control external devices or conduct brain science research.

[0028] Figure 5 This is a schematic diagram illustrating the application scenario of the ultrasound chip in a neuromodulation system according to an embodiment of the present invention, such as... Figure 5As shown, the ultrasound chip can be applied to miniaturized ultrasound systems for preclinical neuroscience research and future implantable neurotherapy. It integrates a 2D phased-array piezoelectric transducer with an ultrasound ASIC and can be precisely implanted epidurally to achieve intracranial ultrasound neuromodulation and wireless power supply for implantable devices. In ultrasound neuromodulation scenarios, the device employs 1–5MHz high-frequency ultrasound (center frequency 2–3MHz) and 2D phased-array technology, with array elements configured from 8×8 to 36×36. This generates a focusing point with a volume resolution as low as 0.001mm³. Precise adjustment of the focusing position is achieved through electronic three-dimensional beam deflection, adapting to the modulation needs of 500 deep brain neural targets, overcoming the size and scenario limitations of traditional ultrasound neuromodulation. Simultaneously, the device integrates ultrasound imaging guidance, enabling real-time monitoring of the focusing point position and avoiding targeting deviations caused by sound refraction in large blood vessels or brain tissue displacement, thus improving safety and reliability.

[0029] Figure 6 This is a schematic diagram illustrating the working principle of the ultrasonic chip in an embodiment of the present invention, as shown below. Figure 6 As shown, when ultrasound is transmitted using the ultrasonic chip provided by this invention, the transmitting beamformer delays and adjusts the phase of the electrical pulse to direct the synthesized beam towards the target area. The pulse generator generates a high-voltage pulse based on the delay and phase of the electrical pulse, which triggers the transducer to vibrate and transmit ultrasonic waves. During ultrasound reception, the ultrasonic waves are reflected by tissue and act on the transducer, generating a signal through the positive piezoelectric effect. The signal amplifier amplifies and reduces the noise of the weak electrical signal output by the transducer, improving the signal-to-noise ratio. The receiving beamformer performs phase compensation on the electrical signals received by each array element, superimposing and enhancing the target echo. The target echo is transmitted to the host system through the output channel, thereby realizing image reconstruction and real-time display.

[0030] Figure 7 This is a schematic diagram of a dual-redundancy thermal protection system for an ultrasonic probe chip in an embodiment of the present invention, as shown below. Figure 7 As shown, the dual-redundancy thermal protection system for ultrasonic probe chips provided by the present invention includes: an on-chip ultrasonic system and a host system; the on-chip ultrasonic system is an ultrasonic device that can realize ultrasonic wave transmission and echo signal acquisition through a single chip, i.e., an ultrasonic chip, the ultrasonic chip including an ultrasonic transceiver array, a digital control module, an on-chip temperature sensor and an over-temperature protection unit. The ultrasonic transceiver array includes multiple ultrasonic transceiver elements, used to drive the transducer elements to emit ultrasonic waves and receive echo signals. The on-chip temperature sensor is used to output a temperature signal that is correlated with the real-time temperature of the chip. The over-temperature protection unit is used to acquire a threshold signal associated with a temperature threshold, continuously compare the temperature signal with the threshold signal, and output a first over-temperature signal when the temperature signal is greater than the threshold signal. The digital control module is used to control the ultrasonic transceiver array to perform cooling operations based on the first over-temperature signal.

[0031] In this embodiment of the invention, controlling the ultrasonic transceiver array to perform cooling operation includes: controlling the ultrasonic transceiver array to reset, controlling the ultrasonic transceiver array to stop working, controlling some array elements of the ultrasonic transceiver array to stop working or reducing the transmission voltage of the ultrasonic transceiver array.

[0032] In this embodiment of the invention, the dual redundancy thermal protection system provided by the present invention further includes a host system; The host system is electrically connected to the on-chip temperature sensor and the digital control module, and is used to acquire the temperature signal in real time, continuously compare the temperature signal with the threshold signal, and output the second over-temperature signal when the temperature signal is greater than the threshold signal. The digital control module is used to receive the second over-temperature signal and control the ultrasonic transceiver array to perform cooling operation according to the second over-temperature signal.

[0033] In this embodiment of the invention, the threshold signal is pre-stored in the storage unit OTP on the ultrasound chip, or sent to the ultrasound chip through the host system.

[0034] In this embodiment of the invention, the temperature sensor includes a first PTAT current generation unit, a CTAT current generation unit, a resistor network, and a weighted linearization unit. The first PTAT current generation unit is used to generate a first positive temperature coefficient current; The CTAT current generation unit is used to generate negative temperature coefficient current; The resistor network is used to generate a positive temperature coefficient voltage based on the first positive temperature coefficient current and to generate a negative temperature coefficient voltage based on the negative temperature coefficient current. The weighted linearization unit is used to generate a temperature signal that is linearly related to temperature by weighting and summing the positive temperature coefficient voltage and the negative temperature coefficient voltage to cancel out their respective nonlinearities.

[0035] Figure 8 This is a circuit diagram of the temperature sensor in an embodiment of the present invention, such as... Figure 8 As shown, the on-chip temperature sensor includes: The first current mirror unit includes transistor PM1, transistor PM2 and transistor PM3, wherein the sources of transistors PM1, PM2 and PM3 are all connected to the power supply terminal and their gates are connected to each other. Operational amplifier A2 has its non-inverting input connected to one end of resistor R2 and the drain of transistor PM1, its inverting input connected to the drain of transistor PM2, and its output connected to the gate of each transistor in the first current mirror unit. The other end of resistor R2 is grounded. The first bipolar transistor pair includes transistor Q1 and transistor Q2. The base and collector of transistor Q1 are grounded, and the emitter is connected to the drain of transistor PM2. The base and collector of transistor Q2 are grounded, and the emitter is connected to one end of resistor R1. Operational amplifier A1 has its non-inverting input connected to one end of resistor R3, its inverting input connected to the drain of transistor PM3 and the other end of resistor R1, and its output connected to the Vout port. The resistor network includes resistors R3 and R4. One end of resistor R3 is connected to the drain of transistor PM2, and the other end is connected to the Vout port. One end of resistor R4 is connected to the inverting input of operational amplifier A1, and the other end is connected to the output Vout port.

[0036] In this embodiment of the invention, the emitter area ratio of transistor Q1 and transistor Q2 is 1:N, where N is any natural number between 5 and 10.

[0037] Figure 9 The circuit diagram of the temperature sensor in a modified embodiment of the present invention is shown below. Figure 9 As shown, the on-chip temperature sensor includes: The first current mirror unit includes transistors PM1, PM2, PM3, and PM4. The sources of transistors PM1, PM2, PM3, and PM4 are all connected to the power supply terminal, and their gates are connected to each other. Operational amplifier A2 has its non-inverting input connected to one end of resistor R2 and the drain of transistor PM1, its inverting input connected to the drain of transistor PM2, and its output connected to the gate of each transistor in the first current mirror unit. The other end of resistor R2 is grounded. The first bipolar transistor pair includes transistor Q1 and transistor Q2. The base and collector of transistor Q1 are grounded, and the emitter is connected to the drain of transistor PM2. The base and collector of transistor Q2 are grounded, and the emitter is connected to one end of resistor R1. Operational amplifier A1 has its non-inverting input connected to one end of resistor R3, and its inverting input connected to the drain of transistor PM3 and the other end of resistor R1. A resistor network, including resistors R3, R4, and R... trim_os and resistance R trim_slope One end of resistor R3 is connected to the drain of transistor PM2, and the other end is connected to resistor R. trim_slope One end of the resistor R4 is connected to the inverting input of the operational amplifier A1, and the other end is connected to the resistor R. trim_slope One end of the resistor R trim_slope The other end and the output terminal of the operational amplifier A1 are connected to the resistor R. trim_os One end; The second current mirror unit includes a transistor PM5 and a second PTAT current generation unit. The second PTAT current generation unit is used to generate a second positive temperature coefficient current. The transistor PM5 is used to replicate the second positive temperature coefficient current. The source of the transistor PM5 is connected to the power supply terminal, and the drains of the transistor PM5 and the transistor PM4 are connected to the resistor R. trim_os At the other end, and the resistor R trim_os The other end is connected to the Vout port.

[0038] In this embodiment of the invention, transistor PM4 copies the negative temperature coefficient current, and transistor PM5 copies the second positive temperature coefficient current, thereby supplying power to resistor R. trim_os and the resistor R trim_slope Provides a constant temperature coefficient current; The resistor R trim_os This is used to compensate for offset errors in chip manufacturing, ensuring that the offset of the temperature-sensing voltage VTSOS ≈ 0V at 300K (27℃); the resistor R trim_slope It is used to compensate for the weighting ratio deviation between negative temperature coefficient current and positive temperature coefficient current, so that the temperature-voltage slope is stabilized at 12mV / K.

[0039] In this embodiment of the invention, the operational amplifier A2 is used to control the first current mirror unit through negative feedback, so that the drain voltages of transistor PM1 and transistor PM2 are equal, thereby replicating the negative temperature coefficient current I. CTAT ; The first bipolar transistor pair is used to apply the generated emitter-junction voltage difference across the resistor R1 to form a first positive temperature coefficient current IPTAT; The operational amplifier A1 is used to superimpose the negative temperature coefficient current and the first positive temperature coefficient current through negative feedback, and output a temperature signal that is linearly related to the temperature. The temperature signal is output through the Vout port.

[0040] In this embodiment of the invention, the dual-redundancy thermal protection system for an ultrasonic probe chip provided by the present invention further includes a gain amplifier and an off-chip capacitor C. L ; The resistor R trim_slope The other end is connected to the Vout port via the gain amplifier; The off-chip capacitor C L One end is connected to the gain amplifier, and the other end is grounded.

[0041] Figure 10 This is a circuit diagram of the over-temperature protection unit in an embodiment of the present invention, as shown below. Figure 10 As shown, the over-temperature protection unit includes transistor PM6, transistor PM7, transistor NM1, transistor NM2, resistor R5, digital-to-analog converter, and comparator; The transistor PM6 is used to replicate negative temperature coefficient current; The transistor PM7 is used to replicate the second positive temperature coefficient current; the sources of the transistors PM6 and PM7 are connected to the power supply terminal, and their drains are connected to the drain of the transistor NM1. The gates of transistors NM1 and NM2 are connected to form a third current mirror unit, and the sources of transistors NM1 and NM2 are grounded; the gate of transistor NM1 is connected to its drain. One output port of the digital-to-analog converter is connected to one end of resistor R5 and the inverting input of the comparator to set the over-temperature protection threshold. The other output port is connected to the drain of transistor NM2 to set the output current ratio of the third current mirror unit. The other end of resistor R5 is grounded. The Vout port is connected to the non-inverting input of the comparator, and the output of the comparator is used to output the first over-temperature signal.

[0042] In this embodiment of the invention, the output terminal of the comparator is connected to the first input terminal of the AND gate. The first input terminal of the AND gate is used to receive an enable signal. Only when the enable signal is valid and the comparator outputs a high level will the final first over-temperature signal, i.e., the overheat protection signal, be output. If the enable signal is invalid, the protection will not be triggered even if the temperature exceeds the limit, thus realizing the flexible switching of the protection function.

[0043] In various embodiments of the present invention, the resistance values ​​of resistor R3 and resistor R4 are the same.

[0044] In this embodiment of the invention, the threshold calibration process of the over-temperature protection unit is as follows: at the calibration reference temperature T A To bring the over-temperature protection unit to thermal steady state, the comparator flips the corresponding calibration code k via the digital-to-analog converter. A ; Based on kA and target threshold temperature T B Calculate the target calibration code k B The calibration formula is:

[0045] Where V∣ T=0℃ The voltage parameter is V at a temperature of 0℃. T=TA For calibration reference temperature T A The voltage under the current mirror is k0, where k0 is the fixed bias ratio of the current mirror.

[0046] Figure 11 The circuit diagram of the second PTAT current generation unit in an embodiment of the present invention is shown below. Figure 11 As shown, the second PTAT current generation unit includes: The fourth current mirror unit includes transistor PM8 and transistor PM9. The sources of transistors PM8, PM9 and PM5 are all connected to the power supply terminal, and their gates are connected to each other. Operational amplifier A5 has its inverting input connected to one end of resistor R6 and the drain of transistor PM9, its non-inverting input connected to the drain of transistor PM8, and its output connected to the gates of transistors PM8 and PM9. The second bipolar transistor pair includes transistor Q3 and transistor Q4. The base and collector of transistor Q3 are grounded, and the emitter is connected to the drain of transistor PM8. The base and collector of transistor Q4 are grounded, and the emitter is connected to the other end of resistor R6.

[0047] In this embodiment of the invention, the emitter area ratio of transistors Q3 and Q4 is 1:M, where M is any natural number between 5 and 10.

[0048] Figure 12 This is a working logic diagram of the digital control module in an embodiment of the present invention, such as... Figure 12 As shown, the digital control module controls the ultrasonic transceiver array to perform cooling operations based on the first over-temperature signal or the second over-temperature signal, including: Set the on-chip temperature sensor to normally open and turn off the over-temperature protection unit; The over-temperature protection unit is activated, enabling it to continuously detect over-temperature conditions. When the first over-temperature signal is detected or the second over-temperature signal is received, the ultrasonic chip is controlled to reset, and the over-temperature protection unit automatically shuts down after reset.

[0049] In this embodiment of the invention, two registers are used to configure the basic switches for the temperature detection and over-temperature protection units. The default value of TS_EN is 1, indicating that the temperature sensor is always on, ensuring continuous temperature detection unaffected by the chip's operating state or reset. The default value of TSP_EN is 0, indicating that the function is only enabled when over-temperature protection is required.

[0050] When an overtemperature event occurs, it triggers a chip reset. Since the temperature typically doesn't drop quickly after the reset and remains above the threshold, a default value of TSP_EN of 1 could cause a cycle of repeated overtemperature events and chip resets. Therefore, after an overtemperature reset, TSP_EN is automatically reset to 0, disabling overtemperature protection. At this point, because the chip is reset, it is not in transmit or receive mode, so the temperature will only decrease and will not continue to accumulate.

[0051] In addition, the digital control module removes metastability and performs digital filtering on the over-temperature indication signal output by the over-temperature protection circuit to avoid misjudgment of over-temperature caused by metastability generated by asynchronous sampling signals and repeated oscillation of the over-temperature indication signal when the temperature is near the threshold.

[0052] Figure 13 This is a logic diagram of temperature coefficient weighting in an embodiment of the present invention, such as... Figure 13 As shown, this invention utilizes the temperature characteristics of a BJT to achieve temperature response regulation of the voltage, where a×ΔV BE ΔV BE It is the voltage difference between the base and emitter of the two BJTs. k is Boltzmann's constant, q is the electron charge, and N is the transistor current ratio, which has a positive temperature coefficient. As the temperature increases, ΔV... BE It will increase, therefore this dashed line rises as temperature increases. For b×V BE Chinese V BE VBE is the voltage between the base and emitter of the BJT, and it has a negative temperature coefficient. As temperature increases, VBE decreases; therefore, this dashed line decreases with rising temperature. Vp is a × ΔV BE With b×V BE The weighted summation result is the induced voltage of the corresponding temperature sensor; through the complementary voltage compensation of positive and negative temperature coefficients, Vp exhibits a smooth and controllable temperature response within the operating range.

[0053] Figure 14 This is a logic diagram for fine-tuning the temperature sensing output voltage in an embodiment of the present invention, as shown below. Figure 14 As shown, in order to ensure that the temperature sensing voltage exhibits a precise linear positive temperature response within the operating range, and to guarantee the resolution and accuracy of temperature detection, a resistor R is used. trim_os and resistance R trim_slope Fine-tuning is performed on resistor R.trim_os Resistor R is used to adjust the vertical offset of the VTS (temperature-sensing voltage) curve, ensuring that the VTS is precisely aligned with the reference voltage at the reference temperature (300K), compensating for voltage offsets caused by process factors, etc. trim_slope Used to adjust the slope of VTS as a function of temperature (e.g., to ensure that the increment of VTS is precisely 12mV for every 1K increase in temperature) and to compensate for slope errors caused by processes, etc.

[0054] After fine-tuning, VTS increases by 12mV for every 1K increase in temperature. At 300K (27℃), the VTS offset is 0mV. The detection range of the temperature sensor module is 10℃~70℃, the detection resolution is 1℃, and the detection accuracy is less than ±0.3℃.

[0055] In an embodiment of the present invention, the ultrasonic chip provided by the present invention includes an ultrasonic transceiver array, a digital control module, an on-chip temperature sensor, and an over-temperature protection unit. The ultrasonic transceiver array includes multiple ultrasonic transceiver array elements, which are used to drive the ultrasonic transducer array elements to emit ultrasonic waves and receive echoes through the ultrasonic transducer array elements to generate echo signals. The on-chip temperature sensor is used to output a temperature signal that is correlated with the real-time temperature of the chip. The over-temperature protection unit is used to acquire a threshold signal associated with a temperature threshold, continuously compare the temperature signal with the threshold signal, and output a first over-temperature signal when the temperature signal is greater than the threshold signal. The digital control module is used to control the ultrasonic transceiver array to perform cooling operations based on the first over-temperature signal.

[0056] In this embodiment of the invention, a dual redundancy system is formed by the primary protection of an on-chip temperature sensor and an over-temperature protection unit integrated within the chip, and the secondary protection of the host system reading the temperature electrical signal. The on-chip protection can independently monitor the comparison result between the temperature electrical signal and the threshold electrical signal, and directly trigger the ultrasound transceiver array to stop working after the temperature exceeds the limit, without relying on an external system. The host system synchronously acquires the temperature electrical signal and makes a secondary judgment, forming a redundancy check. This solves the problems of delayed response and single-point failure of traditional single-system protection, ensuring that when the ultrasound probe (such as an intracardiac interventional probe or a wearable patch probe) is in direct contact with human tissue, even if any protection link is abnormal, the risk of burns caused by excessive temperature can still be avoided through the other link. The temperature sensor of this invention achieves linear temperature and voltage response by weighted summation of positive temperature coefficient current and negative temperature coefficient current, and is equipped with a dual fine-tuning structure and a 9-bit offset fine-tuning resistor R. trim_os To compensate for chip manufacturing offset errors, the temperature-sensing voltage offset (VTSOS) at 300K (27℃) is approximately 0V; 6-bit slope trimming resistor Rtrim_slope The current weighting ratio is compensated for to ensure that the temperature and voltage slopes remain stable at 12mV / K. Simultaneously, the design employs BJT transistor pairs (Q1 / Q2) emitter area ratio and operational amplifier negative feedback control of the current mirror, enabling a temperature detection range of 10℃~70℃ with a resolution of 1℃ and an accuracy of less than ±0.3℃. This solves the problems of traditional RTD sensors, such as inability to integrate and large temperature measurement deviations, ensuring accurate triggering of over-temperature protection thresholds (e.g., adjustable from 45℃ to 60℃) and avoiding false or missed protection due to inaccurate temperature measurement.

[0057] This invention suppresses false triggering caused by power supply noise and signal crosstalk by performing metastability removal and digital filtering on the over-temperature state signal, thus avoiding unnecessary shutdown of the ultrasound transceiver array. Furthermore, it includes an enable signal and a 7-bit DAC (Digital-to-Analog Converter) threshold adjustment. When the enable signal is low, the over-temperature protection unit is forced to ground, disabling the protection function. The protection threshold can be adjusted in 1°C steps by controlling the current ratio of the current mirror via the DAC. Additionally, the comparator employs a two-stage folded cascode structure, achieving a maximum response time ≤158ns under 1pF load and SSL corner PVT conditions, balancing fast response and interference resistance. This design meets the needs of various ultrasound scenarios (such as high-frame-rate intracardiac imaging and wearable long-term monitoring), ensuring stable protection signals while supporting flexible configuration of protection logic according to clinical needs.

[0058] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0059] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A dual-redundancy thermal protection system for an ultrasonic probe chip, characterized in that, include: An ultrasonic chip and a host system; the ultrasonic chip includes an ultrasonic transceiver array, a digital control module, an on-chip temperature sensor, and an over-temperature protection unit. The ultrasonic transceiver array includes multiple ultrasonic transceiver elements, used to drive the transducer elements to emit ultrasonic waves and receive echo signals. The on-chip temperature sensor is used to output a temperature signal that is correlated with the real-time temperature of the chip. The over-temperature protection unit is used to acquire a threshold signal associated with a temperature threshold, continuously compare the temperature signal with the threshold signal, and output a first over-temperature signal when the temperature signal is greater than the threshold signal. The host system is electrically connected to the on-chip temperature sensor and the digital control module, and is used to acquire the temperature signal in real time, continuously compare the temperature signal with the threshold signal, and output a second over-temperature signal when the temperature signal is greater than the threshold signal. The digital control module is used to receive the first over-temperature signal and the second over-temperature signal, and control the ultrasonic transceiver array to perform cooling operation according to the first over-temperature signal or the second over-temperature signal.

2. The dual redundancy thermal protection system according to claim 1, characterized in that, The digital control module controls the ultrasonic transceiver array to perform cooling operations based on the first over-temperature signal or the second over-temperature signal, including: Set the on-chip temperature sensor to normally open and turn off the over-temperature protection unit; The over-temperature protection unit is activated, enabling it to continuously detect over-temperature conditions. When the first over-temperature signal is detected or the second over-temperature signal is received, the ultrasonic chip is controlled to reset, and the over-temperature protection unit automatically shuts down after reset.

3. The dual redundancy thermal protection system according to claim 1, characterized in that, The threshold signal is pre-stored in the storage unit on the ultrasound chip, or sent to the ultrasound chip through the host system.

4. The dual redundancy thermal protection system according to claim 1, characterized in that, The on-chip temperature sensor includes a first PTAT current generation unit, a CTAT current generation unit, a resistor network, and a weighted linearization unit. The first PTAT current generation unit is used to generate a first positive temperature coefficient current; The CTAT current generation unit is used to generate negative temperature coefficient current; The resistor network is used to generate a positive temperature coefficient voltage based on the first positive temperature coefficient current and to generate a negative temperature coefficient voltage based on the negative temperature coefficient current. The weighted linearization unit is used to generate a temperature signal that is linearly related to temperature by weighting and summing the positive temperature coefficient voltage and the negative temperature coefficient voltage to cancel out their respective nonlinearities.

5. The dual redundancy thermal protection system according to claim 1, characterized in that, The on-chip temperature sensor includes: The first current mirror unit includes transistor PM1, transistor PM2 and transistor PM3, wherein the sources of transistors PM1, PM2 and PM3 are all connected to the power supply terminal and their gates are connected to each other. Operational amplifier A2 has its non-inverting input connected to one end of resistor R2 and the drain of transistor PM1, its inverting input connected to the drain of transistor PM2, and its output connected to the gate of each transistor in the first current mirror unit. The other end of resistor R2 is grounded. The first bipolar transistor pair includes transistor Q1 and transistor Q2. The base and collector of transistor Q1 are grounded, and the emitter is connected to the drain of transistor PM2. The base and collector of transistor Q2 are grounded, and the emitter is connected to one end of resistor R1. Operational amplifier A1 has its non-inverting input connected to one end of resistor R3, its inverting input connected to the drain of transistor PM3 and the other end of resistor R1, and its output connected to the Vout port. The resistor network includes resistors R3 and R4. One end of resistor R3 is connected to the drain of transistor PM2, and the other end is connected to the Vout port. One end of resistor R4 is connected to the inverting input of operational amplifier A1, and the other end is connected to the output Vout port.

6. The dual redundancy thermal protection system according to claim 1, characterized in that, The on-chip temperature sensor includes: The first current mirror unit includes transistors PM1, PM2, PM3, and PM4. The sources of transistors PM1, PM2, PM3, and PM4 are all connected to the power supply terminal, and their gates are connected to each other. Operational amplifier A2 has its non-inverting input connected to one end of resistor R2 and the drain of transistor PM1, its inverting input connected to the drain of transistor PM2, and its output connected to the gate of each transistor in the first current mirror unit. The other end of resistor R2 is grounded. The first bipolar transistor pair includes transistor Q1 and transistor Q2. The base and collector of transistor Q1 are grounded, and the emitter is connected to the drain of transistor PM2. The base and collector of transistor Q2 are grounded, and the emitter is connected to one end of resistor R1. Operational amplifier A1 has its non-inverting input connected to one end of resistor R3, and its inverting input connected to the drain of transistor PM3 and the other end of resistor R1. A resistor network, including resistors R3, R4, and R... trim_os and resistance R trim_slope One end of resistor R3 is connected to the drain of transistor PM2, and the other end is connected to resistor R. trim_slope One end of the resistor R4 is connected to the inverting input of the operational amplifier A1, and the other end is connected to the resistor R. trim_slope One end of the resistor R trim_slope The other end and the output terminal of the operational amplifier A1 are connected to the resistor R. trim_os One end; The second current mirror unit includes a transistor PM5 and a second PTAT current generation unit. The second PTAT current generation unit is used to generate a second positive temperature coefficient current. The transistor PM5 is used to replicate the second positive temperature coefficient current. The source of the transistor PM5 is connected to the power supply terminal, and the drains of the transistor PM5 and the transistor PM4 are connected to the resistor R. trim_os At the other end, and the resistor R trim_os The other end is connected to the Vout port.

7. The dual redundancy thermal protection system according to claim 5 or 6, characterized in that, The operational amplifier A2 is used to control the first current mirror unit through negative feedback, so that the drain voltages of transistor PM1 and transistor PM2 are equal, thereby replicating the negative temperature coefficient current I. CTAT ; The first bipolar transistor pair is used to apply the generated emitter-junction voltage difference across the resistor R1 to form a first positive temperature coefficient current IPTAT; The operational amplifier A1 is used to superimpose the negative temperature coefficient current and the first positive temperature coefficient current through negative feedback, and output a temperature signal that is linearly related to the temperature. The temperature signal is output through the Vout port.

8. The dual redundancy thermal protection system according to claim 6, characterized in that, The over-temperature protection unit includes transistor PM6, transistor PM7, transistor NM1, transistor NM2, resistor R5, digital-to-analog converter, and comparator; The transistor PM6 is used to replicate negative temperature coefficient current; The transistor PM7 is used to replicate the second positive temperature coefficient current; the sources of the transistors PM6 and PM7 are connected to the power supply terminal, and their drains are connected to the drain of the transistor NM1. The gates of transistors NM1 and NM2 are connected to form a third current mirror unit, and the sources of transistors NM1 and NM2 are grounded; the gate of transistor NM1 is connected to its drain. One output port of the digital-to-analog converter is connected to one end of resistor R5 and the inverting input of the comparator to set the over-temperature protection threshold. The other output port is connected to the drain of transistor NM2 to set the output current ratio of the third current mirror unit. The other end of resistor R5 is grounded. The Vout port is connected to the non-inverting input of the comparator, and the output of the comparator is used to output the first over-temperature signal.

9. The dual redundancy thermal protection system according to claim 6, characterized in that, The second PTAT current generation unit includes: The fourth current mirror unit includes transistor PM8 and transistor PM9. The sources of transistors PM8, PM9 and PM5 are all connected to the power supply terminal, and their gates are connected to each other. Operational amplifier A5 has its inverting input connected to one end of resistor R6 and the drain of transistor PM9, its non-inverting input connected to the drain of transistor PM8, and its output connected to the gates of transistors PM8 and PM9. The second bipolar transistor pair includes transistor Q3 and transistor Q4. The base and collector of transistor Q3 are grounded, and the emitter is connected to the drain of transistor PM8. The base and collector of transistor Q4 are grounded, and the emitter is connected to the other end of resistor R6.

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