A base station direct current power supply control method based on micro-wind power generation

Abstract

The application discloses a base station direct current power supply control method based on micro-wind power generation, relates to the field of wind power cooperative power supply control, and comprises the following steps: parallelly connecting wide-range alternating current of a micro-wind power generator to a base station direct current bus after rectifying the wide-range alternating current through an AC / DC conversion module; sampling the bus voltage through a resistance network, reading the bus voltage in real time after isolation amplification by a digital signal processor; under normal circumstances, the DSP carries out closed-loop PWM control with the bus voltage as a target, so that automatic voltage stabilization is realized; when a central controller issues a regulation and control instruction through RS485, the DSP is switched to a controlled output mode, the duty cycle is dynamically adjusted according to given voltage and power limit values, and it is ensured that the output does not exceed the limit; after communication abnormality or a recovery instruction is received, the system is automatically switched back to a voltage tracking mode. The application has the advantages that wide-range fluctuating micro-wind power is stably consumed, the self-powered reliability and the base station centralized dispatching flexibility are considered, and the stability and continuity of direct current power supply are ensured.

Description

Technical Field

[0001] This invention relates to the field of wind power coordinated power supply control, and in particular to a DC power supply control method for base stations based on micro-wind power generation. Background Technology

[0002] With the advancement of 5G communication network coverage across the entire region, many base stations in remote mountainous areas, suburbs, and islands face challenges such as unstable mains power supply, high maintenance costs of diesel generators, and excessive carbon emissions. The industry is widely adopting renewable energy-assisted power supply to reduce costs and carbon emissions. Base station communication equipment has a standard load of DC 48V, and micro-wind generators are compatible with integrated tower installation and can generate electricity even at low wind speeds. This can compensate for the insufficient output of photovoltaic power during cloudy and rainy weather, and has broad application value.

[0003] Current mainstream micro-wind power generation base station power supply solutions generally suffer from shortcomings such as single control dimensions, weak dynamic adaptability, and insufficient fault tolerance mechanisms. Most solutions employ non-isolated voltage sampling, resulting in low sampling accuracy and poor anti-interference capabilities in the complex electromagnetic environment of base stations, easily leading to control deviations. The control logic is mostly a single constant voltage or maximum power point tracking mode, lacking standardized communication interaction and centralized control interfaces with the base station's central controller. This makes it impossible to respond to the dual voltage and power scheduling constraints on the base station side, and difficult to match the refined power supply management requirements of communication networks. Addressing the wide fluctuations in micro-wind power generation, existing solutions generally lack input voltage feedforward compensation mechanisms, resulting in lag in adjustment when faced with input voltage jumps caused by sudden wind speed changes, leading to large bus voltage fluctuations. The step-down regulation lacks a cycle-by-cycle limiting mechanism, easily causing overmodulation and exacerbating switching transistor stress and output ripple. Furthermore, most solutions lack robust frame verification and automatic timeout fallback mechanisms in the communication link, easily leading to loss of control or shutdown during communication anomalies, resulting in insufficient power supply continuity and system reliability, making it difficult to adapt to the high-reliability DC power supply requirements of base stations. Summary of the Invention

[0004] To improve existing methods, a DC power supply control method for base stations based on micro-wind power generation is provided. This method adopts a dual-mode architecture of voltage tracking and controlled output, and relies on isolated sampling, feedforward compensation, cycle-by-cycle limiting and RS485 centralized control with timeout protection to stably absorb micro-wind power with wide fluctuations, taking into account the reliability of autonomous power supply and the flexibility of centralized scheduling of base stations, and ensuring stable and continuous DC power supply.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A DC power supply control method for a base station based on micro-wind power generation, comprising:

[0007] The wide-range alternating current output from the micro wind turbine is connected to the AC input port of the AC / DC converter module, and the DC output port of the AC / DC converter module is connected in parallel to the DC bus of the base station to establish a power transmission path from the generator set through the AC / DC converter module to the bus.

[0008] A resistor voltage divider sampling network is set up between the positive and negative buses of the base station DC bus. The low voltage signal is led out from the voltage divider node, isolated and amplified, and then sent to the analog-to-digital conversion port inside the AC / DC conversion module. The digital signal processor reads and calculates the digital quantization value of the bus voltage at a fixed sampling period.

[0009] When no external limiting command is received, the digital signal processor uses the digital quantization value of the bus voltage as the output target setpoint, and adjusts the pulse width modulation duty cycle of the internal switching transistor of the AC / DC conversion module through closed loop. When the bus voltage increases, the duty cycle is increased, and when the bus voltage decreases, the duty cycle is decreased.

[0010] When the base station central controller sends a control command to the AC / DC conversion module through the RS485 communication bus, the digital signal processor receives and verifies the command frame, parses out the output voltage limit value and the output power limit value, and switches the control mode from voltage tracking mode to controlled output mode.

[0011] In controlled output mode, the digital signal processor compares the actual bus voltage value with the output voltage limit value, and compares the actual output power value of the module with the output power limit value. It selects the more stringent condition as the final control constraint and dynamically adjusts the pulse width modulation duty cycle to ensure that the output voltage and output power do not exceed the limit value. When the communication times out or a recovery command is received, the digital signal processor switches back to voltage tracking mode.

[0012] Preferably, the step of setting up a resistor divider sampling network, extracting a low-voltage signal from the voltage divider node, and then sending it to the analog-to-digital conversion port inside the AC / DC conversion module after isolation and amplification, specifically includes:

[0013] A first voltage divider resistor and a second voltage divider resistor are connected in series between the positive and negative terminals of the DC bus of the base station. The upper end of the first voltage divider resistor is connected to the positive terminal, and the lower end is connected to the upper end of the second voltage divider resistor. The lower end of the second voltage divider resistor is connected to the negative terminal. A low-voltage sampling signal with an amplitude lower than the bus voltage is taken out from the connection node of the first voltage divider resistor and the second voltage divider resistor.

[0014] The low-voltage sampling signal is sent to the input side of the linear optocoupler isolation amplifier. The output side of the linear optocoupler isolation amplifier outputs a differential voltage signal that is proportional to the low-voltage sampling signal. After high-frequency noise is filtered out by a filter capacitor, the signal is connected to the analog-to-digital conversion differential input pin of the digital signal processor in the AC / DC conversion module.

[0015] The analog-to-digital converter built into the digital signal processor continuously samples the differential input pins and calculates the arithmetic mean as the digital quantization value of the bus voltage for the current control cycle.

[0016] Preferably, the step of adjusting the pulse width modulation duty cycle of the internal switching transistors of the AC / DC converter module via closed-loop control specifically includes:

[0017] Read the historical value of the bus voltage stored in the previous control cycle, combine it with the digital quantized value of the bus voltage in the current control cycle, and calculate the difference between the two to obtain the instantaneous change in the bus voltage.

[0018] The digital signal processor determines whether the absolute value of the instantaneous change is less than the preset voltage change threshold. If it is less than the threshold, the bus voltage is determined to be in a stable state. The digital signal processor uses the current bus voltage digital quantization value as the given target of the proportional-integral regulator. The proportional-integral regulator outputs the duty cycle adjustment amount according to the error between the given target and the actual output voltage feedback value, so that the actual output voltage smoothly approaches the bus voltage.

[0019] If the absolute value of the instantaneous change is greater than or equal to the preset voltage change threshold, the bus voltage is determined to be in a jumping state. In each control cycle, the digital signal processor increases or decreases the given target by a fixed step based on the current value until the given target reaches the current digital quantization value of the bus voltage. In each cycle, the instantaneous change is recalculated and the judgment is repeated.

[0020] Preferably, when adjusting the pulse width modulation duty cycle, input voltage feedforward compensation is introduced to accelerate the response, specifically including:

[0021] An AC voltage sampling circuit is set at the AC input port of the AC / DC conversion module. The secondary signal of the input AC voltage is obtained through a voltage transformer. After full-wave rectification and RC filtering, the secondary signal is used to obtain a DC level signal that reflects the effective value of the input voltage, and then connected to the auxiliary analog-to-digital conversion input channel of the digital signal processor.

[0022] In each control cycle, the digital signal processor reads the digital value of the DC level signal as the current input voltage amplitude, subtracts the current input voltage amplitude from the input voltage amplitude stored in the previous control cycle to obtain the amount of change in the input voltage, and records the direction of change.

[0023] The digital signal processor calculates the feedforward compensation coefficient based on the obtained input voltage change and direction. When the input voltage increases, the feedforward compensation coefficient is positive. The digital signal processor multiplies the feedforward compensation coefficient by a preset scaling factor to obtain the feedforward duty cycle increment. The feedforward duty cycle increment is then superimposed on the feedback duty cycle adjustment output of the proportional-integral controller to synthesize the final duty cycle control quantity and output it to the pulse width modulation generator.

[0024] When the input voltage decreases, the feedforward compensation coefficient becomes negative, and the feedforward duty cycle increment becomes negative. This is superimposed on the feedback regulation to achieve the output voltage's advance suppression of input voltage fluctuations.

[0025] Preferably, when the bus voltage decreases and the duty cycle is reduced, a cycle-by-cycle limiting voltage reduction is used to prevent overmodulation, specifically including:

[0026] The digital signal processor calculates the difference between the current bus voltage digital quantization value and the current actual output voltage feedback value. If the difference is negative, it determines that the output voltage needs to be reduced, and the absolute value of the difference is taken as the total amount of voltage reduction required.

[0027] The digital signal processor compares the total voltage reduction with the preset maximum allowable voltage reduction step size per single cycle. If the total voltage reduction is less than or equal to the step size, the digital signal processor directly uses the digital quantized value of the bus voltage as the new given target, calculates the duty cycle adjustment amount, and adjusts it to the correct position in one go.

[0028] If the total voltage drop exceeds the preset maximum allowable step size for a single cycle, the digital signal processor sets the given target for the current control cycle to the value of the current actual output voltage minus the step size, and deducts the step size from the total voltage drop. In the next control cycle, the remaining total voltage drop is recalculated, and the comparison and adjustment process is repeated until the remaining total voltage drop is zero. The actual voltage drop in each control cycle does not exceed the preset step size.

[0029] Preferably, the digital signal processor receiving and verifying the instruction frame specifically includes:

[0030] The RS485 communication circuit continuously monitors the serial data on the bus. When it detects the start byte that matches the protocol frame header characteristics, it receives subsequent data bytes and stores the received bytes in the receive buffer in sequence. When it receives the end byte of the frame, the communication circuit triggers a receive completion interrupt signal to the digital signal processor.

[0031] After the digital signal processor responds to the interrupt, it reads the entire frame data from the receive buffer, extracts the frame length field, reads all data bytes according to the length, performs cyclic redundancy check calculation on the data bytes from the frame header to the check code, compares the calculated check value with the check code attached to the frame tail bit by bit, if they are completely consistent, the frame data is determined to be valid, if they are inconsistent, the frame is discarded and the buffer is cleared, without any parameter updates.

[0032] The valid frame data is parsed, and the opcode is extracted from the instruction type field of the frame. If the opcode is a power limiting instruction, the voltage limit value of two bytes is extracted from the voltage limit field of the frame, and the two bytes are combined into a sixteen-bit integer with the high byte first and the low byte last and stored in the first limiting register. The power limit value of two bytes is extracted from the power limit field and stored in the second limiting register. At the same time, the internal control mode flag is set from 0 to 1, and the flag is switched to the controlled output mode.

[0033] Preferably, comparing the actual bus voltage value with the output voltage limit value and comparing the actual output power value of the module with the output power limit value specifically includes:

[0034] The digital signal processor reads the current bus voltage digital quantization value and the output voltage limit value in the first limit register. The two are subtracted. If the bus voltage is greater than the limit value, the digital signal processor uses the output voltage limit value as the upper limit of the output voltage for the current cycle. If the bus voltage is less than or equal to the limit value, the bus voltage itself is used as the upper limit.

[0035] The digital signal processor acquires the current sensor signal at the DC output terminal of the AC / DC converter module, obtains the digital value of the output current after analog-to-digital conversion, multiplies the current digital value of the actual output voltage by the digital value of the output current to obtain the actual output power value, reads the output power limit value in the second limit register, and subtracts the actual output power value from the limit value to obtain the power deviation.

[0036] If the obtained power deviation is greater than zero, the digital signal processor sends the power deviation to the proportional-integral regulator, which outputs a negative correction amount. This correction amount is superimposed on the determined upper limit of the output voltage to obtain the corrected final set value, so that the output power corresponding to the corrected set value is reduced to below the limit value.

[0037] If the power deviation is less than or equal to zero, no power correction is needed, and the given upper limit is directly used as the final given value.

[0038] Preferably, the step of the digital signal processor switching back to voltage tracking mode when communication times out or a recovery command is received specifically includes:

[0039] The digital signal processor has an internal decrementing timer with an initial value of a preset timeout threshold. The timer automatically decrements by 1 at the beginning of each control cycle. When a valid control command is successfully received, the timer is reset to the initial threshold and decrements again.

[0040] The digital signal processor detects the current value of the decrementing timer in each control cycle. If the current value is reduced to zero, it determines that the communication has timed out, restores the control mode flag from 1 to 0, clears the values ​​in the first and second limit registers, stops the controlled output mode, and switches to the execution voltage tracking mode.

[0041] If the timer does not decrement to zero, the digital signal processor continues to check whether the RS485 communication circuit has received a new valid instruction frame. If it is received and the opcode in the instruction frame is a recovery instruction, the digital signal processor does not wait for the timer to expire, immediately clears the control mode flag and the limiting register, directly switches to the voltage tracking mode, and resets the timer to its initial value.

[0042] Compared with the prior art, the advantages of the present invention are:

[0043] A sampling scheme combining resistive voltage division and linear optocoupler isolation amplification ensures accurate bus voltage acquisition and anti-interference capabilities, providing reliable data support for closed-loop control. The default voltage tracking mode adapts to the characteristics of clean energy output. Dynamic response is accelerated through PI closed-loop regulation and input voltage feedforward compensation. A cycle-by-cycle limiting and step-down mechanism is introduced to avoid overmodulation risks and maintain stable output voltage. The method supports centralized control via RS485 bus, with CRC verification ensuring command reliability. It achieves dual voltage and power limiting constraints and uses the most stringent conditions to control the output, meeting the needs of base station scheduling. A built-in automatic switchback mechanism for communication timeouts seamlessly restores autonomous power supply in case of anomalies, improving system fault tolerance and power supply continuity. The overall solution can efficiently absorb clean energy from light winds, reduce base station dependence on mains power, balance autonomous operation stability with centralized control flexibility, and is suitable for high-reliability DC power supply scenarios for communication base stations. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a DC power supply control method for a base station based on micro-wind power generation proposed in this invention;

[0045] Figure 2 This is a schematic diagram of the adjustable pulse width modulation duty cycle proposed in this invention;

[0046] Figure 3 This is a schematic diagram of the digital signal processor proposed in this invention receiving and verifying instruction frames. Detailed Implementation

[0047] The following description is intended to disclose the invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art.

[0048] See Figure 1 As shown, a DC power supply control method for a base station based on micro-wind power generation includes:

[0049] The wide-range alternating current output from the micro wind turbine is connected to the AC input port of the AC / DC converter module, and the DC output port of the AC / DC converter module is connected in parallel to the DC bus of the base station to establish a power transmission path from the generator set through the AC / DC converter module to the bus.

[0050] A resistor voltage divider sampling network is set up between the positive and negative buses of the base station DC bus. The low voltage signal is led out from the voltage divider node, isolated and amplified, and then sent to the analog-to-digital conversion port inside the AC / DC conversion module. The digital signal processor reads and calculates the digital quantization value of the bus voltage at a fixed sampling period.

[0051] When no external limiting command is received, the digital signal processor uses the digital quantization value of the bus voltage as the output target setpoint, and adjusts the pulse width modulation duty cycle of the internal switching transistor of the AC / DC conversion module through closed loop. When the bus voltage increases, the duty cycle is increased, and when the bus voltage decreases, the duty cycle is decreased.

[0052] When the base station central controller sends a control command to the AC / DC conversion module through the RS485 communication bus, the digital signal processor receives and verifies the command frame, parses out the output voltage limit value and the output power limit value, and switches the control mode from voltage tracking mode to controlled output mode.

[0053] In controlled output mode, the digital signal processor compares the actual bus voltage value with the output voltage limit value, and compares the actual output power value of the module with the output power limit value. It selects the more stringent condition as the final control constraint and dynamically adjusts the pulse width modulation duty cycle to ensure that the output voltage and output power do not exceed the limit value. When the communication times out or a recovery command is received, the digital signal processor switches back to voltage tracking mode.

[0054] Specifically, in the base station power supply system, two small and medium-sized micro wind turbine generator sets with a rated power of 600W are selected. The three-phase AC output leads of each generator set are led out through a waterproof junction box and connected to the AC input port of the corresponding AC / DC conversion module. The three-phase leads are rectified by the rectifier bridge inside the module. The rectified pulsating DC is pre-filtered by a thin film capacitor and then sent to the main circuit of the subsequent DC / DC conversion.

[0055] The DC output port of the AC / DC converter module consists of a positive output terminal and a negative terminal. The positive terminal contains a reverse-current protection Schottky diode and a resettable fuse connected in series to prevent backflow damage to the module when the bus voltage exceeds the module's output voltage. The positive DC output terminal of the AC / DC converter module is connected to the 48V positive busbar of the base station's DC distribution cabinet via a flame-retardant copper core cable. The negative terminal is connected to the negative busbar via a cable of the same specification, forming a parallel connection.

[0056] After connection, the wide-range alternating voltage output from the micro-wind generator is transmitted to the AC / DC conversion module via an AC cable. The module performs rectification and DC conversion internally, then feeds power to the base station's DC bus via a DC output cable, forming a complete electrical path from the generator to the busbar via the AC / DC conversion module. Once this path is established, the busbar voltage is fed back to the AC / DC module via a separately configured voltage sampling line. Simultaneously, no additional switches or isolation devices are connected in series between the module's DC output and the busbar.

[0057] See Figure 2 As shown, a voltage divider sampling network composed of high-precision metal film resistors is directly connected between the positive and negative busbars of the base station's DC bus. The upper lead of the first voltage divider resistor R1 is crimped to the positive terminal of the busbar via a copper lug. The lower end of R1 is connected in series with the upper end of the second voltage divider resistor R2, and the lower lead of R2 is connected to the negative terminal of the busbar. The resistance ratio of R1 to R2 is designed to be 100:1, where R1 is 100kΩ and R2 is 1kΩ. Both have an accuracy of ±0.1% and a temperature coefficient of no more than 25ppm / ℃ to ensure the stability of the voltage division ratio within the range of ambient temperature variations in the base station. A low-voltage sampling signal line is drawn from the series connection point of R1 and R2. The potential at this point is the low-voltage analog quantity of the busbar voltage after resistor division. This voltage division relationship satisfies:

[0058]

[0059] in, This is the actual DC voltage between the positive and negative terminals of the busbar. This is the amplitude of the low-voltage sampled signal output from the voltage divider node. After the high-frequency ripple is initially filtered out by an RC low-pass filter, this low-voltage signal enters the next stage of the isolation amplifier circuit.

[0060] The low-voltage sampling signal drawn from the voltage divider node The input signal is fed into the input side of the linear optocoupler isolation amplifier. After electro-optical-electro-electrical conversion, a differential voltage signal with a fixed ratio to the input signal is generated at the output side. The gain of the isolation amplifier is set by an external feedback resistor. In this embodiment, the gain K is set to 2, i.e., the output differential voltage... With input voltage The following conditions must be met:

[0061]

[0062] Where K is the transmission gain of the isolation amplifier. After isolation, the output ground is completely isolated from the negative terminal of the bus, thus completely blocking common-mode interference on the high-voltage side. The differential voltage signal output by the isolation amplifier... The signal then passes through a first-stage second-order low-pass active filter with a cutoff frequency set at 100Hz to filter out high-frequency noise and bus ripple generated by the switching power supply. The filtered signal is then directly connected to the differential input pin of the 12-bit successive approximation analog-to-digital converter built into the digital signal processor in the AC / DC conversion module. The reference voltage of the ADC is 2.5V, so the input signal is fully utilized and has a margin.

[0063] The digital signal processor (DSP) is internally configured with an ADC that initiates conversion at a fixed sampling period, producing a 12-bit digital value after each conversion. (i) The digital signal processor continuously acquires N=20 samples in each control cycle and stores these 20 samples in a circular data buffer. When the buffer is full, the digital signal processor reads all sample values ​​and calculates their arithmetic mean, which is used as the digital quantized value of the bus voltage for the current control cycle. , where k is the control cycle number. The calculation formula is as follows:

[0064]

[0065] This average value is the feedback benchmark value used in subsequent closed-loop adjustments. After the calculation is complete, The data is stored in the DSP's internal registers, and the write pointer of the buffer is automatically moved forward in preparation for data updates in the next control cycle.

[0066] In each control cycle, the digital signal processor reads the current bus voltage digital quantization value from its internal register. Simultaneously, it reads the historical bus voltage value stored in the previous control cycle. The difference between the two is used to obtain the instantaneous change in bus voltage. DSP will The absolute value and the preset voltage change threshold Compare the data to determine the condition of the busbar.

[0067] like If the bus voltage is considered to be in a relatively stable state, then the DSP will directly... As a given target of the proportional-integral controller The PI regulator simultaneously acquires the actual output voltage feedback value from the DC output terminal of the AC / DC converter module. The calculation error e(k) = - The feedback duty cycle adjustment amount is output according to the discrete PI algorithm. DSP will The duty cycle of the previous cycle is superimposed on the duty cycle to generate a new PWM duty cycle, so that the actual output voltage smoothly approaches the bus voltage.

[0068] like If a sudden change in the bus voltage is detected, the DSP will determine that a jump has occurred. To avoid drastic fluctuations in the output voltage, the DSP will not directly use the current bus value as the target, but will instead use a fixed step size. Approximating periodically. Specifically, if Then let the current period be given a target. ;like Then let After each cycle, the DSP recalculates. And make another judgment until the given target reaches the actual bus value.

[0069] To further improve the response speed to sudden changes in wind speed, this embodiment introduces input voltage feedforward compensation in the regulation loop. At the AC input port of the AC / DC converter module, the secondary signal of the input AC voltage is obtained through a voltage transformer. This signal is then converted into a DC level signal reflecting the effective value of the input voltage after full-wave rectification and RC filtering, and connected to the auxiliary analog-to-digital conversion channel of the DSP. The DSP reads the digital value of this channel in each control cycle. and with the previous cycle Subtracting them, we get the change in input voltage Δ. At the same time, the direction of change is recorded.

[0070] DSP based on Δ Calculate the feedforward compensation coefficient ,in This is the experimentally calibrated feedforward scaling factor. When the input voltage increases, Δ... If the value is greater than 0, the feedforward compensation is positive. The DSP multiplies this positive value by a preset scaling factor to obtain the feedforward duty cycle increment Δ. = Δ When the input voltage decreases, Δ <0, Δ The result is negative. Ultimately, the DSP adds the feedforward increment to the feedback regulation output of the PI controller to synthesize the total duty cycle control quantity Δ. (k)= +Δ The input voltage is fed forward and output to the PWM generator. Since the feedforward component takes effect instantly when the input voltage changes, there is no need to wait for the feedback error to accumulate, thus achieving proactive suppression of input fluctuations and complementing the feedback regulation.

[0071] When a decrease in bus voltage necessitates a step-down adjustment of the AC / DC module, this embodiment employs a cycle-by-cycle limiting method to prevent overmodulation or inductor current runaway caused by excessive duty cycle adjustments at once. The DSP calculates the current bus voltage digital quantization value. Feedback value of actual output voltage The difference; if the difference is negative, then the total pressure drop... =∣ - | DSP Comparison Compared with the preset maximum allowable step size of voltage reduction per cycle .like ≤ Then directly As a given goal, adjust it in one go; if Then the target for the current period is set as = - At the same time Updated to - The above comparison is repeated in the next control cycle until the remaining total pressure drop is zero. The pressure drop in each cycle does not exceed [a certain value]. This ensures the stability of the dynamic process.

[0072] See Figure 3 As shown, the RS485 communication circuit of the AC / DC converter module uses a half-duplex transceiver. Its receive enable pin is always active, continuously monitoring the differential level signal on the communication bus. The transceiver converts the differential signal into a TTL level serial data stream, which is sent to the DSP's universal asynchronous transceiver interface at a baud rate of 9600bps. The UART interface samples the data bits on the rising edge of each baud rate clock, performs start bit detection, data bit shifting, and stop bit confirmation, and stores the received bytes sequentially into the UART's receive holding register.

[0073] The communication protocol frame structure defined in this embodiment is as follows: the frame header flag is fixed at two bytes (0xAA, 0x55), followed by the frame length field (1 byte), the destination address field (1 byte), the instruction type field (1 byte), the data field (several bytes, including output voltage and output power limits), the checksum field (2 bytes of CRC-16), and the end-of-frame byte (0x0D). When the RS485 communication circuit detects that two consecutive received bytes completely match the frame header flag (0xAA, 0x55), it determines that a valid start position has been detected, and then stores the subsequent data bytes sequentially into the receive buffer inside the DSP. Each time a byte is stored in the buffer, the buffer write pointer is automatically incremented by 1. When the received byte matches the end-of-frame byte (0x0D), the communication circuit determines that a frame of data has been received, and then triggers a receive completion interrupt signal to the DSP, notifying the DSP to perform frame processing.

[0074] After the DSP responds to an interrupt, it reads the frame length field from the receive buffer to obtain the total number of data bytes contained in the frame, and verifies whether the read length is within a reasonable range specified by the protocol. In this embodiment, it is limited to 8-20 bytes. If it exceeds the range, the frame is discarded and the buffer is cleared. For frames with a valid length, the DSP performs cyclic redundancy check (CRC) calculations on all data bytes after the frame header and before the checksum, starting from the buffer's starting address. This embodiment uses CRC-16 / IBM polynomials, and the generator polynomial is... Its hexadecimal representation is 0x8005. The CRC calculation process proceeds byte by byte according to the following recursive relationship:

[0075]

[0076] For each data byte currently involved in the calculation First, shift it left by 8 bits and then combine it with the previous CRC register value. Perform an XOR operation, then right-shift the result bit by bit. If the shifted-out bit is 1, XOR it with the polynomial 0x8005. Repeat this process 8 times before moving to the next byte. To process the CRC register value after the j-th byte, the value of j starts from 1, with an initial value of... After all data bytes have been processed, the final CRC result is 16 bits. The DSP compares this calculation result with the two-byte checksum attached to the end of the frame. If they match perfectly, the frame data is considered valid. If they do not match, an error has occurred during transmission. The frame is immediately discarded, the receive buffer is cleared, no parameters are updated, and the current control mode remains unchanged.

[0077] For valid frames that pass verification, the DSP further extracts the opcode (1 byte) from the instruction type field in the frame. In this embodiment, opcode 0x01 is predefined to represent a power limiting instruction, 0x02 to represent a recovery instruction, and other values ​​are invalid instructions. If the opcode is 0x01, it is confirmed as a power limiting instruction, and the DSP continues to locate the beginning of the data field. The data field contains a total of 4 bytes: the first two bytes are the output voltage limit value. The data are combined into a 16-bit unsigned integer in big-endian format (most significant byte first, least significant byte last) and stored in the first limiting register inside the DSP. The last two bytes are the output power limit. Similarly, the data is combined into a 16-bit integer in big-endian format and stored in the second limiting register. The above combination relationship can be expressed as:

[0078]

[0079]

[0080] in, For the high-order byte of the voltage-limited field, The least significant byte; For the high byte of the power limit field, This is the least significant byte. The values ​​of both limiting registers are stored in two's complement form, with the actual physical dimensions determined by the communication protocol. After the parameters are stored, the DSP sets its internal control mode flag from 0 to 1 (0 represents voltage tracking mode, 1 represents controlled output mode), indicating that the control logic has switched from adaptive tracking to controlled limiting mode. If the opcode is a recovery instruction (0x02), the DSP does not extract the limiting parameters, but still sets the mode flag to 1, with recovery triggered subsequently by the timer timeout processing flow.

[0081] When the AC / DC conversion module is in controlled output mode, the digital signal processor first reads the current bus voltage digital quantization value from its internal register at the beginning of each control cycle. Simultaneously, it reads the output voltage limit value issued by the central controller from the first limiting register. The DSP compares the two values ​​and determines the upper limit of the output voltage for the current cycle based on the comparison result. The specific judgment logic is as follows: if > This indicates that the current bus voltage has exceeded the limit set by the communication command. To prevent the bus voltage from rising further, the DSP will... As a given upper limit; if ≤ If the bus voltage itself is still within the allowable range, the DSP will... Given an upper limit, the above relationship can be expressed as:

[0082]

[0083] in, Set an upper limit for the output voltage of the current control cycle. The output voltage limit value carried in the communication command. This is the digitally quantized value of the current bus voltage. This upper limit determines the maximum target output voltage that can be achieved in this cycle.

[0084] While determining the upper limit of the voltage, the DSP acquires the current signal at the DC output terminal of the AC / DC converter module. Specifically, a precision shunt resistor is connected in series in the output circuit. The slight voltage drop across the shunt resistor is amplified by a differential amplifier and sent to the DSP's analog-to-digital conversion input channel. The DSP reads the conversion value from this channel and converts it into the actual digital value of the output current. At the same time, the DSP reads the current actual digital value of the output voltage from the output voltage feedback channel. Multiplying the two values ​​gives the actual output power of the AC / DC converter module. :

[0085]

[0086] The DSP then reads the output power limit value from the second limit register. The system calculates the power deviation. If the power deviation is greater than 0, it indicates that the current output power has exceeded the limit and power limitation adjustment is required; if the power deviation is less than or equal to 0, it indicates that the output power has not exceeded the limit and no power correction is required.

[0087] When the power deviation is greater than 0, the DSP will... The voltage is fed into a proportional-integral (PI) regulator. This PI regulator takes the power deviation as input and outputs a negative voltage correction. This is used to lower the output voltage setpoint to reduce output power. The discrete recursive relationship of the PI regulator is:

[0088]

[0089] in, The proportional gain of the power loop, This is the integral gain of the power loop. This is the cumulative sum of power deviations from the start of entering controlled mode to the current cycle. This is the voltage correction amount for the current cycle output. This correction amount is negative, and its absolute value dynamically changes with the degree and duration of power overrun. The DSP will calculate the... Superimposed on a given upper limit of voltage The above yields the corrected final given value. .because If the value is negative, the corrected setpoint is lower than the original upper limit, and the corresponding output power decreases until the actual power falls below the limit. After the power deviation becomes negative, the correction value output by the PI regulator gradually returns to zero. If the power deviation is less than or equal to 0, then the setting is directly zero. No power correction is performed. Final setpoint It is fed into the PWM duty cycle regulation stage to achieve dual constraints on voltage and power.

[0090] During controlled output mode, the DSP internally maintains a decrementing timer for communication timeout monitoring. The initial value of this timer is set to a preset timeout threshold, and it automatically decrements by 1 at the start of each control cycle. Simultaneously, the DSP checks whether the RS485 communication circuit has received a valid control command frame in each control cycle. If a valid power limiting command from the central controller is successfully received in the current cycle, the timer is immediately reset and decrementing resumes. If the timer's current value reaches 0, a communication timeout is determined. At this point, the DSP immediately restores the control mode flag from 1 to 0, clears and releases both the first and second limiting registers, stops the controlled output mode, and switches the control logic back to voltage tracking mode.

[0091] If the DSP detects that the RS485 communication circuit has received a new valid instruction frame while the timer has not decremented to 0, and after parsing it is found that the instruction frame opcode is a recovery instruction, the DSP will not wait for the timer to expire and will immediately perform a mode switching operation: clear the control mode flag bit, clear the two limit registers, directly switch to voltage tracking mode, and reset the timer at the same time.

[0092] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this specification. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0093] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0094] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A DC power supply control method for a base station based on micro-wind power generation, characterized in that, include: The wide-range alternating current output from the micro wind turbine is connected to the AC input port of the AC / DC converter module, and the DC output port of the AC / DC converter module is connected in parallel to the DC bus of the base station to establish a power transmission path from the generator set through the AC / DC converter module to the bus. A resistor voltage divider sampling network is set up between the positive and negative buses of the base station DC bus. The low voltage signal is led out from the voltage divider node, isolated and amplified, and then sent to the analog-to-digital conversion port inside the AC / DC conversion module. The digital signal processor reads and calculates the digital quantization value of the bus voltage at a fixed sampling period. When no external limiting command is received, the digital signal processor uses the digital quantization value of the bus voltage as the output target setpoint, and adjusts the pulse width modulation duty cycle of the internal switching transistor of the AC / DC conversion module through closed loop. When the bus voltage increases, the duty cycle is increased, and when the bus voltage decreases, the duty cycle is decreased. When the base station central controller sends a control command to the AC / DC conversion module through the RS485 communication bus, the digital signal processor receives and verifies the command frame, parses out the output voltage limit value and the output power limit value, and switches the control mode from voltage tracking mode to controlled output mode. In controlled output mode, the digital signal processor compares the actual bus voltage value with the output voltage limit value, and compares the actual output power value of the module with the output power limit value. It selects the more stringent condition as the final control constraint and dynamically adjusts the pulse width modulation duty cycle to ensure that the output voltage and output power do not exceed the limit value. When the communication times out or a recovery command is received, the digital signal processor switches back to voltage tracking mode.

2. The DC power supply control method for a base station based on micro-wind power generation according to claim 1, characterized in that, The aforementioned resistor divider sampling network, which extracts low-voltage signals from the divider nodes, amplifies them through isolation, and then sends them to the analog-to-digital conversion port inside the AC / DC converter module, specifically includes: A first voltage divider resistor and a second voltage divider resistor are connected in series between the positive and negative terminals of the DC bus of the base station. The upper end of the first voltage divider resistor is connected to the positive terminal, and the lower end is connected to the upper end of the second voltage divider resistor. The lower end of the second voltage divider resistor is connected to the negative terminal. A low-voltage sampling signal with an amplitude lower than the bus voltage is taken out from the connection node of the first voltage divider resistor and the second voltage divider resistor. The low-voltage sampling signal is sent to the input side of the linear optocoupler isolation amplifier. The output side of the linear optocoupler isolation amplifier outputs a differential voltage signal that is proportional to the low-voltage sampling signal. After high-frequency noise is filtered out by a filter capacitor, the signal is connected to the analog-to-digital conversion differential input pin of the digital signal processor in the AC / DC conversion module. The analog-to-digital converter built into the digital signal processor continuously samples the differential input pins and calculates the arithmetic mean as the digital quantization value of the bus voltage for the current control cycle.

3. The DC power supply control method for a base station based on micro-wind power generation according to claim 1, characterized in that, The specific steps of adjusting the pulse width modulation duty cycle of the internal switching transistors of the AC / DC converter module via closed-loop control include: Read the historical value of the bus voltage stored in the previous control cycle, combine it with the digital quantized value of the bus voltage in the current control cycle, and calculate the difference between the two to obtain the instantaneous change in the bus voltage. The digital signal processor determines whether the absolute value of the instantaneous change is less than the preset voltage change threshold. If it is less than the threshold, the bus voltage is determined to be in a stable state. The digital signal processor uses the current bus voltage digital quantization value as the given target of the proportional-integral regulator. The proportional-integral regulator outputs the duty cycle adjustment amount according to the error between the given target and the actual output voltage feedback value, so that the actual output voltage smoothly approaches the bus voltage. If the absolute value of the instantaneous change is greater than or equal to the preset voltage change threshold, the bus voltage is determined to be in a jumping state. In each control cycle, the digital signal processor increases or decreases the given target by a fixed step based on the current value until the given target reaches the current digital quantization value of the bus voltage. In each cycle, the instantaneous change is recalculated and the judgment is repeated.

4. The DC power supply control method for a base station based on micro-wind power generation according to claim 3, characterized in that, When adjusting the pulse width modulation duty cycle, input voltage feedforward compensation is introduced to accelerate the response, specifically including: An AC voltage sampling circuit is set at the AC input port of the AC / DC conversion module. The secondary signal of the input AC voltage is obtained through a voltage transformer. After full-wave rectification and RC filtering, the secondary signal is used to obtain a DC level signal that reflects the effective value of the input voltage, and then connected to the auxiliary analog-to-digital conversion input channel of the digital signal processor. In each control cycle, the digital signal processor reads the digital value of the DC level signal as the current input voltage amplitude, subtracts the current input voltage amplitude from the input voltage amplitude stored in the previous control cycle to obtain the amount of change in the input voltage, and records the direction of change. The digital signal processor calculates the feedforward compensation coefficient based on the obtained input voltage change and direction. When the input voltage increases, the feedforward compensation coefficient is positive. The digital signal processor multiplies the feedforward compensation coefficient by a preset scaling factor to obtain the feedforward duty cycle increment. The feedforward duty cycle increment is then superimposed on the feedback duty cycle adjustment output of the proportional-integral controller to synthesize the final duty cycle control quantity and output it to the pulse width modulation generator. When the input voltage decreases, the feedforward compensation coefficient becomes negative, and the feedforward duty cycle increment becomes negative. This is superimposed on the feedback regulation to achieve the output voltage's advance suppression of input voltage fluctuations.

5. The DC power supply control method for a base station based on micro-wind power generation according to claim 1, characterized in that, When the bus voltage decreases and the duty cycle is reduced, a cycle-by-cycle limiting voltage reduction is used to prevent overmodulation, specifically including: The digital signal processor calculates the difference between the current bus voltage digital quantization value and the current actual output voltage feedback value. If the difference is negative, it determines that the output voltage needs to be reduced, and the absolute value of the difference is taken as the total amount of voltage reduction required. The digital signal processor compares the total voltage reduction with the preset maximum allowable voltage reduction step size per single cycle. If the total voltage reduction is less than or equal to the step size, the digital signal processor directly uses the digital quantized value of the bus voltage as the new given target, calculates the duty cycle adjustment amount, and adjusts it to the correct position in one go. If the total voltage drop exceeds the preset maximum allowable step size for a single cycle, the digital signal processor sets the given target for the current control cycle to the value of the current actual output voltage minus the step size, and deducts the step size from the total voltage drop. In the next control cycle, the remaining total voltage drop is recalculated, and the comparison and adjustment process is repeated until the remaining total voltage drop is zero. The actual voltage drop in each control cycle does not exceed the preset step size.

6. The DC power supply control method for a base station based on micro-wind power generation according to claim 1, characterized in that, The digital signal processor receives and verifies instruction frames specifically including: The RS485 communication circuit continuously monitors the serial data on the bus. When it detects the start byte that matches the protocol frame header characteristics, it receives subsequent data bytes and stores the received bytes in the receive buffer in sequence. When it receives the end byte of the frame, the communication circuit triggers a receive completion interrupt signal to the digital signal processor. After the digital signal processor responds to the interrupt, it reads the entire frame data from the receive buffer, extracts the frame length field, reads all data bytes according to the length, performs cyclic redundancy check calculation on the data bytes from the frame header to the check code, compares the calculated check value with the check code attached to the frame tail bit by bit, if they are completely consistent, the frame data is determined to be valid, if they are inconsistent, the frame is discarded and the buffer is cleared, without any parameter updates. The valid frame data is parsed, and the opcode is extracted from the instruction type field of the frame. If the opcode is a power limiting instruction, the voltage limit value of two bytes is extracted from the voltage limit field of the frame, and the two bytes are combined into a sixteen-bit integer with the high byte first and the low byte last and stored in the first limiting register. The power limit value of two bytes is extracted from the power limit field and stored in the second limiting register. At the same time, the internal control mode flag is set from 0 to 1, and the flag is switched to the controlled output mode.

7. A DC power supply control method for a base station based on micro-wind power generation according to claim 1, characterized in that, The comparison of the actual bus voltage value with the output voltage limit value and the comparison of the actual output power value of the module with the output power limit value specifically include: The digital signal processor reads the current bus voltage digital quantization value and the output voltage limit value in the first limit register. The two are subtracted. If the bus voltage is greater than the limit value, the digital signal processor uses the output voltage limit value as the upper limit of the output voltage for the current cycle. If the bus voltage is less than or equal to the limit value, the bus voltage itself is used as the upper limit. The digital signal processor acquires the current sensor signal at the DC output terminal of the AC / DC converter module, obtains the digital value of the output current after analog-to-digital conversion, multiplies the current digital value of the actual output voltage by the digital value of the output current to obtain the actual output power value, reads the output power limit value in the second limit register, and subtracts the actual output power value from the limit value to obtain the power deviation. If the obtained power deviation is greater than zero, the digital signal processor sends the power deviation to the proportional-integral regulator, which outputs a negative correction amount. This correction amount is superimposed on the determined upper limit of the output voltage to obtain the corrected final set value, so that the output power corresponding to the corrected set value is reduced to below the limit value. If the power deviation is less than or equal to zero, no power correction is needed, and the given upper limit is directly used as the final given value.

8. The DC power supply control method for a base station based on micro-wind power generation according to claim 1, characterized in that, The specific steps for the digital signal processor to switch back to voltage tracking mode when communication times out or a recovery command is received include: The digital signal processor has an internal decrementing timer with an initial value of a preset timeout threshold. The timer automatically decrements by 1 at the beginning of each control cycle. When a valid control command is successfully received, the timer is reset to the initial threshold and decrements again. The digital signal processor detects the current value of the decrementing timer in each control cycle. If the current value is reduced to zero, it determines that the communication has timed out, restores the control mode flag from 1 to 0, clears the values ​​in the first and second limit registers, stops the controlled output mode, and switches to the execution voltage tracking mode. If the timer does not decrement to zero, the digital signal processor continues to check whether the RS485 communication circuit has received a new valid instruction frame. If it is received and the opcode in the instruction frame is a recovery instruction, the digital signal processor does not wait for the timer to expire, immediately clears the control mode flag and the limiting register, directly switches to the voltage tracking mode, and resets the timer to its initial value.

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