Voltage dip fast response oscillation control method based on physical constraint layout

Abstract

The application discloses a voltage drop rapid response oscillation control method based on physical constraint layout, comprising: constructing a biaxial delay line physical constraint layout architecture, setting a time delay unit grid arrangement pitch according to an oscillation frequency distribution and constructing a time delay matching path of a feedback oscillation loop, introducing a biaxial time delay adaptive anti-interference regulation algorithm to generate a preliminary oscillation suppression signal, inputting the preliminary suppression signal into an oscillation mode time domain entropy discrimination function to calculate a time domain entropy value and output a mode discrimination label, activating a time delay unit nonlinear correction function according to the mode discrimination label to perform amplitude distortion correction and phase offset compensation, feeding the corrected signal into the feedback oscillation loop and iteratively updating the time delay matching path until the time domain entropy value converges, and then loading different test cases on a power supply drop multi-scene simulation verification platform to verify the suppression effect. The method realizes rapid response and stable suppression of voltage drop oscillation through the cooperation of physical layout constraints and an adaptive regulation algorithm.

Description

Technical Field

[0001] This invention relates to the field of voltage sag response control technology, and in particular to a voltage sag fast response oscillation control method based on physical constraint layout. Background Technology

[0002] The frequent occurrence of voltage dips in modern power electronic systems, accompanied by high-frequency oscillations, seriously threatens the normal operation of sensitive load equipment. With the increase in the grid-connected capacity of distributed power sources and the growing proportion of nonlinear loads, voltage dip waveforms exhibit characteristics such as time-varying oscillation frequencies, complex modes, and extremely short transient response times. Traditional fixed-parameter compensation methods are difficult to adapt to the rapid switching of oscillation modes, necessitating new solutions that combine time-delay physical layout with signal processing algorithms.

[0003] Existing technologies for suppressing voltage sag oscillations generally employ a Fourier transform-based spectral analysis method to extract the dominant oscillation frequency. Based on this, fixed time delay compensation parameters are set, and a PID-type feedback regulator is used to compensate for the amplitude of the voltage sag. Some solutions also introduce a lookup table method to store preset correction coefficients for several typical operating conditions to address different sag depth scenarios. Other implementations use a digital signal processor to construct oscillation discrimination logic. This logic triggers the switching action of the time delay unit by calculating the root mean square value or peak value change rate of the waveform. The voltage deviation is then converted from analog to digital and sent to a microcontroller, which outputs a pulse width modulation signal to drive the compensation circuit.

[0004] However, the aforementioned existing technologies have two drawbacks. First, time delay compensation mechanisms based on fixed spectrum analysis or lookup table presets lack the ability to adaptively adjust to the time-varying characteristics of oscillation modes. When the oscillation frequency drifts or the mode transitions caused by the drop, the preset time delay parameters cannot match the actual oscillation state, resulting in a delayed compensation response and a deterioration in the suppression effect. Second, the time delay units inside conventional digital signal processors lack constraints and optimization at the physical spatial arrangement level. The time delay matching path has uncertain parasitic parameter interference in electrical connections. In addition, the nonlinear distortion caused by signal amplitude saturation is not effectively corrected, causing the oscillation suppression signal to generate amplitude-phase coupling errors during the transient response, affecting the convergence stability of the control system. Summary of the Invention

[0005] To overcome the shortcomings and deficiencies of existing technologies, this invention provides a voltage dip fast response oscillation control method based on physical constraint layout.

[0006] The technical solution adopted in this invention is a voltage sag fast response oscillation control method based on physical constraint layout, comprising the following steps: S1, constructing a dual-axis delay line physical constraint layout architecture, setting the grid spacing of the delay unit according to the oscillation frequency distribution during the voltage sag transient process, and constructing the time delay matching path of the feedback oscillation loop; S2, introducing a dual-axis time delay adaptive disturbance rejection control algorithm, adjusting the time delay compensation coefficients of the forward channel and the feedback channel according to the real-time captured voltage deviation, and generating a preliminary oscillation suppression signal; S3, inputting the preliminary oscillation suppression signal into the oscillation mode time domain entropy discriminant function to calculate the current oscillation wave. S4. Based on the mode discrimination label, the nonlinear correction function of the time delay unit is activated to perform amplitude distortion correction and phase shift compensation on the preliminary oscillation suppression signal, generating a corrected oscillation suppression signal; S5. The corrected oscillation suppression signal is fed into the feedback oscillation loop, the physical tap position of the time delay unit is adjusted, and the time delay matching path is iteratively updated until the time domain entropy value converges to the preset threshold range; S6. Based on the power supply drop multi-scenario simulation verification platform, test cases with different drop depths and drop durations are loaded to verify the oscillation suppression effect.

[0007] Furthermore, the expression for the dual-axis time-delay adaptive disturbance rejection control algorithm is as follows: ,in Characterizing the time-domain cumulative deviation control amount, Characterizes the current time parameter. Characterizing the width of the time delay window, Characterizing the cumulative gain coefficient of deviation, Characterization The instantaneous value of the voltage deviation at time t. Characterization The confidence weighting factor for the deviation at time. Characterizing the integral variable; based on the above Construct forward compensation quantity ,in The output value representing the time delay compensation of the forward channel. Characterizes the scaling factor of the compensation amplitude. Characterization bias sensitive attenuation coefficient, The instantaneous value of the voltage deviation at the current moment is represented by exp, which represents the natural exponent operation.

[0008] Furthermore, the expression for the oscillation mode time-domain entropy discriminant function is: in The time-domain entropy criterion value characterizing the oscillation waveform. Characterizes the total number of time-domain segmentation sub-intervals. Characterizing the first The normalized probability of the oscillation amplitude occurring within each sub-interval A regularized minima representing the avoidance of singularities. Representing the base-2 logarithmic operation; based on the above Construct the mode belonging discriminant ,in The modality discrimination label representing the output, Index variables representing modal categories, Characterizing the length of the observation time window, Characterization The instantaneous amplitude of the oscillation at time t. Characterizing the first Modal reference amplitude benchmark Characterizing the first Entropy weight mapping coefficients of class modes Characterizes the integral time variable.

[0009] Furthermore, the expression for the nonlinear correction function of the time delay unit is: in Characterizing the amplitude of the output signal after nonlinear correction, Characterizing the instantaneous amplitude of the input signal, Characterizing the linear magnitude scaling reference factor, Characterizing the nonlinear distortion adjustment coefficient, Characterizing the arctangent nonlinear mapping operation, Characterizing the amplitude compression sensitivity coefficient, Characterization based on phase deviation Phase compensation factor, It represents the instantaneous value of the phase deviation of the current output signal relative to the input signal.

[0010] Furthermore, the physical constraint layout architecture of the dual-axis delay line includes a programmable electronically controlled delay unit array arranged along the orthogonal dual-axis direction. Each delay unit adopts a tapped delay chain structure based on gallium nitride high-speed switching transistors. The grid spacing is set according to the half wavelength of the main frequency component of the voltage drop oscillation spectrum. The feedback oscillation circuit includes a transconductance amplification stage and a level clamping stage. The iterative update of the delay matching path changes the delay amount by adjusting the tap selection register value of each delay unit. The judgment condition for the time domain entropy value to converge to the preset threshold range is that the relative change rate of the time domain entropy value calculated by three consecutive iterations is less than a set percentage. The voltage deviation is picked up in real time at the common coupling point by a differential probe group. The preliminary oscillation suppression signal is fed into the front end of the tapped delay chain structure via a digital-to-analog converter.

[0011] Further, S2 includes the following sub-steps: S21, capturing the instantaneous voltage waveform at the common coupling point and extracting the instantaneous voltage deviation value; S22, based on the instantaneous voltage deviation value, querying the preset time delay compensation parameter table to obtain the time delay window width corresponding to the current operating condition; S23, substituting the instantaneous voltage deviation value and the time delay window width into the dual-axis time delay adaptive anti-disturbance control algorithm to calculate the time-domain cumulative deviation control amount; S24, based on the time-domain cumulative deviation control amount, generating the time delay compensation output amount of the forward channel as the preliminary oscillation suppression signal.

[0012] Further, S3 includes the following sub-steps: S31, extracting the discrete amplitude sequence of the current oscillation waveform within the observation window; S32, dividing the discrete amplitude sequence into several sub-intervals according to the amplitude interval, and counting the frequency of amplitude occurrence in each sub-interval; S33, calculating the normalized occurrence probability of each sub-interval based on the occurrence frequency of each sub-interval; S34, substituting the normalized occurrence probability of each sub-interval into the oscillation mode time-domain entropy discriminant function, calculating the time-domain entropy criterion value, comparing the time-domain entropy criterion value with the reference entropy value of each mode, and outputting the mode discrimination label.

[0013] Further, step S4 includes the following sub-steps: S41, reading the nonlinear correction parameter group corresponding to the mode based on the mode discrimination tag; S42, using the current amplitude of the preliminary oscillation suppression signal as the input signal amplitude, inputting it into the nonlinear correction function of the time delay unit; S43, capturing the phase deviation of the preliminary oscillation suppression signal relative to the original voltage deviation signal, and generating a phase compensation factor; S44, performing amplitude distortion correction and phase offset compensation on the input signal amplitude and the phase compensation factor in the nonlinear correction function of the time delay unit, and outputting the corrected oscillation suppression signal.

[0014] Further, step S5 includes the following sub-steps: S51, feeding the corrected oscillation suppression signal into the feedback oscillation loop and measuring the actual delay at each delay unit tap; S52, calculating the tap position adjustment step size for each delay unit based on the deviation between the actual delay and the target delay; S53, driving the tap selection register of each delay unit to update its value based on the tap position adjustment step size, thereby changing the delay of each delay unit; S54, recalculating the time-domain entropy value of the updated feedback oscillation loop, determining whether the time-domain entropy value converges to a preset threshold range, and repeating the tap position adjustment step if it does not converge.

[0015] A voltage sag fast response oscillation control method based on physical constraint layout is implemented through a voltage sag fast response oscillation control system based on physical constraint layout. The method includes: a dual-axis orthogonal time-delay grid array arrangement module, used to set the physical spacing of the time-delay units in the orthogonal dual-axis direction according to the voltage sag transient oscillation frequency distribution, constructing a time-delay matching path for the feedback oscillation loop; a dual-axis time-delay adaptive deviation accumulation compensation module, with its input connected to the output of the dual-axis orthogonal time-delay grid array arrangement module, used to adjust the time-delay compensation coefficient and generate a preliminary oscillation suppression signal based on the real-time captured voltage deviation; and an online oscillation mode time-domain entropy discrimination module, with its input connected to the output of the dual-axis time-delay adaptive deviation accumulation compensation module, used to calculate the time-domain entropy value of the oscillation waveform and output the mode judgment. The system includes: a nonlinear amplitude-phase joint correction module for time delay units, whose input is connected to the output of the online time-domain entropy discrimination module for oscillation modes, used to correct amplitude distortion and compensate phase shift of the initial oscillation suppression signal based on the mode discrimination label; a tap position iterative optimization feedback adjustment module, whose input is connected to the output of the nonlinear amplitude-phase joint correction module for time delay units, and whose output is connected to the feedback input of the dual-axis orthogonal time delay grid array arrangement module, used to feed the corrected oscillation suppression signal into the feedback oscillation loop and iteratively update the time delay matching path; and a multi-scenario drop condition simulation excitation loading module, whose output is connected to the test input of the dual-axis orthogonal time delay grid array arrangement module, used to load test cases with different drop depths and drop durations to verify the oscillation suppression effect.

[0016] Beneficial Effects: This invention proposes a voltage sag fast response oscillation control method based on physical constraint layout. It uses a physical constraint layout of the time delay unit grid spacing in the dual-axis orthogonal directions according to the oscillation frequency distribution. Combined with the construction of the time delay matching path in the feedback oscillation loop, this makes the physical basis of time delay compensation deterministic, reducing the interference of parasitic parameters on time delay accuracy. Simultaneously, a dual-axis time delay adaptive disturbance rejection control algorithm is used to capture the voltage deviation in real time and dynamically adjust the time delay compensation coefficient. This is combined with an oscillation mode time-domain entropy discriminant function to perform online discrimination of the oscillation mode. Based on the discrimination result, the nonlinear correction function of the time delay unit is activated to jointly correct amplitude distortion and phase shift. The corrected signal is fed into the feedback oscillation loop and the time delay matching path is iteratively updated until the time-domain entropy value converges, thus enabling... The time delay compensation parameters can be adaptively adjusted to follow the real-time changes of the oscillation mode, solving the shortcomings of fixed spectrum analysis or lookup table preset schemes that cannot adapt to oscillation frequency drift and mode transitions. At the same time, the tap delay chain structure based on gallium nitride high-speed switching transistors, combined with iterative optimization feedback adjustment of tap position, enables deterministic constraints and dynamic optimization of the time delay matching path at the physical layout and electrical connection levels. Combined with the comprehensive test coverage of different drop depths and durations by the multi-scenario drop condition simulation verification platform, the uncertain parasitic parameter interference introduced by the lack of physical layout optimization of the internal time delay unit of the digital signal processor and the amplitude-phase coupling error caused by signal amplitude saturation are eliminated, thus improving the convergence stability and mode adaptive tracking capability of the oscillation suppression system in the transient response process. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the overall process of the method of the present invention.

[0018] Figure 2 This is a flowchart of method step S2 of the present invention;

[0019] Figure 3 This is a flowchart of method step S3 of the present invention;

[0020] Figure 4 This is a flowchart of method step S4 of the present invention;

[0021] Figure 5 This is a flowchart of step S5 of the method of the present invention. Detailed Implementation

[0022] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] like Figure 1As shown, a voltage sag fast response oscillation control method based on physical constraint layout is characterized by the following steps: S1, constructing a dual-axis delay line physical constraint layout architecture, setting the grid spacing of the delay units according to the oscillation frequency distribution during the voltage sag transient process, and constructing a time delay matching path for the feedback oscillation loop; S2, introducing a dual-axis time delay adaptive disturbance rejection control algorithm, adjusting the time delay compensation coefficients of the forward and feedback channels according to the real-time captured voltage deviation, and generating a preliminary oscillation suppression signal; S3, inputting the preliminary oscillation suppression signal into the oscillation mode time domain entropy discriminant function to calculate the current oscillation waveform. S4. Based on the mode discrimination label, the nonlinear correction function of the time delay unit is activated to perform amplitude distortion correction and phase shift compensation on the preliminary oscillation suppression signal, generating a corrected oscillation suppression signal; S5. The corrected oscillation suppression signal is fed into the feedback oscillation loop, the physical tap position of the time delay unit is adjusted, and the time delay matching path is iteratively updated until the time domain entropy value converges to a preset threshold range; S6. Based on the power supply drop multi-scenario simulation verification platform, test cases with different drop depths and drop durations are loaded to verify the oscillation suppression effect.

[0024] In step S1, a physical constraint layout architecture for the dual-axis delay line is constructed. Delay unit arrays are arranged on the insulating substrate along mutually orthogonal X and Y axes. Each delay unit adopts a tapped delay chain structure based on gallium nitride high-speed switches, with a total of 128 taps. Based on the distribution range of the oscillation frequency during the voltage drop transient, obtained through Fast Fourier Transform, the dominant frequency component is typically concentrated between 150Hz and 450Hz. Half the wavelength of the dominant frequency component is used as the basis for setting the grid spacing, corresponding to a delay step reference value of 0.8μs. Sixteen delay units are arranged along the X-axis and sixteen along the Y-axis, forming a 16x16 grid array. The tap position of each delay unit is controlled by an 8-bit binary value in the tap selection register. The feedback oscillation circuit consists of a transconductance amplifier stage and a level clamping stage connected in series. The transconductance gain of the transconductance amplifier stage is set to 25ms, and the clamping voltage of the level clamping stage is set to ±5V. The delay matching path is constructed by traversing each grid node along the X-axis from the input of the feedback oscillation loop to the target coordinates, then turning to the Y-axis and continuing to traverse to the output, forming an L-shaped or Z-shaped trace path. The total delay corresponding to the total path length is continuously adjustable in the range of 1.6μs to 8.0μs. The physical pin spacing of each delay unit is set to 2.54mm to ensure deterministic delay of signal transmission between adjacent units.

[0025] In step S2, a dual-axis time-delay adaptive anti-interference control algorithm is introduced. A differential probe group is used to acquire three-phase voltage signals in real time at the common coupling point. The bandwidth of the differential probe group is set to 1MHz, and the sampling rate is set to 200kS / s. Instantaneous values ​​are extracted from the acquired three-phase voltage signals. The difference between the voltage amplitude at the current sampling moment and the rated voltage amplitude is calculated. The rated voltage amplitude is set to 311V. A voltage deviation event is triggered when the absolute value of the difference exceeds 5V. Based on the real-time captured voltage deviation, a preset time-delay compensation parameter table is consulted. This parameter table is divided into nine levels from 0.1pu to 0.9pu based on the drop depth. Each level corresponds to a time-delay window width value, ranging from 0.5ms to 4.0ms. When the drop depth is 0.5pu, the corresponding time-delay window width is 1.8ms. After substituting the instantaneous voltage deviation value and the time delay window width obtained from the lookup table into the algorithm, the time delay compensation coefficients of the forward and feedback channels are adjusted. The compensation coefficient of the forward channel ranges from 0.3 to 0.9, and the compensation coefficient of the feedback channel ranges from 0.1 to 0.7. After accumulating and weighting the voltage deviation and the compensation coefficients, a preliminary oscillation suppression signal is generated. This signal is in the form of an analog voltage with an amplitude range of ±10V, and is fed into the subsequent processing stage via a digital-to-analog converter.

[0026] In step S3, the preliminary oscillation suppression signal is input into the oscillation mode time-domain entropy discriminant function. First, a discrete amplitude sequence of the current oscillation waveform within the observation window is extracted. The observation window length is set to 10ms, including 2000 sampling points. The extracted discrete amplitude sequence is divided into 32 sub-intervals according to the amplitude range. The amplitude width of each sub-interval is set to 0.625V, and the total amplitude coverage range is ±10V. The frequency of amplitude occurrence in each sub-interval is statistically counted, and the count value is divided by the total number of sampling points 2000 to obtain the normalized occurrence probability of each sub-interval. The time-domain entropy criterion value is calculated based on the normalized occurrence probability of each sub-interval. The output range of the time-domain entropy criterion value is between 0.5 and 4.5. The calculated time-domain entropy criterion value is compared item by item with the pre-stored reference entropy values ​​for five modes: underdamped oscillation mode, critically damped oscillation mode, overdamped oscillation mode, intermittent oscillation mode, and high-frequency harmonic superposition mode. The corresponding reference entropy values ​​for each mode are 2.1, 3.0, 3.8, 1.6, and 4.2, respectively. The mode category with the smallest absolute deviation between the time-domain entropy criterion value and the reference entropy value is selected as the current oscillation mode, and a mode discrimination label is output. This label uses a 3-bit binary code to represent the above five modes.

[0027] In step S4, the nonlinear correction parameter set corresponding to the mode is read from the non-volatile memory based on the mode discrimination tag. The parameter set includes the linear amplitude scaling reference coefficient, the nonlinear distortion adjustment coefficient, and the amplitude compression sensitivity coefficient. The three parameters for the underdamped oscillation mode are 1.05, 0.12, and 0.35; for the critically damped mode, they are 0.98, 0.08, and 0.50; for the overdamped mode, they are 0.92, 0.05, and 0.65; for the intermittent mode, they are 1.12, 0.18, and 0.25; and for the high-frequency harmonic superposition mode, they are 0.88, 0.22, and 0.45. The current amplitude of the preliminary oscillation suppression signal is used as the input signal amplitude. The read three parameters are substituted into the nonlinear correction function of the time delay unit to perform amplitude distortion correction. The scaling ratio of the corrected amplitude relative to the input amplitude varies in the range of 0.80 to 1.25. The phase deviation of the initial oscillation suppression signal relative to the original voltage deviation signal is captured. The phase deviation is measured using a zero-crossing detection method with a measurement accuracy of 0.5 degrees and a deviation range between -30 degrees and +30 degrees. A phase compensation factor is generated based on the phase deviation, with a value ranging from 0.85 to 1.15. The amplitude-corrected signal is multiplied by this phase compensation factor to achieve phase shift compensation, outputting a corrected oscillation suppression signal with an amplitude range of ±12V.

[0028] In step S5, the corrected oscillation suppression signal is fed into the feedback oscillation circuit via the drive amplifier stage. The voltage gain of the drive amplifier stage is set to 2 times, and the output impedance is set to 50Ω. The actual delay at each delay unit tap is measured using the time-domain reflectometry method with a resolution of 0.05μs. The difference between the actual delay and the target delay is calculated. The target delay is calculated by dividing the period of the current oscillation frequency by 64. The current oscillation frequency is measured in real time using the zero-crossing detection method. Based on the difference result, the adjustment step size of the tap position of each delay unit is calculated using a proportional-integral method. The proportional coefficient is set to 0.6, the integral coefficient is set to 0.1, and the step size unit is the number of tap levels. The tap selection register of each delay unit is updated incrementally or decrementally according to the adjustment step size, with each update step not exceeding 4 levels. After updating, the time-domain entropy value of the feedback oscillation loop under the current time delay matching path is recalculated. The recalculated time-domain entropy value is compared with a preset threshold interval, with the lower limit set at 1.8 and the upper limit at 4.2. If the time-domain entropy value falls within this interval, convergence is determined and iteration stops; otherwise, the tap position measurement, step size calculation, and register update operations are repeated until convergence. The maximum number of iterations is set to 15.

[0029] In step S6, test cases are loaded based on a power supply drop multi-scenario simulation verification platform. This platform includes a real-time digital simulator and a power hardware-in-the-loop interface. The calculation step size of the real-time digital simulator is set to 50μs, and the voltage output range of the power hardware-in-the-loop interface is set to 0V to 400V. The loaded test cases are generated based on a combination of two dimensions: drop depth and drop duration. The drop depth is divided into 9 levels from 0.1pu to 0.9pu with a step size of 0.1pu, and the drop duration is divided into 12 levels from 20ms to 500ms with a logarithmic scale, generating a total of 108 test cases. The execution flow of each test case is as follows: the simulation platform outputs a voltage drop waveform, which is injected into the controlled object under test through a power amplifier with a bandwidth set to 5kHz. The time required for the controlled object under test to decay from the drop trigger moment to within ±2% of the steady-state amplitude under each test case is recorded as the response time index, and the ratio of the peak value of the amplitude overshoot during the oscillation to the steady-state amplitude is recorded as the overshoot index. The average values ​​of the response time and overshoot of the 108 test cases were calculated. The oscillation suppression effect was deemed to be satisfactory if the average response time did not exceed 3ms and the average overshoot did not exceed 5%.

[0030] Preferably, the expression for the dual-axis time-delay adaptive disturbance rejection control algorithm is: ,in Characterizing the time-domain cumulative deviation control amount, Characterizes the current time parameter. Characterizing the width of the time delay window, Characterizing the cumulative gain coefficient of deviation, Characterization The instantaneous value of the voltage deviation at time t. Characterization The confidence weighting factor for the deviation at time. Characterizing the integral variable; based on the above Construct forward compensation quantity ,in The output value representing the time delay compensation of the forward channel. Characterizes the scaling factor of the compensation amplitude. Characterization bias sensitive attenuation coefficient, The instantaneous value of the voltage deviation at the current moment is represented by exp, which represents the natural exponent operation.

[0031] Specifically, the establishment of the time-domain cumulative deviation control quantity in the dual-axis time-delay adaptive disturbance rejection control algorithm is based on the weighted integral theory of the historical trajectory of voltage deviation within a sliding time window. Its physical essence is the quantification of the continuous accumulation effect of deviation signals over a specific historical period. The integral operation can smooth instantaneous noise interference and reflect the cumulative trend of the deviation. The window width is determined based on the typical period of voltage drop oscillation. In the weighted processing, the deviation confidence weight factor is dynamically assigned according to the magnitude of the deviation. When the absolute value of the deviation is less than 10V, the weight factor is 0.6; when the absolute value of the deviation is between 10V and 30V, it is 0.9; and when the absolute value of the deviation is greater than 30V, it is 1.0. The deviation cumulative gain coefficient is set based on the system inertia constant, with a value between 0.05 and 0.20. The lower limit of integration in this expression is the current time minus the time-delay window width, and the upper limit of integration is the current time, ensuring that the cumulative amount depends only on a finite historical interval, avoiding numerical divergence from infinite integration. The forward compensation is established based on the nonlinear product relationship between the time-domain cumulative deviation control and the current instantaneous deviation value. The natural exponential decay operation is introduced to moderately compress the compensation output under large deviations to prevent overshoot. The deviation-sensitive decay coefficient is set to 0.08. The compensation amplitude scaling factor is set according to the forward channel gain, with a value between 0.5 and 1.2. The two expressions form a cascaded derivation logic. The forward compensation directly uses the time-domain cumulative deviation control as the core independent variable, achieving an ordered mapping from historical deviation accumulation to the current compensation output.

[0032] Preferably, the expression for the oscillation mode time-domain entropy discriminant function is: in The time-domain entropy criterion value characterizing the oscillation waveform. Characterizes the total number of time-domain segmentation sub-intervals. Characterizing the first The normalized probability of the oscillation amplitude occurring within each sub-interval A regularized minima representing the avoidance of singularities. Representing the base-2 logarithmic operation; based on the above Construct the mode belonging discriminant ,in The modality discrimination label representing the output, Index variables representing modal categories, Characterizing the length of the observation time window, Characterization The instantaneous amplitude of the oscillation at time t. Characterizing the first Modal reference amplitude benchmark Characterizing the first Entropy weight mapping coefficients of class modes Characterizes the integral time variable.

[0033] Specifically, the time-domain entropy criterion in the oscillation mode time-domain entropy discriminant function is established based on the uncertainty measurement method in information entropy theory, mapping the probability distribution of the oscillation waveform within the time-domain amplitude interval to a single scalar value. The number of amplitude sub-intervals is dynamically determined based on the total number of sampling points; when the number of sampling points is 2000, the number of sub-intervals is 32. The normalized occurrence probability is calculated by dividing the frequency of amplitude occurrence in each sub-interval by the total number of sampling points, and the sum of the probabilities of all sub-intervals is always equal to 1. The regularization factor to avoid singularities is set to 10 to the power of -10 to prevent the logarithmic operation from tending to negative infinity when the probability is zero. The mode attribution discriminant is based on the criterion of minimizing the deviation between the time-domain entropy criterion and the reference entropy values ​​of each mode, while introducing a mode entropy weight mapping coefficient to weight and modulate the deviation value. The observation time window length is 10ms, corresponding to two complete cycles of the oscillation waveform. The time integral of the instantaneous amplitude of the oscillation within the observation window divided by the observation time window length is equivalent to the time average of the amplitude. The reference amplitude for each mode is obtained by averaging typical waveforms for each mode: 30V for underdamped modes, 25V for critically damped modes, 20V for overdamped modes, 35V for intermittent modes, and 15V for high-frequency harmonic superposition modes. The entropy weighting mapping coefficients for each mode are determined based on the statistical variance of the amplitude fluctuation of each mode, with values ​​ranging from 0.7 to 1.3. This discriminant jointly compares the time-domain average deviation of the amplitude with the time-domain entropy criterion value, avoiding the risk of misclassification at boundary modes using a single entropy criterion.

[0034] Preferably, the expression for the nonlinear correction function of the time delay unit is: in Characterizing the amplitude of the output signal after nonlinear correction, Characterizing the instantaneous amplitude of the input signal, Characterizing the linear magnitude scaling reference factor, Characterizing the nonlinear distortion adjustment coefficient, Characterizing the arctangent nonlinear mapping operation, Characterizing the amplitude compression sensitivity coefficient, Characterization based on phase deviation Phase compensation factor, It represents the instantaneous value of the phase deviation of the current output signal relative to the input signal.

[0035] Specifically, the nonlinear correction function of the delay unit is modeled based on the nonlinear characteristics of the input-output amplitude response curve of the delay unit. The delay unit exhibits a saturation compression effect when the signal amplitude is large, and linear transmission characteristics when the signal amplitude is small, with the overall response curve showing an inverse S-shaped nonlinear shape. The linear amplitude scaling reference coefficient is set based on the measured transmission gain of the delay unit when the input signal amplitude is 1V, and is set to a value of 0.95. The nonlinear distortion adjustment coefficient controls the distortion intensity of the arctangent function, and is set to a value of 0.15, so that the nonlinear correction gradually increases from 0 to 18% of the input amplitude as the output signal changes from 0V to 10V. The amplitude compression sensitivity coefficient controls the inflection point of the nonlinear compression effect, and is set to a value of 0.40 per volt. This value ensures that the compression inflection point appears near the input amplitude of 2.5V, matching the actual saturation starting point of the delay unit. The phase compensation factor is obtained by interpolation through a lookup table based on the phase deviation; a change of 5 degrees in the phase deviation corresponds to a change of 0.025 in the compensation factor. The phase deviation was measured using a zero-crossing detection method with a resolution of 0.5 degrees. The expression multiplies the amplitude nonlinearity correction term by the phase compensation factor through a product operation, allowing amplitude correction and phase compensation to be processed jointly within the same mathematical framework, avoiding the amplitude-phase coupling mismatch problem introduced by separate corrections. The parameter values ​​were calibrated using a time delay unit frequency response test, covering a frequency range of 150Hz to 450Hz. The calibration results were stored in non-volatile memory for real-time retrieval.

[0036] Preferably, the dual-axis delay line physical constraint layout architecture includes a programmable electronically controlled delay unit array arranged along the orthogonal dual-axis direction. Each delay unit adopts a tapped delay chain structure based on gallium nitride high-speed switching transistors. The grid spacing is set according to the half wavelength of the main frequency component of the voltage drop oscillation spectrum. The feedback oscillation circuit includes a transconductance amplification stage and a level clamping stage. The iterative update of the delay matching path changes the delay amount by adjusting the tap selection register value of each delay unit. The judgment condition for the time domain entropy value to converge to a preset threshold range is that the relative change rate of the time domain entropy value calculated by three consecutive iterations is less than a set percentage. The voltage deviation is picked up in real time at the common coupling point by a differential probe group. The preliminary oscillation suppression signal is fed into the front end of the tapped delay chain structure via a digital-to-analog converter.

[0037] Preferably, step S2 includes the following sub-steps: S21, capturing the instantaneous voltage waveform at the common coupling point and extracting the instantaneous voltage deviation value; S22, based on the instantaneous voltage deviation value, querying a preset time delay compensation parameter table to obtain the time delay window width corresponding to the current operating condition; S23, substituting the instantaneous voltage deviation value and the time delay window width into the dual-axis time delay adaptive anti-disturbance control algorithm to calculate the time-domain cumulative deviation control amount; S24, based on the time-domain cumulative deviation control amount, generating the time delay compensation output amount of the forward channel as the preliminary oscillation suppression signal.

[0038] Specifically, in step S21, the three-phase voltage waveform is captured in real time at the common coupling point using a differential probe group. The common-mode rejection ratio of the differential probe group is set to 80dB, the bandwidth is set to 1MHz, the aperture time of the sample-and-hold circuit is set to 2ns, and the voltage signal of each phase is sent to the analog-to-digital converter after passing through an anti-aliasing filter. The analog-to-digital converter has a resolution of 12 bits and a sampling rate of 200kS / s. The instantaneous values ​​of the three-phase voltage are captured simultaneously in each sampling period and stored in the circular buffer. The buffer depth is set to 4096 sampling points. In step S22, the maximum absolute value of the difference between the instantaneous amplitude of the three-phase voltage at the current sampling moment and the rated voltage amplitude of 311V is calculated. This maximum value is divided by the rated voltage amplitude to obtain the voltage drop depth percentage. Based on the drop depth percentage, a preset time delay compensation parameter table is consulted. The parameter table is divided into 9 levels according to the drop depth from 0.1pu to 0.9pu, and each level corresponds to a time delay window width value. The window width value is distributed according to a non-linear curve in the range of 0.5ms to 4.0ms. When the drop depth is 0.3pu, the corresponding window width is 2.5ms, and when the drop depth is 0.7pu, the corresponding window width is 1.2ms. In step S23, the historical voltage deviation sequence covering the time delay window width before the current moment is read from the buffer. Each deviation value in the sequence is multiplied point by point by the confidence weight factor of the corresponding moment, and the sum is accumulated. The sum is multiplied by the deviation accumulation gain coefficient of 0.12, and the product result is output as the time domain cumulative deviation control quantity. In step S24, the time-domain cumulative deviation adjustment amount is multiplied by the compensation amplitude scaling factor of 0.85, and then multiplied by the result of the natural exponential decay operation on the absolute value of the current voltage deviation instantaneous value. The deviation-sensitive decay factor in the decay operation is 0.08 per volt. The product result is used as the time delay compensation output of the forward channel. This output is converted into an analog voltage signal by the digital-to-analog converter and then fed into the subsequent processing stage as a preliminary oscillation suppression signal.

[0039] Preferably, step S3 includes the following sub-steps: S31, extracting the discrete amplitude sequence of the current oscillation waveform within the observation window; S32, dividing the discrete amplitude sequence into several sub-intervals according to the amplitude interval, and counting the frequency of amplitude occurrence in each sub-interval; S33, calculating the normalized occurrence probability of each sub-interval based on the occurrence frequency of each sub-interval; S34, substituting the normalized occurrence probability of each sub-interval into the oscillation mode time-domain entropy discriminant function, calculating the time-domain entropy criterion value, comparing the time-domain entropy criterion value with the reference entropy value of each mode, and outputting the mode discrimination label.

[0040] Specifically, in step S31, a discrete amplitude sequence corresponding to the current oscillation waveform is extracted from the observation window. The observation window starts 10ms prior to the current time and ends at the current time. The window contains 2000 discrete sampling points, each corresponding to an amplitude value, which is stored in a buffer as a signed integer. In step S32, the maximum and minimum values ​​in the discrete amplitude sequence are detected. The upper limit of the maximum value is 12V, and the lower limit of the minimum value is -12V. The amplitude range between the maximum and minimum values ​​is divided into 32 sub-intervals, each with an amplitude width of 0.75V. All 2000 sampling points are traversed, and the number of sampling points falling within each amplitude sub-interval is counted to obtain the frequency statistics of each sub-interval. In step S33, the frequency statistics of each sub-interval are divided by the total number of sampling points, 2000, to obtain the normalized occurrence probability of each sub-interval. The sum of the normalized occurrence probabilities of all 32 sub-intervals equals 1, and the normalized occurrence probability value is retained to 4 decimal places. In step S34, the normalized occurrence probability of each sub-interval is added to a regularization factor of 10 to the power of -10, and the logarithm is taken to the base 2. The logarithm is multiplied by the normalized occurrence probability of the corresponding sub-interval, and the sum of the 32 sub-intervals is taken as a negative value to obtain the temporal entropy criterion value. The absolute value of the deviation between this temporal entropy criterion value and the pre-stored 5 modal reference entropy values ​​is calculated one by one. The encoding value corresponding to the modal category with the smallest absolute deviation value is output as the modal discrimination label, and the encoding value is represented by 3 bits.

[0041] Preferably, step S4 includes the following sub-steps: S41, reading the nonlinear correction parameter group corresponding to the mode based on the mode discrimination tag; S42, using the current amplitude of the preliminary oscillation suppression signal as the input signal amplitude, and inputting it into the nonlinear correction function of the time delay unit; S43, capturing the phase deviation of the preliminary oscillation suppression signal relative to the original voltage deviation signal, and generating a phase compensation factor; S44, performing amplitude distortion correction and phase offset compensation on the input signal amplitude and the phase compensation factor in the nonlinear correction function of the time delay unit, and outputting the corrected oscillation suppression signal.

[0042] Specifically, in step S41, the modal discrimination tag output from step S3 is received and used as an address index in the non-volatile memory. The non-volatile memory stores 5 sets of nonlinear correction parameters, each set including 3 parameter values. When the tag is 000, the parameter values ​​are read as 1.05, 0.12, and 0.35; when the tag is 001, the parameter values ​​are read as 0.98, 0.08, and 0.50; when the tag is 010, the parameter values ​​are read as 0.92, 0.05, and 0.65; when the tag is 011, the parameter values ​​are read as 1.12, 0.18, and 0.25; and when the tag is 100, the parameter values ​​are read as 0.88, 0.22, and 0.45. In step S42, the instantaneous voltage amplitude of the preliminary oscillation suppression signal is used as the input signal amplitude. This instantaneous voltage amplitude ranges from -12V to +12V. The input signal amplitude is multiplied by the linear amplitude scaling reference coefficient to obtain the linear reference value. The absolute value of the input signal amplitude is multiplied by the amplitude compression sensitivity coefficient and then substituted into the arctangent function for calculation. The result is multiplied by the nonlinear distortion adjustment coefficient and then added to a constant 1. The linear reference value is multiplied by this sum to obtain the amplitude-corrected signal. In step S43, the phase deviation between the preliminary oscillation suppression signal and the original voltage deviation signal is captured. This is done by generating square wave pulses from the two signals through zero-crossing comparators, measuring the time interval between the rising edges of the two square wave pulses, dividing the time interval by the signal period, and then multiplying by 360 degrees to obtain the phase deviation. The phase deviation measurement resolution is set to 0.5 degrees, and the measurement range is limited to -45 degrees to +45 degrees. In step S44, the phase compensation factor value is obtained from the phase compensation factor table by linear interpolation based on the phase deviation. The amplitude-corrected signal is multiplied by the phase compensation factor to complete the phase offset compensation. The multiplication result is output as the corrected oscillation suppression signal to the feedback oscillation circuit.

[0043] Preferably, step S5 includes the following sub-steps: S51, feeding the corrected oscillation suppression signal into the feedback oscillation loop and measuring the actual delay at each delay unit tap; S52, calculating the tap position adjustment step size for each delay unit based on the deviation between the actual delay and the target delay; S53, driving the tap selection register of each delay unit to update its value based on the tap position adjustment step size, thereby changing the delay of each delay unit; S54, recalculating the time-domain entropy value of the updated feedback oscillation loop, determining whether the time-domain entropy value converges to a preset threshold range, and repeating the tap position adjustment step if it does not converge.

[0044] Specifically, in step S51, the corrected oscillation suppression signal output from step S4 is fed into the feedback oscillation circuit of the drive amplifier stage. The voltage gain of the drive amplifier stage is set to 2 times, and the output impedance is set to 50Ω. The signal is transmitted along the time delay matching path to each time delay unit tap. The arrival time of the reflected wave at each tap is measured using a time domain reflectometer. The pulse rise time of the time domain reflectometer is set to 1ns, and the measurement time resolution is set to 0.05μs. The arrival time of the reflected wave is converted into the actual delay at each tap. In step S52, the signal period value is calculated based on the zero-crossing detection result of the current oscillation frequency. The period value is divided by 64 to obtain the target delay for each tap. The difference between the actual delay and the target delay for each tap is calculated one by one. The difference is divided by the target delay to obtain the relative deviation rate. When the absolute value of the relative deviation rate exceeds 0.02, adjustment is triggered. The proportional coefficient 0.6 is multiplied by the difference to obtain the proportional adjustment component, and the integral coefficient 0.1 is multiplied by the accumulated historical difference to obtain the integral adjustment component. The two are added together to obtain the tap position adjustment step size. In step S53, the tap position adjustment step size is converted into an integer increment or decrement of the tap level. The conversion method is to divide the adjustment step size by the single-level delay amount of 0.8μs and round it to the nearest integer. The rounded result is limited to the range of -4 levels to +4 levels. The rounded result is added to the current value of the tap selection register and written to the register. After the register value is updated, the physical tap position of each delay unit changes accordingly. In step S54, after the register is updated, the oscillation waveform truncation and time-domain entropy value calculation are re-executed. The recalculated time-domain entropy value is compared with the preset threshold range of 1.8 to 4.2. If the time-domain entropy value falls within the range, convergence is determined and the iteration stops. If it does not fall within the range, steps S51 to S54 are repeated. When the cumulative number of repetitions reaches 15, the iteration is forcibly terminated and the current tap position is used as the final output.

[0045] A voltage sag fast response oscillation control method based on physical constraint layout is implemented through a voltage sag fast response oscillation control system based on physical constraint layout. The method includes: a dual-axis orthogonal time-delay grid array arrangement module, used to set the physical spacing of the time-delay units in the orthogonal dual-axis direction according to the voltage sag transient oscillation frequency distribution, constructing a time-delay matching path for the feedback oscillation loop; a dual-axis time-delay adaptive deviation accumulation compensation module, with its input connected to the output of the dual-axis orthogonal time-delay grid array arrangement module, used to adjust the time-delay compensation coefficient and generate a preliminary oscillation suppression signal based on the real-time captured voltage deviation; and an online oscillation mode time-domain entropy discrimination module, with its input connected to the output of the dual-axis time-delay adaptive deviation accumulation compensation module, used to calculate the time-domain entropy value of the oscillation waveform and output the mode judgment. The system includes: a nonlinear amplitude-phase joint correction module for time delay units, whose input is connected to the output of the online time-domain entropy discrimination module for oscillation modes, used to correct amplitude distortion and compensate phase shift of the initial oscillation suppression signal based on the mode discrimination label; a tap position iterative optimization feedback adjustment module, whose input is connected to the output of the nonlinear amplitude-phase joint correction module for time delay units, and whose output is connected to the feedback input of the dual-axis orthogonal time delay grid array arrangement module, used to feed the corrected oscillation suppression signal into the feedback oscillation loop and iteratively update the time delay matching path; and a multi-scenario drop condition simulation excitation loading module, whose output is connected to the test input of the dual-axis orthogonal time delay grid array arrangement module, used to load test cases with different drop depths and drop durations to verify the oscillation suppression effect.

[0046] A voltage sag fast response oscillation control method based on physical constraint layout utilizes a dual-axis orthogonal time delay grid array. The spacing of the time delay units is set according to the oscillation frequency distribution, ensuring the time delay matching path exhibits deterministic low parasitic parameter characteristics in electrical connection, significantly improving the accuracy and consistency of time delay compensation. Combined with an iterative optimization feedback adjustment mechanism for tap positions, the delay of each time delay unit is dynamically updated until the time-domain entropy value converges, enabling physical-level time delay adjustments to follow oscillation mode changes. A dual-axis time-delay adaptive disturbance rejection control algorithm adjusts the time delay compensation coefficient in real time, an oscillation mode time-domain entropy discrimination function determines mode assignment online, and a nonlinear correction function for the time delay units jointly corrects amplitude distortion and phase shift. The cascaded cooperation of these three elements ensures that the oscillation suppression signal maintains amplitude and phase coordination throughout the entire transient process, avoiding the response lag problem of conventional single compensation methods.

[0047] This invention calculates the entropy value of the oscillation waveform online using a time-domain entropy discriminant function and compares it with the reference entropy value of each mode. It outputs mode labels in real time to drive the adaptive switching of correction parameters, enabling the time delay compensation coefficient and nonlinear correction parameters to dynamically adjust with mode changes, thus overcoming the limitations of preset fixed parameters. Simultaneously, this method employs a dual-axis physical constraint layout architecture combined with a tapped delay chain structure composed of gallium nitride high-speed switches. The delay units are deployed on defined grid nodes, and the tap positions are iteratively updated via a feedback loop, making the adjustment process of the physical delay deterministic and traceable. Coupled with the phase compensation mechanism in the nonlinear correction function, it effectively decouples the mutual influence between amplitude distortion and phase shift, simultaneously eliminating the impact of parasitic parameter uncertainties and amplitude-phase coupling errors on control stability from both physical arrangement and signal correction dimensions.

[0048] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," "link," and "fix" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0049] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various equivalent changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A voltage sag fast response oscillation control method based on physical constraint layout, characterized in that, Includes the following steps: S1. Construct a physical constraint layout architecture for dual-axis delay lines. Based on the oscillation frequency distribution during the voltage drop transient process, set the grid spacing of the delay units and construct the delay matching path of the feedback oscillation loop. S2. Introduce a dual-axis time-delay adaptive anti-disturbance control algorithm. Based on the real-time captured voltage deviation, adjust the time-delay compensation coefficients of the forward channel and the feedback channel to generate a preliminary oscillation suppression signal. S3, input the preliminary oscillation suppression signal into the oscillation mode time-domain entropy discrimination function, calculate the time-domain entropy value of the current oscillation waveform, determine the oscillation mode category, and output the mode discrimination label; S4. Based on the modal discrimination label, activate the nonlinear correction function of the time delay unit to perform amplitude distortion correction and phase shift compensation on the preliminary oscillation suppression signal to generate the corrected oscillation suppression signal. S5, the corrected oscillation suppression signal is fed into the feedback oscillation loop, the physical tap position of the delay unit is adjusted, and the delay matching path is iteratively updated until the time domain entropy value converges to the preset threshold range; S6, based on the power supply drop multi-scenario simulation verification platform, test cases with different drop depths and drop durations are loaded to verify the oscillation suppression effect.

2. The voltage sag fast response oscillation control method based on physical constraint layout according to claim 1, characterized in that, The expression for the dual-axis time-delay adaptive disturbance rejection control algorithm is as follows: ,in Characterizing the time-domain cumulative deviation control amount, Characterizes the current time parameter. Characterizing the width of the time delay window, Characterizing the cumulative gain coefficient of deviation, Characterization The instantaneous value of the voltage deviation at time t. Characterization The confidence weighting factor for the deviation at time. Characterizing the integral variable; based on the above Construct forward compensation quantity ,in The output value representing the time delay compensation of the forward channel. Characterizes the scaling factor of the compensation amplitude. Characterization bias sensitive attenuation coefficient, The instantaneous value of the voltage deviation at the current moment is represented by exp, which represents the natural exponent operation.

3. The voltage sag fast response oscillation control method based on physical constraint layout according to claim 1, characterized in that, The expression for the time-domain entropy discriminant function of the oscillation mode is: in The time-domain entropy criterion value characterizing the oscillation waveform. Characterizes the total number of time-domain segmentation sub-intervals. Characterizing the first The normalized probability of the oscillation amplitude occurring within each sub-interval A regularized minima representing the avoidance of singularities. Representing the base-2 logarithmic operation; based on the above Construct the mode belonging discriminant ,in The modality discrimination label representing the output, Index variables representing modal categories, Characterizing the length of the observation time window, Characterization The instantaneous amplitude of the oscillation at time t. Characterizing the first Modal reference amplitude benchmark Characterizing the first Entropy weight mapping coefficients of class modes Characterizes the integral time variable.

4. The voltage sag fast response oscillation control method based on physical constraint layout according to claim 1, characterized in that, The expression for the nonlinear correction function of the time delay unit is: in Characterizing the amplitude of the output signal after nonlinear correction, Characterizing the instantaneous amplitude of the input signal, Characterizing the linear magnitude scaling reference factor, Characterizing the nonlinear distortion adjustment coefficient, Characterizing the arctangent nonlinear mapping operation, Characterizing the amplitude compression sensitivity coefficient, Characterization based on phase deviation Phase compensation factor, It represents the instantaneous value of the phase deviation of the current output signal relative to the input signal.

5. The voltage sag fast response oscillation control method based on physical constraint layout according to claim 1, characterized in that, The dual-axis delay line physical constraint layout architecture includes a programmable electronically controlled delay unit array arranged along the orthogonal dual-axis direction. Each delay unit adopts a tapped delay chain structure based on gallium nitride high-speed switching transistors. The grid spacing is set according to the half wavelength of the main frequency component of the voltage drop oscillation spectrum. The feedback oscillation circuit includes a transconductance amplification stage and a level clamping stage. The iterative update of the delay matching path changes the delay amount by adjusting the value of the tap selection register of each delay unit. The judgment condition for the time domain entropy value to converge to the preset threshold range is that the relative change rate of the time domain entropy value calculated by three consecutive iterations is less than a set percentage. The voltage deviation is picked up in real time at the common coupling point by a differential probe group. The preliminary oscillation suppression signal is fed into the front end of the tapped delay chain structure via a digital-to-analog converter.

6. The voltage sag fast response oscillation control method based on physical constraint layout according to claim 1, characterized in that, S2 includes: Capture the instantaneous voltage waveform at the common coupling point and extract the instantaneous voltage deviation value; Based on the instantaneous value of the voltage deviation, the preset time delay compensation parameter table is consulted to obtain the time delay window width corresponding to the current operating condition; Substitute the instantaneous voltage deviation value and the time delay window width into the dual-axis time delay adaptive anti-disturbance control algorithm to calculate the time-domain cumulative deviation control amount; Based on the time-domain cumulative deviation control amount, a time delay compensation output amount is generated for the forward channel, which serves as the initial oscillation suppression signal.

7. The voltage sag fast response oscillation control method based on physical constraint layout according to claim 1, characterized in that, S3 includes: S32. Extract the discrete amplitude sequence of the current oscillation waveform within the observation window; S33. Divide the discrete amplitude sequence into several sub-intervals according to the amplitude interval, and count the frequency of amplitude occurrence in each sub-interval; Based on the frequency of occurrence of each sub-interval, the normalized occurrence probability of each sub-interval is calculated; the normalized occurrence probability of each sub-interval is substituted into the oscillation mode time-domain entropy discriminant function to calculate the time-domain entropy criterion value; the time-domain entropy criterion value is compared with the reference entropy value of each mode, and the mode discrimination label is output.

8. The voltage sag fast response oscillation control method based on physical constraint layout according to claim 1, characterized in that, S4 includes: Based on the mode discrimination label, read the nonlinear correction parameter group corresponding to the mode; use the current amplitude of the preliminary oscillation suppression signal as the input signal amplitude, and input it into the nonlinear correction function of the time delay unit; capture the phase deviation of the preliminary oscillation suppression signal relative to the original voltage deviation signal, and generate a phase compensation factor; The amplitude of the input signal and the phase compensation factor are used in the nonlinear correction function of the time delay unit to perform amplitude distortion correction and phase offset compensation, and the corrected oscillation suppression signal is output.

9. The voltage sag fast response oscillation control method based on physical constraint layout according to claim 1, characterized in that, S5 includes: The corrected oscillation suppression signal is fed into the feedback oscillation circuit to measure the actual delay at each delay unit tap; based on the deviation between the actual delay and the target delay, the tap position adjustment step size of each delay unit is calculated. The step size is adjusted according to the tap position to drive the tap selection register of each delay unit to update the value and change the delay amount of each delay unit; the time domain entropy value of the updated feedback oscillation loop is recalculated, and it is determined whether the time domain entropy value converges to the preset threshold range. If it does not converge, the tap position adjustment step is repeated.

10. The voltage sag fast response oscillation control method based on physical constraint layout according to any one of claims 1-9, characterized in that, This method is implemented through a voltage sag fast-response oscillation control system based on physical constraint layout, including: A dual-axis orthogonal time-delay grid array arrangement module is used to set the physical spacing of the time-delay units in the orthogonal dual-axis direction according to the voltage drop transient oscillation frequency distribution, and to construct the time-delay matching path of the feedback oscillation loop; a dual-axis time-delay adaptive deviation accumulation compensation module, with its input connected to the output of the dual-axis orthogonal time-delay grid array arrangement module, is used to adjust the time-delay compensation coefficient and generate a preliminary oscillation suppression signal according to the real-time captured voltage deviation; an online oscillation mode time-domain entropy discrimination module, with its input connected to the output of the dual-axis time-delay adaptive deviation accumulation compensation module, is used to calculate the time-domain entropy value of the oscillation waveform and output the mode discrimination label; The delay unit nonlinear amplitude-phase joint correction module, with its input connected to the output of the oscillation mode time-domain entropy online discrimination module, is used to correct amplitude distortion and compensate phase shift of the preliminary oscillation suppression signal based on the mode discrimination label. The tap position iterative optimization feedback adjustment module, with its input connected to the output of the delay unit nonlinear amplitude-phase joint correction module and its output connected to the feedback input of the dual-axis orthogonal delay grid array arrangement module, is used to feed the corrected oscillation suppression signal into the feedback oscillation loop and iteratively update the delay matching path. The multi-scenario drop condition simulation excitation loading module, with its output connected to the test input of the dual-axis orthogonal delay grid array arrangement module, is used to load test cases with different drop depths and drop durations to verify the oscillation suppression effect.

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