Charging input protection circuit, charging protection system and charging input overvoltage protection method

Abstract

The application discloses a charging input protection circuit, a charging protection system and a charging input overvoltage protection method. The circuit comprises a first MOS tube connected in series in an input positive path, a sampling branch, a software control branch and a detection control branch. A processor cancels on-off control of the charging input protection circuit according to a charging input voltage sampling signal output by the sampling branch when a software protection threshold is reached. The detection control branch independently detects the charging input voltage, and disconnects the charging input positive path when a hardware action threshold higher than the software protection threshold is reached, even if the software control branch still maintains on-off control. The scheme forms an independent hardware shutdown path while maintaining the software threshold setting capability, and can improve the input side protection integrity in cooperation with the anti-reverse connection, sampling clamping and recovery on structure.

Description

Technical Field

[0001] This invention relates to the field of charging protection technology, and in particular to charging input protection circuits, charging protection systems, and charging input overvoltage protection methods. Background Technology

[0002] When the charging power supply is connected to the battery system, there may be incorrect wiring polarity or abnormal increase in charging input voltage on the input side. In order to prevent abnormal input from being transmitted to subsequent circuits, the input side is usually equipped with reverse connection protection structure and overvoltage protection structure.

[0003] In existing technologies, a processor is typically used to control the power switch to turn off based on the sampled voltage, thereby achieving configurable overvoltage protection. The processor's sampling, comparison, and control processes directly affect this protection process.

[0004] In existing technologies, threshold devices are also used to directly drive the switch to turn off. However, when using a fixed hardware threshold alone, it is difficult to simultaneously take into account the flexibility of setting the software threshold and the protection requirements when the control is abnormal.

[0005] Therefore, there is an urgent need for a charging input protection scheme that can maintain overvoltage shutdown capability even when software control is abnormal, in order to overcome the above-mentioned defects. Summary of the Invention

[0006] The purpose of this invention is to provide a charging input protection circuit, a charging protection system, and a charging input overvoltage protection method, so as to maintain the settableness of the software protection threshold while reducing the risk of unreliable disconnection of the charging path due to untimely processor response or control failure when the charging input voltage is abnormal.

[0007] To achieve this objective, the present invention adopts the following technical solution: In a first aspect, the present invention provides a charging input protection circuit, comprising: Input positive electrode path; The first MOSFET is connected in series in the input positive path; The sampling branch has an output terminal that forms a sampling terminal for electrical connection with the processor. The sampling branch is used to output a sampling signal characterizing the charging input voltage. The software control branch has an input terminal that forms a control terminal for electrical connection with the processor, and an output terminal that is electrically connected to the gate of the first MOS transistor. The software control branch is used to control the first MOS transistor to turn on when the control terminal PV-EN receives a turn-on control signal, and to control the first MOS transistor to turn off when the control terminal does not receive a turn-on control signal. The sampling terminal and the control terminal are used to be electrically connected to the same processor so that the processor stops outputting the conduction control signal to the control terminal when the charging input voltage represented by the sampling signal reaches or exceeds the software protection threshold. A detection control branch is used to detect the charging input voltage. Its control output terminal is electrically connected to the gate of the first MOS transistor. The operation of the detection control branch does not depend on the conduction control signal. Wherein, the software protection threshold is lower than the hardware action threshold of the detection and control branch; When the charging input voltage reaches or exceeds the hardware action threshold, the detection and control branch turns off the first MOSFET; when the charging input voltage reaches or exceeds the hardware action threshold and the software control branch still keeps the first MOSFET on according to the conduction control signal, the detection and control branch still turns off the first MOSFET.

[0008] In one embodiment, the input terminal of the sampling branch and the detection input terminal of the detection control branch are both electrically connected to the input side of the first MOS transistor.

[0009] In one embodiment, the detection and control branch includes a reference device, a third resistor, a ninth resistor, a twelfth resistor, and a second transistor; The third resistor, the ninth resistor, and the twelfth resistor are connected in series between the input side and the negative terminal of the first MOS transistor to form a voltage divider network. The reference terminal of the reference device is electrically connected to the connection node of the third resistor and the ninth resistor, the anode is electrically connected to the negative terminal, and the cathode is electrically connected to the input side of the first MOS transistor and the base of the second transistor. The emitter of the second transistor is electrically connected to the input side of the first MOSFET, and the collector is electrically connected to the gate of the first MOSFET.

[0010] Specifically, the hardware action threshold V HW The theoretical value satisfies the following formula: .

[0011] In one embodiment, the first MOSFET is a P-channel MOSFET, and the software control branch includes a fifth transistor, a tenth resistor, a fifteenth resistor, and a seventeenth resistor. The control terminal is electrically connected to the base of the fifth transistor via the fifteenth resistor, the seventeenth resistor is electrically connected between the base and the negative node of the fifth transistor, the emitter of the fifth transistor is electrically connected to the negative node, and the collector is electrically connected to the gate of the first MOS transistor via the tenth resistor.

[0012] In one embodiment, the charging input protection circuit further includes a fourth resistor electrically connected between the source and gate of the first MOSFET to keep the first MOSFET off when no turn-on control signal is received at the control terminal.

[0013] In one embodiment, the processor is further configured to output a conduction control signal to the control terminal when the charging input voltage drops to a recovery threshold, wherein the recovery threshold is lower than the software protection threshold.

[0014] In one embodiment, the sampling branch includes a sixteenth resistor and a third MOS transistor, the sixteenth resistor and the third MOS transistor are connected in series, and their connection node is electrically connected to the sampling terminal; The gate of the third MOS transistor is electrically connected to the bias network to clamp the voltage drop across the sixteenth resistor and protect the sampling pin of the processor.

[0015] In one embodiment, the charging input protection circuit further includes a second MOS transistor, which is an N-channel MOS transistor connected in series in the input negative terminal path. The gate of the second MOS transistor is electrically connected to the input positive terminal network via a fifth resistor and electrically connected to the negative terminal node via an eleventh resistor, so as to conduct under normal polarity and block the input negative terminal circuit under reverse polarity.

[0016] Specifically, the charging input protection circuit further includes a second capacitor, a third capacitor, and a Zener diode. The second capacitor and the third capacitor are connected in series and then connected across the drain and source of the second MOSFET. The Zener diode is connected in parallel between the gate and source of the second MOSFET.

[0017] In a second aspect, the present invention provides a charging protection system, which includes a processor and a charging input protection circuit, wherein the charging input protection circuit includes an input positive path, a first MOSFET, a sampling branch, a software control branch, and a detection control branch. The first MOSFET is connected in series in the input positive path; The output terminal of the sampling branch forms a sampling terminal, the input terminal of the software control branch forms a control terminal, and the output terminal of the software control branch and the control output terminal of the detection control branch are both electrically connected to the gate of the first MOS transistor. The processor is electrically connected to the sampling terminal and the control terminal respectively, and is used to receive the sampling signal representing the charging input voltage, and compare the charging input voltage represented by the sampling signal with the software protection threshold. When the charging input voltage reaches or exceeds the software protection threshold, the processor controls the first MOS transistor to turn off through the software control branch. The detection and control branch is used to detect the charging input voltage, and its operation does not depend on the comparison result and control of the processor; Wherein, the software protection threshold is lower than the hardware action threshold of the detection and control branch; When the charging input voltage reaches or exceeds the hardware action threshold, the detection and control branch turns off the first MOSFET; when the charging input voltage reaches or exceeds the hardware action threshold and the processor still keeps the first MOSFET on through the software control branch, the detection and control branch still turns off the first MOSFET.

[0018] In one embodiment, the charging protection system further includes a buck-boost module and a battery module. The charging input protection circuit is electrically connected to the buck-boost module, and the buck-boost module is electrically connected to the positive and negative battery interfaces of the battery module.

[0019] Thirdly, the present invention provides a charging input overvoltage protection method, applied to the charging input protection circuit described above, wherein the sampling terminal and control terminal of the charging input protection circuit are electrically connected to the same processor, and the charging input overvoltage protection method includes the following steps: S1. The processor acquires a sampling signal representing the charging input voltage output by the sampling branch; S2. The processor compares the charging input voltage represented by the sampling signal with a software protection threshold, wherein the software protection threshold is lower than the hardware action threshold of the detection and control branch. S3. When the charging input voltage reaches or exceeds the software protection threshold, the processor stops outputting the turn-on control signal to the control terminal, so that the software control branch controls the first MOS transistor to turn off and disconnects the input positive terminal path. S4. The charging input voltage is detected by the detection control branch; S5. The operation of the detection and control branch does not depend on the comparison result and control of the processor; when the charging input voltage reaches or exceeds the hardware action threshold, the detection and control branch turns off the first MOSFET; when the charging input voltage reaches or exceeds the hardware action threshold and the processor still outputs a conduction control signal to the control terminal, the detection and control branch still turns off the first MOSFET.

[0020] In some embodiments, the charging input overvoltage protection method further includes: When the charging input voltage is lower than the recovery threshold, the processor outputs a turn-on control signal to the control terminal to enable the software control branch to control the first MOS transistor to turn on and connect the input positive path, wherein the recovery threshold is lower than the software protection threshold.

[0021] Compared with the prior art, the present invention has the following beneficial effects: On the one hand, the present invention uses a software control branch and a detection control branch to work together on the positive charging input path, so that the software protection threshold can be set according to the application, and the independent hardware branch will shut down when the software control fails to shut down properly; on the other hand, by setting a second MOSFET, a third MOSFET, a recovery threshold and a spike absorption branch, auxiliary support is provided for reverse connection protection, sampling pin protection, recovery conduction and device protection, respectively. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a circuit diagram of the charging protection system according to Embodiment 1 of the present invention.

[0024] Figure 2 This is a schematic diagram of the electrical connection between the charging input protection circuit and the processor in Embodiment 1 of the present invention.

[0025] Figure 3 This is a flowchart of the charging input overvoltage protection method according to Embodiment 2 of the present invention.

[0026] Explanation of reference numerals in the attached figures 100. Charging input protection circuit; 10. Positive input path; 20. Sampling branch; 30. Software control branch; 40. Detection and control branch; 50. Negative input path; 200. Processor; 300. Buck-boost module; 400. Battery module; PV1, charging input interface; F1, fuse; Q1, first MOSFET; Q2, second transistor; Q3, third MOSFET; Q4, second MOSFET; Q5, fifth transistor; U1, reference device; R1, first sampling resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, second sampling resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R11, eleventh resistor; R12, twelfth resistor; R13, thirteenth resistor; R14, fourteenth resistor; R15, fifteenth resistor; R16, sixteenth resistor; R17, seventeenth resistor; C1, First capacitor; C2, Second capacitor; C3, Third capacitor; ZD1, First Zener diode; ZD2, Second Zener diode; PV-VIN, Input positive terminal; PV-AD, Sampling terminal; PV-EN, Control terminal; PV-GND, Negative terminal; DGND, Digital ground; VIN, Protection output terminal; P+, Battery positive terminal; P-, Battery negative terminal; DC+, Charging positive terminal; DC-, Charging negative terminal. Detailed Implementation

[0027] The following combination Figure 1 and Figure 2 The technical solution of the present invention will be further described below. The following embodiments are only used to explain the present invention and do not constitute a limitation on the scope of protection of the present invention.

[0028] Example 1 Please see Figure 1 and Figure 2 The charging protection system of this embodiment includes a charging input protection circuit 100, a processor 200, a buck-boost module 300, and a battery module 400. The charging input protection circuit 100 includes an input positive terminal path 10, a first MOS transistor Q1 connected in series in the input positive terminal path 10, a sampling branch 20, a software control branch 30, and a detection control branch 40.

[0029] The sampling branch 20 forms the sampling terminal PV-AD, the software control branch 30 forms the control terminal PV-EN, and the control output terminals of both the software control branch 30 and the detection control branch 40 are electrically connected to the gate of the first MOS transistor Q1.

[0030] The processor 200 is electrically connected to the sampling terminal PV-AD and the control terminal PV-EN, respectively. The buck-boost module 300 is electrically connected to the charging input protection circuit 100 and the battery positive terminal P+ and battery negative terminal P- of the battery module 400.

[0031] The charging positive terminal DC+ of the charging input interface PV1 forms the input positive node PV-VIN through the fuse F1, and the input positive node PV-VIN is connected to the input positive path 10.

[0032] Fuse F1 is located between the charging positive interface DC+ and the input positive node PV-VIN, and is used to provide basic overcurrent protection for the input positive path 10.

[0033] The charging negative terminal DC- of the charging input interface PV1 is connected to the negative terminal node PV-GND via the second MOS transistor Q4 to form the input negative terminal path 50.

[0034] The second MOSFET Q4 is an N-channel MOSFET, connected in series in the negative input path 50. Its drain is electrically connected to the DC- terminal of the charging input interface PV1, and its source is electrically connected to the negative node PV-GND. The gate of the second MOSFET Q4 is electrically connected to the positive input node PV-VIN after the fuse F1 via the fifth resistor R5, and is electrically connected to the negative node PV-GND via the eleventh resistor R11.

[0035] It is understandable that when the charging input polarity is normal, the second MOSFET Q4 conducts the negative input path; while when the charging input polarity is reversed, the second MOSFET Q4 blocks the negative input circuit.

[0036] The second Zener diode ZD2 is connected in parallel between the gate and source of the second MOSFET Q4 to limit the gate-source voltage of the second MOSFET Q4. The second capacitor C2 and the third capacitor C3 are connected in series across the drain and source of the second MOSFET Q4 to absorb the voltage spikes between the drain and source of the second MOSFET Q4.

[0037] The input terminal of sampling branch 20 is electrically connected to the input side of the first MOS transistor Q1. Specifically, the positive input node PV-VIN is electrically connected to the drain of the third MOS transistor Q3 via the first sampling resistor R1 and the second sampling resistor R7 in sequence.

[0038] The source of the third MOSFET Q3 is electrically connected to one end of the sixteenth resistor R16 and one end of the fourteenth resistor R14. The other end of the sixteenth resistor R16 is electrically connected to the digital ground DGND. The other end of the fourteenth resistor R14 forms the sampling terminal PV-AD, and the first capacitor C1 is connected between the sampling terminal PV-AD and the digital ground DGND.

[0039] The eighth resistor R8 is connected between the 3.3V bias power supply and the gate of the third MOSFET Q3, and the thirteenth resistor R13 is connected between the gate of the third MOSFET Q3 and the digital ground DGND. The two form a bias network to limit the gate potential of the third MOSFET Q3.

[0040] The third MOSFET Q3 clamps the voltage drop across the sixteenth resistor R16 to protect the sampling pin of the processor 200, rather than acting as an on / off switch for the sampling branch 20.

[0041] In this embodiment, the first MOSFET Q1 is a P-channel MOSFET, with its source electrically connected to the input positive node PV-VIN and its drain electrically connected to the protection output terminal VIN. A first Zener diode ZD1 and a fourth resistor R4 are both connected between the source and gate of the first MOSFET Q1. The first Zener diode ZD1 limits the gate-source voltage of the first MOSFET Q1, and the fourth resistor R4 keeps the first MOSFET Q1 off when the control terminal PV-EN does not receive a turn-on control signal.

[0042] The control terminal PV-EN is electrically connected to the base of the fifth transistor Q5 via the fifteenth resistor R15, and the seventeenth resistor R17 is connected between the base of the fifth transistor Q5 and the negative node PV-GND. The emitter of the fifth transistor Q5 is electrically connected to the negative node PV-GND, and the collector is electrically connected to the gate of the first MOSFET Q1 via the tenth resistor R10.

[0043] The processor 200 obtains the sampling signal through the sampling terminal PV-AD and outputs the conduction control signal to the software control branch 30 through the control terminal PV-EN.

[0044] It is understandable that when the processor 200 outputs a turn-on control signal, the fifth transistor Q5 controls the first MOSFET Q1 to turn on via the tenth resistor R10; and when the processor 200 cancels the turn-on control signal when the charging input voltage reaches or exceeds the software protection threshold, the fifth transistor Q5 is turned off, and the fourth resistor R4 keeps the first MOSFET Q1 off, thereby implementing software-level overvoltage protection.

[0045] The detection input terminal of the detection control branch 40 is also electrically connected to the input side of the first MOSFET Q1. Specifically, the third resistor R3, the ninth resistor R9 and the twelfth resistor R12 are connected in series between the input side of the first MOSFET Q1 and the negative terminal node PV-GND to form a voltage divider network.

[0046] The reference terminal of reference device U1 is electrically connected to the connection node of the third resistor R3 and the ninth resistor R9, and the anode is electrically connected to the negative terminal node PV-GND. The cathode of reference device U1 is electrically connected to the input side of the first MOSFET Q1 via the second resistor R2, and to the base of the second transistor Q2 via the sixth resistor R6. The emitter of the second transistor Q2 is electrically connected to the input side of the first MOSFET Q1, and the collector is electrically connected to the gate of the first MOSFET Q1. In this embodiment, the type of reference device U1 is a three-terminal adjustable precision parallel voltage regulator, exemplarily model TL431. Of course, the specific type and model of reference device U1 can be set according to actual needs and are not limited here.

[0047] Specifically, the hardware action threshold V of the detection and control branch 40 in this embodiment... HW The theoretical value satisfies the following formula: .

[0048] Where 2.5V is the typical voltage value of the reference terminal of the reference device U1, and the total resistance of the series connection of the ninth resistor R9 and the twelfth resistor R12 is used to select or adjust the hardware action threshold. For example, the theoretical value of the hardware action threshold in this embodiment can be 27.5V.

[0049] It is worth noting that the actual operating value may vary due to errors in the reference device and resistor, as well as the circuit operating conditions. 27.5V is only a theoretical example and does not constitute a limitation.

[0050] Understandably, when the charging input voltage reaches or exceeds the hardware action threshold, the reference device U1 and the second transistor Q2 cooperate to bring the gate potential of the first MOSFET Q1 close to its source potential, thereby turning off the first MOSFET Q1. Therefore, the detection and control branch 40 directly acts on the gate of the first MOSFET Q1 and does not depend on the comparison result and control of the processor 200. So even if the processor 200 abnormally continues to output the conduction control signal through the control terminal PV-EN, and the fifth transistor Q5 still maintains the conduction control of the first MOSFET Q1, the second transistor Q2 still turns off the first MOSFET Q1, thus forming an independent hardware failure fallback path to avoid circuit malfunction due to software failure.

[0051] For example, in this embodiment, the software protection threshold can be 25V, the recovery threshold can be 24V, and the software protection threshold is lower than the hardware action threshold. It is understood that when the charging input voltage is lower than the software protection threshold, the processor 200 can output a conduction control signal; When the charging input voltage reaches or exceeds the software protection threshold, the processor 200 cancels the conduction control signal. After the software protection action, when the charging input voltage is lower than the recovery threshold, the processor 200 re-outputs the conduction control signal.

[0052] The above thresholds are typical settings for the current implementation and can be adjusted according to the charging application, but the hierarchical relationship of the recovery threshold being lower than the software protection threshold and the software protection threshold being lower than the hardware action threshold is maintained.

[0053] The negative terminal PV-GND is connected to the negative terminal P- of the battery module 400 via a common mode inductor, and the digital ground DGND is connected to the negative terminal P- of the battery module 400 via a 0Ω resistor.

[0054] In addition, the processor 200 can be installed on the same circuit board as the charging input protection circuit 100, or it can be installed as an external or separate control component, as long as it can receive the sampling signal from the sampling terminal PV-AD and output the conduction control signal to the control terminal PV-EN. Therefore, the specific location of the processor 200 is not limited here.

[0055] From the perspective of the system energy path, the protection output terminal VIN of the charging input protection circuit 100 is electrically connected to the buck-boost module 300, and the buck-boost module 300 is then electrically connected to the battery positive terminal P+ and the battery negative terminal P- of the battery module 400. Thus, Embodiment 1 simultaneously discloses the composition, connection, and cooperation relationship of the circuit group and the system group.

[0056] To better understand the setup of this embodiment, the specific working process of this charging protection system will be described in detail below: When the normal polarity is and the charging input voltage is lower than the software protection threshold, the second MOSFET Q4 turns on the negative input path 50, and the processor 200 outputs a turn-on control signal through the control terminal PV-EN, turning on the first MOSFET Q1. When the input polarity is reversed, the second MOSFET Q4 blocks the negative input circuit; When the charging input voltage reaches or exceeds the software protection threshold but has not yet reached the hardware action threshold, the processor 200 cancels the conduction control signal, and the fourth resistor R4 keeps the first MOSFET Q1 off. If the software control fails to properly turn off the first MOSFET Q1 and the charging input voltage continues to reach or exceed the hardware action threshold, the reference device U1 and the second transistor Q2 will turn off the first MOSFET Q1. After the software protection action, when the charging input voltage is lower than the recovery threshold, the processor 200 outputs the turn-on control signal again to turn on the first MOSFET Q1.

[0057] Example 2 Please see Figures 1-3 The charging input overvoltage protection method in this embodiment is applied to the charging input protection circuit described in Embodiment 1. The sampling terminal PV-AD and the control terminal PV-EN of this circuit are electrically connected to the same processor 200. The processor 200 can be located on the same PCB as this circuit or it can be externally connected, as long as it can receive the sampling signal and output the conduction control signal.

[0058] The charging input overvoltage protection method in this embodiment includes the following steps: S1. The processor 200 acquires a sampling signal representing the charging input voltage output by the sampling branch 20.

[0059] Understandably, the processor 200 acquires the sampled signal output by the sampling branch 20 through the sampling terminal PV-AD.

[0060] The first sampling resistor R1, the second sampling resistor R7, the third MOSFET Q3, the sixteenth resistor R16, the fourteenth resistor R14, and the first capacitor C1 in the sampling branch 20 jointly realize input voltage sampling and sampling pin protection; among them, the third MOSFET Q3 is used to clamp the voltage drop across the sixteenth resistor R16 to protect the sampling pin of the processor 200.

[0061] S2. The processor 200 compares the charging input voltage represented by the sampling signal with a software protection threshold, wherein the software protection threshold is lower than the hardware action threshold of the detection control branch 40.

[0062] The processor 200 compares the charging input voltage represented by the sampled signal. Specifically, when the charging input voltage reaches or exceeds the software protection threshold, the processor 200 first executes the software protection action.

[0063] The software protection threshold is lower than the hardware action threshold of the detection and control branch 40, so as to form a hierarchical relationship of software priority and hardware fallback.

[0064] S3. When the charging input voltage reaches or exceeds the software protection threshold, the processor 200 stops outputting the turn-on control signal to the control terminal PV-EN, so that the software control branch 30 controls the first MOS transistor Q1 to turn off and disconnects the input positive terminal path 10.

[0065] Understandably, the processor 200 stops outputting the turn-on control signal through the control terminal PV-EN, and the software control branch 30 accordingly stops maintaining the turn-on control of the first MOSFET Q1. The fourth resistor R4 keeps the first MOSFET Q1 off, thereby disconnecting the input positive terminal path 10.

[0066] In the corresponding specific driver implementation, the fifth transistor Q5, the tenth resistor R10, the fifteenth resistor R15, and the seventeenth resistor R17 constitute the software control branch 30. It is worth noting that these components are only specific implementations of this embodiment, and the actual circuit settings can be flexibly adjusted according to requirements.

[0067] S4. The charging input voltage is detected by the detection control branch 40.

[0068] Understandably, the detection and control branch 40 and the sampling branch 20 detect the charging input voltage in parallel. Specifically, the detection and control branch 40 forms an independent hardware detection and shutdown path through the third resistor R3, the ninth resistor R9, the twelfth resistor R12, the reference device U1, the second resistor R2, the sixth resistor R6, and the second transistor Q2.

[0069] It is worth noting that this path does not rely on the software comparison results of processor 200 as a prerequisite for action.

[0070] S5. The operation of the detection control branch 40 does not depend on the comparison result and control of the processor 200; when the charging input voltage reaches or exceeds the hardware action threshold, the detection control branch 40 turns off the first MOS transistor Q1; when the charging input voltage reaches or exceeds the hardware action threshold and the processor 200 still outputs a conduction control signal to the control terminal PV-EN, the detection control branch 40 still turns off the first MOS transistor Q1.

[0071] When the charging input voltage reaches or exceeds the hardware action threshold, the detection and control branch 40, containing the reference device U1 and the second transistor Q2, turns off the first MOSFET Q1, thereby disconnecting the input positive terminal path 10. Even if the processor 200 still outputs a turn-on control signal through the control terminal PV-EN, the detection and control branch 40 can still turn off the first MOSFET Q1, thus forming a hardware fallback shutdown independent of the processor's software path.

[0072] S6. When the charging input voltage is lower than the recovery threshold, the processor 200 outputs a turn-on control signal to the control terminal PV-EN, so that the software control branch 30 controls the first MOS transistor Q1 to turn on and connect the input positive terminal path 10, wherein the recovery threshold is lower than the software protection threshold.

[0073] After the software protection has been activated, when the charging input voltage falls below the recovery threshold, the processor 200 restores the output conduction control signal via the control terminal PV-EN. The software control branch 30 then re-controls the first MOSFET Q1 to turn on, thereby connecting the input positive path 10. The recovery threshold is lower than the software protection threshold, thus distinguishing the recovery conduction condition from the software shutdown condition and avoiding repeated switching near the threshold.

[0074] Combination Figures 1-3On the one hand, the present invention uses the software control branch 30 and the detection control branch 40 to work together on the input positive path 10, so that the software protection threshold can be set according to the application, and the detection control branch 40 will turn off the first MOSFET Q1 when the software control branch 30 fails to turn it off normally. On the other hand, by setting the second MOSFET Q4, the third MOSFET Q3, the recovery threshold, and the spike absorption branch composed of the second capacitor C2 and the third capacitor C3, auxiliary support is provided for reverse connection protection, sampling pin protection, recovery conduction and device protection, respectively.

[0075] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. For those skilled in the art, equivalent substitutions or adjustments can be made to the non-essential technical features in the embodiments without departing from the technical concept of the present invention.

Claims

1. A charging input protection circuit, characterized in that, include: Input positive electrode path (10); The first MOSFET (Q1) is connected in series in the input positive path (10); The sampling branch (20) has an output terminal that forms a sampling terminal (PV-AD) for electrical connection with the processor (200). The sampling branch (20) is used to output a sampling signal that characterizes the charging input voltage. The software control branch (30) has an input terminal forming a control terminal (PV-EN) for electrical connection with the processor (200), and an output terminal electrically connected to the gate of the first MOS transistor (Q1). The software control branch (30) is used to control the first MOS transistor (Q1) to turn on when the control terminal (PV-EN) receives a turn-on control signal, and to control the first MOS transistor (Q1) to turn off when the control terminal (PV-EN) does not receive a turn-on control signal. The sampling terminal (PV-AD) and the control terminal (PV-EN) are used to be electrically connected to the same processor (200) so that the processor (200) stops outputting the conduction control signal to the control terminal (PV-EN) when the charging input voltage represented by the sampling signal reaches or exceeds the software protection threshold. The detection control branch (40) is used to detect the charging input voltage. Its control output terminal is electrically connected to the gate of the first MOS transistor (Q1). The operation of the detection control branch (40) does not depend on the conduction control signal. Wherein, the software protection threshold is lower than the hardware action threshold of the detection control branch (40); When the charging input voltage reaches or exceeds the hardware action threshold, the detection control branch (40) turns off the first MOS transistor (Q1); when the charging input voltage reaches or exceeds the hardware action threshold and the software control branch (30) still keeps the first MOS transistor (Q1) on according to the conduction control signal, the detection control branch (40) still turns off the first MOS transistor (Q1).

2. The charging input protection circuit as described in claim 1, characterized in that, The input terminal of the sampling branch (20) and the detection input terminal of the detection control branch (40) are both electrically connected to the input side of the first MOS transistor (Q1).

3. The charging input protection circuit as described in claim 1, characterized in that, The detection and control branch (40) includes a reference device (U1), a third resistor (R3), a ninth resistor (R9), a twelfth resistor (R12), and a second transistor (Q2). The third resistor (R3), the ninth resistor (R9), and the twelfth resistor (R12) are connected in series between the input side of the first MOS transistor (Q1) and the negative terminal (PV-GND) to form a voltage divider network. The reference terminal of the reference device (U1) is electrically connected to the connection node of the third resistor (R3) and the ninth resistor (R9), the anode is electrically connected to the negative terminal (PV-GND), and the cathode is electrically connected to the input side of the first MOS transistor (Q1) and the base of the second transistor (Q2). The emitter of the second transistor (Q2) is electrically connected to the input side of the first MOS transistor (Q1), and the collector is electrically connected to the gate of the first MOS transistor (Q1).

4. The charging input protection circuit as described in claim 3, characterized in that, The hardware action threshold V HW The theoretical value satisfies the following formula: 。 5. The charging input protection circuit as described in claim 1, characterized in that, The first MOSFET (Q1) is a P-channel MOSFET, and the software control branch (30) includes a fifth transistor (Q5), a tenth resistor (R10), a fifteenth resistor (R15), and a seventeenth resistor (R17). The control terminal (PV-EN) is electrically connected to the base of the fifth transistor (Q5) via the fifteenth resistor (R15), the seventeenth resistor (R17) is electrically connected between the base and the negative node (PV-GND) of the fifth transistor (Q5), the emitter of the fifth transistor (Q5) is electrically connected to the negative node (PV-GND), and the collector is electrically connected to the gate of the first MOS transistor (Q1) via the tenth resistor (R10).

6. The charging input protection circuit as described in claim 1, characterized in that, It also includes a fourth resistor (R4), which is electrically connected between the source and gate of the first MOSFET (Q1) to keep the first MOSFET (Q1) off when no turn-on control signal is received at the control terminal (PV-EN).

7. The charging input protection circuit as described in claim 1, characterized in that, The processor (200) is also configured to output a conduction control signal to the control terminal (PV-EN) when the charging input voltage drops to a recovery threshold, wherein the recovery threshold is lower than the software protection threshold.

8. The charging input protection circuit as described in claim 1, characterized in that, The sampling branch (20) includes a sixteenth resistor (R16) and a third MOS transistor (Q3). The sixteenth resistor (R16) and the third MOS transistor (Q3) are connected in series, and their connection node is electrically connected to the sampling terminal (PV-AD). The gate of the third MOS transistor (Q3) is electrically connected to the bias network to clamp the voltage drop across the sixteenth resistor (R16) and protect the sampling pin of the processor (200).

9. The charging input protection circuit as described in claim 1, characterized in that, It also includes a second MOSFET (Q4), which is an N-channel MOSFET connected in series in the input negative path (50). The gate of the second MOSFET (Q4) is electrically connected to the input positive network via a fifth resistor (R5) and to the negative node (PV-GND) via an eleventh resistor (R11) so that it can be turned on in normal polarity and blocked in reverse polarity.

10. The charging input protection circuit as described in claim 9, characterized in that, It also includes a second capacitor (C2), a third capacitor (C3), and a Zener diode (ZD2). The second capacitor (C2) and the third capacitor (C3) are connected in series and then connected across the drain and source of the second MOSFET (Q4). The Zener diode (ZD2) is connected in parallel between the gate and source of the second MOSFET (Q4).

11. A charging protection system, characterized in that, It includes a processor (200) and a charging input protection circuit (100), the charging input protection circuit (100) including an input positive terminal path (10), a first MOS transistor (Q1), a sampling branch (20), a software control branch (30) and a detection control branch (40). The first MOS transistor (Q1) is connected in series in the input positive path (10); The output terminal of the sampling branch (20) forms a sampling terminal (PV-AD), the input terminal of the software control branch (30) forms a control terminal (PV-EN), and the output terminal of the software control branch (30) and the control output terminal of the detection control branch (40) are both electrically connected to the gate of the first MOS transistor (Q1). The processor (200) is electrically connected to the sampling terminal (PV-AD) and the control terminal (PV-EN) respectively, and is used to receive the sampling signal characterizing the charging input voltage and compare the charging input voltage characterized by the sampling signal with the software protection threshold. When the charging input voltage reaches or exceeds the software protection threshold, the processor (200) controls the first MOS transistor (Q1) to turn off through the software control branch (30); The detection control branch (40) is used to detect the charging input voltage, and its operation is independent of the comparison result and control of the processor (200); Wherein, the software protection threshold is lower than the hardware action threshold of the detection control branch (40); When the charging input voltage reaches or exceeds the hardware action threshold, the detection control branch (40) turns off the first MOS transistor (Q1); when the charging input voltage reaches or exceeds the hardware action threshold and the processor (200) still keeps the first MOS transistor (Q1) on through the software control branch (30), the detection control branch (40) still turns off the first MOS transistor (Q1).

12. The charging protection system as described in claim 11, characterized in that, It also includes a buck-boost module (300) and a battery module (400). The charging input protection circuit is electrically connected to the buck-boost module (300). The buck-boost module (300) is electrically connected to the battery positive terminal (P+) and the battery negative terminal (P-) of the battery module (400).

13. A charging input overvoltage protection method, applied to the charging input protection circuit (100) according to any one of claims 1 to 10, characterized in that, The sampling terminal (PV-AD) and control terminal (PV-EN) of the charging input protection circuit (100) are electrically connected to the same processor (200), and the charging input overvoltage protection method includes the following steps: The processor (200) acquires a sampling signal representing the charging input voltage output by the sampling branch (20); The processor (200) compares the charging input voltage represented by the sampled signal with a software protection threshold, wherein the software protection threshold is lower than the hardware action threshold of the detection control branch (40). When the charging input voltage reaches or exceeds the software protection threshold, the processor (200) stops outputting the turn-on control signal to the control terminal (PV-EN) so that the software control branch (30) controls the first MOS transistor (Q1) to turn off and disconnects the input positive terminal path (10). The charging input voltage is detected by the detection control branch (40); The operation of the detection control branch (40) does not depend on the comparison result and control of the processor (200); when the charging input voltage reaches or exceeds the hardware action threshold, the detection control branch (40) turns off the first MOS transistor (Q1); when the charging input voltage reaches or exceeds the hardware action threshold and the processor (200) still outputs a conduction control signal to the control terminal (PV-EN), the detection control branch (40) still turns off the first MOS transistor (Q1).

14. The charging input overvoltage protection method as described in claim 13, characterized in that, The charging input overvoltage protection method further includes: When the charging input voltage is lower than the recovery threshold, the processor (200) outputs a turn-on control signal to the control terminal (PV-EN) so that the software control branch (30) controls the first MOS transistor (Q1) to turn on and connect the input positive terminal path (10), wherein the recovery threshold is lower than the software protection threshold.

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