Model prediction-based solid-state transformer voltage balance control method and system

Abstract

The application discloses a model prediction-based solid-state transformer voltage balance control method and system, and relates to the field of power control.The method comprises the following steps: in a current control period, the equivalent series resistance and equivalent capacitance value of each cascade submodule are determined; the effective value of the capacitor ripple current is extracted; the capacitor physical damage value of each cascade submodule is calculated, and the equivalent series resistance and equivalent capacitance value are corrected to obtain the corrected equivalent series resistance and equivalent capacitance value; the corrected equivalent series resistance and equivalent capacitance value are substituted into a discrete-time state prediction model to obtain a preliminary prediction voltage value; the prediction error of the last control period is obtained, and a prediction compensation amount is calculated; the prediction compensation amount is superimposed on the preliminary prediction voltage value to obtain a corrected prediction voltage value; and the optimal switching control vector is solved, a PWM control signal is generated, and the PWM control signal is sent to the driving circuit of each cascade submodule. The application can accurately predict the voltage variation trend of each submodule.

Description

Technical Field

[0001] This application relates to the field of power control, and in particular to a model-predictive-based solid-state transformer voltage balance control method and system. Background Technology

[0002] With the rapid development of power electronics technology, solid-state transformers, as a new generation of power conversion devices, have shown broad application prospects in fields such as smart grids, new energy integration, and electrified transportation. Solid-state transformers typically adopt a modular multilevel converter topology, achieving high-voltage, high-power conversion through multiple cascaded submodules connected in series. Each cascaded submodule contains core components such as power switching devices and DC-side filter capacitors. Among these, the DC-side capacitors play important roles in energy storage, filtering, and voltage support, and are key components determining system reliability.

[0003] During the long-term operation of solid-state transformers, due to slight differences in manufacturing processes, varying heat dissipation conditions caused by installation location, and uneven ambient temperature distribution, the DC-side filter capacitors within each sub-module exhibit significant heterogeneous physical aging characteristics. This aging phenomenon manifests as an abnormal increase in the equivalent series resistance of the capacitors, a gradual decrease in capacitance, and inconsistent degradation rates among different modules. As operating time extends, the capacitor parameters of some sub-modules may deteriorate far more than those of others, resulting in significant performance differences.

[0004] When asymmetrical transient conditions such as single-phase grounding faults, sudden load changes, and three-phase imbalances occur on the grid side, solid-state transformers need to withstand significant instantaneous current surges and voltage fluctuations. Under these conditions, traditional model predictive control methods typically employ a uniform capacitor parameter model, assuming all cascaded submodules have the same electrical characteristics, failing to consider the heterogeneous characteristics of capacitor aging. This uniform prediction model can produce severe prediction biases due to parameter mismatch, causing the controller to be unable to accurately predict the voltage change trends of each submodule, thus affecting the accuracy and response speed of voltage balance control.

[0005] There is currently no effective solution to the above problems. Summary of the Invention

[0006] This application provides a model-based prediction-based voltage balance control method and system for solid-state transformers, which accurately predicts the voltage change trends of each sub-module, ensuring the accuracy and response speed of voltage balance control.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions: Firstly, a model-predictive-based voltage balance control method for solid-state transformers is provided, applied to a solid-state transformer control system. The solid-state transformer control system includes multiple cascaded submodules, sensor components, and a controller. The sensor components are electrically connected to the controller, and the controller is electrically connected to the drive circuits of each cascaded submodule. The method includes: Under the current control cycle, obtain the DC-side capacitor voltage, input current, and heat sink temperature of each level of the interconnected sub-module; Based on the DC-side capacitor voltage and input current, the equivalent series resistance and equivalent capacitance values ​​of each stage of the interconnected sub-modules are determined; Extract the RMS value of the capacitor ripple current from the input current; Based on the heat sink temperature and the effective value of capacitor ripple current, the physical damage values ​​of capacitors in each stage of the interconnect sub-module are calculated, and the equivalent series resistance and equivalent capacitance values ​​are corrected based on the physical damage values ​​of capacitors to obtain the corrected equivalent series resistance and equivalent capacitance values. Substituting the corrected equivalent series resistance and the corrected equivalent capacitance into the discrete-time state prediction model, we obtain the preliminary predicted voltage values ​​of each series submodule at the next time step. The prediction error of the previous control cycle is obtained, and the prediction compensation amount is calculated based on the prediction error. The prediction compensation amount is then added to the initial prediction voltage value to obtain the corrected prediction voltage value. Based on the physical damage values ​​of the capacitors, the cascaded sub-modules are divided into a high-quality response group, a maintenance group, and a stress avoidance group. The switching state of the cascaded sub-modules in the stress avoidance group remains unchanged, while the cascaded sub-modules in the high-quality response group participate in the switching action. Based on the corrected predicted voltage value and the preset multi-objective cost function, the optimal switching control vector is solved in the switching state combination of the high-quality response group; PWM control signals are generated based on the optimal switching control vector and then sent to the drive circuits of each stage of the interconnected sub-modules.

[0008] In one possible implementation of the first aspect, the equivalent series resistance and equivalent capacitance values ​​of each stage of the interconnecting submodules are determined based on the DC-side capacitor voltage and the input current, including: Obtain the voltage sampling sequence of the DC-side capacitor voltage and the current sampling sequence of the input current; Calculate the voltage change between adjacent sampling points in the voltage sampling sequence within a preset time period, and calculate the current integral value in the current sampling sequence within the preset time period; The equivalent capacitance value is calculated based on the ratio of the voltage change to the integral value of the current. Extract the AC component from the input current and calculate the effective value of the AC component. Calculate the peak-to-peak value of the ripple voltage of the DC-side capacitor voltage, and calculate the equivalent series resistance based on the ratio of the effective value of the AC component to the peak-to-peak value of the ripple voltage.

[0009] In another possible implementation of the first aspect, the effective value of the capacitive ripple current in the input current is extracted, including: Perform a fast Fourier transform on the input current to obtain the frequency domain current component; Identify the fundamental frequency point with the largest amplitude in the frequency domain current component; Centered on the fundamental frequency point, a ripple frequency extraction window is determined, wherein the ripple frequency extraction window is used to characterize the bandwidth covering the harmonic range of the fundamental frequency. Extract all frequency domain components within the ripple frequency extraction window; The extracted frequency domain components are subjected to inverse Fourier transform to reconstruct the time-domain ripple current waveform; Calculate the root mean square value of the time-domain ripple current waveform over a complete power frequency cycle; The root mean square value is output as the effective value of the capacitor ripple current.

[0010] In another possible implementation of the first aspect, the equivalent series resistance and equivalent capacitance values ​​are corrected based on the physical damage values ​​of the capacitor to obtain corrected equivalent series resistance and corrected equivalent capacitance values, including: Based on the heat sink temperature, query the preset capacitor temperature characteristic curve to obtain the capacitor capacitance decay coefficient and equivalent series resistance temperature correction coefficient at the current temperature. Based on the effective value of the capacitor ripple current, calculate the ripple heating power of the capacitor under the current operating state, and calculate the cumulative amount of thermal stress inside the capacitor based on the ripple heating power. The accumulated thermal stress is matched with the preset capacitor life model to obtain the equivalent aging time of the capacitor. Based on the equivalent aging time and capacitance decay coefficient, the capacitance degradation rate is calculated, and the capacitance degradation rate is multiplied by the initial equivalent capacitance value to obtain the first corrected capacitance value under the dual effects of temperature and aging. Based on the physical damage values ​​of the capacitor, a mapping function between the damage degree and the parameter offset is constructed to calculate the additional capacitance attenuation and the additional equivalent series resistance increase caused by the physical damage of the capacitor. The capacitance attenuation is subtracted from the first corrected capacitance value to obtain the corrected equivalent capacitance value. The equivalent series resistance temperature correction factor is multiplied by the initial equivalent series resistance to obtain the intermediate value of the equivalent series resistance after temperature correction. The equivalent series resistance is increased by adding the increment to the median value of the equivalent series resistance to obtain the corrected equivalent series resistance.

[0011] In another possible implementation of the first aspect, the corrected equivalent series resistance and the corrected equivalent capacitance are substituted into the discrete-time state prediction model to obtain the preliminary predicted voltage values ​​of each series submodule at the next time step, including: The corrected equivalent series resistance is used as a resistive loss term, and the corrected equivalent capacitance value is used as a capacitive integral term. These are embedded into the preset continuous-time state equation to construct a parameter-corrected continuous state space model. The continuous-time state equation is constructed based on the cascaded topology of a solid-state transformer and includes input current, capacitor voltage, and switching state. The continuous state-space model after parameter correction is discretized in the time domain, and the sampling interval of the current control cycle is used as the discrete step size to derive the voltage discrete prediction equation for the next moment with input current, current DC side capacitor voltage and switching action as independent variables. The input current obtained in the current control cycle and the current DC-side capacitor voltage of each stage of the interconnected sub-module are input into the discrete-time state prediction model. Based on the actual switching state combination of each level of the interconnected sub-module in the current control cycle, calculate the charging and discharging state of the capacitor and the equivalent series resistance voltage drop in the current cycle; The voltage change of the capacitor generated during charging and discharging is superimposed with the voltage drop of the equivalent series resistance to output the preliminary predicted voltage value of each sub-module at the next moment.

[0012] In another possible implementation of the first aspect, a prediction compensation amount is calculated based on the prediction error, and the prediction compensation amount is superimposed on the initial predicted voltage value to obtain a corrected predicted voltage value, including: The prediction error is input into an adaptive filter, and the prediction compensation is calculated through the adaptive filter. The adaptive filter is a decision feedback equalization filter, which includes multiple tap coefficients. The tap coefficients are updated adaptively according to the historical prediction error. The predicted compensation is superimposed on the initial predicted voltage value to obtain the corrected predicted voltage value.

[0013] In another possible implementation of the first aspect, the various cascaded submodules are divided into a high-quality response group, a maintenance group, and a stress avoidance group based on the physical damage values ​​of the capacitors, including: Cascaded sub-modules whose capacitor physical damage values ​​are less than the first damage threshold are classified as high-quality response groups. Cascaded sub-modules whose capacitor physical damage values ​​are greater than or equal to the first damage threshold and less than the second damage threshold are classified into maintenance groups. Cascaded sub-modules whose physical damage values ​​to capacitors are greater than or equal to the second damage threshold are classified into stress avoidance groups, wherein the first damage threshold is less than the second damage threshold.

[0014] In another possible implementation of the first aspect, based on the corrected predicted voltage value and a preset multi-objective cost function, the optimal switching control vector is solved in the switching state combination of the high-quality response group, including: In the switching state combinations of the high-quality response group, the corrected predicted voltage value corresponding to each switching state combination is substituted into the multi-objective cost function to calculate the cost function value corresponding to each switching state combination. The multi-objective cost function includes a voltage deviation term, a switching loss term, and a circulating current suppression term. The voltage deviation term is the sum of the squares of the differences between the corrected predicted voltage value of each stage of the interconnected sub-module and the preset DC voltage reference value. The switching loss term is positively correlated with the number of switching state switching times. The circulating current suppression term is the square of the interphase circulating current. The optimal switch control vector is determined by identifying the switch state combination that minimizes the cost function value.

[0015] Secondly, this application provides a controller, including: The memory is configured to store instructions; and The processor is configured to retrieve the instructions from the memory and, when executing the instructions, to implement the model-predictive solid-state transformer voltage balance control method described above.

[0016] Thirdly, this application provides a solid-state transformer control system, comprising: Multiple cascaded submodules are used to implement voltage transformation; Sensor components are used to acquire the DC-side capacitor voltage, input current, and heat sink temperature of each stage of the interconnecting submodule; The controller is electrically connected to the sensor assembly and to the drive circuits of each level of the sub-modules.

[0017] By employing the aforementioned technical solution, the equivalent series resistance and equivalent capacitance values ​​of each submodule are identified in real time. Combined with multi-dimensional information such as temperature, ripple current, and physical damage, parameter correction is performed, accurately reflecting the actual electrical characteristics of the capacitor and effectively solving the prediction bias problem caused by parameter model mismatch in traditional methods. Introducing an adaptive filter to compensate for prediction errors significantly improves the accuracy and robustness of the prediction model, enabling the controller to accurately predict the voltage change trends of each submodule under asymmetric transient conditions. Through group management based on capacitor health status, differentiated control of submodules with different aging levels is achieved, prioritizing the use of submodules in good health and protecting severely aged submodules, effectively extending the overall lifespan of the system and reducing maintenance costs. Furthermore, through the optimization of multi-objective cost functions, an optimal trade-off is achieved among multiple control objectives such as voltage balance, reducing switching losses, and suppressing circulating current, improving the overall performance of the system. Compared with traditional equal-parameter predictive control methods, this approach fully considers the heterogeneous characteristics of capacitor aging, effectively avoiding the problems of decreased control accuracy and slower response speed caused by parameter mismatch. In summary, this technical solution is not only applicable to voltage balance control of solid-state transformers, but can also be extended to other power electronic devices that adopt modular multilevel topologies. It provides an effective technical means to improve the reliability and economy of power electronic systems under complex operating conditions, and strongly promotes the development of smart grid and new energy access technologies.

[0018] Other features and advantages of the embodiments of this application will be described in detail in the following detailed description section. Attached Figure Description

[0019] Figure 1 A schematic flowchart illustrating a model-predictive-based voltage balance control method for solid-state transformers provided in this application embodiment; Figure 2 An architecture diagram of a solid-state transformer control system provided in an embodiment of this application; Figure 3 This is a flowchart illustrating the division of sub-modules at various levels, as provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for illustration and explanation of the embodiments of this application and are not intended to limit the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0021] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0022] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0023] Figure 1 The illustration schematically shows a flowchart of a model-predictive-based solid-state transformer voltage balance control method according to an embodiment of this application. Figure 1 As shown in the figure, this application provides a model prediction-based solid-state transformer voltage balance control method, which is applied to a solid-state transformer control system. The solid-state transformer control system includes multiple cascaded sub-modules, sensor components, and a controller. The sensor components are electrically connected to the controller, and the controller is electrically connected to the drive circuits of each cascaded sub-module. The method may include the following steps.

[0024] S110. Under the current control cycle, obtain the DC side capacitor voltage, input current and heat sink temperature of each level of the interconnected sub-module; S120. Based on the DC-side capacitor voltage and input current, determine the equivalent series resistance and equivalent capacitance values ​​of each stage of the interconnected sub-modules; S130. Extract the effective value of the capacitor ripple current from the input current; S140. Based on the heat sink temperature and the effective value of capacitor ripple current, calculate the physical damage values ​​of capacitors in each stage of the interconnection sub-module, and correct the equivalent series resistance and equivalent capacitance values ​​based on the physical damage values ​​of capacitors to obtain the corrected equivalent series resistance and corrected equivalent capacitance values. S150. Substitute the corrected equivalent series resistance and the corrected equivalent capacitance into the discrete-time state prediction model to obtain the preliminary predicted voltage values ​​of each stage of the series sub-module at the next moment. S160. Obtain the prediction error of the previous control cycle, calculate the prediction compensation amount based on the prediction error, and add the prediction compensation amount to the initial prediction voltage value to obtain the corrected prediction voltage value. S170. Based on the physical damage values ​​of the capacitor, each cascade submodule is divided into a high-quality response group, a maintenance group, and a stress avoidance group. The switching state of the cascade submodules in the stress avoidance group remains unchanged, while the cascade submodules in the high-quality response group participate in the switching action. S180. Based on the corrected predicted voltage value and the preset multi-objective cost function, the optimal switching control vector is solved in the switching state combination of the high-quality response group. S190. Generate a PWM control signal based on the optimal switching control vector and send the PWM control signal to the drive circuit of each stage of the sub-module.

[0025] In this embodiment, generating a PWM control signal based on the optimal switching control vector and sending the PWM control signal to the drive circuits of each stage of the interconnected submodules may include the following steps: converting the optimal switching control vector into switching state commands corresponding to each stage of the interconnected submodules; generating a PWM control signal according to the switching state commands; and sending the PWM control signal to the gate drive circuits of each stage of the interconnected submodules through a communication interface.

[0026] In another embodiment of this invention, before generating the PWM control signal based on the optimal switching control vector, the following steps may be included: acquiring the instantaneous values ​​of the grid voltage and the inverter-side output current during the current control cycle; using the corrected predicted voltage value as the initial state value, calculating the advanced predicted capacitor voltage of each stage of the interconnected submodule at the end of the next control cycle; calculating the voltage phase shift deviation caused by the turn-on and turn-off delays of the switching devices according to the system matrix in the two-step advanced state prediction algorithm; linearizing the voltage phase shift deviation and extracting the delayed voltage compensation component; vector-adding the advanced predicted capacitor voltage and the delayed voltage compensation component to synthesize the final predicted reference voltage that eliminates the calculation and switching delay; substituting the final predicted reference voltage into the multi-objective cost function for optimal vector optimization to obtain the optimal switching action command after delay compensation; and generating a time-axis aligned PWM control signal and sending it to the drive circuit according to the optimal switching action command after delay compensation.

[0027] In another embodiment of this example, after dividing each cascaded submodule into a high-quality response group, a maintenance group, and a stress avoidance group based on the physical damage values ​​of the capacitors, the method may further include: real-time monitoring of switching events of cascaded submodules transitioning from the high-quality response group or the maintenance group to the stress avoidance group; upon detecting a switching event, locking the current on / off state of the switch of the avoided cascaded H-bridge submodule and marking it as a passive operating mode; calculating the predicted voltage drift trajectory of the DC-side capacitor of the avoided cascaded H-bridge submodule in the locked state; constructing a transient charge redistribution matrix with the remaining active submodules as the main carriers to distribute the voltage imbalance caused by locking; generating a slope limit coefficient for dynamic voltage redistribution based on the voltage imbalance and the remaining absorption capacity of each active submodule; introducing a slope limit coefficient to limit the rate of change of the predicted voltage reference value of the active submodule in the subsequent control cycles to prevent DC-side overvoltage surges; updating the multi-objective cost function based on the smoothed predicted voltage reference value so that the switching action of the active submodule converges along the slope trajectory during the voltage smooth transition.

[0028] In another embodiment of this example, before generating the PWM control signal based on the optimal switching control vector, the method may further include: obtaining the corrected equivalent capacitance values ​​of each cascaded submodule and calculating the overall equivalent capacitive reactance of the cascaded system; calculating the characteristic resonant frequency of the grid-connected side of the system based on the overall equivalent capacitive reactance of the cascaded system and the inductance parameters of the grid-connected filter; determining whether the characteristic resonant frequency enters the cutoff frequency bandwidth of the grid-connected current control loop; if it does, introducing a first-order high-pass filter in the current feedback channel of the controller based on the drift of the characteristic resonant frequency to construct a virtual damper; calculating the virtual resistance and virtual capacitance values ​​required for the virtual damper, wherein the virtual resistance value is positively correlated with the offset of the characteristic resonant frequency; performing phase shifting and amplitude modulation on the feedback current through the virtual damper to generate a high-frequency resonant voltage compensation amount; and superimposing the high-frequency resonant voltage compensation amount onto the output of the multi-objective cost function to inject an inverse resonant damping component into the optimal switching control vector.

[0029] The solid-state transformer control system in this embodiment adopts a modular multilevel converter topology. Figure 2 This paper illustrates an architecture diagram of a solid-state transformer control system according to an embodiment of this application. (Refer to...) Figure 2The solid-state transformer control system comprises multiple cascaded submodules, sensor components, and a controller. Each cascaded submodule consists of an H-bridge power unit, a DC-side filter capacitor, power switching devices, and a heatsink. The sensor components include voltage sensors, current sensors, and temperature sensors, used to acquire the DC-side capacitor voltage, input current, and heatsink temperature of each cascaded submodule, respectively. The controller is electrically connected to the sensor components to acquire real-time measurement data and is also electrically connected to the drive circuits of each cascaded submodule to send PWM control signals. The controller integrates a data acquisition module, a parameter identification module, a predictive calculation module, a group management module, and an optimization solution module, which are used to handle the functions in steps S110 to S190, respectively.

[0030] In practical implementation, when the controller starts the current control cycle, it first synchronously collects the operating status parameters of each stage of the interconnecting submodules through sensor components. Voltage sensors employ Hall effect voltage sensors or resistive voltage divider sampling circuits to acquire the instantaneous value of the DC-side capacitor voltage at microsecond-level sampling intervals. Current sensors employ Hall effect current sensors or current transformers to measure the input current flowing through each stage of the interconnecting submodules in real time. Temperature sensors employ thermistors or semiconductor temperature sensors, installed on the surface of the heat sinks of each stage of the interconnecting submodules to measure the real-time temperature of the heat sinks; the sampling period can be set to an integer multiple of the control cycle.

[0031] The controller transmits the acquired voltage, current, and temperature data to its internal memory via a high-speed serial communication interface or a parallel digital interface, establishing a data snapshot for the current control cycle. To ensure data synchronization, a timestamp mechanism is used to mark the sampling time of each sensor, and an interpolation algorithm is used to align data from different sampling rates to a unified time base. In multiphase systems, voltage and current data for each phase need to be acquired separately, and phase information needs to be labeled. Through this step, the controller obtains the complete real-time dataset required for subsequent parameter identification and predictive control, laying the data foundation for accurate voltage balance control.

[0032] After acquiring real-time measurement data, the controller initiates a parameter identification algorithm. Based on the sampled data of DC-side capacitor voltage and input current, it identifies the equivalent series resistance and equivalent capacitance values ​​of each stage of the interconnecting submodules online. Specifically, it first extracts the voltage sampling sequence of the most recent N sampling points from the data storage. and current sampling sequence Where N is the sliding window length, typically 50 to 100 sampling points. Calculate the voltage change between adjacent sampling points within a preset time period. Where k is the time step. Simultaneously, numerical integration is performed on the current sampling sequence to calculate the current integral value. ,in The sampling period is determined based on the fundamental charging and discharging relationship of a capacitor. and charge The equivalent capacitance value can be obtained. .

[0033] To improve identification accuracy, the least squares method is used to linearly fit multiple sets of voltage changes and current integral values, resulting in a more stable capacitance estimate. For the identification of the equivalent series resistance, the AC component of the input current is first extracted using a high-pass filter. The filter cutoff frequency is set to 1 / 10 of the fundamental frequency, for example, 5Hz in a 50Hz system. The effective value of the AC component is then calculated. Where M is the number of sampling points within one power frequency cycle. Simultaneously, the peak-to-peak value of the ripple voltage of the DC-side capacitor voltage is extracted. This is the difference between the maximum and minimum voltage values ​​within one cycle. According to Ohm's law, the equivalent series resistance can be approximated as... .

[0034] To eliminate the influence of measurement noise, an exponentially weighted average filter was applied to the identification results of multiple consecutive control cycles, with the filter coefficient set between 0.9 and 0.95 to ensure smooth convergence of the parameter estimates. This step yielded equivalent parameters reflecting the current electrical characteristics of each stage of the interconnected submodules, providing benchmark values ​​for subsequent parameter correction and predictive modeling.

[0035] After completing the basic parameter identification, the controller further extracts the effective value of the capacitor ripple current in the input current to quantify the high-frequency stress borne by the capacitor. Specifically, a Fast Fourier Transform (FFT) is performed on the input current sequence acquired in the current control cycle to convert the time-domain current signal into frequency-domain current components. The FFT calculation uses a radix-2 algorithm, and the number of sampling points is chosen to be an integer power of 2, such as 1024 or 2048 points, to improve computational efficiency.

[0036] In the frequency domain, the frequency point with the largest amplitude is identified as the fundamental frequency, which corresponds to the power grid's operating frequency or the converter's modulation frequency. Using the fundamental frequency... Centered on the ripple frequency extraction window, the window bandwidth is set to [value missing]. The frequency range covers the 2nd to 20th harmonics, encompassing the main frequency components of capacitor ripple current. All frequency domain components within the window are extracted, including the amplitude and phase information of each harmonic. An inverse Fourier transform (IFFT) is performed on the extracted frequency domain components to reconstruct the time-domain ripple current waveform. Calculate the root mean square value of the reconstructed waveform over one complete power frequency cycle. Where T is the power frequency period. In the digital implementation, the integration operation is converted into discrete summation. The calculated root mean square (RMS) value is output as the effective value of the capacitor ripple current, which directly reflects the AC loss and thermal stress level inside the capacitor. Through frequency domain analysis, the DC component and low-frequency disturbances are effectively separated, and the high-frequency ripple component that has the most significant impact on capacitor lifespan is accurately extracted, providing key input parameters for subsequent damage assessment.

[0037] After obtaining the heatsink temperature and the effective value of the capacitor ripple current, the controller calculates the physical damage values ​​of the capacitors in each stage of the interconnected submodules and corrects the equivalent series resistance and equivalent capacitance values. In specific implementation, the heatsink temperature is first determined... The system queries the capacitor temperature characteristic curve pre-stored in the controller's memory. This curve, provided by the capacitor manufacturer or obtained through experimental testing, describes how the capacitance and equivalent series resistance change with temperature. The capacitance decay coefficient at the current temperature is then obtained through linear interpolation or spline interpolation. and equivalent series resistance temperature correction factor A typical aluminum electrolytic capacitor may increase its capacitance by 10% to 20% when the temperature rises from 25°C to 85°C, while its equivalent series resistance may decrease by 30% to 50%.

[0038] Next, based on the effective value of the capacitor ripple current and equivalent series resistance Calculate the ripple heating power of the capacitor. Based on ripple heating power, combined with the thermal resistance parameters of the capacitor. Calculate the temperature rise inside the capacitor. Thus, the temperature of the capacitor core can be obtained. Based on the capacitor core temperature and ripple current, the accumulated thermal stress is calculated using a capacitor lifetime model. The commonly used lifetime model is the Arrhenius model, expressed as... ,in For rated life, Rated temperature This is the rated ripple current. Using this model, the equivalent aging time of the capacitor under current operating conditions can be calculated. This refers to the time a capacitor operates under current stress, which is equivalent to the time it operates under rated conditions. The accumulated equivalent aging time is the time the capacitor is considered to have failed when the accumulated value reaches the rated life. Based on the equivalent aging time and the capacitance decay coefficient, the capacitance degradation rate is calculated. ,in This is the capacitance degradation ratio, typically 0.2 to 0.3, indicating a 20% to 30% capacitance degradation at the end of its lifespan. It is calculated by comparing the capacitance degradation rate with the initial equivalent capacitance value. Multiplying these values ​​yields the first corrected capacitance value under the combined effects of temperature and aging. .

[0039] Furthermore, based on the physical damage values ​​of the capacitor A mapping function between damage level and parameter offset is constructed. Damage values ​​are calculated by comprehensively evaluating multiple indicators such as capacitance decay, increase in equivalent series resistance, and increase in leakage current. A typical calculation formula is as follows: ,in These are the weighting coefficients. These represent the changes in capacitance, equivalent series resistance, and leakage current, respectively. Based on the damage values, the additional capacitance attenuation is calculated. and the additional increment of equivalent series resistance ,in This is the damage sensitivity coefficient. The additional capacitance attenuation is subtracted from the first corrected capacitance value to obtain the corrected equivalent capacitance value. .

[0040] For the equivalent series resistance, first multiply the temperature correction factor by the initial value to obtain the temperature-corrected intermediate value. Then, by adding the damage increment, the corrected equivalent series resistance is obtained. This step enables precise correction of the capacitance parameters of each stage of the interconnecting submodules, fully considering the combined effects of temperature, aging, and physical damage, and significantly improving the accuracy of subsequent prediction models.

[0041] After obtaining the corrected equivalent parameters, the controller substitutes them into the discrete-time state prediction model to predict the capacitor voltage of each cascaded submodule at the next time step. In practice, the continuous-time state equations of the solid-state transformer cascaded submodules are first constructed. Based on the circuit topology, the dynamic equation for the capacitor voltage of a single submodule is: ,in This indicates the switch state, with values ​​of +1, 0, or -1, corresponding to the capacitor charging, bypassing, and discharging states, respectively. Let be the input current. This equation describes the rate of change of the capacitor voltage, which is determined by both the charging / discharging current and the equivalent series resistance loss. The corrected equivalent capacitance value... and equivalent series resistance Substitute the state equations to construct a continuous state-space model with corrected parameters. Discretize the continuous model using the forward Euler method or the trapezoidal rule for time-domain discretization.

[0042] Taking the forward Euler method as an example, the discrete prediction equation is: ,in To control the cycle, For the current moment, For the next moment, the input current collected in the current control cycle will be used. and DC side capacitor voltage Substitute the values ​​into the discrete prediction equation. Based on the actual switching states of each stage of the interconnected submodules in the current control cycle... Calculate the charging and discharging current of the capacitor. and equivalent series resistance voltage drop The change in capacitor voltage caused by charging and discharging. The voltage drop at the equivalent series resistance is superimposed to obtain the preliminary predicted voltage value for the next moment. For multiple cascaded submodules, the above calculations are performed separately to obtain the preliminary predicted voltage value vector for each submodule. Through this step, based on the corrected parameter model and the current state, an accurate prediction of the capacitor voltage at the next moment is achieved, providing a reliable state estimate for subsequent optimized control.

[0043] To further improve prediction accuracy, the controller introduces a prediction error compensation mechanism. Specifically, it first obtains the prediction error from the previous control cycle, which is the difference between the predicted voltage value and the actual measured value from the previous cycle. The prediction error sequence The input is an adaptive filter, where L is the error history length. The adaptive filter employs a decision feedback equalizer structure, consisting of a feedforward filter and a feedback filter. The feedforward filter processes the current prediction error, while the feedback filter utilizes historical error information. The filter's tap coefficients are adaptively updated using the Least Mean Square (LMS) algorithm, with the update formula as follows: ,in Let i be the tap coefficient. This is the step size factor, typically ranging from 0.01 to 0.1. This is the corresponding input signal.

[0044] Through adaptive adjustment, the filter can track the statistical characteristics of the prediction error and extract systematic biases and periodic disturbances. The filter output is the prediction compensation amount. ,in This refers to the filter order, typically 5 to 10. The predicted compensation is then added to the initial predicted voltage value to obtain the corrected predicted voltage value. This step effectively compensates for prediction biases caused by model simplification, parameter drift, and external disturbances, significantly improving the accuracy and robustness of the prediction model and enabling the controller to more accurately predict the voltage change trends of each stage of the interconnected submodules.

[0045] After obtaining the corrected predicted voltage value, the controller groups and manages the various interconnecting submodules according to the physical damage values ​​of the capacitors. In specific implementation, two damage thresholds are set: the first damage threshold... Second damage threshold ,in The first damage threshold is typically set to 0.3 to 0.4, indicating that the capacitor has experienced 30% to 40% of its lifespan; the second damage threshold is set to 0.7 to 0.8, indicating that the capacitor is nearing the end of its lifespan. The physical damage values ​​of capacitors in each level of the interconnect submodule are then analyzed. Then, perform grouping and judgment. If This submodule is classified as a high-quality response group, indicating that the capacitor is in good condition and can withstand frequent switching operations and large current stress. If... This submodule is classified as a maintenance group, indicating that the capacitors have aged to some extent but can still function normally; their usage frequency should be appropriately limited. If... The submodule is classified into the stress avoidance group, indicating that the capacitor is severely aged and continued use may lead to failure; therefore, its participation in switching operations should be avoided. For submodules in the stress avoidance group, the controller locks their switching state in the current state, preventing further changes, to reduce switching losses and electrical stress, and extend their remaining lifespan. Submodules in the high-quality response group are allowed to participate in normal switching operations and undertake the main voltage regulation tasks. Submodules in the maintenance group can participate in switching operations, but with lower priority than those in the high-quality response group, and are only used when necessary. This step achieves differentiated management based on capacitor health status, prioritizing the use of submodules in good health and protecting severely aged submodules, effectively extending the lifespan of the entire solid-state transformer system and improving system reliability and economy.

[0046] After grouping the submodules, the controller solves for the optimal switching control vector in the switching state combination space of the high-quality response group, based on the corrected predicted voltage value and the multi-objective cost function. In specific implementation, the number of submodules in the high-quality response group is first determined. Each submodule has 3 switch states (+1, 0, -1), therefore the total number of switch state combinations is: .

[0047] To reduce computational complexity, constraints can be used to reduce the search space, such as limiting the number of sub-modules that operate simultaneously, or employing a hierarchical optimization strategy. For each possible combination of switch states... The corresponding corrected predicted voltage value is then substituted into the multi-objective cost function for evaluation. The multi-objective cost function includes three main terms: voltage deviation term, switching loss term, and circulating current suppression term. The voltage deviation term is defined as follows: ,in This is a preset DC voltage reference value. This item measures the deviation of each submodule's voltage from the reference value, with the goal of making all submodule voltages converge. The switching loss item is defined as follows: ,in This is the switching loss weighting coefficient, which is positively correlated with the number of switching state transitions. Its goal is to reduce unnecessary switching actions, thereby lowering switching losses and device stress. The circulating current suppression term is defined as... ,in This is the circulation suppression weighting coefficient. The interphase circulating current is the target of this project, which aims to suppress the circulating current caused by interphase voltage imbalance and improve system efficiency. The total cost function is... Iterate through all possible combinations of switch states and calculate the total cost function value for each combination. Choose the combination of switch states that minimizes the total cost function value. This serves as the optimal switching control vector. Through this step, an optimal trade-off is achieved among multiple control objectives, such as satisfying voltage balance, reducing switching losses, and suppressing circulating current, resulting in a switching control strategy with the best overall performance. This ensures the stable and efficient operation of the solid-state transformer under complex operating conditions.

[0048] Finally, the controller generates a PWM control signal based on the optimal switching control vector and sends it to the drive circuits of each sub-module. In specific implementation, the optimal switching control vector is first... Converted into the switch status instructions of the corresponding sub-modules at each level.

[0049] For each submodule, a corresponding PWM signal is generated based on its switching state value. At this time, a PWM signal is generated that turns on the upper arm of the H-bridge and turns off the lower arm, and the capacitor is in a charging state; when At this time, a PWM signal is generated that turns off all switches in the H-bridge or turns on the diagonal switches, and the capacitors are in a bypass state; when At this time, a PWM signal is generated that turns on the lower arm of the H-bridge and turns off the upper arm, and the capacitor is in a discharging state.

[0050] The PWM signal is generated using a digital pulse width modulator, with the duty cycle and phase of the PWM waveform set according to the switching state command. To prevent shoot-through between the upper and lower arms of the H-bridge, a dead time, typically 1 to 2 microseconds, is inserted into the PWM signal. The generated PWM control signal is transmitted to the gate drive circuits of each stage of the interconnected submodules via fiber optic cable or high-speed digital isolators. The drive circuits convert the low-voltage control signal into a high-voltage drive signal suitable for the power switching devices, typically 15V to 20V. The drive circuits also include overcurrent protection, overvoltage protection, and short-circuit protection to ensure the safe operation of the power devices. Through this step, the optimized control strategy is transformed into actual switching actions, achieving precise control of each stage of the interconnected submodules and completing the closed-loop process of the entire voltage balance control.

[0051] This embodiment identifies the equivalent series resistance and equivalent capacitance of each submodule in real time and corrects parameters by combining multi-dimensional information such as temperature, ripple current, and physical damage. This accurately reflects the actual electrical characteristics of the capacitor and effectively solves the prediction bias problem caused by parameter model mismatch in traditional methods. By introducing an adaptive filter to compensate for prediction errors, the accuracy and robustness of the prediction model are significantly improved, enabling the controller to accurately predict the voltage change trend of each submodule under asymmetric transient conditions. Through group management based on capacitor health status, differentiated control of submodules with different aging levels is achieved, prioritizing the use of submodules in good health and protecting severely aged submodules, effectively extending the overall service life of the system and reducing maintenance costs. In addition, through the optimization solution of multi-objective cost functions, the optimal trade-off is achieved among multiple control objectives such as voltage balance, reducing switching losses, and suppressing circulating current, improving the overall performance of the system. Compared with the traditional equal parameter predictive control method, this method fully considers the heterogeneous characteristics of capacitor aging and effectively avoids the problems of decreased control accuracy and slower response speed caused by parameter mismatch. In summary, this technical solution is not only applicable to voltage balance control of solid-state transformers, but can also be extended to other power electronic devices that adopt modular multilevel topologies. It provides an effective technical means to improve the reliability and economy of power electronic systems under complex operating conditions, and strongly promotes the development of smart grid and new energy access technologies.

[0052] In one embodiment of this invention, the equivalent series resistance and equivalent capacitance values ​​of each stage of the interconnect submodule are determined based on the DC-side capacitor voltage and the input current, including the following steps: S210. Obtain the voltage sampling sequence of the DC side capacitor voltage and the current sampling sequence of the input current; S220. Calculate the voltage change between adjacent sampling points in the voltage sampling sequence within the preset time period, and calculate the current integral value in the current sampling sequence within the preset time period. S230. The equivalent capacitance value is calculated based on the ratio of the voltage change to the integral value of the current. S240. Extract the AC component from the input current and calculate the effective value of the AC component. S250. Calculate the peak-to-peak value of the ripple voltage of the DC-side capacitor voltage, and calculate the equivalent series resistance based on the ratio of the effective value of the AC component to the peak-to-peak value of the ripple voltage.

[0053] In this embodiment, in order to accurately obtain the equivalent series resistance and equivalent capacitance values ​​of each stage of the series sub-module, the controller needs to extract valid information from the raw data collected by the sensor components and perform parameter identification calculations.

[0054] Specifically, the controller extracts the voltage sampling sequence of the DC-side capacitor voltage and the current sampling sequence of the input current from the buffer of the data acquisition module. In practice, the controller sets a sliding data window with a window length of N sampling points, typically 50 to 100 sampling points, corresponding to a time span of 5 to 10 milliseconds. The voltage sampling sequence is represented as follows: ,in This is the voltage sample value at the current moment. This is the sampling sequence number. The current sampling sequence is represented as follows: It is strictly synchronized with the voltage sampling time.

[0055] To ensure data quality, the controller first preprocesses the sampled sequence, including removing obvious outliers and performing median filtering, with the filtering window length set to 3 to 5 sampling points. In this embodiment, the sampled sequence is stored in a circular buffer, which is updated once per control cycle. New sampled values ​​enter the buffer, while the oldest sampled values ​​are removed, maintaining a constant window length.

[0056] To extract the key feature quantities needed for parameter identification, the controller performs numerical calculations on the voltage and current sampling sequences. For the calculation of voltage changes, the controller selects the start and end points within a preset time period, with a time span of... Set the typical time constant for capacitor charging and discharging. Calculate the voltage change between adjacent sampling points. ,in , The sampling period.

[0057] To improve computational stability, a multi-point averaging method is used to calculate the voltage changes at multiple adjacent points within the window and then take the average value. , where M is the average number of groups.

[0058] For calculating the integral value of the current, the trapezoidal integration method is used to numerically integrate the current sampling sequence. The integral value represents the time period The amount of charge flowing through the capacitor.

[0059] To eliminate the effects of DC bias, the average value of the current sequence is calculated before integration. Then, the current sequence after removing the average value is integrated. This embodiment effectively extracts key feature quantities of the capacitor charging and discharging process, laying the foundation for accurate identification of the equivalent capacitance value and effectively solving the problem of parameter identification error.

[0060] The controller calculates the equivalent capacitance value based on the basic charge-discharge relationship of a capacitor, according to the definition of capacitance. Substituting the integral value of the current (charge) and the voltage change, a preliminary equivalent capacitance value is obtained. .

[0061] Because single calculations may be affected by measurement noise and transient disturbances, the controller uses recursive least squares method for parameter estimation. A linear regression model is then established. ,in To mitigate measurement error, collect multiple sets of data within the window. By minimizing the sum of squared errors Solve for the optimal equivalent capacitance value .

[0062] To further improve the stability of the estimation, an exponentially weighted moving average filter is applied to the identification results over multiple consecutive control cycles. ,in The filter coefficients, typically 0.1 to 0.2, ensure smooth convergence of parameter estimates, effectively suppressing the influence of random noise and obtaining stable and reliable equivalent capacitance values. This effectively solves the problem of parameter identification fluctuations caused by transient disturbances, ensuring the accuracy of parameters in subsequent prediction models.

[0063] The controller extracts the AC component from the input current and calculates its effective value for identification of the equivalent series resistance. In practice, a high-pass filter is first designed to separate the AC and DC components. The high-pass filter employs a second-order Butterworth structure, with a cutoff frequency set to 1 / 10 of the fundamental frequency to retain all AC components contributing to the equivalent series resistance.

[0064] The filter's transfer function is ,in Let be the cutoff angular frequency. In the digital implementation, a bilinear transform is used to convert the continuous-domain transfer function into a discrete-domain difference equation. ,in For the input current sequence, This is the filtered AC component.

[0065] Filter coefficients The sampling frequency and cutoff frequency are pre-calculated and stored. The filtered AC component sequence is then processed. Calculate the RMS value, where P is the number of sampling points within a complete power frequency cycle. The formula for calculating the RMS value is: .

[0066] In this embodiment, to improve computational efficiency, a sliding window accumulation algorithm is adopted. Each control cycle only needs to update the squared values ​​of two sampling points at the window boundary, avoiding repeated calculations of the entire sequence. This embodiment reflects the key parameters of capacitor AC loss and makes a significant contribution to solving the problem of equivalent series resistance identification error caused by DC component interference.

[0067] The controller calculates the peak-to-peak value of the ripple voltage of the DC-side capacitor and, in conjunction with the effective value of the AC component, calculates the equivalent series resistance. In practice, the maximum and minimum values ​​are first searched within the voltage sampling sequence window. and Calculate the peak-to-peak value of the ripple voltage. .

[0068] To avoid occasional spike interference, a sorting method is used to remove a number of the largest and smallest sampling points, for example, removing the top and bottom 5% of extreme points. Then, the maximum and minimum values ​​are found in the remaining data. A calculation model is established based on the relationship between the voltage drop generated by the equivalent series resistance under AC current and the ripple voltage. This formula is based on the assumption that the ripple voltage is mainly caused by the voltage drop across the equivalent series resistance, and the coefficient... This is derived from the conversion relationship between peak value and effective value.

[0069] Considering that the ripple voltage in actual circuits also includes voltage changes caused by capacitor charging and discharging, a correction factor is introduced. The revised calculation formula is as follows: ,in The values ​​were determined through offline calibration experiments, with typical values ​​ranging from 0.7 to 0.9.

[0070] First-order inertial filtering is applied to the identification results of multiple consecutive control cycles. Filter coefficients Setting the value to 0.05 to 0.15 smooths out the estimated equivalent series resistance. Through correlation analysis of voltage ripple and current RMS values, online identification of the equivalent series resistance is achieved, effectively solving the model mismatch problem caused by changes in equivalent series resistance with temperature and aging.

[0071] This embodiment effectively extracts high-quality voltage and current sampling sequences by establishing a sliding data window and a preprocessing mechanism, providing a reliable data foundation for parameter identification and solving the problems of measurement noise and outlier interference. Through precise numerical integration and voltage change calculation, combined with the recursive least squares method, a stable estimate of the equivalent capacitance value is obtained, overcoming the influence of transient disturbances and random noise. By separating the AC component using a high-pass filter and calculating the effective value, key information reflecting the AC loss of the capacitor is accurately extracted, providing precise input for the identification of the equivalent series resistance. Furthermore, by correlating the peak-to-peak value of the ripple voltage with the effective value of the AC current, online identification of the equivalent series resistance is achieved, fully considering its dynamic changes with temperature and aging. Compared with traditional offline calibration or fixed parameter methods, this embodiment can track changes in capacitance parameters in real time, effectively solving the problem of parameter heterogeneity caused by manufacturing differences, installation location, and operating time, and significantly improving the accuracy of the prediction model. In summary, this embodiment is a key technical link in achieving precise voltage balance control, strongly supporting the stable and reliable operation of solid-state transformers under complex operating conditions.

[0072] In one embodiment of this invention, extracting the effective value of the capacitor ripple current in the input current includes the following steps: S310. Perform a fast Fourier transform on the input current to obtain the frequency domain current component. S320: Identify the fundamental frequency point with the largest amplitude in the frequency domain current component; S330. Determine the ripple frequency extraction window centered on the fundamental frequency point, wherein the ripple frequency extraction window is used to characterize the bandwidth covering the harmonic range of the fundamental frequency. S340, Extract all frequency domain components within the ripple frequency extraction window; S350. Perform inverse Fourier transform on the extracted frequency domain components to reconstruct the time domain ripple current waveform. S360. Calculate the root mean square value of the time-domain ripple current waveform over a complete power frequency cycle. S370 outputs the root mean square value as the effective value of the capacitor ripple current.

[0073] In this embodiment, in order to accurately extract the effective value of the capacitor ripple current in the input current, the controller uses a frequency domain analysis method to refine the current signal.

[0074] Specifically, the controller performs a Fast Fourier Transform (FFT) on the input current sampling sequence to convert the time-domain current signal into frequency-domain current components. First, a complete analysis window is extracted from the current sampling buffer, with the window length set to an integer power of 2 to improve FFT computation efficiency. If the number of sampling points is insufficient, zero-padding is used to pad to the target length; if the number of sampling points is too large, the nearest N data points are truncated.

[0075] To reduce spectral leakage, a window function is applied to the time-domain signal before FFT calculation. Commonly used window functions include the Hanning window or the Hamming window. The expression for the Hanning window is as follows: Where n is the sampling point number and N is the window length. The windowed current sequence is: .

[0076] Perform FFT calculation on the windowed current sequence The frequency domain complex sequence is obtained. Where k is the frequency index. Calculate the amplitude at each frequency point. and phase The frequency resolution is ,in The sampling frequency is used. Frequency domain transformation decomposes the complex time-domain current signal into different frequency components, providing clear spectral information for subsequent ripple frequency identification and extraction.

[0077] The controller identifies the fundamental frequency point with the largest amplitude in the frequency domain current component to determine the dominant frequency component of the current signal. This involves traversing the frequency domain amplitude sequence. Search for the maximum amplitude and its corresponding frequency index. To avoid interference from the DC component, the search range starts from k=1, excluding DC terms with k=0. The fundamental frequency is calculated as follows: .

[0078] In practical applications, due to limitations in frequency resolution, the fundamental frequency may not perfectly correspond to a specific discrete frequency point. Therefore, parabolic interpolation is used for frequency refinement. The point of maximum amplitude and its two adjacent points are selected. The precise frequency offset is calculated by fitting a three-point parabola. The corrected fundamental frequency is .

[0079] To improve the robustness of identification, a reasonable range for the fundamental frequency is set. If the identified frequency exceeds this reasonable range, a preset nominal frequency is used as the fundamental frequency. Through precise frequency identification and refinement techniques, the fundamental frequency of the current signal is accurately located, effectively solving the fundamental frequency identification error problem caused by frequency fluctuations and frequency resolution limitations.

[0080] The controller uses the identified fundamental frequency as the center to determine the ripple frequency extraction window, which is used to selectively extract frequency components related to capacitor ripple. Based on the modulation characteristics of the solid-state transformer and the frequency distribution of capacitor ripple, the ripple frequency is mainly concentrated within integer multiples of the fundamental frequency. The lower limit frequency of the ripple frequency extraction window is set to... The upper limit frequency is It covers the range of 2nd to 20th harmonics.

[0081] Convert frequency range to frequency index range and ,in Indicates rounding up. This indicates rounding down. The ripple frequency extraction window is defined as the frequency index range. .

[0082] In this embodiment, the window range can be dynamically adjusted according to the actual spectral distribution characteristics. For example, by analyzing the energy distribution of the spectrum, the frequency corresponding to when the accumulated energy reaches 95% of the total energy is calculated as the upper limit frequency to adaptively eliminate high-frequency noise. By reasonably setting the frequency extraction window, the capacitor ripple component is effectively separated from other frequency components, which can effectively solve the problem of DC component and fundamental component interference ripple current extraction in traditional methods.

[0083] The controller extracts all frequency components within the ripple frequency extraction window to construct a clean ripple frequency spectrum. A new frequency domain sequence with the same length as the original frequency domain sequence is then created. Initialize all elements to zero. Iterate through the frequency index range of the ripple frequency extraction window. Copy the corresponding frequency components from the original frequency domain sequence to the new sequence. For frequencies outside the window, maintain the zero value of the new sequence. .

[0084] Due to the symmetry of the FFT, for a real-valued input signal, the latter half of the frequency domain sequence is the conjugate symmetry of the former half; therefore, the negative frequency portion also needs to be processed. For a frequency index k, the index of its symmetric point is... The frequency domain components of the symmetrical points are also extracted accordingly. .

[0085] This embodiment employs a gradual transition at the window boundary. The transition band width is set to 5% to 10% of the window width, and a gradual weight is applied to the frequency domain components within the transition band. ,in This represents the frequency index number corresponding to the transition band width. By selectively extracting frequencies and smoothing the transition, a frequency domain sequence containing only ripple frequency components is constructed, which can effectively solve the problem of time-domain waveform distortion caused by frequency truncation.

[0086] The controller performs an inverse Fourier transform (IFFT) on the extracted frequency domain components to reconstruct the time-domain ripple current waveform. This process is then applied to the pure ripple frequency domain sequence. Perform IFFT operation The time-domain ripple current sequence is obtained. .

[0087] Since the input signal is a real number, the output of the IFFT should theoretically also be a real number. However, due to numerical calculation errors, there may be a small imaginary part. Therefore, the real part is taken as the final ripple current waveform. To compensate for the amplitude attenuation introduced by the window function during the FFT process, amplitude correction is performed on the reconstructed ripple current waveform. The correction coefficient is the average value of the window function. The corrected ripple current is .

[0088] The reconstructed time-domain ripple current waveform retains the amplitude and phase information of all ripple frequency components in the original current signal, fully reflecting the AC current stress borne by the capacitor. Through inverse frequency domain transformation and amplitude correction, a clean ripple current time-domain waveform is accurately reconstructed, effectively solving the problem that direct time-domain filtering methods cannot completely separate ripple components.

[0089] The controller calculates the root mean square value of the reconstructed time-domain ripple current waveform over a complete power frequency cycle. First, the number of sampling points corresponding to a complete power frequency cycle is determined. ,in Sampling frequency, The fundamental frequency is used. The M most recent sampling points are extracted from the reconstructed ripple current sequence. Calculate the root mean square value. .

[0090] To improve computational efficiency, a sliding window accumulation algorithm is adopted, and a sum of squares accumulator is maintained. During each control cycle update, the squared value of the oldest sampled point is subtracted from the accumulator, and the squared value of the latest sampled point is added. Then calculate the root mean square value. This algorithm avoids repeatedly calculating the sum of squares of the entire sequence, significantly reducing computational complexity.

[0091] To further improve stability, a moving average filter is applied to the root mean square values ​​over multiple consecutive control cycles. Where L is the moving average window length. By accurately calculating the root mean square value and using moving average filtering, a stable and reliable RMS value of the ripple current is obtained, which can effectively solve the problem of transient fluctuations and computational noise affecting the estimation of the RMS value.

[0092] The controller outputs the calculated root mean square (RMS) value as the effective value of the capacitor ripple current for subsequent capacitor physical damage assessment and parameter correction. The filtered RMS value... The data is stored in the controller's shared data area and marked with a timestamp and data validity flag. To ensure data traceability, the controller also records key parameters during the calculation process, including the fundamental frequency. Ripple frequency extraction window range The number of sampling points N and the number of sampling points M for the power frequency cycle, etc.

[0093] In this embodiment, for a multiphase system, the effective value of the ripple current for each phase is calculated separately, and the vector sum or arithmetic mean of the three-phase ripple currents can be further calculated to assess the overall ripple stress level. The output effective value of the ripple current directly reflects the AC loss and thermal stress inside the capacitor, and is a key parameter for assessing physical damage to the capacitor and predicting its remaining life.

[0094] This embodiment converts the time-domain current signal into frequency-domain current components using FFT, clearly separating different frequency components and providing a spectral basis for subsequent ripple identification. By accurately identifying the fundamental frequency point and employing parabolic interpolation refinement technology, the dominant frequency of the current signal is accurately located, overcoming the limitations of frequency resolution and the influence of frequency fluctuations. By reasonably setting the ripple frequency extraction window, the capacitor ripple component is effectively separated from the DC component and the fundamental component, overcoming the problem that traditional time-domain filtering methods cannot completely separate multiple frequency components. Furthermore, by reconstructing the pure ripple current time-domain waveform through inverse Fourier transform and calculating its root mean square value, an accurate effective value of the ripple current reflecting the AC stress of the capacitor is obtained. Compared with traditional time-domain filtering methods, this embodiment has higher frequency selectivity and stronger anti-interference capability, significantly improving the measurement accuracy of the effective value of the ripple current and providing accurate and reliable input data for capacitor physical damage assessment and parameter correction.

[0095] In one embodiment of this invention, the equivalent series resistance and equivalent capacitance values ​​are corrected based on the physical damage values ​​of the capacitor to obtain the corrected equivalent series resistance and equivalent capacitance values, including the following steps: S410. Based on the heat sink temperature, query the preset capacitor temperature characteristic curve to obtain the capacitor capacitance decay coefficient and equivalent series resistance temperature correction coefficient at the current temperature. S420. Based on the effective value of the capacitor ripple current, calculate the ripple heating power of the capacitor under the current operating state, and calculate the accumulated thermal stress inside the capacitor based on the ripple heating power. S430. Match the accumulated thermal stress with the preset capacitor life model to obtain the equivalent aging time of the capacitor. S440. Calculate the capacitance degradation rate of the capacitor based on the equivalent aging time and capacitance decay coefficient, and multiply the capacitance degradation rate by the initial equivalent capacitance value to obtain the first corrected capacitance value under the dual influence of temperature and aging. S450. Based on the physical damage values ​​of the capacitor, construct a mapping function between the degree of damage and the parameter offset, and calculate the additional capacitance attenuation and the additional equivalent series resistance increase caused by the physical damage of the capacitor. S460. Subtract the additional capacitance attenuation from the first corrected capacitance value to obtain the corrected equivalent capacitance value. S470. Multiply the equivalent series resistance temperature correction factor with the initial equivalent series resistance to obtain the intermediate value of the equivalent series resistance after temperature correction. S480. The incremental value of the equivalent series resistance is added to the median value of the equivalent series resistance to obtain the corrected equivalent series resistance.

[0096] In this embodiment, to accurately reflect the actual electrical characteristics of the capacitors in each stage of the interconnect module, the controller needs to perform multi-dimensional corrections on the identified equivalent series resistance and equivalent capacitance values. Specifically, the controller queries a pre-stored capacitor temperature characteristic curve based on the collected heat sink temperature to obtain temperature-related correction coefficients. The capacitor temperature characteristic curve is provided by the capacitor manufacturer or obtained through experimental calibration and is stored in the controller's non-volatile memory in the form of a lookup table. The lookup table contains temperature sampling points and corresponding correction coefficients, with temperature sampling points typically spaced at 5°C or 10°C intervals, covering the operating temperature range.

[0097] For aluminum electrolytic capacitors, the capacitance increases with increasing temperature, while the equivalent series resistance decreases with increasing temperature. When the actual measured temperature of the heatsink... When the sampling point is not in the lookup table, linear interpolation or cubic spline interpolation is used to calculate the correction coefficient. The linear interpolation formula is as follows: ,in and For adjacent temperature sampling points, .

[0098] In this embodiment, a binary search algorithm is used to quickly locate the temperature range to improve query efficiency. By querying the temperature characteristic curve and interpolating, the capacitor parameter correction coefficient at the current temperature is accurately obtained, which can effectively solve the problem of capacitor parameter drift caused by temperature changes.

[0099] The controller calculates the ripple heating power based on the effective value of the capacitor ripple current and assesses the accumulated thermal stress inside the capacitor based on the heating power. The ripple heating power is determined by the Joule heat generated by the ripple current across the equivalent series resistance, and the calculation formula is as follows: ,in This is the effective value of the capacitor ripple current. This is the currently identified equivalent series resistance.

[0100] Considering that the equivalent series resistance is affected by temperature, we can first use the temperature-corrected equivalent series resistance for calculation. Based on the thermal resistance parameters of the capacitor Calculate the temperature rise of the capacitor core caused by ripple heating. The capacitor core temperature is .

[0101] The cumulative thermal stress is calculated using the cumulative damage theory, based on the Arrhenius model. The cumulative thermal stress per unit time is: ,in To control the cycle, For rated life, The rated temperature. The cumulative thermal stress is obtained by integration. By calculating the ripple heating power and thermal resistance model, the thermal stress level borne by the capacitor was accurately assessed, which can effectively solve the problem of life assessment deviation caused by neglecting the thermal effect of ripple current in traditional methods.

[0102] The controller performs a matching calculation between the accumulated thermal stress and a preset capacitor lifespan model to obtain the equivalent aging time of the capacitor. The capacitor lifespan model comprehensively considers the dual effects of temperature stress and current stress, and a modified model is used. ,in denoted as the rated ripple current, and n as the current stress exponent.

[0103] Equivalent aging time is defined as the time taken to operate under rated conditions per unit time under current stress conditions, and the calculation formula is as follows: The cumulative equivalent aging time is .

[0104] To enable online calculations, the controller can maintain an aging time accumulator, which is updated once per control cycle. When the cumulative equivalent aging time reaches the rated life. At this point, the capacitor is considered to have reached the end of its lifespan. To prevent accumulator overflow, double-precision floating-point storage is used, and the accumulated value is periodically written to non-volatile memory to prevent loss upon power failure. Through lifespan model matching calculations, the accumulated thermal stress is converted into a quantifiable equivalent aging time, which effectively solves the problem of the difficulty in quantitatively assessing the degree of capacitor aging.

[0105] The controller calculates the capacitance degradation rate based on the equivalent aging time and capacitance decay coefficient, and obtains the first corrected capacitance value under the combined effects of temperature and aging. The capacitance decay with aging time exhibits a non-linear characteristic, with slow initial decay followed by accelerated decay. A piecewise linear model is used to describe the capacitance decay law, dividing the lifespan into three stages: initial, middle, and final stages.

[0106] The capacity degradation rate is calculated as follows: ,in This represents the maximum attenuation ratio. It is a piecewise linear function. The first correction capacitor value takes into account the effects of temperature and aging. ,in The initial equivalent capacitance value is used for identification. This formula shows that increased temperature increases capacitance, while aging decreases it, and both factors jointly determine the actual capacitance value. Through capacitance degradation rate calculation and dual correction, the combined effects of temperature and aging on capacitance are accurately reflected, effectively solving the parameter deviation problem caused by single-factor correction.

[0107] The controller constructs a mapping function between the degree of damage and parameter offset based on the physical damage values ​​of the capacitor, and calculates the additional parameter changes caused by the physical damage. (Capacitor physical damage values) It was calculated by comprehensively evaluating multiple health indicators, including capacity decay rate. Equivalent series resistance growth rate and leakage current growth rate .

[0108] The formula for calculating damage values ​​is as follows: The weighting coefficient Determined based on the degree of influence of each indicator on capacitor performance, satisfying... .

[0109] The mapping function adopts an exponential model. ,in For parameter offset, These are the initial parameter values. The damage sensitivity coefficient, It is a non-linear exponent. Calculate the additional capacity attenuation. and the additional increment of equivalent series resistance By constructing a nonlinear mapping function, the additional impact of physical damage on capacitance parameters is accurately quantified, which can effectively solve the problem that aging models cannot fully describe the effects of physical damage.

[0110] The controller subtracts the capacitance attenuation from the first corrected capacitance value to obtain the final corrected equivalent capacitance value. The corrected equivalent capacitance value is calculated as follows: .

[0111] To prevent the corrected capacitance value from being unreasonably negative or too small, a lower limit constraint is set. That is, the corrected capacitance value should not be lower than 50% of the initial value. If the calculated result is lower than the lower limit, the corrected value will be set to the lower limit value, and a severe capacitor aging alarm will be triggered.

[0112] In this embodiment, to avoid control instability caused by sudden parameter changes, a rate limit is applied to the corrected capacitance value, ensuring that the change within a single control cycle does not exceed 1% of the initial value. If the calculated change exceeds the limit, a gradual update method will be used. ,in This is the correction value calculated for the current cycle. By adding attenuation deduction and constraint protection, a reasonable and reliable corrected equivalent capacitance value is obtained, which can effectively solve the numerical anomalies and control instability problems that may be caused by parameter correction.

[0113] The controller multiplies the equivalent series resistance temperature correction factor by the initial equivalent series resistance to obtain the intermediate value of the temperature-corrected equivalent series resistance. The temperature-corrected equivalent series resistance is calculated as follows: ,in To identify the initial equivalent series resistance, This is the temperature correction factor obtained.

[0114] Since the equivalent series resistance decreases with increasing temperature, when the heat sink temperature is higher than the nominal temperature, This reduces the corrected equivalent series resistance; conversely, when the temperature is below the nominal temperature, This increases the corrected equivalent series resistance. This temperature correction reflects the changes in the conductivity of the electrolyte and the dielectric loss within the capacitor with temperature.

[0115] To improve the accuracy of the correction, the effect of the rate of temperature change can be considered, and a dynamic correction term can be introduced. ,in The coefficient of temperature change. The rate of change of the heat sink temperature is calculated using the temperature difference between adjacent control cycles. Through multiplication using a temperature correction coefficient, the effect of temperature on the equivalent series resistance is accurately reflected, effectively solving the problem of prediction deviation in equivalent series resistance caused by temperature changes.

[0116] The controller adds an increment to the equivalent series resistance and adds it to the median value of the equivalent series resistance to obtain the final corrected equivalent series resistance. The corrected equivalent series resistance is calculated as follows: This formula takes into account both the effects of temperature and physical damage on the equivalent series resistance.

[0117] To prevent the corrected equivalent series resistance from becoming unreasonably high, an upper limit constraint is set. That is, the corrected equivalent series resistance shall not exceed three times the initial value. If the calculated result exceeds the upper limit, the corrected value shall be set to the upper limit, and a severe capacitor aging alarm shall be triggered. Similarly, a rate limit shall be applied to the corrected equivalent series resistance, and the change within a single control cycle shall not exceed 2% of the initial value. .

[0118] The corrected equivalent series resistance and equivalent capacitance values ​​together constitute a parametric model reflecting the actual electrical characteristics of the capacitor, which is used for subsequent state prediction and control optimization. By adding incremental superposition and constraint protection, an accurate and reliable corrected equivalent series resistance is obtained, ensuring the accuracy of the prediction model and the stability of the control system.

[0119] This embodiment accurately obtains temperature-related correction coefficients through temperature characteristic curve lookup and interpolation calculations, solving the problem of capacitor parameter drift caused by temperature changes. By calculating ripple heating power and assessing accumulated thermal stress, the thermal stress level borne by the capacitor is accurately quantified, overcoming the limitation of traditional methods that ignore the thermal effect of ripple current. Through lifetime model matching calculations, the accumulated thermal stress is converted into a quantifiable equivalent aging time, achieving a quantitative assessment of the capacitor's aging degree. Furthermore, by constructing a nonlinear mapping function between damage degree and parameter offset, the additional impact of physical damage on capacitor parameters is accurately quantified, compensating for the shortcomings of the aging model. Through step-by-step correction and constraint protection, corrected equivalent parameters that comprehensively consider temperature, aging, and physical damage are obtained, significantly improving the accuracy of the parameter model. Compared with traditional fixed-parameter or single-factor correction methods, this embodiment fully considers the complex characteristics of heterogeneous capacitor aging, effectively solving the prediction bias problem caused by parameter mismatch, and providing a reliable parameter basis for subsequent accurate voltage prediction and balance control.

[0120] In one embodiment of this invention, the corrected equivalent series resistance and the corrected equivalent capacitance are substituted into the discrete-time state prediction model to obtain the preliminary predicted voltage values ​​of each series submodule at the next time step, including the following steps: S510. The corrected equivalent series resistance is used as a resistive loss term, and the corrected equivalent capacitance value is used as a capacitive integral term. These are then embedded into the preset continuous-time state equation to construct a parameter-corrected continuous state space model. The continuous-time state equation is constructed based on the cascaded topology of a solid-state transformer and includes input current, capacitor voltage, and switching state. S520. The continuous state-space model after parameter correction is discretized in the time domain, and the sampling interval of the current control cycle is used as the discrete step size to derive the voltage discrete prediction equation for the next moment with input current, current DC side capacitor voltage and switching action as independent variables. S530: Input the input current obtained in the current control cycle and the current DC-side capacitor voltage of each stage of the interconnected sub-module into the discrete-time state prediction model; S540. Based on the actual switching state combination of each level of the interconnected sub-module in the current control cycle, calculate the charging and discharging state of the capacitor and the equivalent series resistance voltage drop in the current cycle. S550 superimposes the change in capacitor voltage generated during charging and discharging with the voltage drop across the equivalent series resistance to output the preliminary predicted voltage value of each sub-module at the next moment.

[0121] In this embodiment, to accurately predict the capacitor voltage of each cascaded submodule at the next moment, the controller needs to substitute the corrected equivalent parameters into the discrete-time state prediction model for forward prediction calculation. Specifically, the controller embeds the corrected equivalent series resistance and equivalent capacitance values ​​into a preset continuous-time state equation to construct a parameter-corrected continuous state-space model. According to the cascaded H-bridge topology of the solid-state transformer, the dynamic characteristics of the capacitor voltage of a single submodule are jointly determined by the charging and discharging process of the capacitor and the energy loss of the equivalent series resistance.

[0122] The continuous-time state equation is based on Kirchhoff's current law and is expressed as follows: ,in The voltage across the capacitor. This is the corrected equivalent capacitance value. This is a switch state function, taking values ​​of +1 (charging), 0 (bypassing), or -1 (discharging). For input current, This represents the corrected equivalent series resistance. The physical meaning of this equation is: the rate of change of the capacitor voltage is determined by the charging and discharging current. and equivalent series resistance loss current The difference determines the value. The corrected equivalent capacitance value, as the coefficient of the capacitive integral term, directly affects the magnitude of the voltage change rate; the corrected equivalent series resistance, as the parameter of the resistive loss term, determines the rate of energy loss.

[0123] By combining the state equations of each level of connected submodules, a continuous state-space model with multiple inputs and multiple outputs is constructed. ,in For state vectors, For the input vector, and The system matrix and input matrix are defined by their elements, which are determined by the modified equivalent parameters. By embedding heterogeneous parameters into the state equations, a continuous state-space model reflecting the actual electrical characteristics of each submodule is constructed, which can effectively solve the problem that traditional equal parameter models cannot describe the differences between submodules.

[0124] The controller discretizes the continuous state-space model after parameter correction in the time domain, deriving the discrete prediction equation. Forward Euler discretization is used, with the sampling interval of the current control cycle as the basis. As the distance from the step length. The basic principle of the forward Euler method is to approximate the differential with a difference, that is... ,in Indicates the current moment. Indicates the next moment.

[0125] Discretizing the continuous-time state equation yields After simplification, the discrete prediction equation is obtained. .

[0126] This equation shows that the capacitor voltage at the next moment consists of three parts: the decay term of the current voltage. and charge / discharge increment terms Attenuation coefficient This reflects the energy loss caused by the equivalent series resistance. The coefficient is less than 1, indicating that the capacitor voltage will gradually decrease when there is no external charging.

[0127] In this embodiment, to ensure discretization accuracy, the control period is... It should be much smaller than the system's time constant. For applications requiring higher precision, the trapezoidal rule or Runge-Kutta method can be used for discretization. By discretizing in the time domain, the continuous state-space model is transformed into discrete predictive equations suitable for digital controller implementation, effectively solving the problem that continuous models cannot be directly used for digital control.

[0128] The controller inputs real-time measurement data acquired during the current control cycle into the discrete-time state prediction model. It reads the input current at the current moment from the sensor data buffer. DC-side capacitor voltage of each level of interconnecting sub-module To ensure data consistency over time, the sampling times of all sensors should be strictly synchronized.

[0129] The collected data undergoes validity checks, including numerical range checks and rate of change checks. Voltage values ​​should be within a reasonable range; current values ​​should be within a reasonable range of the rated current. The rate of change check determines whether there are abnormal jumps by calculating the difference between adjacent sampling points. If the voltage or current change within a single control cycle exceeds a set threshold, it is considered abnormal data, and the data from the previous cycle or linear interpolation data is used instead.

[0130] The validated data is organized into a vector form according to the submodule numbers and used as the initial conditions for the discrete prediction equation. Real-time data input and validity checks provide an accurate and reliable initial state for the prediction calculation, effectively addressing the problem of measurement noise and outlier data affecting prediction accuracy.

[0131] The controller calculates the charging / discharging state of the capacitors and the equivalent series resistance voltage drop based on the actual switching state combinations of each submodule in the current control cycle. It also reads the switching state of each submodule. The switching state is determined by the optimized control algorithm of the previous control cycle and has been executed.

[0132] For each submodule, the charging and discharging current is calculated based on its switching state and input current. .when hour, When the capacitor is charging, current flows into the capacitor; when hour, When the capacitor is in a discharging state, current flows out of the capacitor; when hour, The capacitor is in bypass mode and there is no charging or discharging current.

[0133] Calculate the change in capacitor voltage caused by charging and discharging. At the same time, calculate the voltage drop across the equivalent series resistance. The voltage drop across the capacitor caused by the equivalent series resistance voltage drop is: By analyzing switch states and calculating current paths, the charging and discharging states and energy losses of the capacitor are accurately determined, effectively solving the problem of unclear relationship between switch action and voltage changes.

[0134] The controller superimposes the capacitor voltage change generated during charging and discharging with the equivalent series resistance voltage drop, and outputs the preliminary predicted voltage values ​​of each stage of the series submodules at the next time step. According to the discrete prediction equation, the predicted voltage at the next time step is... Expand to .

[0135] This formula shows that the predicted voltage consists of three parts: the current voltage, the charge / discharge increment, and the attenuation. Performing the above calculations on all cascaded submodules yields the predicted voltage vector. .

[0136] To improve computational efficiency, vectorized operations are adopted, merging the calculations of all submodules into matrix operations. ,in and This is a diagonal matrix, where the diagonal elements represent the corrected equivalent series resistance and equivalent capacitance values ​​of each submodule. It is an identity matrix.

[0137] The initial predicted voltage value output serves as the basis for subsequent error compensation and optimized control. By superimposing voltage changes and performing vectorized calculations, voltage prediction for each submodule is completed efficiently and accurately, effectively solving the problem of high computational complexity in parallel prediction across multiple modules.

[0138] This embodiment constructs a state-space model reflecting the actual electrical characteristics of each submodule by embedding the modified heterogeneous parameters into the continuous-time state equation, thus solving the problem that traditional equal-parameter models cannot describe the differences between submodules. The continuous model is converted into discrete prediction equations suitable for digital controller implementation, overcoming the limitation that continuous models cannot be directly applied. Real-time data input and validity checks provide accurate and reliable initial states for prediction calculations, ensuring a solid data foundation for prediction. Furthermore, through switching state analysis and charge / discharge calculations, the operating state of the capacitor and voltage change patterns are accurately determined, clarifying the causal relationship between switching actions and voltage changes. Finally, through the superposition and vectorized calculation of voltage changes, parallel prediction of multiple modules is achieved, significantly improving computational efficiency. Compared with traditional fixed-parameter prediction methods, this embodiment fully considers the heterogeneous aging characteristics of capacitors, effectively solving the prediction deviation problem caused by parameter mismatch, significantly improving the accuracy of voltage prediction, and providing a reliable prediction foundation for subsequent error compensation and optimized control.

[0139] In one embodiment of this invention, a prediction compensation amount is calculated based on the prediction error, and the prediction compensation amount is superimposed on the initial prediction voltage value to obtain a corrected prediction voltage value. This includes the following steps: S610. Input the prediction error into the adaptive filter and calculate the prediction compensation amount through the adaptive filter. The adaptive filter is a decision feedback equalization filter, which includes multiple tap coefficients. The tap coefficients are adaptively updated according to the historical prediction error. S620. The predicted compensation amount is superimposed on the initial predicted voltage value to obtain the corrected predicted voltage value.

[0140] The process of adding the predicted compensation amount to the initial predicted voltage value to obtain the corrected predicted voltage value includes: subtracting the actual DC-side capacitor voltage at the current moment from the predicted voltage obtained in the previous control cycle to obtain the single prediction deviation for the current control cycle; applying a sliding window smoothing filter to the single prediction deviation to remove high-frequency random measurement noise from the sensor and obtain the steady-state prediction deviation; inputting the steady-state prediction deviation into a decision feedback equalization filter to calculate the dynamic prediction compensation amount; calculating the rate of change of the single prediction deviation to characterize the transient trend of voltage fluctuations; calculating a dynamic forgetting adjustment coefficient based on the rate of change to adjust the fusion ratio of the steady-state prediction deviation and the dynamic prediction compensation amount in real time; multiplying the dynamic prediction compensation amount by the dynamic forgetting adjustment coefficient and weighting it with the steady-state prediction deviation to generate the final prediction compensation amount; and accumulating the final prediction compensation amount to the initial predicted voltage value of each stage of the interconnected submodule at the next moment to output the corrected predicted voltage value.

[0141] In this embodiment, to further improve the accuracy of voltage prediction, the controller introduces a prediction error compensation mechanism based on an adaptive filter. Specifically, the controller inputs the prediction error into the adaptive filter to calculate the prediction compensation amount. First, the single prediction deviation for the current control cycle is calculated. ,in This represents the actual DC-side capacitor voltage measured by the sensor at the current moment. This is the voltage value at the current moment predicted in the previous control cycle. This prediction deviation reflects the difference between the prediction model and the actual system.

[0142] Because sensor measurements contain high-frequency random noise, directly using a single prediction error would introduce unnecessary fluctuations. Therefore, a sliding window smoothing filter is used. The sliding window length is set to L control cycles, and the steady-state prediction error is calculated. This moving average filter effectively eliminates high-frequency random measurement noise while retaining the low-frequency components of systematic bias.

[0143] The steady-state prediction bias is input into the decision feedback equalization filter (DFE), which consists of a feedforward filter and a feedback filter. The feedforward filter processes both current and historical steady-state prediction biases, while the feedback filter utilizes compensated historical error information. The dynamic prediction compensation output by the filter is... ,in and These are the orders of the feedforward and feedback filters, respectively. and This is the tap coefficient.

[0144] The tap coefficients are adaptively updated using the Least Mean Square (LMS) algorithm. ,in The step size factor is used to balance convergence speed and stability. Through adaptive filtering, systematic biases and periodic disturbances in the prediction error are accurately extracted, effectively solving the problem that fixed compensation cannot track dynamic changes.

[0145] To further improve the adaptability of the compensation, the controller calculates the rate of change of a single prediction error. This rate of change reflects the transient trend of voltage fluctuations. When the rate of change is large, it indicates that the system is in a rapidly changing transient process, and more reliance should be placed on dynamic prediction compensation. When the rate of change is small, it indicates that the system is in a steady state, and more reliance should be placed on steady-state prediction deviation.

[0146] Calculate the dynamic forgetting regulation coefficient based on the rate of change. ,in This is the sensitivity coefficient. This coefficient decreases as the rate of change increases, achieving adaptive weight adjustment for transient and steady-state conditions.

[0147] The dynamic prediction compensation is multiplied by the dynamic forgetting adjustment coefficient and then weighted and synthesized with the steady-state prediction bias to generate the final prediction compensation. This weighted synthesis strategy relies more on the dynamic compensation of the adaptive filter in the transient state and more on the smoothed steady-state deviation in the steady state, achieving an optimal balance between transient response speed and steady-state accuracy.

[0148] In this embodiment, the dynamic adjustment mechanism can effectively solve the problem that fixed weights cannot adapt to different working conditions, and significantly improve the adaptability and robustness of compensation.

[0149] The controller adds the final predicted compensation to the initial predicted voltage value to obtain the corrected predicted voltage value. Compensation is then performed separately for each stage of the interconnecting submodules. ,in Let be the initial predicted voltage value for the i-th submodule. This is the corresponding predicted compensation amount.

[0150] To prevent excessive compensation from distorting the predicted values, an amplitude limit is set for the compensation amount. ,in This is a DC voltage reference value. If the calculated compensation exceeds the limit, saturation processing is performed. .

[0151] Meanwhile, to avoid abrupt changes introduced by compensation, the compensation amount is rate-limited, and the change in compensation amount within a single control cycle does not exceed 1% of the reference voltage, i.e. .

[0152] The corrected predicted voltage value integrates the initial prediction based on the physical model and the compensation correction based on historical errors, making full use of the physical mechanism of the model and the statistical regularity of the data, thus significantly improving the prediction accuracy. Through the superposition of compensation amounts and constraint protection, the final correction of the predicted voltage is completed, effectively solving the problem of insufficient accuracy of a single prediction method.

[0153] The corrected predicted voltage value is stored in the controller's shared data area for use by the optimized control algorithm. To facilitate subsequent analysis and debugging, the controller also records the prediction error sequence, compensation sequence, and tap coefficient sequence, and calculates prediction accuracy indicators, including mean absolute error (MAE) and root mean square error (RMSE).

[0154] The mean absolute error is calculated as follows: The root mean square error is calculated as follows: , where M is the statistical window length. These accuracy metrics are used to evaluate the performance of prediction models and compensation algorithms, and can serve as criteria for triggering model recalibration or parameter updates.

[0155] This embodiment eliminates measurement noise and extracts systematic prediction bias through sliding window smoothing filtering, solving the problem of accuracy in random noise interference compensation. Adaptive processing using a decision feedback equalization filter accurately extracts systematic bias and periodic disturbances from the prediction error, overcoming the limitation of fixed compensation in tracking dynamic changes. The introduction of a dynamic forgetting adjustment coefficient enables adaptive weight adjustment for transient and steady-state conditions, significantly improving the adaptability and robustness of the compensation. Finally, through compensation superposition and constraint protection, the predicted voltage is corrected, effectively compensating for prediction biases caused by model simplification, parameter drift, and external disturbances. Compared to prediction methods without error compensation, this embodiment significantly improves the accuracy and reliability of voltage prediction, providing a high-precision prediction foundation for subsequent optimized control.

[0156] In one embodiment of this example, refer to Figure 3 Based on the physical damage values ​​of the capacitors, each level of the interconnected submodules is divided into a high-quality response group, a maintenance group, and a stress avoidance group, including the following steps: S710. Classify cascaded sub-modules whose capacitor physical damage values ​​are less than the first damage threshold into a high-quality response group. S720. The cascaded sub-modules whose capacitor physical damage values ​​are greater than or equal to the first damage threshold and less than the second damage threshold are divided into maintenance groups. S730. Cascaded sub-modules whose physical damage values ​​of capacitors are greater than or equal to the second damage threshold are classified into stress avoidance groups, wherein the first damage threshold is less than the second damage threshold.

[0157] In this embodiment, to achieve differentiated control based on capacitor health status, the controller divides each cascaded submodule into different operating groups according to the physical damage value of the capacitor. Specifically, the controller classifies cascaded submodules with physical damage values ​​less than a first damage threshold into a high-quality response group. The first damage threshold... A value of 0.3 to 0.4 indicates that the capacitor has experienced 30% to 40% of its lifespan and is still in a healthy state. Iterate through all cascaded submodules; for the i-th submodule, if its capacitor's physical damage value... If so, mark the submodule as a member of the high-quality response group and set its running mode flag to "active mode".

[0158] The capacitors in the high-quality response group are in good condition, with both the increase in equivalent series resistance and the decrease in capacitance within acceptable ranges, enabling them to withstand frequent switching operations and large current stresses. These submodules will serve as the main force in voltage balance control, undertaking the primary voltage regulation task.

[0159] The controller creates an index list for high-quality response groups. ,in This index list represents the number of submodules in the high-quality response group and is used for subsequent on / off state optimization calculations. By filtering by health status, submodules that can be used frequently are identified, effectively solving the problem of resource waste caused by indiscriminate use.

[0160] The controller categorizes cascaded sub-modules with moderate levels of physical capacitor damage into maintenance groups. Second damage threshold. Setting it to 0.7 to 0.8 indicates that the capacitor is nearing the end of its lifespan and has a limited remaining lifespan. For the i-th submodule, if... If so, mark the submodule as a member of the maintenance group and set its running mode flag to "restricted mode".

[0161] The capacitors in the maintenance group's submodules have aged to some extent, with a significant increase in equivalent series resistance and a decrease in capacitance, but they can still function normally. The usage frequency of these submodules should be appropriately limited, and they should only participate in switching operations when the high-quality response group cannot meet the control requirements.

[0162] The controller sets the priority coefficient for the maintenance group. This indicates that its usage priority is half that of the high-quality response group. In the multi-objective cost function, the switching loss weighting coefficient of the maintenance group submodule is set to 1.5 to 2 times that of the high-quality response group to reduce its usage frequency. The controller also establishes an index list for the maintenance group. ,in To maintain the number of submodules in a group, the problem of accelerated failure due to overuse of aged submodules can be effectively solved by identifying and limiting the use of moderately aged submodules.

[0163] The controller categorizes cascaded submodules with severe physical damage to capacitors into stress avoidance groups. For the i-th submodule, if... If so, mark the submodule as a member of the stress avoidance group and set its operating mode flag to "passive mode".

[0164] The capacitors in the stress avoidance group are severely aged, with a significant increase in equivalent series resistance and a marked decrease in capacitance. Continued frequent use may lead to sudden failure. The switching states of these submodules will be locked in their current state, and they will no longer participate in switching operations to reduce switching losses and electrical stress, thereby extending their remaining lifespan.

[0165] The controller records the current on / off state of the stress avoidance submodule. And this state remains unchanged in subsequent control cycles. The submodule of the stress avoidance group remains in the circuit, and its capacitor voltage is slowly adjusted through a natural charging and discharging process, without actively participating in rapid voltage balance control.

[0166] The controller establishes an index list for stress avoidance groups. ,in To avoid increasing the number of submodules in stress groups, the controller triggers a maintenance alarm signal, notifying maintenance personnel that the submodule needs to be replaced or repaired at an appropriate time. By identifying and avoiding the use of severely aged submodules, the problem of decreased system reliability caused by the continued use of aged submodules can be effectively solved, thus effectively extending the overall service life of the system.

[0167] In this embodiment, after grouping, the controller calculates statistical information for each group, including the number of submodules, average damage value, and standard deviation of damage value. This statistical information is used to assess the overall health status and aging balance of the system. If the number of submodules in the high-quality response group is less than 50% of the total, a system performance degradation alarm is triggered; if the number of submodules in the stress avoidance group exceeds 20% of the total, an emergency system maintenance alarm is triggered. The grouping results are updated periodically to track the dynamic changes in capacitor aging.

[0168] This embodiment effectively solves the problem of resource waste by identifying high-quality response groups. By limiting the use of maintenance groups, the aging submodules are protected, avoiding accelerated failure caused by overuse. Finally, by using stress avoidance groups, the remaining lifespan of severely aged submodules is effectively extended, significantly improving the overall reliability of the system. Compared with traditional equal-use strategies, this embodiment fully considers the heterogeneous aging characteristics of capacitors, achieving a rational allocation and optimized utilization of lifespan resources.

[0169] In one embodiment of this invention, the optimal switching control vector is solved in the switching state combination of the high-quality response group based on the corrected predicted voltage value and the preset multi-objective cost function, including the following steps: S810. In the switching state combinations of the high-quality response group, the corrected predicted voltage value corresponding to each switching state combination is substituted into the multi-objective cost function to calculate the cost function value corresponding to each switching state combination. The multi-objective cost function includes a voltage deviation term, a switching loss term, and a circulating current suppression term. The voltage deviation term is the sum of the squares of the differences between the corrected predicted voltage value of each stage of the interconnected sub-module and the preset DC voltage reference value. The switching loss term is positively correlated with the number of switching state switching times. The circulating current suppression term is the square of the interphase circulating current. S820. Determine the switch state combination that minimizes the cost function value as the optimal switch control vector.

[0170] In this embodiment, to achieve an optimal trade-off among multiple control objectives, the controller solves for the optimal switching control vector in the switching state combination space of the high-quality response group based on the corrected predicted voltage value and the multi-objective cost function. Specifically, the controller calculates the cost function value corresponding to each combination of switching states in the high-quality response group. First, the number of sub-modules in the high-quality response group is determined. Each submodule has three switching states (+1 for charging, 0 for bypassing, and -1 for discharging), therefore theoretically there are... A combination of switch states.

[0171] To reduce computational complexity, constraints are introduced to decrease the search space. These constraints include: an output voltage constraint, requiring the sum of the switching states of all submodules. The output voltage requirements of the solid-state transformer should be met within permissible limits; simultaneously, the number of actions should be constrained to limit the number of submodules allowed to switch states within a single control cycle to no more than [a certain number]. To reduce switching losses.

[0172] The set of switch state combinations that satisfy the constraints In the middle, for each possible combination of switching states The corresponding corrected predicted voltage value Substitute the multi-objective cost function for evaluation.

[0173] The multi-objective cost function consists of three main terms. The voltage deviation term is defined as follows: ,in This is a preset DC voltage reference value. This item measures the degree of deviation of each submodule voltage from the reference value. The goal is to make the voltages of all submodules tend to be consistent and achieve voltage balance.

[0174] The switching loss term is defined as follows: ,in This is the switching loss weighting coefficient. This represents the switching state of the i-th submodule at the current moment. This value is positively correlated with the number of switching state transitions, with each switch state change contributing one unit of switching loss. Switching loss includes the on / off losses of the switching device and the energy consumption of the drive circuit. Frequent switching operations increase power loss, reduce efficiency, and accelerate device aging.

[0175] The circulation suppression term is defined as follows: ,in This is the circulation suppression weighting coefficient. This refers to the interphase circulating current. In a three-phase solid-state transformer, interphase circulating current is generated due to voltage imbalance between phases. This circulating current not only increases system losses but also causes additional stress on capacitors and switching devices. The circulating current is obtained by measuring the output current of each phase and calculating its zero-sequence component. Alternatively, it can be calculated based on the voltage difference between each phase using a predictive model. ,in This is the equivalent impedance.

[0176] The total cost function is a weighted sum of three terms. Weighting coefficients and The settings need to be adjusted according to the actual application requirements. In applications requiring high voltage balance accuracy, the settings can be reduced. and This allows for more frequent switching operations; in applications where efficiency and lifespan are critical, it can improve... and This reduces switching actions and circulating current.

[0177] Iterate through all combinations of switch states that satisfy the constraints. Calculate the total cost function value for each combination. In this embodiment, to improve computational efficiency, a branch-and-bound method or a heuristic search algorithm is used to prune obviously suboptimal combinations during the search process, avoiding traversing all combinations. This approach combines various control objectives. By constructing and calculating a multi-objective cost function, multiple control objectives such as voltage balance, switching losses, and circulating current suppression are unified into an optimization framework, effectively resolving conflicts and trade-offs among these objectives.

[0178] The controller determines the optimal switching control vector as the combination of switching states that minimizes the cost function value. This is based on all calculated cost function values. In the search, the minimum value and its corresponding index are found. Where M is the total number of switch state combinations that satisfy the constraints. The optimal switch control vector is: .

[0179] This optimal switching control vector achieves an optimal trade-off among multiple control objectives, including voltage balance, switching losses, and circulating current suppression, and represents the best switching action scheme for the current control cycle. To prevent local optima, multi-starting-point search or simulated annealing algorithms can be used to optimize from different initial states, compare multiple local optima, and select the global optimum.

[0180] The controller stores the optimal switching control vector in the control command buffer and records the corresponding minimum cost function value for performance monitoring and algorithm tuning.

[0181] For submodules in the maintenance group, the controller decides whether to include them in the optimization calculation based on the current control requirements. If the number of submodules in the high-quality response group is insufficient to meet the voltage balance requirements, or if the optimal cost function value of the high-quality response group exceeds a preset threshold, then several submodules with the smallest damage values ​​in the maintenance group are temporarily added to the optimization calculation to expand the search space and obtain better control performance. Submodules in the stress avoidance group always remain in their locked switching state and do not participate in the optimization calculation. Through the search for the minimum cost function value and the determination of the optimal solution, the solution process for multi-objective optimization control is completed.

[0182] This embodiment unifies multiple control objectives, such as voltage balance, switching losses, and circulating current suppression, into a single optimization framework by constructing a multi-objective cost function, thus resolving conflicts and trade-offs among these objectives. By introducing constraints and optimizing the search space, computational complexity is significantly reduced, enabling real-time optimization. Finally, by searching for the minimum cost function value, the optimal switching control strategy with the best overall performance is obtained, significantly improving the voltage balance accuracy, operating efficiency, and system reliability of the solid-state transformer.

[0183] This application also provides a controller, including: The memory is configured to store instructions; and The processor is configured to retrieve the instructions from the memory and, when executing the instructions, to implement the model-predictive solid-state transformer voltage balance control method described above.

[0184] Reference Figure 2 This application also provides a solid-state transformer control system, including: Multiple cascaded submodules are used to implement voltage transformation; Sensor components are used to acquire the DC-side capacitor voltage, input current, and heat sink temperature of each stage of the interconnecting submodule; The controller is electrically connected to the sensor assembly and to the drive circuits of each level of the sub-modules.

[0185] In this embodiment, the controller can be a device with a processor, such as a tablet computer, desktop computer, laptop computer, handheld computer, wearable device, laptop computer, ultra-mobile personal computer (UMPC), or netbook. Of course, the controller can also be a server. This application does not impose any special limitations on the specific form of the controller.

[0186] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0187] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0188] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0189] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0190] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0191] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0192] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0193] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0194] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A model-predictive-based voltage balance control method for solid-state transformers, characterized in that, This method is applied to a solid-state transformer control system, which includes multiple cascaded submodules, sensor components, and a controller. The sensor components are electrically connected to the controller, and the controller is electrically connected to the drive circuits of each cascaded submodule. Under the current control cycle, obtain the DC-side capacitor voltage, input current, and heat sink temperature of each level of the interconnected sub-module; Based on the DC-side capacitor voltage and input current, the equivalent series resistance and equivalent capacitance values ​​of each stage of the interconnected sub-modules are determined; Extract the RMS value of the capacitor ripple current from the input current; Based on the heat sink temperature and the effective value of capacitor ripple current, the physical damage values ​​of capacitors in each stage of the interconnect sub-module are calculated, and the equivalent series resistance and equivalent capacitance values ​​are corrected based on the physical damage values ​​of capacitors to obtain the corrected equivalent series resistance and equivalent capacitance values. Substituting the corrected equivalent series resistance and the corrected equivalent capacitance into the discrete-time state prediction model, we obtain the preliminary predicted voltage values ​​of each series submodule at the next time step. The prediction error of the previous control cycle is obtained, and the prediction compensation amount is calculated based on the prediction error. The prediction compensation amount is then added to the initial prediction voltage value to obtain the corrected prediction voltage value. Based on the physical damage values ​​of the capacitors, the cascaded sub-modules are divided into a high-quality response group, a maintenance group, and a stress avoidance group. The switching state of the cascaded sub-modules in the stress avoidance group remains unchanged, while the cascaded sub-modules in the high-quality response group participate in the switching action. Based on the corrected predicted voltage value and the preset multi-objective cost function, the optimal switching control vector is solved in the switching state combination of the high-quality response group; PWM control signals are generated based on the optimal switching control vector and then sent to the drive circuits of each stage of the interconnected sub-modules.

2. The method according to claim 1, characterized in that, Based on the DC-side capacitor voltage and input current, the equivalent series resistance and equivalent capacitance values ​​of each stage of the interconnect sub-module are determined, including: Obtain the voltage sampling sequence of the DC-side capacitor voltage and the current sampling sequence of the input current; Calculate the voltage change between adjacent sampling points in the voltage sampling sequence within a preset time period, and calculate the current integral value in the current sampling sequence within the preset time period; The equivalent capacitance value is calculated based on the ratio of the voltage change to the integral value of the current. Extract the AC component from the input current and calculate the effective value of the AC component. Calculate the peak-to-peak value of the ripple voltage of the DC-side capacitor voltage, and calculate the equivalent series resistance based on the ratio of the effective value of the AC component to the peak-to-peak value of the ripple voltage.

3. The method according to claim 2, characterized in that, Extract the RMS value of the capacitor ripple current from the input current, including: Perform a fast Fourier transform on the input current to obtain the frequency domain current component; Identify the fundamental frequency point with the largest amplitude in the frequency domain current component; Centered on the fundamental frequency point, a ripple frequency extraction window is determined, wherein the ripple frequency extraction window is used to characterize the bandwidth covering the harmonic range of the fundamental frequency. Extract all frequency domain components within the ripple frequency extraction window; The extracted frequency domain components are subjected to inverse Fourier transform to reconstruct the time-domain ripple current waveform; Calculate the root mean square value of the time-domain ripple current waveform over a complete power frequency cycle; The root mean square value is output as the effective value of the capacitor ripple current.

4. The method according to claim 1, characterized in that, The equivalent series resistance and equivalent capacitance values ​​are corrected based on the physical damage values ​​of the capacitor, resulting in corrected equivalent series resistance and equivalent capacitance values, including: Based on the heat sink temperature, query the preset capacitor temperature characteristic curve to obtain the capacitor capacitance decay coefficient and equivalent series resistance temperature correction coefficient at the current temperature. Based on the effective value of the capacitor ripple current, calculate the ripple heating power of the capacitor under the current operating state, and calculate the cumulative amount of thermal stress inside the capacitor based on the ripple heating power. The accumulated thermal stress is matched with the preset capacitor life model to obtain the equivalent aging time of the capacitor. Based on the equivalent aging time and capacitance decay coefficient, the capacitance degradation rate is calculated, and the capacitance degradation rate is multiplied by the initial equivalent capacitance value to obtain the first corrected capacitance value under the dual effects of temperature and aging. Based on the physical damage values ​​of the capacitor, a mapping function between the damage degree and the parameter offset is constructed to calculate the additional capacitance attenuation and the additional equivalent series resistance increase caused by the physical damage of the capacitor. The capacitance attenuation is subtracted from the first corrected capacitance value to obtain the corrected equivalent capacitance value. The equivalent series resistance temperature correction factor is multiplied by the initial equivalent series resistance to obtain the intermediate value of the equivalent series resistance after temperature correction. The equivalent series resistance is increased by adding the increment to the median value of the equivalent series resistance to obtain the corrected equivalent series resistance.

5. The method according to claim 1, characterized in that, Substituting the corrected equivalent series resistance and equivalent capacitance values ​​into the discrete-time state prediction model, the preliminary predicted voltage values ​​of each series submodule at the next time step are obtained, including: The corrected equivalent series resistance is used as a resistive loss term, and the corrected equivalent capacitance value is used as a capacitive integral term. These are embedded into the preset continuous-time state equation to construct a parameter-corrected continuous state space model. The continuous-time state equation is constructed based on the cascaded topology of a solid-state transformer and includes input current, capacitor voltage, and switching state. The continuous state-space model after parameter correction is discretized in the time domain, and the sampling interval of the current control cycle is used as the discrete step size to derive the voltage discrete prediction equation for the next moment with input current, current DC side capacitor voltage and switching action as independent variables. The input current obtained in the current control cycle and the current DC-side capacitor voltage of each stage of the interconnected sub-module are input into the discrete-time state prediction model. Based on the actual switching state combination of each level of the interconnected sub-module in the current control cycle, calculate the charging and discharging state of the capacitor and the equivalent series resistance voltage drop in the current cycle; The voltage change of the capacitor generated during charging and discharging is superimposed with the voltage drop of the equivalent series resistance to output the preliminary predicted voltage value of each sub-module at the next moment.

6. The method according to claim 1, characterized in that, The prediction compensation amount is calculated based on the prediction error, and then superimposed on the initial prediction voltage value to obtain the corrected prediction voltage value, including: The prediction error is input into an adaptive filter, and the prediction compensation is calculated through the adaptive filter. The adaptive filter is a decision feedback equalization filter, which includes multiple tap coefficients. The tap coefficients are updated adaptively according to the historical prediction error. The predicted compensation is superimposed on the initial predicted voltage value to obtain the corrected predicted voltage value.

7. The method according to claim 1, characterized in that, Based on the physical damage values ​​of the capacitors, each level of the interconnected submodules is divided into a high-quality response group, a maintenance group, and a stress avoidance group, including: Cascaded sub-modules whose capacitor physical damage values ​​are less than the first damage threshold are classified as high-quality response groups. Cascaded sub-modules whose capacitor physical damage values ​​are greater than or equal to the first damage threshold and less than the second damage threshold are classified into maintenance groups. Cascaded sub-modules whose physical damage values ​​to capacitors are greater than or equal to the second damage threshold are classified into stress avoidance groups, wherein the first damage threshold is less than the second damage threshold.

8. The method according to claim 1, characterized in that, Based on the corrected predicted voltage value and the preset multi-objective cost function, the optimal switching control vector is solved in the switching state combination of the high-quality response group, including: In the switching state combinations of the high-quality response group, the corrected predicted voltage value corresponding to each switching state combination is substituted into the multi-objective cost function to calculate the cost function value corresponding to each switching state combination. The multi-objective cost function includes a voltage deviation term, a switching loss term, and a circulating current suppression term. The voltage deviation term is the sum of the squares of the differences between the corrected predicted voltage value of each stage of the interconnected sub-module and the preset DC voltage reference value. The switching loss term is positively correlated with the number of switching state switching times. The circulating current suppression term is the square of the interphase circulating current. The optimal switch control vector is determined by identifying the switch state combination that minimizes the cost function value.

9. A controller, characterized in that, include: The memory is configured to store instructions; as well as A processor is configured to retrieve the instructions from the memory and, when executing the instructions, to implement the model-predictive solid-state transformer voltage balance control method according to any one of claims 1 to 8.

10. A solid-state transformer control system, characterized in that, include: Multiple cascaded submodules are used to implement voltage transformation; Sensor components are used to acquire the DC-side capacitor voltage, input current, and heat sink temperature of each stage of the interconnecting submodule; The controller according to claim 9 is electrically connected to the sensor assembly and to the drive circuits of each level of the sub-module.

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