An inverter circuit for an active power filter

Abstract

The application relates to the technical field of power filters, and discloses an inverter circuit for an active power filter, which comprises a DC bus, a live wire inverter bridge arm and a zero wire inverter bridge arm; the negative pole of a first capacitor group and the positive pole of a second capacitor group are connected and serve as the midpoint of the DC bus; the live wire inverter bridge arm comprises a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor; the zero wire inverter bridge arm comprises a fifth insulated gate bipolar transistor, a sixth insulated gate bipolar transistor, a seventh insulated gate bipolar transistor and an eighth insulated gate bipolar transistor; a live wire output node is connected to the live wire of a power grid through an output filter, and a zero wire output node is connected to the zero wire of the power grid through an output filter or directly connected to the zero wire of the power grid. The application ensures the reliability of high-frequency harmonic treatment and even harmonic compensation of the active power filter.

Description

Technical Field

[0001] This invention relates to the field of power filter technology, and more specifically, to an inverter circuit for an active power filter. Background Technology

[0002] With the rapid development of power supply systems, industrial frequency conversion loads, and high-power rectifier equipment, the number of nonlinear loads in the power grid is constantly increasing, and problems such as higher harmonics, even harmonics, reactive power disturbances, and current distortion are becoming increasingly prominent. Active power filters introduce compensating current into the power grid through inverter circuits, thereby canceling the harmonic components generated on the load side. Therefore, the topology and modulation method of the inverter circuit directly affect the response speed of active power filters to higher and even harmonics.

[0003] Existing patent CN109546879A discloses a single-phase three-level hybrid clamped inverter circuit and an inverter with it, which uses multiple switching devices to form a bridge arm and uses a corresponding modulation control method to achieve compensated current output. However, in 1140V active power filters, the I-shaped three-level topology is limited by the voltage withstand capability and losses of the devices, and its switching frequency should not be too high. It is not suitable for suppressing high-order harmonics such as the 23rd and 25th harmonics (harmonic components above 1kHz), nor does it support the suppression of even-order harmonics. Existing patent CN111342475A discloses a modulation method for an H-bridge cascaded active power filter, which suppresses the generation of energy unevenness by optimizing the carrier frequency and combining it with the periodic rotation of triangular carriers. It can be seen that after the number of cascaded devices increases, the actual operating frequency of a single IGBT is lower than the equivalent switching frequency of the system, resulting in insufficient transient response capability of the control, making it difficult to simultaneously achieve high-frequency harmonic suppression, even-order harmonic compensation, and control response speed.

[0004] Therefore, it is necessary to design an inverter circuit for active power filters to solve the problems existing in the current technology. Summary of the Invention

[0005] In view of this, the present invention proposes an inverter circuit for active power filters, which aims to solve the problems of improving the actual switching response capability, reducing the requirements of the filter circuit, and meeting the requirements for the control of high-order harmonics and even-order harmonics while ensuring the withstand voltage of the devices.

[0006] This invention proposes an inverter circuit for an active power filter, comprising: A DC bus, a live-wire inverter bridge arm, and a neutral-wire inverter bridge arm, wherein the DC bus is connected to the live-wire inverter bridge arm and the neutral-wire inverter bridge arm respectively; The DC bus includes a first capacitor bank and a second capacitor bank. The positive terminal of the first capacitor bank serves as the positive terminal of the DC bus, and the negative terminal of the second capacitor bank serves as the negative terminal of the DC bus. The negative terminal of the first capacitor bank and the positive terminal of the second capacitor bank are connected and serve as the midpoint of the DC bus. The fire-wire inverter bridge arm includes a first insulated-gate bipolar transistor, a second insulated-gate bipolar transistor, a third insulated-gate bipolar transistor, and a fourth insulated-gate bipolar transistor. The emitter of the third insulated-gate bipolar transistor is connected to the collector of the fourth insulated-gate bipolar transistor to serve as the fire-wire output node of the fire-wire inverter bridge arm. The zero-line inverter bridge arm includes a fifth insulated-gate bipolar transistor, a sixth insulated-gate bipolar transistor, a seventh insulated-gate bipolar transistor, and an eighth insulated-gate bipolar transistor. The emitter of the seventh insulated-gate bipolar transistor is connected to the collector of the eighth insulated-gate bipolar transistor to serve as the zero-line output node of the zero-line inverter bridge arm. The live wire output node is connected to the live wire of the power grid via an output filter, and the neutral wire output node is connected to the neutral wire of the power grid via an output filter or directly connected to the neutral wire of the power grid.

[0007] Furthermore, the fire-wire inverter bridge arm also includes: The collector of the first insulated gate bipolar transistor is connected to the positive terminal of the DC bus, and the emitter of the first insulated gate bipolar transistor is connected to the collector of the second insulated gate bipolar transistor and the collector of the third insulated gate bipolar transistor.

[0008] Furthermore, the fire-wire inverter bridge arm also includes: The emitter of the second insulated-gate bipolar transistor is connected to the midpoint of the DC bus, the emitter of the third insulated-gate bipolar transistor is connected to the collector of the fourth insulated-gate bipolar transistor, and the emitter of the fourth insulated-gate bipolar transistor is connected to the negative terminal of the DC bus.

[0009] Furthermore, the neutral line inverter bridge arm also includes: The collector of the fifth insulated-gate bipolar transistor is connected to the positive terminal of the DC bus, and the emitter of the fifth insulated-gate bipolar transistor is connected to the collector of the sixth insulated-gate bipolar transistor and the collector of the seventh insulated-gate bipolar transistor, respectively.

[0010] Furthermore, the neutral line inverter bridge arm also includes: The emitter of the sixth insulated-gate bipolar transistor is connected to the midpoint of the DC bus, the emitter of the seventh insulated-gate bipolar transistor is connected to the collector of the eighth insulated-gate bipolar transistor, and the emitter of the eighth insulated-gate bipolar transistor is connected to the negative terminal of the DC bus.

[0011] Furthermore, the inverter circuit for the active power filter further includes: the rated voltage of the first capacitor bank and the second capacitor bank is greater than or equal to 700V. The first insulated-gate bipolar transistor, the second insulated-gate bipolar transistor, the third insulated-gate bipolar transistor, the fifth insulated-gate bipolar transistor, the sixth insulated-gate bipolar transistor, and the seventh insulated-gate bipolar transistor are 1200V; The fourth insulated-gate bipolar transistor and the eighth insulated-gate bipolar transistor are 1700V; The switching frequencies of the first, second, fifth, and sixth insulated-gate bipolar transistors are set to high frequency, while the switching frequencies of the third, fourth, seventh, and eighth insulated-gate bipolar transistors are set to low frequency.

[0012] Furthermore, the inverter circuit for the active power filter further includes: The operating voltage of the first capacitor bank and the second capacitor bank is Udc. Based on the turn-off and turn-on of each insulated gate bipolar transistor in the live wire inverter bridge arm and the neutral wire inverter bridge arm, five levels are output. The five voltage levels include inverter output voltages of 0, Udc, 2Udc, -Udc, and -2Udc.

[0013] Furthermore, the inverter circuit for the active power filter further includes: If the first, third, fifth, and seventh insulated-gate bipolar transistors (IGBTs) are turned on, or if the second, fourth, sixth, and eighth IGBTs are turned on, or if the second, third, sixth, and seventh IGBTs are turned on, the inverter circuit output voltage is 0.

[0014] Furthermore, the inverter circuit for the active power filter further includes: If the second, third, fifth, and seventh insulated-gate bipolar transistors are turned on, or if the second, fourth, sixth, and seventh insulated-gate bipolar transistors are turned on, the inverter circuit output voltage is -Udc.

[0015] Furthermore, the inverter circuit for the active power filter further includes: If the first insulated-gate bipolar transistor, the third insulated-gate bipolar transistor, the sixth insulated-gate bipolar transistor, and the seventh insulated-gate bipolar transistor are turned on, or if the second insulated-gate bipolar transistor, the third insulated-gate bipolar transistor, the sixth insulated-gate bipolar transistor, and the eighth insulated-gate bipolar transistor are turned on, the inverter circuit output voltage is Udc; If the first insulated-gate bipolar transistor, the third insulated-gate bipolar transistor, the sixth insulated-gate bipolar transistor, and the eighth insulated-gate bipolar transistor are turned on, the inverter circuit output voltage is 2Udc; If the second insulated-gate bipolar transistor, the fourth insulated-gate bipolar transistor, the fifth insulated-gate bipolar transistor, and the seventh insulated-gate bipolar transistor are turned on, the inverter circuit output voltage is -2Udc.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: by forming a DC bus with a midpoint through the first capacitor bank and the second capacitor bank, and setting the live wire inverter bridge arm and the neutral wire inverter bridge arm respectively, five levels of output are formed between the live wire and the neutral wire. Compared with the I-shaped three-level topology, the voltage stress is shared by the combination of different bridge arm devices. The topology supports even harmonics, and the overall primary circuit characteristics are close to two cascaded H-bridges. At the same time, compared with the cascaded H-bridge topology, the bridge arm structure and control logic are close to the three-level control method, the control algorithm complexity is lower, and the actual IGBT operating frequency is close to the equivalent switching frequency. The control system response capability is better than that of the cascaded H-bridge. It can take into account the device withstand voltage, switching frequency, output level quality and control response speed in the 1140V active power filter application scenario, thereby meeting the requirements for high-order harmonics and even-order harmonics mitigation. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A circuit schematic diagram of an inverter circuit for an active power filter provided in an embodiment of the present invention; Figure 2 for Figure 1 Circuit diagram of the positive and negative terminals of the switching device. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] The I-shaped three-level topology used in an 1140V active power filter requires 1700V IGBTs, and the switching frequency should not be too high. It is unsuitable for controlling high-order harmonics such as the 23rd and 25th harmonics (harmonic components above 1kHz), and it also does not support even-order harmonic control. Furthermore, the low switching frequency places high demands on the output filter inductor / capacitor, resulting in insufficient harmonic output capability. While a cascaded H-bridge can use 1200V or lower voltage IGBTs, offering a higher switching frequency suitable for high-order harmonic control, the actual IGBT operating frequency of a cascaded H-bridge is only 1 / 2n of the equivalent switching frequency (where n is the number of cascaded IGBTs), leading to insufficient control response capability.

[0022] See Figure 1 As shown in some embodiments of this application, an inverter circuit for an active power filter includes: DC bus, live wire inverter bridge arm and neutral wire inverter bridge arm, the DC bus is connected to the live wire inverter bridge arm and the neutral wire inverter bridge arm respectively; The DC bus includes a first capacitor bank and a second capacitor bank. The positive terminal of the first capacitor bank serves as the positive terminal of the DC bus, and the negative terminal of the second capacitor bank serves as the negative terminal of the DC bus. The negative terminal of the first capacitor bank and the positive terminal of the second capacitor bank are connected and serve as the midpoint of the DC bus. The fire-wire inverter bridge arm includes a first insulated-gate bipolar transistor, a second insulated-gate bipolar transistor, a third insulated-gate bipolar transistor, and a fourth insulated-gate bipolar transistor. The emitter of the third insulated-gate bipolar transistor is connected to the collector of the fourth insulated-gate bipolar transistor to serve as the fire-wire output node of the fire-wire inverter bridge arm. The zero-line inverter bridge arm includes a fifth insulated-gate bipolar transistor, a sixth insulated-gate bipolar transistor, a seventh insulated-gate bipolar transistor, and an eighth insulated-gate bipolar transistor. The emitter of the seventh insulated-gate bipolar transistor is connected to the collector of the eighth insulated-gate bipolar transistor to serve as the zero-line output node of the zero-line inverter bridge arm. The live wire output node is connected to the live wire of the power grid via an output filter, and the neutral wire output node is connected to the neutral wire of the power grid via an output filter or directly to the neutral wire of the power grid.

[0023] Specifically, the inverter circuit of this application is applied in an active power filter with a voltage level of 1140V to output a corresponding compensation voltage or compensation current to the power grid according to the compensation requirements of the active power filter, thereby realizing the compensation processing of power grid harmonics, reactive components or current distortion.

[0024] The inverter circuit includes a DC bus, a live-wire inverter arm, and a neutral-wire inverter arm. The DC bus is connected to both the live-wire and neutral-wire inverter arms. The live-wire inverter arm forms the live-wire output node corresponding to the live wire of the power grid, and the neutral-wire inverter arm forms the neutral-wire output node corresponding to the neutral wire of the power grid. By controlling the on and off states of the insulated-gate bipolar transistors in the live-wire and neutral-wire inverter arms, different levels of output voltage can be generated between the live-wire and neutral-wire output nodes.

[0025] The DC bus includes a first capacitor bank C+ and a second capacitor bank C-. The positive terminal of the first capacitor bank C+ serves as the positive terminal of the DC bus, and the negative terminal of the second capacitor bank C- serves as the negative terminal of the DC bus. The negative terminal of the first capacitor bank C+ is connected to the positive terminal of the second capacitor bank C-, and serves as the midpoint of the DC bus.

[0026] The live-wire inverter bridge arm includes a first insulated-gate bipolar transistor (IGBT) T1, a second IGBT T2, a third IGBT T3, and a fourth IGBT T4. The collector of the first IGBT T1 is connected to the positive terminal of the DC bus. The emitter of the first IGBT T1 is connected to the collectors of both the second IGBT T2 and the third IGBT T3. The emitter of the second IGBT T2 is connected to the midpoint of the DC bus. The emitter of the third IGBT T3 is connected to the collector of the fourth IGBT T4. The connection point between the emitter of the third IGBT T3 and the collector of the fourth IGBT T4 serves as the live-wire output node of the live-wire inverter bridge arm. The emitter of the fourth IGBT T4 is connected to the negative terminal of the DC bus.

[0027] In the live-line inverter bridge arm, the first insulated-gate bipolar transistor T1 is located on the positive side of the DC bus, the fourth insulated-gate bipolar transistor T4 is located on the negative side of the DC bus, and the second insulated-gate bipolar transistor T2 is connected to the midpoint of the DC bus. Different inverter output levels can be formed by different combinations of the first insulated-gate bipolar transistor T1, the second insulated-gate bipolar transistor T2, the third insulated-gate bipolar transistor T3, and the fourth insulated-gate bipolar transistor T4 being turned on.

[0028] The neutral-line inverter bridge arm includes a fifth insulated-gate bipolar transistor (IGBT) T5, a sixth IGBT T6, a seventh IGBT T7, and an eighth IGBT T8. The collector of the fifth IGBT T5 is connected to the positive terminal of the DC bus. The emitter of the fifth IGBT T5 is connected to the collectors of both the sixth IGBT T6 and the seventh IGBT T7. The emitter of the sixth IGBT T6 is connected to the midpoint of the DC bus. The emitter of the seventh IGBT T7 is connected to the collector of the eighth IGBT T8. The connection point between the emitter of the seventh IGBT T7 and the collector of the eighth IGBT T8 serves as the neutral-line output node of the neutral-line inverter bridge arm. The emitter of the eighth IGBT T8 is connected to the negative terminal of the DC bus.

[0029] The live wire inverter bridge arm is used to form the live wire output, and the neutral wire inverter bridge arm is used to form the neutral wire output. The live wire output node is connected to the live wire of the power grid through the output filter, and the neutral wire output node is connected to the neutral wire of the power grid through the output filter or directly to the neutral wire of the power grid. That is to say, the live wire output node is connected to the live wire of the 1140V power grid, and the neutral wire output node is connected to the neutral wire of the 1140V power grid.

[0030] Among them, the operating voltage of the first capacitor group C+ and the second capacitor group C- is 600V. The rated voltage of the capacitor group needs to be higher than the actual operating voltage to reserve margin for voltage fluctuations and transient impacts, and to avoid the capacitor group being in the critical withstand voltage state for a long time. Therefore, the rated voltage of the first capacitor group C+ and the second capacitor group C- is selected to be greater than or equal to 700V. Correspondingly, two types of insulated gate bipolar transistors are selected. The first selection scheme is as follows: the first insulated gate bipolar transistor T1, the second insulated gate bipolar transistor T2, the third insulated gate bipolar transistor T3, the fifth insulated gate bipolar transistor T5, the sixth insulated gate bipolar transistor T6 and the seventh insulated gate bipolar transistor T7 are selected as 1200V IGBTs, and the fourth insulated gate bipolar transistor T4 and the eighth insulated gate bipolar transistor T8 are selected as 1700V IGBTs.

[0031] The second selection scheme is as follows: the first insulated gate bipolar transistor T1, the second insulated gate bipolar transistor T2, the fifth insulated gate bipolar transistor T5, and the sixth insulated gate bipolar transistor T6 are selected using 1200V half-bridge IGBT modules, and the third insulated gate bipolar transistor T3, the fourth insulated gate bipolar transistor T4, the seventh insulated gate bipolar transistor T7, and the eighth insulated gate bipolar transistor T8 are selected using 1700V half-bridge IGBT modules.

[0032] Let Udc denote the operating voltage of the first capacitor bank C+ and the second capacitor bank C-. Based on the turn-off and turn-on states of the insulated-gate bipolar transistors (IGBTs) in the live-wire and neutral-wire inverter bridge arms, the inverter circuit will have nine conduction states, resulting in five different output voltage levels. It is important to note that when a specific IGBT is turned on, the other IGBTs are turned off.

[0033] The first conduction state is as follows: if the first insulated-gate bipolar transistor T1, the third insulated-gate bipolar transistor T3, the fifth insulated-gate bipolar transistor T5, and the seventh insulated-gate bipolar transistor T7 are turned on, and the remaining insulated-gate bipolar transistors are turned off, the inverter circuit output voltage is 0.

[0034] The second conduction state is as follows: if the second insulated-gate bipolar transistor T2, the fourth insulated-gate bipolar transistor T4, the sixth insulated-gate bipolar transistor T6, and the eighth insulated-gate bipolar transistor T8 are turned on, and the remaining insulated-gate bipolar transistors are turned off, then the inverter circuit output voltage is 0.

[0035] The third conduction state is as follows: if the second insulated-gate bipolar transistor T2, the third insulated-gate bipolar transistor T3, the sixth insulated-gate bipolar transistor T6, and the seventh insulated-gate bipolar transistor T7 are turned on, and the remaining insulated-gate bipolar transistors are turned off, then the inverter circuit output voltage is 0.

[0036] The fourth conduction state is as follows: if the second insulated gate bipolar transistor T2, the third insulated gate bipolar transistor T3, the fifth insulated gate bipolar transistor T5 and the seventh insulated gate bipolar transistor T7 are turned on, and the remaining insulated gate bipolar transistors are turned off, then the inverter circuit output voltage is -Udc.

[0037] The fifth conduction state is as follows: if the second insulated gate bipolar transistor T2, the third insulated gate bipolar transistor T3, the sixth insulated gate bipolar transistor T6 and the eighth insulated gate bipolar transistor T8 are turned on, and the remaining insulated gate bipolar transistors are turned off, then the inverter circuit output voltage is Udc.

[0038] The sixth conduction state is as follows: if the second insulated gate bipolar transistor T2, the fourth insulated gate bipolar transistor T4, the sixth insulated gate bipolar transistor T6 and the seventh insulated gate bipolar transistor T7 are turned on, and the remaining insulated gate bipolar transistors are turned off, the inverter circuit output voltage is -Udc.

[0039] The seventh conduction state is as follows: if the first insulated gate bipolar transistor T1, the third insulated gate bipolar transistor T3, the sixth insulated gate bipolar transistor T6 and the seventh insulated gate bipolar transistor T7 are turned on, and the remaining insulated gate bipolar transistors are turned off, then the inverter circuit output voltage is Udc.

[0040] The eighth conduction state is as follows: if the first insulated gate bipolar transistor T1, the third insulated gate bipolar transistor T3, the sixth insulated gate bipolar transistor T6 and the eighth insulated gate bipolar transistor T8 are turned on, and the remaining insulated gate bipolar transistors are turned off, the inverter circuit output voltage is 2Udc.

[0041] The ninth conduction state is as follows: if the second insulated gate bipolar transistor T2, the fourth insulated gate bipolar transistor T4, the fifth insulated gate bipolar transistor T5 and the seventh insulated gate bipolar transistor T7 are turned on, and the remaining insulated gate bipolar transistors are turned off, the inverter circuit output voltage is -2Udc.

[0042] During inverter circuit modulation, the switching frequencies of the first insulated-gate bipolar transistor (IGBT) T1, the second IGBT T2, the fifth IGBT T5, and the sixth IGBT T6 are set to a high frequency, such as 20kHz, while the switching frequencies of the third IGBT T3, the fourth IGBT T4, the seventh IGBT T7, and the eighth IGBT T8 are set to a low frequency, such as 1kHz. The modulation voltage U is then determined. Since the inverter circuit involves two capacitor banks, the first capacitor bank C+ and the second capacitor bank C-... In actual operation, the voltages of the first capacitor bank C+ and the second capacitor bank C- may not be completely equal. Therefore, a correction amount ΔU is added to adjust the balance of the positive and negative DC bus voltages. ΔU=k*C*(Udc1-Udc2) / (i*Tsl), where Udc1 represents the current positive DC bus voltage, Udc2 represents the current negative DC bus voltage, C represents the total capacitance of the DC capacitors, i represents the current output current, Tsl represents the switching cycle of the low-frequency IGBT, and k represents the control parameter for DC voltage equalization, with a typical value of 1.

[0043] For the live-wire inverter bridge arm, its modulation voltage is U + ΔU: If U+ΔU is a positive voltage, the third insulated-gate bipolar transistor T3 is turned on, the fourth insulated-gate bipolar transistor T4 is turned off, and the first insulated-gate bipolar transistor T1 and the second insulated-gate bipolar transistor T2 are complementary and turned on (high frequency). The duty cycle of the first insulated-gate bipolar transistor T1 is (U+ΔU) / 2Udc.

[0044] If U+ΔU is a negative voltage, the second insulated-gate bipolar transistor T2 is turned on, the first insulated-gate bipolar transistor T1 is turned off, and the third insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T4 are turned on complementaryly. The duty cycle of the fourth insulated-gate bipolar transistor T4 is (-U-ΔU) / 2Udc.

[0045] For the neutral line inverter bridge arm, its modulation voltage is -U + ΔU: If -U+ΔU is a positive voltage, the seventh insulated-gate bipolar transistor T7 is turned on, the eighth insulated-gate bipolar transistor T8 is turned off, and the fifth insulated-gate bipolar transistor T5 and the sixth insulated-gate bipolar transistor T6 are complementaryly turned on (low frequency). The duty cycle of the fifth insulated-gate bipolar transistor T5 is (-U+ΔU) / 2Udc.

[0046] If -U+ΔU is a negative voltage, the sixth insulated-gate bipolar transistor T6 is turned on, the fifth insulated-gate bipolar transistor T5 is turned off, and the seventh insulated-gate bipolar transistor T7 and the eighth insulated-gate bipolar transistor T8 are turned on complementaryly. The duty cycle of the eighth insulated-gate bipolar transistor T8 is (U-ΔU) / 2Udc.

[0047] See Figure 2 As shown, Figure 2 and Figure 1 The circuit principles are essentially the same, only the arrangement of the positive and negative terminals of the components is reversed. Therefore, for Figure 2 The device names in the text are simplified. For example, the first insulated gate bipolar transistor T1 is simplified to T1, which means the first insulated gate bipolar transistor. The same applies to the other devices.

[0048] The inverter circuit also includes a DC bus, a live inverter bridge arm, and a neutral inverter bridge arm. The DC bus is composed of C+ and C-, where the positive terminal of C+ serves as the positive terminal of the DC bus, and the negative terminal of C- serves as the negative terminal of the DC bus. The negative terminal of C+ is connected to the positive terminal of C-, serving as the midpoint of the DC bus.

[0049] The live-wire inverter bridge arm consists of 4 IGBTs. The emitter of T4 is connected to the negative terminal of the DC bus, the emitters of T2 and T3 are connected to the collector of T4, the collector of T3 is connected to the midpoint of the DC bus, the emitter of T1 is connected to the collector of T2, the collector of T1 is connected to the positive terminal of the DC bus, and the connection between the emitter of T1 and the collector of T2 serves as the output node of the live-wire bridge arm.

[0050] The neutral line inverter bridge arm consists of 4 IGBTs. The emitter of T8 is connected to the negative terminal of the DC bus, the emitters of T6 and T7 are connected to the collector of T8, the collector of T7 is connected to the midpoint of the DC bus, the emitter of T5 is connected to the collector of T6, the collector of T5 is connected to the positive terminal of the DC bus, and the connection between the emitter of T5 and the collector of T6 serves as the output node of the neutral line bridge arm.

[0051] The output node of the live-wire inverter bridge arm is connected to the live wire of the power grid, and the output node of the neutral-wire inverter bridge arm is connected to the neutral wire of the power grid.

[0052] For devices with C+ and C- rated voltages greater than or equal to 700V, there are two selection options: 1. T2, T3, T4, T6, T7 and T8 use 1200V IGBTs, while T1 and T5 use 1700V IGBTs.

[0053] 2. T3, T4, T7 and T8 use 1200V half-bridge IGBT modules, while T1, T2, T5 and T6 use 1700V half-bridge IGBT modules.

[0054] The operating voltage of C+ / C- is Udc. The inverter circuit includes the following nine conduction states, with a total of five output levels.

[0055] If T1, T3, T5, and T7 are turned on and the remaining IGBTs are turned off, the inverter circuit output voltage is 0.

[0056] If T2, T3, T6, and T7 are turned on and the remaining IGBTs are turned off, the inverter circuit output voltage is 0.

[0057] If T2, T4, T6, and T8 are turned on and the remaining IGBTs are turned off, the inverter circuit output voltage is 0.

[0058] If T2, T3, T5, and T7 are turned on and the remaining IGBTs are turned off, the inverter circuit output voltage is -Udc.

[0059] If T2, T3, T6, and T8 are turned on and the remaining IGBTs are turned off, the inverter circuit output voltage is Udc.

[0060] If T2, T4, T6, and T7 are turned on and the remaining IGBTs are turned off, the inverter circuit output voltage is -Udc.

[0061] If T1, T3, T6, and T7 are turned on and the remaining IGBTs are turned off, the inverter circuit output voltage is Udc.

[0062] If T1, T3, T6, and T8 are turned on and the remaining IGBTs are turned off, the inverter circuit output voltage is 2Udc.

[0063] If T2, T4, T5, and T7 are turned on and the remaining IGBTs are turned off, the inverter circuit output voltage is -2Udc.

[0064] When the inverter circuit is modulated, the switching frequencies of T1, T2, T5 and T6 are set to high frequency, such as 20kHz, and the switching frequencies of T3, T4, T7 and T8 are set to low frequency, such as 1kHz. Similarly, the modulation voltages U and ΔU are determined.

[0065] For the live inverter bridge arm, the modulation voltage is U+ΔU.

[0066] If U+ΔU is a positive voltage, T3 is turned on, T4 is turned off, and T1 / T2 are complementary and turned on. The duty cycle of T1 is (U+ΔU) / 2Udc.

[0067] If U+ΔU is a negative voltage, T2 is turned on, T1 is turned off, and T3 / T4 are turned on complementaryly. The duty cycle of T4 is (-U-ΔU) / 2Udc.

[0068] For the neutral line inverter bridge arm, the modulation voltage is -U+ΔU.

[0069] If -U+ΔU is a positive voltage, T7 is turned on, T8 is turned off, and T5 / T6 are turned on complementaryly. The duty cycle of T5 is (-U+ΔU) / 2Udc.

[0070] If -U+ΔU is a negative voltage, T6 is turned on, T5 is turned off, and T7 / T8 are turned on complementaryly. The duty cycle of T8 is (U-ΔU) / 2Udc.

[0071] In summary, a DC bus with a midpoint is formed by the first and second capacitor banks, and a live-wire inverter bridge arm and a neutral-wire inverter bridge arm are respectively set up, thus forming five output levels between the live and neutral wires. Compared with the I-shaped three-level topology, the voltage stress is shared by the combination of different bridge arm devices. The topology supports even harmonics, and the overall primary circuit characteristics are close to two cascaded H-bridges. At the same time, compared with the cascaded H-bridge topology, the bridge arm structure and control logic are close to the three-level control method, the control algorithm complexity is lower, and the actual IGBT operating frequency is close to the equivalent switching frequency. The control system response capability is better than that of the cascaded H-bridge. It can take into account the device withstand voltage, switching frequency, output level quality and control response speed in the 1140V active power filter application scenario, thereby meeting the requirements for high-order harmonics and even-order harmonics mitigation.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An inverter circuit for an active power filter, characterized in that, include: A DC bus, a live-wire inverter bridge arm, and a neutral-wire inverter bridge arm, wherein the DC bus is connected to the live-wire inverter bridge arm and the neutral-wire inverter bridge arm respectively; The DC bus includes a first capacitor bank and a second capacitor bank. The positive terminal of the first capacitor bank serves as the positive terminal of the DC bus, and the negative terminal of the second capacitor bank serves as the negative terminal of the DC bus. The negative terminal of the first capacitor bank and the positive terminal of the second capacitor bank are connected and serve as the midpoint of the DC bus. The fire-wire inverter bridge arm includes a first insulated-gate bipolar transistor, a second insulated-gate bipolar transistor, a third insulated-gate bipolar transistor, and a fourth insulated-gate bipolar transistor. The emitter of the third insulated-gate bipolar transistor is connected to the collector of the fourth insulated-gate bipolar transistor to serve as the fire-wire output node of the fire-wire inverter bridge arm. The zero-line inverter bridge arm includes a fifth insulated-gate bipolar transistor, a sixth insulated-gate bipolar transistor, a seventh insulated-gate bipolar transistor, and an eighth insulated-gate bipolar transistor. The emitter of the seventh insulated-gate bipolar transistor is connected to the collector of the eighth insulated-gate bipolar transistor to serve as the zero-line output node of the zero-line inverter bridge arm. The live wire output node is connected to the live wire of the power grid via an output filter, and the neutral wire output node is connected to the neutral wire of the power grid via an output filter or directly connected to the neutral wire of the power grid.

2. The inverter circuit for an active power filter according to claim 1, characterized in that, The fire-wire inverter bridge arm also includes: The collector of the first insulated gate bipolar transistor is connected to the positive terminal of the DC bus, and the emitter of the first insulated gate bipolar transistor is connected to the collector of the second insulated gate bipolar transistor and the collector of the third insulated gate bipolar transistor.

3. The inverter circuit for an active power filter according to claim 2, characterized in that, The fire-wire inverter bridge arm also includes: The emitter of the second insulated-gate bipolar transistor is connected to the midpoint of the DC bus, the emitter of the third insulated-gate bipolar transistor is connected to the collector of the fourth insulated-gate bipolar transistor, and the emitter of the fourth insulated-gate bipolar transistor is connected to the negative terminal of the DC bus.

4. The inverter circuit for an active power filter according to claim 1, characterized in that, The neutral line inverter bridge arm also includes: The collector of the fifth insulated-gate bipolar transistor is connected to the positive terminal of the DC bus, and the emitter of the fifth insulated-gate bipolar transistor is connected to the collector of the sixth insulated-gate bipolar transistor and the collector of the seventh insulated-gate bipolar transistor, respectively.

5. The inverter circuit for an active power filter according to claim 3, characterized in that, The neutral line inverter bridge arm also includes: The emitter of the sixth insulated-gate bipolar transistor is connected to the midpoint of the DC bus, the emitter of the seventh insulated-gate bipolar transistor is connected to the collector of the eighth insulated-gate bipolar transistor, and the emitter of the eighth insulated-gate bipolar transistor is connected to the negative terminal of the DC bus.

6. The inverter circuit for an active power filter according to claim 1, characterized in that, Also includes: The rated voltage of the first capacitor bank and the second capacitor bank is greater than or equal to 700V; The first insulated-gate bipolar transistor, the second insulated-gate bipolar transistor, the third insulated-gate bipolar transistor, the fifth insulated-gate bipolar transistor, the sixth insulated-gate bipolar transistor, and the seventh insulated-gate bipolar transistor are 1200V; The fourth insulated-gate bipolar transistor and the eighth insulated-gate bipolar transistor are 1700V; The switching frequencies of the first, second, fifth, and sixth insulated-gate bipolar transistors are set to high frequency, while the switching frequencies of the third, fourth, seventh, and eighth insulated-gate bipolar transistors are set to low frequency.

7. The inverter circuit for an active power filter according to claim 6, characterized in that, Also includes: The operating voltage of the first capacitor bank and the second capacitor bank is Udc. Based on the turn-off and turn-on of each insulated gate bipolar transistor in the live wire inverter bridge arm and the neutral wire inverter bridge arm, five levels are output. The five voltage levels include inverter output voltages of 0, Udc, 2Udc, -Udc, and -2Udc.

8. The inverter circuit for an active power filter according to claim 7, characterized in that, Also includes: If the first, third, fifth, and seventh insulated-gate bipolar transistors (IGBTs) are turned on, or if the second, fourth, sixth, and eighth IGBTs are turned on, or if the second, third, sixth, and seventh IGBTs are turned on, the inverter circuit output voltage is 0.

9. The inverter circuit for an active power filter according to claim 8, characterized in that, Also includes: If the second, third, fifth, and seventh insulated-gate bipolar transistors are turned on, or if the second, fourth, sixth, and seventh insulated-gate bipolar transistors are turned on, the inverter circuit output voltage is -Udc.

10. The inverter circuit for an active power filter according to claim 9, characterized in that, Also includes: If the first insulated-gate bipolar transistor, the third insulated-gate bipolar transistor, the sixth insulated-gate bipolar transistor, and the seventh insulated-gate bipolar transistor are turned on, or if the second insulated-gate bipolar transistor, the third insulated-gate bipolar transistor, the sixth insulated-gate bipolar transistor, and the eighth insulated-gate bipolar transistor are turned on, the inverter circuit output voltage is Udc; If the first insulated-gate bipolar transistor, the third insulated-gate bipolar transistor, the sixth insulated-gate bipolar transistor, and the eighth insulated-gate bipolar transistor are turned on, the inverter circuit output voltage is 2Udc; If the second insulated-gate bipolar transistor, the fourth insulated-gate bipolar transistor, the fifth insulated-gate bipolar transistor, and the seventh insulated-gate bipolar transistor are turned on, the inverter circuit output voltage is -2Udc.

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