ANPC type high-frequency isolation DC converter power module control method and test method

Abstract

The application relates to a control method and a test method for an ANPC high-frequency isolation DC converter power module, and belongs to the technical field of high-frequency isolation DC converters. The control method in the steady-state control stage is as follows: the DC side capacitor voltages of all chain links are collected in real time and averaged to obtain the average DC side voltage of all chain links, the average DC side voltage of all chain links is subtracted from the preset target DC side voltage of the whole device, and a global voltage reference value is obtained according to the difference; the output voltages of the H-bridge circuits of all modules in the same phase are averaged to obtain the average DC voltage of the commutation chain of the phase, the average DC voltage is subtracted from the global voltage reference value, and a reference voltage of each chain link in the phase is obtained according to the difference; the DC side capacitor voltage of each chain link is subtracted from the reference voltage of the chain link, and a driving pulse signal of each module H-bridge circuit is obtained according to the difference. The application solves the problems of high-frequency loss and voltage imbalance of the converter under the conditions of high frequency and high power.

Description

Technical Field

[0001] This invention belongs to the technical field of high-frequency isolated DC-DC converters, specifically relating to a power module control method and a drag test method for an ANPC type high-frequency isolated DC-DC converter. Background Technology

[0002] High-frequency isolated DC-DC converters are an important research area in power electronics, their development stemming from the size and weight limitations of traditional power frequency transformers. With advancements in power semiconductor devices (such as MOSFETs and IGBTs) and high-frequency magnetic materials, switching frequencies have increased from tens of kHz to the MHz level, significantly reducing converter size. This technology achieves electrical isolation through high-frequency transformers, ensuring safety while enabling voltage conversion and power transfer. Typical topologies include flyback, forward, LLC resonant, and dual active bridge (DAB) converters, among which soft-switching technology effectively reduces switching losses. They play a crucial role in new energy power generation, electric vehicle charging, and data center power supply.

[0003] Current technologies face challenges such as high-frequency losses, EMI suppression, and isolation reliability, and are developing towards wide-bandgap device applications, digital control, and magnetic integration. The introduction of third-generation semiconductors (SiC / GaN) has further driven the improvement of switching frequency and power density, enabling converters to be continuously optimized in terms of efficiency, size, and cost, becoming a core component of modern power electronic systems.

[0004] For example, Chinese invention patent application CN115714521A discloses a soft-switching domain optimization control method and system for a DAB converter. The DAB converter consists of an ANPC converter, a high-frequency transformer, and an H-bridge converter. The soft-switching domain optimization control method involves: calculating the boundary values ​​of the soft-switching region control quantities, the zero-voltage duty cycle, and the shift ratio based on the photovoltaic voltage reference value, the real-time acquisition of the voltage of the primary-side voltage divider capacitor, and the secondary-side output voltage of the DAB converter; determining the duty cycle command and shift ratio command of the DAB converter using a hysteresis control method; correcting the duty cycle command of the DAB converter using a voltage balancing method; and obtaining the switching trigger signal of the DAB converter based on the corrected duty cycle command and shift ratio command using a preset modulation method. While this control method achieves soft-switching operation capability near half-load of the DAB converter to some extent, the converter still faces high-frequency losses and voltage imbalance problems when operating under high-power, high-frequency conditions. Summary of the Invention

[0005] The purpose of this invention is to provide a power module control method and a drag test method for an ANPC type high-frequency isolated DC-DC converter, in order to solve the problems of high-frequency loss and voltage imbalance in existing ANPC type high-frequency isolated DC-DC converters when operating under high power and high frequency conditions.

[0006] To address the aforementioned technical problems, the first aspect of this invention provides a control method for an ANPC-type high-frequency isolated DC-DC converter module. The power module includes an ANPC-type three-level half-bridge circuit, an H-bridge circuit, and a high-frequency isolation transformer. The output terminal of the ANPC-type three-level half-bridge circuit is connected to the primary winding of the high-frequency isolation transformer, and the secondary winding of the high-frequency isolation transformer is connected to the input terminal of the H-bridge circuit. One power module is denoted as one link. The control method for entering the steady-state control phase after system startup is as follows: The DC-side capacitor voltages of all links are collected in real-time and averaged to obtain the voltage of all links. The DC-side average voltage is calculated by subtracting the average DC-side voltage of all links from the preset target DC-side voltage of the entire device, and obtaining the global voltage reference value based on the difference. The DC-side capacitor voltage of all links in the same phase is averaged to obtain the average DC voltage of each phase commutator chain. The average DC voltage of each phase commutator chain is then subtracted from the global voltage reference value, and the reference voltage of each link in each phase is obtained based on the difference. Finally, the DC-side capacitor voltage of each link is subtracted from the reference voltage of that link, and the drive pulse signal of each power module H-bridge circuit is obtained based on the difference.

[0007] In one possible implementation, the ANPC-type three-level half-bridge circuit includes two DC capacitors, a main power arm, and an active clamping arm. The two DC capacitors are connected in series and then in parallel with the main power arm. The main power arm includes a first, second, third, and fourth switch connected in series. The active clamping arm includes a fifth and a sixth switch. One end of the fifth switch is connected to one end of the sixth switch. The connection point of the second and third switches is the AC output terminal of the ANPC-type three-level half-bridge circuit. The connection point of the first and second switches is connected to the other end of the fifth switch, the connection point of the third and fourth switches is connected to the other end of the sixth switch, and the connection point of the fifth and sixth switches is connected to the connection point of the two DC capacitors. During modulation, the first and fifth switches are controlled to conduct complementaryly, and the fourth and sixth switches are controlled to conduct complementaryly. The drive signals of the second and sixth switches are consistent except that the high-level duration of the second switch is shorter than that of the sixth switch and the low-level duration is longer than that of the sixth switch. The drive signals of the third and fifth switches are consistent except that the high-level duration of the third switch is shorter than that of the fifth switch and the low-level duration is longer than that of the sixth switch.

[0008] In one possible implementation, when the converter is in the startup phase, the driving timing of each switch in the ANPC-type three-level half-bridge circuit is modulated as follows: In the first phase, the ANPC-type three-level half-bridge circuit first performs variable duty cycle startup, with the square wave voltage duty cycle gradually increasing from 0 to a first set value, and the switches in the ANPC-type three-level half-bridge circuit are locked, waiting for a first set time; In the second phase, the ANPC-type three-level half-bridge circuit and the H-bridge circuit simultaneously perform variable duty cycle startup, with the square wave voltage duty cycle gradually increasing from 0 to a first set value, and the square wave voltage phases of the first and second phases remain synchronized during the variable duty cycle startup process.

[0009] In one possible implementation, when the system is in a shutdown phase, after the converter receives a shutdown command, if the converter is operating in voltage source mode, it will directly lock all switches; if the converter is operating in current source mode, it will control the converter's power transmission towards zero power, and when the converter power drops to the set power value, it will directly lock all switches.

[0010] In one possible implementation, a hysteresis approach is used to set the control trajectory inflection point switching logic.

[0011] To solve the above-mentioned technical problems, the second aspect of the present invention provides a method for testing the ANPC type high-frequency isolated DC-DC converter module. The power module is controlled by an ANPC type high-frequency isolated DC-DC converter power module control method. The ANPC type high-frequency isolated DC-DC converter module control method is as follows: the power module includes an ANPC type three-level half-bridge circuit, an H-bridge circuit, and a high-frequency isolation transformer. The output terminal of the ANPC type three-level half-bridge circuit is connected to the primary of the high-frequency isolation transformer, and the secondary of the high-frequency isolation transformer is connected to the input terminal of the H-bridge circuit. One power module is denoted as one link. The control method for entering the steady-state control stage after the system starts up is as follows: the DC-side capacitor voltages of all links are collected in real time and averaged to obtain the average DC-side voltage of all links. The difference between the average DC-side voltage of all links and the preset target DC-side voltage of the entire device is calculated, and the global voltage reference value is obtained based on the obtained difference. The same phase... The average DC-side capacitor voltage of all links is calculated to obtain the average DC voltage of each phase commutator chain. The average DC voltage of each phase commutator chain is then subtracted from the global voltage reference value. The reference voltage of each link in each phase is obtained based on the difference. The DC-side capacitor voltage of each link is then subtracted from the reference voltage of that link. The drive pulse signal of the H-bridge circuit of each power module is obtained based on the difference. The counter-driving test method is as follows: At least two power modules are used for counter-driving test. First, the low-voltage side module of the two power modules completes phase shifting. After the phase shifting is started, the high-voltage side module control board is energized and the low-voltage side module drive pulse is blocked. Then, the H-bridge circuit of the two power modules is started synchronously by phase shifting, and the synchronization error of the drive pulse of the low-voltage side module and the high-voltage side module is lower than the set error value. After the phase shifting of the H-bridge circuit of the two power modules is completed, the high-voltage side module start command is issued to the two power modules. One power module completes Buck-Boost open-loop modulation, and the other power module completes Buck-Boost closed-loop modulation.

[0012] In one possible implementation, the ANPC-type three-level half-bridge circuit includes two DC capacitors, a main power arm, and an active clamping arm. The two DC capacitors are connected in series and then in parallel with the main power arm. The main power arm includes a first, second, third, and fourth switch connected in series. The active clamping arm includes a fifth and a sixth switch. One end of the fifth switch is connected to one end of the sixth switch. The connection point of the second and third switches is the AC output terminal of the ANPC-type three-level half-bridge circuit. The connection point of the first and second switches is connected to the other end of the fifth switch, the connection point of the third and fourth switches is connected to the other end of the sixth switch, and the connection point of the fifth and sixth switches is connected to the connection point of the two DC capacitors. During modulation, the first and fifth switches are controlled to conduct complementaryly, and the fourth and sixth switches are controlled to conduct complementaryly. The drive signals of the second and sixth switches are consistent except that the high-level duration of the second switch is shorter than that of the sixth switch and the low-level duration is longer than that of the sixth switch. The drive signals of the third and fifth switches are consistent except that the high-level duration of the third switch is shorter than that of the fifth switch and the low-level duration is longer than that of the sixth switch.

[0013] In one possible implementation, when the converter is in the startup phase, the driving timing of each switch in the ANPC-type three-level half-bridge circuit is modulated as follows: In the first phase, the ANPC-type three-level half-bridge circuit first performs variable duty cycle startup, with the square wave voltage duty cycle gradually increasing from 0 to a first set value, and the switches in the ANPC-type three-level half-bridge circuit are locked, waiting for a first set time; In the second phase, the ANPC-type three-level half-bridge circuit and the H-bridge circuit simultaneously perform variable duty cycle startup, with the square wave voltage duty cycle gradually increasing from 0 to a first set value, and the square wave voltage phases of the first and second phases remain synchronized during the variable duty cycle startup process.

[0014] In one possible implementation, when the system is in a shutdown phase, after the converter receives a shutdown command, if the converter is operating in voltage source mode, it will directly lock all switches; if the converter is operating in current source mode, it will control the converter's power transmission towards zero power, and when the converter power drops to the set power value, it will directly lock all switches.

[0015] In one possible implementation, a hysteresis approach is used to set the control trajectory inflection point switching logic.

[0016] In one possible implementation, in current source mode, current commands are issued through a monitoring backend, and after receiving the current commands, the controller performs current control output on the ANPC type high-frequency isolated DC-DC converter power module to start energy flow; in voltage source mode, voltage commands are issued through a monitoring backend, and after receiving the voltage commands, the controller performs stable voltage control on the ANPC type high-frequency isolated DC-DC converter power module.

[0017] In one possible implementation, after the low-voltage side module of the two power modules completes the blocking drive pulse, the H-bridge circuit of the two power modules is synchronously phase-shifted after waiting for a second set time.

[0018] In one possible implementation, the Buck-Boost open-loop modulation of the power module is as follows: the Buck-Boost open-loop modulation wave on the high-voltage side of the power module is compared with the carrier wave. If the amplitude of the modulation wave is greater than the amplitude of the carrier wave, a high level is output; if the amplitude of the modulation wave is less than or equal to the amplitude of the carrier wave, a low level is output, thereby obtaining the modulation pulse of the upper half-bridge transistor of the power module; the modulation pulse of the upper half-bridge transistor is inverted to obtain the modulation pulse of the lower half-bridge transistor.

[0019] In one possible implementation, the Buck-Boost closed-loop modulation of the power module is as follows: the Buck-Boost closed-loop modulation wave on the high-voltage side of the power module is compared with the carrier wave. If the amplitude of the modulation wave is greater than the amplitude of the carrier wave, a high level is output; if the amplitude of the modulation wave is less than or equal to the amplitude of the carrier wave, a low level is output, thereby obtaining the modulation pulse of the upper half-bridge transistor of the power module; the modulation pulse of the upper half-bridge transistor is inverted to obtain the modulation pulse of the lower half-bridge transistor.

[0020] The beneficial effects of this invention are as follows: This invention employs a three-level control system for each H-bridge circuit of the converter. The first level ensures that the global average DC voltage (the average capacitor voltage shared by all links) approaches the set target value, guaranteeing the overall power conversion efficiency and safe operating range of the system. The second level ensures that the DC voltage (i.e., the average phase voltage) between each phase remains consistent, eliminating current cycling or bus over / undervoltage caused by phase imbalance. The third level precisely adjusts the capacitor voltage of each link to the global-phase-layer comprehensive reference, thereby achieving voltage balance between links and preventing overload or undervoltage of any submodule. Through the hierarchical control structure (global-phase-link), global steady-state, phase-to-phase, and link-to-link DC bus voltage is achieved, thus ensuring soft switching, low EMI, power sharing, and reliable start-stop under high-frequency and high-power conditions. Attached Figure Description

[0021] Figure 1 This is the circuit schematic diagram of the ANPC type three-level half-bridge circuit of the present invention; Figure 2 This is a schematic diagram of the drive signal waveforms of each switching transistor in the ANPC-type three-level half-bridge circuit of the present invention; Figure 3 This is a schematic diagram of the topology of the ANPC type three-level DC / DC converter of the present invention; Figure 4 This is a schematic diagram of the drive signal waveforms of each switching transistor in the half-bridge circuit of the ANPC-type three-level DC / DC converter of the present invention; Figure 5 This is a schematic diagram of the switching logic of the inflection point of the inner and outer phase shift control trajectory in this invention; Figure 6 This is a schematic diagram of the steady-state control strategy of the ANPC type three-level DC / DC converter of the present invention; Figure 7 This is a schematic diagram of the system architecture of the ANPC-type three-level DC / DC converter of the present invention; Figure 8 This is a schematic diagram illustrating the test principle of the ANPC type high-frequency isolated DC-DC converter module drag test method of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0023] Implementation method of ANPC type high-frequency isolated DC-DC converter power module control method: The control method of this invention is based on an ANPC-type high-frequency isolated DC-DC converter power module, such as... Figure 3 As shown, each power module includes an ANPC-type three-level half-bridge circuit, an H-bridge circuit, and a high-frequency isolation transformer. The output of the ANPC-type three-level half-bridge circuit is connected to the primary winding of the high-frequency isolation transformer, and the secondary winding of the high-frequency isolation transformer is connected to the input of the H-bridge circuit. One power module is denoted as one link. The ANPC-type three-level half-bridge circuit includes two DC capacitors, a main power arm, and an active clamping arm. The two DC capacitors are connected in series and then in parallel with the main power arm. The main power arm includes first, second, third, and fourth switches connected in series. The active clamping arm includes fifth and sixth switches. One end of the fifth switch is connected to one end of the sixth switch. The connection point of the second and third switches is the AC output of the ANPC-type three-level half-bridge circuit. The connection point of the first and second switches is connected to the other end of the fifth switch. The connection point of the third and fourth switches is connected to the other end of the sixth switch. The connection point of the fifth and sixth switches is connected to the connection point of the two DC capacitors.

[0024] After the system starts up, the control method for entering the steady-state control stage is as follows: The DC-side capacitor voltages of all links are collected in real time and averaged to obtain the average DC-side voltage of all links. The difference between the average DC-side voltage of all links and the preset target DC-side voltage of the entire device is calculated, and the global voltage reference value is obtained based on the difference. The DC-side capacitor voltages of all links in the same phase are averaged to obtain the average DC voltage of each phase converter chain. The average DC voltage of each phase converter chain is subtracted from the global voltage reference value, and the reference voltage of each link in each phase is obtained based on the difference. The DC-side capacitor voltage of each link is subtracted from the reference voltage of that link, and the drive pulse signal of each power module H-bridge circuit is obtained based on the difference.

[0025] As one embodiment of the control method, during the modulation process, the first and fifth switches are controlled to conduct complementaryly, the fourth and sixth switches are controlled to conduct complementaryly, and the drive signals of the second and sixth switches are kept consistent except that the high-level duration of the second switch is lower than that of the sixth switch and the low-level duration is higher than that of the sixth switch; the drive signals of the third and fifth switches are kept consistent except that the high-level duration of the third switch is lower than that of the fifth switch and the low-level duration is higher than that of the sixth switch.

[0026] As an embodiment of the control method, when the converter is in the startup phase, the driving timing of each switch of the ANPC type three-level half-bridge circuit is modulated in the following manner: In the first phase, the ANPC type three-level half-bridge circuit first performs variable duty cycle startup, the square wave voltage duty cycle gradually increases from 0 to the first set value, and the switch of the ANPC type three-level half-bridge circuit is locked, waiting for the first set time; In the second phase, the ANPC type three-level half-bridge circuit and the H-bridge circuit simultaneously perform variable duty cycle startup, the square wave voltage duty cycle gradually increases from 0 to the first set value, and the square wave voltage phase of the first phase and the second phase remains synchronized during the variable duty cycle startup process.

[0027] As one embodiment of the first setting value, the first setting value is 50%.

[0028] As one embodiment of the control method, when the system is in the shutdown phase, after the converter receives the shutdown command, if the converter is operating in voltage source mode, all switches are directly locked; if the converter is operating in current source mode, the converter's power transmission is controlled towards zero power, and when the converter power is reduced to the set power value, all switches are directly locked.

[0029] As one embodiment of the control method, a hysteresis approach is used to set the switching logic for control trajectory inflection points, such as... Figure 5 As shown.

[0030] This invention provides an optimal implementation method for controlling the power module of an ANPC-type high-frequency isolated DC-DC converter, as detailed below: Figure 1 This is an ANPC-type three-level half-bridge circuit, which includes six switching transistors T1~T6 and anti-parallel diodes D1~D6 across each transistor. Considering the influence of the dead time of the complementary conducting switching transistors, the drive signal waveforms of each switching transistor in the ANPC-type three-level half-bridge are set as follows: Figure 2 As shown, T s This refers to the control cycle of the switching transistor; D α The following represents the output frequency of the high-frequency square wave U1 at the AC port of the half-bridge circuit: the ratio of the zero-level time to the half-cycle time within half a cycle; the yellow line represents the drive signal waveform of switch T1, the green line represents the drive signal waveform of switch T2, the purple line represents the drive signal waveform of switch T3, the blue line represents the drive signal waveform of switch T4, the gray line represents the drive signal waveform of switch T5, the orange line represents the drive signal waveform of switch T6, and the red line represents the high-frequency square wave output at the AC port of the ANPC type three-level half-bridge circuit; to avoid causing... When the DC bus capacitor is short-circuited and discharged, switches T1 and T5 conduct complementaryly (when T1 is off, T5 conducts), switches T4 and T6 conduct complementaryly, and the drive signals for switches T2 and T6 are basically the same. However, the high-level duration of switch T2 is slightly shorter than that of switch T6 (T2 turns off earlier than T6), and the low-level duration is slightly longer than that of switch T6. The drive signals for switches T3 and T5 are basically the same, but the high-level duration of switch T3 is slightly shorter than that of switch T5, and the low-level duration is slightly longer than that of switch T5.

[0031] By making the pulse width of T2 / T3 (main output transistor) narrower than that of T6 / T5 (clamping auxiliary transistor), a "commutation overlap region" is artificially created to offset the turn-off spike caused by the leakage inductance (L) of the high-frequency transformer. By utilizing the delayed turn-off of T6 / T5, the turn-off point of T2 / T3 is advanced by half a dead window, forcing the inductive current to freewheel through the neutral point clamping transistor (T6 / T5), thereby transforming hard turn-off into soft turn-off under low-voltage clamping, which greatly reduces the turn-off loss of wide bandgap devices.

[0032] Figure 3This is an ANPC-type three-level DC / DC converter topology, mainly composed of a three-level half-bridge circuit, an H-bridge circuit, a high-frequency isolation transformer, a series inductor L, and DC bus capacitors C1, C2, and C. The three-level half-bridge circuit includes six switching transistors T11-T16 and anti-parallel diodes D11-D16 across each transistor. The H-bridge circuit includes four switching transistors T21-T24 and anti-parallel diodes D21-D24 across each transistor. Because the ANPC-type three-level DC / DC converter uses fully controlled switching transistors on both sides and has a symmetrical structure, it can achieve bidirectional energy flow.

[0033] Taking dead zone factors into account, according to Figure 2 The ANPC-type three-level half-bridge circuit shown in the figure is configured by setting the waveforms of the drive signals for each switching transistor. Figure 3 The waveforms of the drive signals for each switch in the ANPC type three-level DC / DC converter shown are as follows: Figure 4 As shown, T s This refers to the control cycle of the switching transistor; D α The ratio of the zero-level time to the half-cycle time of the high-frequency square wave U1 output from the AC port of the half-bridge circuit. D β The following represents the ratio of the time that the center line of the high-frequency square wave U2 lags behind the center line of U1 at the AC port of the H-bridge circuit to half a cycle time; the yellow line represents the drive signal waveform of switch T11, the green line represents the drive signal waveform of switch T12, the purple line represents the drive signal waveform of switch T13, the blue line represents the drive signal waveform of switch T14, the gray line represents the drive signal waveform of switch T15, the orange line represents the drive signal waveform of switch T16, the pink line represents the drive signal waveform of switch T21 / T24, and the brown line represents the drive signal waveform of switch T22 / T23. Signal waveforms: Switches T11 and T15 conduct complementaryly (T15 conducts when T11 is off), switches T14 and T16 conduct complementaryly, the drive signals for switches T12 and T16 are basically the same, but the high-level duration of switch T12 is slightly shorter than that of switch T16 (T12 turns off earlier than T16), and the low-level duration is slightly longer than that of switch T16. The drive signals for switches T13 and T15 are basically the same, but the high-level duration of switch T13 is slightly shorter than that of switch T15, and the low-level duration is slightly longer than that of switch T15.

[0034] To avoid minor power fluctuations causing the control variable to repeatedly switch near the control trajectory inflection point—that is, the controller that actually performs the control function to switch repeatedly—an inner and outer phase-shifting control trajectory inflection point switching logic is adopted, such as... Figure 5 As shown. It is important to note that the controller must be a PI controller with additional enable and initialization functions. The switching logic is set using a hysteresis approach, as shown below. Figure 5 As shown, a hysteresis loop (dashed box) is introduced, which sets two different thresholds (external threshold and internal threshold) for the switching action, forming a buffer. When the control variable is within the buffer, the current state remains unchanged. When the control variable exceeds the buffer, the mode switch is triggered, thereby ensuring that the system can operate smoothly and robustly near the turning point. Figure 5 middle, D α It is the duty cycle of the power switch on the half-bridge side (high voltage side) (the ratio of the zero-level time to the half-cycle time of the high-frequency square wave U1 output from the AC port of the half-bridge circuit). D β It is the duty cycle of the power switch on the full-bridge side (low-voltage side) (the ratio of the time the center line of the high-frequency square wave U2 output from the AC port of the H-bridge circuit lags behind the center line of U1 to half a cycle time), and A→B→C→D is the control trajectory. D α_min It is the minimum duty cycle of the power switch on the half-bridge side (high-voltage side), and h is the hysteresis bandwidth. D α_edg It is the boundary value of the internal phase-shifting operation mode. D β_edg It is the boundary value of the external phase shifting operation mode.

[0035] The following example, using the control of the DC-side voltage of the H-bridge circuit in a DC / DC converter, illustrates the steady-state control strategy of the converter. Figure 6 As shown, where U rated For reference voltage, U dc_ave i is the average voltage of the DC-side capacitor. d i q It is a current dq transformation, u d u q It refers to voltage dq transformation, and wl is voltage feedforward. To achieve stable DC bus capacitor voltage in the cascaded H-bridge power module, there are three levels of control. The first level is global average DC voltage control, which ensures the average DC-side capacitor voltage of all links equals the reference voltage, thus solving the overall DC-side voltage stability problem of the device. Specifically, it sets the target DC-side voltage (i.e., the reference voltage) for the entire device. U rated The average DC-side capacitor voltage of all links is obtained by weighting and averaging the capacitor voltages collected on all links. U dc_ave Calculate the reference voltage U rated Average voltage of capacitor U dc_aveThe error between the two levels is adjusted by a PI controller and used as the global voltage reference for the next level. To prevent overcharging or undervoltage, the voltage value is also limited. This level ensures that the global average DC voltage (the average capacitor voltage shared by all links) approaches the target value, guaranteeing the overall power conversion efficiency and safe operating range of the system.

[0036] The second level is the DC voltage balance control between converter chain phases, ensuring that the average DC voltage of each phase converter chain equals the global average DC voltage, thus resolving the DC voltage imbalance between phases. Specifically, it involves sampling several links within the same phase (determined by the number of cascaded H-bridges) to obtain the average DC voltage of that phase's converter chain. The error between this average DC voltage and the global average DC voltage obtained from the previous level is calculated, generating a balance correction for that phase. This correction is then PI-regulated, and the PI-regulated voltage value is used to adjust the reference voltage of each link within the phase (e.g., distributing the PI-regulated voltage value to each link within the phase in a fixed proportion or weighted manner). This voltage is then fed into the third level of link DC voltage control as the voltage reference for the next level. This level ensures that the DC voltage (i.e., the average phase voltage) between phases remains consistent, eliminating current circulation or bus over / undervoltage caused by phase imbalance.

[0037] The third level is the link DC voltage control, which controls the DC voltage of each link to equal the average DC voltage of the commutation chain for that phase, thus resolving the DC voltage imbalance problem between links. Specifically, the capacitor voltage of each link (i.e., a single H-bridge power module) is acquired in real time to obtain the capacitor voltage Vdc_i of each link. The difference between the voltage reference value of the connection and Vdc_i is calculated, and the difference of each link is adjusted using PI control to obtain the adjustment command, which is then sent to the PWM modulation module (that is, the adjustment command is added to the reference duty cycle (the reference value given during startup) to generate the PWM control signal for each H-bridge). This level precisely adjusts the capacitor voltage of each link to the global-phase-layer comprehensive reference, thereby achieving voltage balance between links and preventing overload or undervoltage of any submodule.

[0038] In summary, the first level only concerns global balance and does not involve phase-to-phase details, simplifying large-scale power capacity adjustment. The second level, under the premise of global balance, only adjusts phase-to-phase distribution to make the power distribution of each phase smoother. The third level is responsible for fine-tuning to ensure that the operating point of each H-bridge module is optimal. The three levels complement each other, and through a hierarchical control structure (global-phase-link), global steady-state, phase-to-phase, and link-to-link balance of DC bus voltage are achieved, thereby ensuring soft switching, low EMI, power sharing, and reliable start-stop under high-frequency and high-power conditions.

[0039] Implementation method of ANPC type high frequency isolation DC converter power module to-load test method: This invention also provides a system architecture for an ANPC-type three-level DC / DC converter, such as... Figure 7 As shown, the system includes a monitoring backend, a controller, a high-voltage side SCE board (the SEC board is the field control board), and a low-voltage side SCE board. The monitoring backend communicates with the controller. The controller is connected to both the high-voltage and low-voltage side SCE boards via optical fibers. The high-voltage side SCE board is connected to the half-bridge module (half-bridge three-level circuit), and the low-voltage side SCE board is connected to the full-bridge module (H-bridge circuit). The controller is used to implement modulation timing control, start-up and shutdown control, steady-state operation control, and fault protection for the ANPC-type three-level DC / DC converter through control logic. The ANPC-type three-level DC / DC converter communicates with the monitoring backend through the high-voltage side SCE board, the low-voltage side SCE board, and the controller, thereby enabling monitoring of the DC converter's operating data and status, as well as remote control of the DC converter.

[0040] This invention is also based on Figure 6 The steady-state control strategy shown and Figure 7 The control system architecture shown is presented, and a power module-to-power testing method is proposed. The testing principle is as follows: Figure 8 As shown. Module 1 is the power module under test, and module 2 is the auxiliary power module. Module 1 uses constant voltage control, and module 2 uses constant power control. The test method is as follows: At least two power modules are used for the test. First, phase shifting is completed on the low-voltage side of the two power modules. After the phase shifting is started, the control board of the high-voltage side module is energized and the drive pulse of the low-voltage side module is blocked. Then, the H-bridge circuit of the two power modules is started synchronously with phase shifting, and the synchronization error of the drive pulse of the low-voltage side module and the high-voltage side module is lower than the set error value. After the phase shifting of the H-bridge circuit of the two power modules is completed, a high-voltage side module start command is sent to the two power modules. One power module completes Buck-Boost open-loop modulation, and the other power module completes Buck-Boost closed-loop modulation.

[0041] As one embodiment of setting the error value, the set error value is 100 ns. As other embodiments of setting the error value, the set error value may also be 99 ns, 101 ns, etc.

[0042] As one embodiment of the drag test method, in current source mode, current commands are issued through the monitoring backend, and after receiving the current commands, the controller controls the current output of the ANPC high-frequency isolated DC-DC converter power module to start energy flow; in voltage source mode, voltage commands are issued through the monitoring backend, and after receiving the voltage commands, the controller controls the stable voltage of the ANPC high-frequency isolated DC-DC converter power module.

[0043] As an example of the drag test method, after the low-voltage side module of the two power modules completes the blocking drive pulse, the H-bridge circuit of the two power modules is synchronously started after waiting for a second set time.

[0044] As one embodiment of the second set time, the second set time is preferably 1 second. As other embodiments, the second set time can also be 1.5 seconds, 2 seconds, etc.

[0045] As an example of Buck-Boost open-loop modulation of the power module, the Buck-Boost open-loop modulation wave on the high-voltage side of the power module is compared with the carrier wave. If the amplitude of the modulation wave is greater than the amplitude of the carrier wave, a high level is output; if the amplitude of the modulation wave is less than or equal to the amplitude of the carrier wave, a low level is output, thereby obtaining the modulation pulse of the upper half-bridge transistor of the power module. The modulation pulse of the upper half-bridge transistor is inverted to obtain the modulation pulse of the lower half-bridge transistor.

[0046] As an example of Buck-Boost closed-loop modulation of the power module, the Buck-Boost closed-loop modulation wave on the high-voltage side of the power module is compared with the carrier wave. If the amplitude of the modulation wave is greater than the amplitude of the carrier wave, a high level is output; if the amplitude of the modulation wave is less than or equal to the amplitude of the carrier wave, a low level is output, thereby obtaining the modulation pulse of the upper half-bridge transistor of the power module. The modulation pulse of the upper half-bridge transistor is inverted to obtain the modulation pulse of the lower half-bridge transistor.

[0047] This invention provides an optimal implementation method for the power module-to-power test of an ANPC-type high-frequency isolated DC-DC converter. The specific test process of this implementation method is as follows: (1) Send a start command (included in the main control command word) to the SCE board of module 1 and module 2, and send a phase shift start command word (0x6666) at the same time. After the FPGA of the SCE board of module 1 and module 2 receives the start command (included in the main control command word) and the phase shift start command word (0x6666), module 1 and module 2 start phase shift from the low voltage side module at the same time. After the phase shift start is completed, the high voltage side module SCE board of the two modules is energized. At this time, the PWM pulse of the low voltage side module of the two modules is blocked (the low voltage side module SCE board is prohibited from outputting PWM pulse). (2) After the low-voltage side module of the two modules completes the blocking pulse, wait for 1 second, and then the H-bridges on both sides of the two modules start phase shifting at the same time. It is necessary to ensure that the PWM pulses on the high and low voltage sides are synchronized, with an error of ≤100ns. (3) After the phase-shifting start-up of the H-bridges on both sides is completed, the low-voltage side module SCE board of each module sends the phase-shifting start-up completion flag (0x5566) to the interface board, and the interface board then uploads it to the main control FPGA (the main control FPGA is the main control board of the system cabinet). Figure 7The controller shown is responsible for global instruction scheduling and status aggregation, receiving the status of all modules reported by the interface board. The main control FPGA then uploads the data to the ARM controller (running on...). Figure 7 (As shown in the monitoring backend) (4) After receiving the phase-shift start-up completion flag (0x5566), the ARM controller sends a high-voltage side start-up command to both modules; (5) After receiving the start command, the high-voltage side SCE boards of modules 1 and 2 simultaneously unlock the high-voltage side Buck-Boost pulse. The pulse of module 1 is generated by comparing the high-voltage side Buck-Boost open-loop modulation wave (amplitude of 0.8) of module 1 with the triangular carrier. The comparison method is as follows: if the amplitude of the modulation wave is greater than the amplitude of the carrier, the output is high level; if the modulation wave is less than the carrier, the output is low level. This pulse is used for the upper MOSFET pulse of the Buck-Boost half-bridge. The driving circuit inverts this pulse and uses it for the lower MOSFET pulse of the Buck-Boost half-bridge. (6) The pulse of module 2 is generated by comparing the Buck-Boost closed-loop modulation wave on the high-voltage side of module 2 with the triangular carrier wave. The comparison method is: if the amplitude of the modulation wave is greater than the amplitude of the carrier wave, the output is high level; if the modulation wave is less than the carrier wave, the output is low level. This pulse is used for the upper transistor pulse of the Buck-Boost half-bridge. The driving circuit inverts this pulse and uses it for the lower transistor pulse of the Buck-Boost half-bridge.

[0048] The core idea of ​​the above method is as follows: First, phase shifting is completed on the low-voltage side of the module, the high-voltage side capacitor is pre-charged, and the low-voltage side PWM is blocked to prevent cross-conduction between the low-voltage and high-voltage sides. Then, the H-bridge circuits on both sides are started synchronously by phase shifting, requiring the PWM synchronization error between the low-voltage and high-voltage sides to be ≤100ns to ensure that the soft switching or ZVS / ZCS conditions are not violated. After the phase shifting is completed, it is reported to the host computer, and then the high-voltage side start command is sent down layer by layer. Module 1 (constant voltage) completes Buck-Boost open-loop modulation, and module 2 (constant power) completes Buck-Boost closed-loop modulation.

[0049] The control strategy implements voltage and power control for the drive system. In current source mode, current commands are sent through the monitoring backend, and the controller receives the current commands and outputs current control to initiate energy flow. In voltage source mode, voltage commands are sent through the monitoring backend, and the controller receives the voltage commands and performs voltage stabilization control. The control system can also display voltage, current, and module status.

[0050] By keeping one module at a constant voltage and another at a constant power (or current), the mutual influence of voltage source mode / current source mode on the same bus can be directly verified to ensure that it meets design requirements (such as voltage fluctuation, power distribution, and power factor). Through drag-and-drop experiments, the steady-state waveform of the bus voltage, power distribution curve, temperature rise curve, and displacement-power coupling characteristics can be obtained in one go, providing complete experimental evidence for system reliability, thermal-electric coupling design, and parallel operation of multiple modules.

[0051] The high-frequency isolated DC-DC converter of this invention uses an ANPC three-level topology and control strategy to achieve bidirectional energy flow, high-power operation, electrical isolation, data and status monitoring, control and fault protection. After dual-module drag testing, the DC-DC converter can be made to operate more stably and reliably.

Claims

1. A control method for a power module of an ANPC-type high-frequency isolated DC-DC converter, wherein the power module includes an ANPC-type three-level half-bridge circuit, an H-bridge circuit, and a high-frequency isolation transformer, the output terminal of the ANPC-type three-level half-bridge circuit is connected to the primary winding of the high-frequency isolation transformer, the secondary winding of the high-frequency isolation transformer is connected to the input terminal of the H-bridge circuit, and one power module is denoted as one link, characterized in that... After the system starts up, the control method for entering the steady-state control stage is as follows: the DC-side capacitor voltage of all links is collected in real time and averaged to obtain the average DC-side voltage of all links. The difference between the average DC-side voltage of all links and the preset target DC-side voltage of the entire device is calculated, and the global voltage reference value is obtained based on the difference. The average DC-side capacitor voltage of all links in the same phase is calculated to obtain the average DC voltage of each phase commutator chain. The average DC voltage of each phase commutator chain is then subtracted from the global voltage reference value. The reference voltage of each link in each phase is obtained based on the difference. The DC-side capacitor voltage of each link is then subtracted from the reference voltage of that link. The drive pulse signal of each power module H-bridge circuit is obtained based on the difference.

2. The ANPC-type high-frequency isolated DC-DC converter power module control method according to claim 1, characterized in that, The ANPC-type three-level half-bridge circuit includes two DC capacitors, a main power arm, and an active clamping arm. The two DC capacitors are connected in series and then in parallel with the main power arm. The main power arm includes a first, second, third, and fourth switch connected in series. The active clamping arm includes a fifth and a sixth switch. One end of the fifth switch is connected to one end of the sixth switch. The connection point of the second and third switches is the AC output terminal of the ANPC-type three-level half-bridge circuit. The connection point of the first and second switches is connected to the other end of the fifth switch, and the connection point of the third and fourth switches is connected to the other end of the sixth switch. The connection point of the fifth and sixth switches is connected to the connection point of the two DC capacitors. During modulation, the first and fifth switches are controlled to conduct complementaryly, and the fourth and sixth switches are controlled to conduct complementaryly. The drive signals of the second and sixth switches are consistent except that the high-level duration of the second switch is shorter than that of the sixth switch and the low-level duration is longer than that of the sixth switch. The drive signals of the third and fifth switches are consistent except that the high-level duration of the third switch is shorter than that of the fifth switch and the low-level duration is longer than that of the sixth switch.

3. The ANPC-type high-frequency isolated DC-DC converter power module control method according to claim 1, characterized in that, When the converter is in the startup phase, the driving timing of each switch in the ANPC type three-level half-bridge circuit is modulated as follows: In the first phase, the ANPC type three-level half-bridge circuit first performs variable duty cycle startup, and the square wave voltage duty cycle gradually increases from 0 to the first set value. The switches of the ANPC type three-level half-bridge circuit are locked and wait for the first set time. In the second phase, the ANPC type three-level half-bridge circuit and the H-bridge circuit perform variable duty cycle startup simultaneously, and the square wave voltage duty cycle gradually increases from 0 to the first set value. During the variable duty cycle startup process, the square wave voltage phase of the first phase and the second phase remain synchronized.

4. The ANPC-type high-frequency isolated DC-DC converter power module control method according to claim 1, characterized in that, When the system is in a shutdown phase, after the converter receives the shutdown command, if the converter is operating in voltage source mode, it will directly lock all the switching transistors; if the converter is operating in current source mode, it will control the converter's power transmission towards zero power. When the converter power is reduced to the set power value, it will directly lock all the switching transistors.

5. The ANPC type high-frequency isolated DC-DC converter power module control method according to any one of claims 1 to 4, characterized in that, The switching logic for control trajectory inflection points is set using a hysteresis approach.

6. A method for testing the power module of an ANPC-type high-frequency isolated DC-DC converter, characterized in that, The power module is controlled using the ANPC type high-frequency isolated DC-DC converter power module control method according to any one of claims 1 to 5. The counter-driving test method is as follows: at least two power modules are used for counter-driving test. First, the low-voltage side module of the two power modules completes phase shifting. After the phase shifting is started, the high-voltage side module control board is energized and the low-voltage side module drive pulse is blocked. Then, the H-bridge circuit of the two power modules is started synchronously by phase shifting, and the synchronization error of the drive pulse of the low-voltage side module and the high-voltage side module is lower than the set error value. After the phase shifting of the H-bridge circuit of the two power modules is completed, the high-voltage side module start command is sent to the two power modules. One power module completes Buck-Boost open-loop modulation, and the other power module completes Buck-Boost closed-loop modulation.

7. The ANPC type high-frequency isolated DC-DC converter power module power module test method according to claim 6, characterized in that, In current source mode, current commands are sent through the monitoring backend. After receiving the current commands, the controller controls the current output of the ANPC high-frequency isolated DC-DC converter power module to start energy flow. In voltage source mode, voltage commands are sent through the monitoring backend. After receiving the voltage commands, the controller stabilizes the voltage of the ANPC high-frequency isolated DC-DC converter power module.

8. The ANPC type high-frequency isolated DC-DC converter power module power module test method according to claim 6, characterized in that, After the low-voltage side module of the two power modules completes the blocking drive pulse, wait for the second set time, and then synchronously phase-shift to start the H-bridge circuit of the two power modules.

9. The ANPC type high-frequency isolated DC-DC converter power module test method according to claim 6, characterized in that, The Buck-Boost open-loop modulation of the power module is as follows: the Buck-Boost open-loop modulation wave on the high-voltage side of the power module is compared with the carrier wave. If the amplitude of the modulation wave is greater than the amplitude of the carrier wave, a high level is output; if the amplitude of the modulation wave is less than or equal to the amplitude of the carrier wave, a low level is output, thus obtaining the modulation pulse of the upper half-bridge transistor of the power module. The modulation pulse of the upper half-bridge transistor is inverted to obtain the modulation pulse of the lower half-bridge transistor.

10. The ANPC type high-frequency isolated DC-DC converter power module power module test method according to claim 6, characterized in that, The Buck-Boost closed-loop modulation of the power module is as follows: the Buck-Boost closed-loop modulation wave on the high-voltage side of the power module is compared with the carrier wave. If the amplitude of the modulation wave is greater than the amplitude of the carrier wave, a high level is output; if the amplitude of the modulation wave is less than or equal to the amplitude of the carrier wave, a low level is output, thus obtaining the modulation pulse of the upper half-bridge transistor of the power module; the modulation pulse of the upper half-bridge transistor is inverted to obtain the modulation pulse of the lower half-bridge transistor.

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