Control circuit of crystal oscillator, crystal oscillation circuit, and electronic device

Abstract

Provided are a control circuit of a crystal oscillator, a crystal oscillation circuit and an electronic device, and belong to the technical field of integrated circuits. In the control circuit, a timing control circuit and a sweep frequency oscillation loop can cooperate with each other to achieve sweep frequency energy injection in the starting stage of the crystal oscillator, to excite the crystal oscillator to start up rapidly to a stable target amplitude, and the timing control circuit and an amplitude control module can also cooperate with each other to limit the oscillation amplitude through negative feedback in the steady state of the crystal oscillator, i.e., when the crystal oscillator has started up to the stable target amplitude, to achieve steady state gain attenuation. In this way, the working power consumption of the overall circuit can be effectively reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a control circuit for a crystal oscillator, a crystal oscillator circuit, and an electronic device. Background Technology

[0002] A crystal oscillator is a circuit that uses the piezoelectric effect of crystals such as quartz to generate clock signals. It is commonly used in various communication devices (such as mobile phones) as a reference frequency source. For example, common crystal oscillators include digitally controlled crystal oscillators (DCXO). Summary of the Invention

[0003] A control circuit, a crystal oscillation circuit, and an electronic device for a crystal oscillation are provided to effectively reduce the operating power consumption of the crystal oscillation circuit. The technical solution is as follows: On one hand, a control circuit for a crystal oscillator is provided, the crystal oscillator being used to oscillate to generate a clock signal, and being used to stably output the clock signal when the oscillation amplitude reaches a target amplitude; the control circuit includes: The timing control circuit is used to output a frequency injection enable signal when the power is on, and to switch to an output amplifier enable signal when the oscillation amplitude of the crystal oscillator reaches the target amplitude. A frequency sweep oscillation loop is used to receive a frequency injection enable signal and, in response to the frequency injection enable signal, generate a frequency sweep signal whose frequency gradually decreases over time and output it to the crystal oscillator. When the frequency of the frequency sweep signal matches the natural frequency of the crystal in the crystal oscillator, energy is injected into the crystal oscillator to excite the crystal oscillator to quickly start oscillating to the target amplitude. An amplitude control module is used to receive an amplifier enable signal and, in response to the amplifier enable signal, limit the oscillation amplitude of the crystal oscillator through negative feedback to reduce the loop power consumption of the crystal oscillator.

[0004] Optionally, the upper limit of the frequency of the sweep signal is greater than the inherent frequency of the crystal, and the lower limit of the frequency of the sweep signal is less than the inherent frequency of the crystal.

[0005] Optionally, the upper limit of the frequency of the sweep signal is greater than twice the inherent frequency of the crystal, and the lower limit of the frequency of the sweep signal is less than half the inherent frequency of the crystal.

[0006] Optionally, the crystal oscillator further includes: an adjustable load capacitor; The timing control circuit is also used to adjust the capacitance value of the adjustable load capacitor based on the oscillation amplitude of the crystal oscillator, so that the capacitance value is positively correlated with the oscillation amplitude.

[0007] Optionally, the timing control circuit is configured to set the capacitance value of the adjustable load capacitor to a first capacitance value when the power is on, and to switch the capacitance value of the adjustable load capacitor from the first capacitance value to a second capacitance value when the oscillation amplitude of the crystal oscillator reaches the target amplitude. The second capacitance value is greater than the first capacitance value.

[0008] Optionally, the timing control circuit is further configured to stop outputting the frequency injection enable signal when the frequency of the sweep signal matches the inherent frequency of the crystal, so as to instruct the sweep oscillation loop to stop generating the sweep signal; Furthermore, before the oscillation amplitude of the crystal oscillator reaches the target amplitude, the amplifier enable signal is prohibited from being output to disable the amplitude control module.

[0009] Optionally, the swept-frequency oscillation loop includes: a swept-frequency voltage-controlled oscillator and its state control unit; The frequency sweep voltage-controlled oscillator is used to receive the frequency injection enable signal and generate the frequency sweep signal and the frequency sweep control voltage in response to the frequency injection enable signal. The state control unit is used to receive the frequency injection enable signal, the frequency sweep signal, and the frequency sweep control voltage, and in response to the frequency injection enable signal, the frequency sweep signal, and the frequency sweep control voltage, control the on / off state of the frequency sweep voltage-controlled oscillator and the crystal oscillator to control the output state of the frequency sweep signal.

[0010] Optionally, the swept-frequency voltage-controlled oscillator includes: an oscillation switch, a bias circuit, a ring oscillator, and a first filter and voltage regulation circuit; The oscillation switch is used to receive the frequency injection enable signal and control the on / off state of the bias circuit and the ring oscillator in response to the frequency injection enable signal. The bias circuit is used to provide bias to the ring oscillator when it is turned on. The ring oscillator is configured to operate under the control of the bias circuit to generate the sweep frequency signal and the sweep frequency control voltage. The first filtering and voltage regulation circuit is used to filter and regulate the frequency sweep control voltage.

[0011] Optionally, the state control unit includes: a second filter and voltage regulator circuit, an input buffer, a logic processing unit, and a switch control inverting unit; The second filtering and voltage regulation circuit is used to receive the sweep frequency control voltage and to filter and regulate the sweep frequency control voltage. The input buffer is used to receive the sweep frequency control voltage output by the second filter and voltage regulator circuit, and output a reference signal based on the received sweep frequency control voltage. The logic processing unit is used to receive the sweep signal and the reference signal, and to perform logic processing on the sweep signal and the reference signal to output a switch control signal; The switch control inverting section is used to receive the frequency injection enable signal, the switch control signal, and the reference signal, and in response to the switch control signal and the reference signal, control the output voltage of the switch control inverting section, and in response to the frequency injection enable signal, control the on / off state of the sweep frequency voltage-controlled oscillator and the crystal oscillator, so as to control the output state of the sweep frequency signal.

[0012] Optionally, the crystal oscillator further includes: an inverting amplifier; The amplitude control module is used to reduce the negative resistance of the inverting amplifier through negative feedback in response to the amplifier enable signal, so as to limit the oscillation amplitude of the crystal oscillator.

[0013] Optionally, the amplitude control module includes: a control switch section and an amplifier control section; The control switch is used to receive the amplifier enable signal and control the switching between the amplifier control unit and the crystal oscillator in response to the amplifier enable signal. The amplifier control unit is configured to reduce the bias current of the inverting amplifier through negative feedback when the crystal oscillator is turned on, thereby limiting the gain of the inverting amplifier and reducing the negative resistance of the inverting amplifier.

[0014] On the other hand, a crystal oscillation circuit is provided, the crystal oscillation circuit comprising: a crystal oscillator, and a control circuit as described in the above aspect.

[0015] In another aspect, an electronic device is provided, comprising: a load, and a crystal oscillator circuit as described in the other aspect above.

[0016] In summary, the beneficial effects of the technical solution provided in this application can include at least the following: A control circuit, a crystal oscillation circuit, and an electronic device for a crystal oscillator are provided. In this control circuit, the timing control circuit and the frequency sweep oscillation loop can cooperate to inject frequency sweep energy during the crystal oscillator's start-up phase, exciting the crystal oscillator to quickly oscillate to a stable target amplitude. Furthermore, the timing control circuit and the amplitude control module can cooperate to limit the oscillation amplitude through negative feedback in the crystal oscillator's steady-state state, i.e., after oscillating to a stable target amplitude, thus achieving steady-state gain attenuation. This effectively reduces the overall circuit's power consumption. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a crystal oscillator and its control circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of the operating timing waveforms of a crystal oscillator circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of a frequency changing over time provided in an embodiment of this application; Figure 4 This is a schematic diagram of another crystal oscillator and its control circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of a swept-frequency voltage-controlled oscillator in a control circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of the circuit structure of a sweep frequency voltage-controlled oscillator in a control circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a state control machine in a control circuit provided in an embodiment of this application; Figure 8 This is a schematic diagram of the circuit structure of a state control machine in a control circuit provided in an embodiment of this application; Figure 9 This is a schematic diagram of another crystal oscillator and its control circuit provided in the embodiments of this application; Figure 10 This is a schematic diagram of the circuit structure of an amplitude control module in a control circuit provided in an embodiment of this application; Figure 11 This is a schematic diagram of another crystal oscillator and its control circuit provided in an embodiment of this application; Figure 12 This is a schematic diagram of a crystal oscillator circuit provided in an embodiment of this application; Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0020] In the field of chip technology, to save chip power consumption and extend chip lifespan, at least some functional modules in a chip typically operate in a periodic sleep and wake-up mode. When entering sleep mode, the functional module can be shut down and stop working; upon wake-up, the functional mode can be restarted and begin working again. These at least some functional modules may include a crystal oscillator in the chip, such as the common DCXO, which is a circuit that uses digital signals to control the start-up and output frequency of a quartz crystal. DXCOs are often used as chip clock sources due to their advantages such as frequency stability, low phase noise, stable output frequency, and clean spectrum, providing an ideal reference clock or input clock to drive the chip to normal operation. However, current DCXOs typically require several milliseconds to wake up and output a stable frequency; that is, the time required for a DCXO to fully wake up from sleep mode, or the start-up time, is usually quite long. Moreover, during this few milliseconds of start-up time, the chip is in a power-on waiting state and cannot enter normal operation. Thus, the longer the start-up time, the greater the power consumption wasted by the chip while waiting to operate. Therefore, shortening the start-up time of the DCXO is of great significance for reducing the overall power consumption of the chip.

[0021] Currently, there are several methods to shorten the start-up time of a DCXO. For example, in some embodiments, the size of the gain transistor in the DCXO is increased to improve the loop gain, thereby accelerating the start-up process and shortening the start-up time. However, increasing the size significantly increases the static power consumption of the DCXO, causing the static power consumption to double. Another example is the use of a constant frequency clock to inject energy into the DCXO loop to provide initial excitation, allowing the quartz crystal in the DCXO to quickly enter stable oscillation and shorten the start-up time. However, injecting energy usually requires an additional stable clock source capable of generating this constant frequency clock, which not only increases the overall chip area but also introduces additional device power consumption. These methods clearly contradict the low-power design objective, meaning that current methods all have certain limitations.

[0022] Based on this, embodiments of this application provide a control circuit for a crystal oscillator. This circuit can reliably reduce the start-up time of the crystal oscillator based on sweep frequency energy injection and steady-state gain attenuation, and at the same time reliably reduce the operating power consumption of the crystal oscillator. Figure 1 This is a schematic diagram of the control circuit of a crystal oscillator provided in an embodiment of this application.

[0023] refer to Figure 1 The crystal oscillator 10 provided in this application embodiment can be a DCXO, including a quartz crystal XTAL, a bias resistor Rb0, an inverting amplifier INV0, and adjustable load capacitors CN and CP. The connection relationship of each device is as follows: Figure 1 As shown, this will not be repeated here. Of course, it is not limited to... Figure 1 The crystal oscillator shown has the following structure.

[0024] Furthermore, the crystal oscillator 10 provided in this application embodiment can be used to oscillate to generate a clock signal, and can be used to stably output a clock signal when the oscillation amplitude reaches a target amplitude. That is, in combination with Figure 1 The crystal oscillator 10 utilizes the piezoelectric effect of its XTAL quartz crystal to generate a frequency-adjustable clock signal through oscillation. This clock signal can serve as a clock source for internal chip modules, providing a reference clock. Upon power-up, the crystal oscillator 10 first enters a start-up phase, where its oscillation amplitude starts from zero and gradually builds up to the desired target amplitude. Once the target amplitude is reached, the crystal oscillator 10 enters a stable operating state, or steady state. In this steady state, the crystal oscillator 10 outputs a stable clock signal to the connected load, driving the load to operate normally. Figure 1 In this context, OUTP and OUTN can refer to a pair of differential clock signals output by crystal oscillator 10, with exactly opposite phases. P can be used to represent a positive signal, and N can be used to represent a negative signal.

[0025] It is understandable that the piezoelectric effect of a quartz crystal (XTAL) refers to the fact that when an alternating voltage is applied across the XTAL, its physical shape changes, causing the XTAL to vibrate mechanically. Furthermore, when the frequency of the applied alternating voltage is the same as or close to the natural frequency (Fosc) of the XTAL, the oscillation amplitude of the XTAL increases significantly, allowing it to oscillate rapidly.

[0026] Optionally, combined Figure 1It is also known that the inverting amplifier INV0 can be used to provide loop gain and a 180-degree phase shift for the crystal oscillator 10, thereby meeting the phase conditions required for oscillation. The bias resistor Rb0 can be used to bias the voltage across the inverting amplifier INV0, biasing the voltage across the inverting amplifier INV0 to its high-gain linear operating region, also known as the amplification region, so that the inverting amplifier INV0 can amplify the weak feedback signal from the quartz crystal XTAL. The adjustable load capacitors CN and CP can be used to change the equivalent capacitance value of the quartz crystal XTAL, thereby adjusting the oscillation frequency. Generally, the smaller the capacitance value, the larger the loop negative resistance; conversely, the larger the capacitance value, the smaller the loop negative resistance. The negative resistance refers to the equivalent negative resistance formed across the inverting amplifier INV0, which is used to compensate for the energy loss of the quartz crystal XTAL. The magnitude of the negative resistance is determined by the transconductance and equivalent capacitance value of the inverting amplifier INV0. The transconductance of the inverting amplifier INV0 is determined by the device size or the bias current. Furthermore, transconductance is positively correlated with gain and bias current, negative resistance is positively correlated with transconductance, and negative resistance is negatively correlated with equivalent capacitance. Moreover, the higher the gain, the higher the negative resistance, resulting in faster oscillation but increased power consumption; conversely, the lower the gain, the lower the negative resistance, and the lower the power consumption.

[0027] Continue to refer to Figure 1 The control circuit 00 provided in this application embodiment includes: timing control circuit 01, frequency sweep oscillation loop 02, and amplitude control module 03.

[0028] The timing control circuit 01 is used to output the frequency-inject (Freq-inject) enable signal Fin-en when the power is on, and to switch to the output amplifier (AMP) enable signal Amp-en when the oscillation amplitude of the crystal oscillator 10 reaches the target amplitude.

[0029] The sweep frequency oscillation loop 02 is used to receive the frequency injection enable signal Fin-en and generate a sweep frequency signal X whose frequency gradually decreases over time in response to the frequency injection enable signal Fin-en and output it to the crystal oscillator 10. When the frequency of the sweep frequency signal X matches the inherent frequency Fosc of the crystal (e.g., quartz crystal XTAL) in the crystal oscillator 10, energy is injected into the crystal oscillator 10 to excite the crystal oscillator 10 to quickly start oscillating to the target amplitude.

[0030] The amplitude control module 03 receives the amplifier enable signal Amp-en and, in response to the amplifier enable signal Amp-en, limits the oscillation amplitude of the crystal oscillator 10 through negative feedback to reduce the loop power consumption of the crystal oscillator 10. The amplitude control module 03 is also called the Amp Control module.

[0031] That is, in the embodiments of this application, such as Figure 1 As shown, the timing control circuit 01 can be connected to the sweep frequency oscillation loop 02 and the amplitude control module 03 respectively, and the timing control circuit 01, the sweep frequency oscillation loop 02 and the amplitude control module 03 can also be connected to the crystal oscillator 10.

[0032] Furthermore, the timing control circuit 01 can initially output a frequency injection enable signal Fin-en to the sweep frequency oscillation loop 02 upon power-up, thereby controlling the sweep frequency oscillation loop 02 to start operation and achieve sweep frequency energy injection. Specifically, under the control of this frequency injection enable signal Fin-en, the sweep frequency oscillation loop 02 can generate a sweep frequency signal X whose frequency gradually decreases over time, i.e., generate a sweep frequency signal X such as... Figure 1 The waveform shown is a sweep waveform or oscillation waveform where the frequency continuously decreases from high frequency (Fhi) to low frequency (Flo), rather than a constant frequency clock. Figure 1 The diagram shows the X-waveform, with the horizontal axis representing time (t) and the vertical axis representing frequency (Freq). This allows energy to be injected instantaneously into the quartz crystal XTAL when the frequency of the sweep signal X matches its inherent frequency (Fosc), causing it to quickly start oscillating and reach the target amplitude, thus completing the oscillation and stabilizing the output clock signal. This stage from power-on to oscillation completion is the oscillation stage described earlier. In this oscillation stage, the timing control circuit 01 and the sweep oscillation loop 02 can cooperate to inject sweep energy, accelerating oscillation, shortening the start-up time, and allowing the oscillation amplitude to quickly oscillate from 0 to the target amplitude, thereby accelerating the output of a stable clock signal from the crystal oscillator 10. This shortens the power-on waiting time of the chip, avoiding wasted power due to a long power-on waiting time, and reducing the overall power consumption of the chip. Furthermore, the matching of the frequency of the sweep signal X with the inherent frequency (Fosc) of the quartz crystal XTAL can mean that the two frequencies are the same or close.

[0033] Furthermore, the timing control circuit 01 can switch to the output amplifier enable signal Amp-en from the amplitude control module 03 when the oscillation amplitude of the crystal oscillator 10 reaches the target amplitude, i.e., when the crystal oscillator 10 enters a stable operating state and outputs a stable clock signal. This allows the amplitude control module 03 to start operating and achieve steady-state gain attenuation. Specifically, under the control of the amplifier enable signal Amp-en, the amplitude control module 03 can limit the gain of the inverting amplifier INV0 in the crystal oscillator 10 through negative feedback, thereby limiting the oscillation amplitude of the crystal oscillator 10 and preventing excessive oscillation amplitude from causing output distortion and wasted power. In other words, in the steady-state stage, the timing control circuit 01 and the amplitude control module 03 can cooperate to achieve steady-state gain limitation, thus avoiding output distortion of the crystal oscillator 10, ensuring reliable output of a stable clock signal, and preventing excessive power consumption of the crystal oscillator 10, further reducing power consumption. Furthermore, this can limit the oscillation amplitude of the crystal oscillator 10 to be stable near the target amplitude, as close as possible to the target amplitude, without significant fluctuations.

[0034] It can be understood that the timing control circuit 01 switching from outputting the frequency injection enable signal Fin-en to outputting the amplifier enable signal Amp-en means that: during the oscillation phase, the timing control circuit 01 outputs the frequency injection enable signal Fin-en, while during the steady-state phase, it stops outputting the frequency injection enable signal Fin-en and begins outputting the other amplifier enable signal Amp-en. In other words, the timing control circuit 01 outputs the frequency injection enable signal Fin-en and the amplifier enable signal Amp-en in a time-division manner at different time periods, so that the frequency injection enable signal Fin-en and the amplifier enable signal Amp-en are not effective simultaneously.

[0035] Optionally, the timing control circuit 01 can refer to any collection of circuits that rely on sequential logic or level timing to complete signal switching and stage control, including but not limited to: dedicated timing control circuits, general-purpose sequential logic circuits, combinational logic plus flip-flop circuits, dedicated timing controllers, timing units built from microcontroller units (MCUs) or logic gates, etc. The timing control circuit 01 described in the embodiments of this application can also be called a digital state machine.

[0036] In summary, this application provides a control circuit for a crystal oscillator. In this control circuit, the timing control circuit and the frequency sweep oscillation loop can cooperate to inject frequency sweep energy during the crystal oscillator's start-up phase, rapidly exciting the crystal oscillator to a stable target amplitude. Furthermore, the timing control circuit and the amplitude control module can cooperate to limit the oscillation amplitude through negative feedback in the crystal oscillator's steady-state state, i.e., after reaching the stable target amplitude, thus achieving steady-state gain attenuation. In this way, the overall circuit's power consumption can be effectively reduced.

[0037] Optionally, combined Figure 1 It can also be seen that the crystal oscillator 10 may include: an adjustable load capacitor, such as CN and CP. The timing control circuit 01 can also be used to adjust the capacitance value of the adjustable load capacitor based on the oscillation amplitude of the crystal oscillator 10, so that the capacitance value is positively correlated with the oscillation amplitude.

[0038] In other words, as described above, in this embodiment, the timing control circuit 01, in addition to outputting the frequency injection enable signal Fin-en and the amplifier enable signal Amp-en to cooperate with the frequency sweep oscillation loop 02 to achieve frequency sweep energy injection, and cooperating with the amplitude control module 03 to achieve steady-state gain attenuation, can also flexibly adjust the capacitance value of the adjustable load capacitor according to the oscillation amplitude of the crystal oscillator 10, i.e., the equivalent capacitance value described above. Thus, when the oscillation amplitude is small, a smaller equivalent capacitance value can be set to accelerate oscillation; and when the oscillation amplitude is large, a larger equivalent capacitance value can be set to reduce power consumption.

[0039] For example, the timing control circuit 01 can be used to set the capacitance value of the adjustable load capacitor to a first capacitance value upon power-up, and to switch the capacitance value of the adjustable load capacitor from the first capacitance value to a second capacitance value when the oscillation amplitude of the crystal oscillator 10 reaches the target amplitude. The second capacitance value is greater than the first capacitance value.

[0040] That is, in this embodiment, the timing control circuit 01 can set the capacitance value of the adjustable load capacitor to a lower first capacitance value, such as 0, at the initial power-on stage, i.e., during the oscillation start-up phase. This increases the negative resistance of the inverting amplifier INV0 and its gain, thereby further accelerating the start-up and allowing the oscillation amplitude to quickly oscillate from 0 to the target amplitude. This accelerates the output of a stable clock signal from the crystal oscillator 10, ensuring that the amplitude of the output signal from the crystal oscillator 10 via OUTN and OUTP can rapidly increase to the required amplitude in a short time. Furthermore, the timing control circuit 01 can reset the capacitance value of the adjustable load capacitor to a higher second capacitance value during the steady-state phase, i.e., during the steady-state phase. This second capacitance value can be the target value corresponding to the target amplitude, limiting the negative resistance of the inverting amplifier INV0 and reducing its gain, thereby further maintaining the crystal oscillator 10 in low-power operation. Figure 1 In this context, Dac-set is used to represent the capacitance value set by the timing control circuit 01.

[0041] Optionally, in this embodiment, the timing control circuit 01 can also be used to stop outputting the frequency injection enable signal Fin-en when the frequency of the sweep signal X matches the inherent frequency Fosc of the crystal, so as to instruct the sweep oscillation loop 02 to stop generating the sweep signal X. Furthermore, before the oscillation amplitude of the crystal oscillator 10 reaches the target amplitude, the output amplifier enable signal Amp-en is disabled to prevent the amplitude control module 03 from operating. This avoids the sweep oscillation loop 02 and the amplitude control module 03 from erroneously starting up when unnecessary, further ensuring low power consumption.

[0042] Optionally, in the embodiments of this application, the frequency injection enable signal Fin-en output by the timing control circuit 01 can refer to the frequency injection enable signal Fin-en with an effective output level, and the frequency injection de-en output by the timing control circuit 01 can refer to the frequency injection enable signal Fin-en with an invalid output level, or the frequency injection de-en output signal.

[0043] Similarly, the output amplifier enable signal Amp-en of the timing control circuit 01 can refer to the amplifier enable signal Amp-en with an effective output level, while the output amplifier disable signal Amp-en of the timing control circuit 01 can refer to the amplifier enable signal Amp-en with an invalid output level, or the output amplifier de-en signal.

[0044] Optionally, the valid level can be high relative to the invalid level. That is, the valid level can be high and the invalid level can be low. Of course, the valid level can also be low relative to the invalid level.

[0045] For example, with Figure 1 Taking the structure shown, where the effective level is high relative to the ineffective level, as an example, Figure 2 A schematic diagram of the operating timing waveforms of a control circuit 00 is shown. (Combined with...) Figure 2 It can be seen that: First, during the initial start-up phase after power-on, the timing control circuit 01 outputs a high-level frequency injection enable signal Fin-en, enabling Fin-en. Correspondingly, it controls the sweep frequency oscillation loop 02 to start operating and generates a sweep frequency signal X whose frequency decreases from high to low over time, which is output to the crystal oscillator 10, achieving frequency injection (Freq-inject). Furthermore, during this start-up phase, the timing control circuit 01 can also set a small first capacitance value, represented by an 8-bit binary 000000 (but not limited to this), to maximize the negative resistance of the inverting amplifier INV0 in the crystal oscillator 10, accelerating start-up. Based on this, when the frequency of the sweep frequency signal X matches the natural frequency Fosc of the crystal in the crystal oscillator 10, energy can be injected into the crystal oscillator 10, achieving sweep frequency energy injection. This increases the gain of the inverting amplifier INV0 (corresponding to...). Figure 2 The "Gain Boost" designation indicates a gain increase, which triggers the crystal oscillator 10 to quickly start oscillating to a stable target amplitude. Furthermore, during this Start-Up phase, the timing control circuit 01 can output a low-level amplifier enable signal (Amp-en), also known as an output amplifier enable signal (Amp-en), to prevent the amplitude control module 03 from malfunctioning. This also helps to reduce power consumption.

[0046] Next, after the Start-up phase ends and the steady-state phase begins, i.e., when the crystal oscillator 10 oscillates to the target amplitude and outputs a stable clock signal, the timing control circuit 01 can output a high-level amplifier enable signal Amp-en, i.e., Amp-en is enabled. Correspondingly, the amplitude control module 03 can be controlled to start working, thereby limiting the gain of the inverting amplifier INV0 through negative feedback to avoid unnecessary power consumption, thus achieving steady-state gain attenuation (corresponding to...). Figure 2 The purpose of the Gain Reduction indicator (indicating a decrease in gain) is to limit the oscillation amplitude of the crystal oscillator 10 (corresponding to...). Figure 2The Amplitude Control (indicated by amplitude control) reduces the loop power consumption of the crystal oscillator 10. Furthermore, during the Steady State phase, the timing control circuit 01 can also set a larger second capacitance value, denoted as 011011, to further limit the gain, achieving better steady-state gain attenuation and thus further reducing loop power consumption. Additionally, during this Steady State phase, the timing control circuit 01 can output a low-level frequency injection enable signal Fin-en, also known as the stop output frequency injection enable signal Fin-en, to instruct the sweep frequency oscillation loop 02 to stop generating the sweep frequency signal X, preventing the sweep frequency oscillation loop 02 from malfunctioning. This also helps to reduce power consumption.

[0047] Optionally, in the embodiments of this application, the upper limit of the frequency of the sweep signal X (that is, the maximum frequency or the highest frequency Fhi) can be greater than the inherent frequency Fosc of the crystal, and the lower limit of the frequency of the sweep signal X (that is, the minimum frequency or the lowest frequency Flo) can be less than the inherent frequency Fosc of the crystal.

[0048] For example, the upper frequency limit Fhi of the swept frequency signal X can be greater than twice the crystal's intrinsic frequency Fosc, and the lower frequency limit Flo of the swept frequency signal X can be less than half the crystal's intrinsic frequency Fosc. That is, Fhi > 2Fosc; Flo < 1 / 2Fosc.

[0049] This ensures reliable frequency sweep to the crystal's intrinsic frequency (Fosc) under different temperatures or process angles. Specifically, it guarantees that the frequency of the sweep signal X will always match the intrinsic frequency (Fosc) of the crystal in the crystal oscillator 10, reliably injecting sweep energy, accelerating oscillation, and reducing power consumption. Here, "different temperatures" refers to temperature variations encountered by the circuit in its actual operating environment. Temperature changes generally affect the characteristic parameters of the transistors in the circuit, thereby altering the output frequency, oscillation characteristics, etc. "Different process angles" refers to deviations during the fabrication process, such as photolithography and doping. These deviations also affect the transistor's characteristic parameters, thereby altering the output frequency, oscillation characteristics, etc.

[0050] For example, Figure 3 This diagram schematically illustrates the frequency versus time curves at four different temperatures or process angles, where the horizontal axis represents time t and the vertical axis represents frequency Freq. (Combined with...) Figure 3 As can be seen, by setting Fhi>2Fosc and Flo<1 / 2Fosc, it can be guaranteed that at any temperature or process angle, the crystal's intrinsic frequency Fosc can be between the upper frequency limit Fhi and the lower frequency limit Flo of the sweep frequency signal X, thus reliably realizing sweep frequency energy injection.

[0051] Optionally, in Figure 1 Based on this, further reference Figure 4 As can be seen, the swept-frequency oscillation loop 02 described in this application embodiment may include: a swept-frequency voltage-controlled oscillator 021 and its state control machine 022. The state control machine 022 is also called the state machine circuit of the swept-frequency voltage-controlled oscillator 021.

[0052] The sweep frequency voltage-controlled oscillator 021 can be used to receive the frequency injection enable signal Fin-en and generate a sweep frequency signal X and a sweep frequency control voltage Vx in response to the frequency injection enable signal Fin-en.

[0053] The state controller 022 can receive the frequency injection enable signal Fin-en, the sweep signal X, and the sweep control voltage Vx, and respond to the frequency injection enable signal Fin-en, the sweep signal X, and the sweep control voltage Vx to control the on / off state of the sweep voltage-controlled oscillator 021 and the crystal oscillator 10, so as to control the output state of the sweep signal X.

[0054] That is, the sweep frequency oscillation loop 02 can be divided into two parts: a sweep frequency voltage-controlled oscillator 021 that generates the sweep frequency signal X and a state control machine 022 that outputs the sweep frequency signal X, so that the sweep frequency signal X can be reliably output to the crystal oscillator 10 at the appropriate stage, i.e. the oscillation stage.

[0055] Optionally, in Figure 4 Based on this, further reference Figure 5 As can be seen, the sweep frequency voltage-controlled oscillator 021 may include: an oscillation switch 0211, a bias circuit 0212, a ring oscillator 0213, and a first filter and voltage regulation circuit 0214.

[0056] The oscillation switch 0211 can be used to receive the frequency injection enable signal Fin-en and control the switching on and off of the bias circuit 0212 and the ring oscillator 0213 in response to the frequency injection enable signal Fin-en.

[0057] For example, the oscillation switch 0211 can control the bias circuit 0212 and the ring oscillator 0213 to conduct when it receives a high-level frequency injection enable signal Fin-en, and can control the bias circuit 0212 and the ring oscillator 0213 to disconnect when it receives a low-level frequency injection enable signal Fin-en.

[0058] The bias circuit 0212 can be used to provide bias for the ring oscillator 0213 when it is turned on.

[0059] The ring oscillator 0213 can be used to operate under the control of the bias circuit 0212 to generate a sweep frequency signal X and a sweep frequency control voltage Vx.

[0060] The first filter and voltage regulator circuit 0214 is used to filter and regulate the sweep frequency control voltage Vx.

[0061] Accordingly, the oscillation switch 0211 can be connected to the control bias circuit 0212 and the ring oscillator 0213 respectively, and can also be connected to the timing control circuit 01. The bias circuit 0212, the ring oscillator 0213 and the first filter and voltage regulator circuit 0214 can be connected together.

[0062] Optionally, in Figure 5 Based on this, further reference Figure 6 As can be seen, the ring oscillator 0213 may include: a plurality of first inverters INV1 connected in series to form a loop. The bias circuit 0212 may include: a plurality of first bias pairs Bias1 connected one-to-one with the plurality of first inverters INV1, a second bias pair Bias2 connected to the first bias pairs, and a first bias resistor Rb1 and a second bias resistor Rb2. The oscillation switch section 0211 may include: a first switch T1 and a second switch T2. The first filter and voltage regulator circuit 0214 may include: a first resistor R1 and a first capacitor C1.

[0063] Both the first bias pair Bias1 and the second bias pair Bias2 may include a first type of transistor (e.g., a P-type transistor MP) connected to the power supply terminal VDD and a second type of transistor (e.g., an N-type transistor MN) connected to the pull-down terminal (e.g., ground GND). A first bias resistor Rb1 and a second bias resistor Rb2 may be connected in series between the power supply terminal VDD and the pull-down terminal GND. The series connection node A of the first bias resistor Rb1 and the second bias resistor Rb2 may be connected to the gate of the second type of transistor MN via a first resistor R1. A first capacitor C1 may be connected between the gate of the second type of transistor MN and the pull-down terminal GND. A first switch T1 may be connected between the first type of transistor MP and the second type of transistor MN included in the second bias pair Bias2, and a second switch T2 may be connected between the second bias resistor Rb2 and the pull-down terminal GND.

[0064] Among them, the signal output from multiple first inverters INV1 to the output terminal Fout via the loop can be the sweep frequency signal X, and the voltage of the series node A can be the sweep frequency control voltage Vx.

[0065] For example, refer to Figure 6The ring oscillator 0213 shown includes three first inverters INV1, labeled INV11, INV12, and INV13 in the figure. Correspondingly, the bias circuit 0212 may include three first bias pairs Bias1, labeled Bias11, Bias12, and Bias13, connected one-to-one with the three first inverters INV11, INV12, and INV13. Figure 6 In the figure, the first type of transistor can be a P-type transistor MP, and the second type of transistor can be an N-type transistor MN. The other embodiments described below are similar and will not be repeated. For distinction, the first type transistors included in the three first bias pairs Bis11 to Bis13 are also labeled as MP1, MP2, and MP3, respectively; the second type transistors included in the three first bias pairs Bis11 to Bis13 are labeled as MN1, MN2, and MN3, respectively; the first type transistor included in the second bias pair Bis2 is labeled as MP4; and the second type transistor included in the second bias pair Bis2 is labeled as MN4.

[0066] Thus, the swept-frequency voltage-controlled oscillator 021 can also be considered to include: ring oscillators INV11, INV12, and INV13; bias transistors MN1 to MN4 and MP1 to MP4; two bias resistors Rb1 and R2; two switches T1 and T2; and a filter and voltage regulation circuit formed by resistor R1 and capacitor C1. One end of bias resistor Rb1 is connected to the power supply terminal VDD, and the other end is connected to the series node A. One end of bias resistor Rb2 can be connected to the series node A, and the other end can be connected to ground GND via switch T1. In bias transistors MN1 to MN3, the gate of each transistor can be connected to node B, the source of each transistor can be connected to ground GND, and the drain of each transistor can be connected to the corresponding first inverter INV1. In bias transistors MP1 to MP3, the gate of each transistor can be connected to node C, the source of each transistor can be connected to the power supply terminal VDD, and the drain of each transistor can be connected to the corresponding first inverter INV1. The gate of bias transistor MN4 can be connected to node B, the source of bias transistor MN4 can be connected to ground GND, the drain of bias transistor MN4 can be connected to the drain of bias transistor MP4 via switch T2, the gate of bias transistor MP4 can be connected to node C, and the source of bias transistor MP4 can be connected to the power supply terminal VDD. Furthermore, the three first inverters INV11, INV12, and INV13 can be connected in series to form a loop, outputting the generated sweep frequency signal X through the output terminal Fout. For example, resistor R1 can be connected between node A and node B, and capacitor C1 can be connected between node B and ground GND. Of course, this is not limited to... Figure 6The structure shown.

[0067] by Figure 6 Taking the structure shown as an example, the working principle of the sweep frequency voltage-controlled oscillator 021 is explained as follows: First, switches T1 and T2 are turned off, which controls the bias circuit 0212 and the ring oscillator 0213 to conduct. At this time, node A can be charged to a higher voltage. After filtering by the filter and voltage regulation circuit including resistor R1 and capacitor C1, the voltage of node B can be controlled to bias the bias transistors MN1 to MN4. Then, the frequency injection enable signal Fin-en can be transmitted to switches T1 and T2 to control switches T1 and T2 to close. At the moment of closing, due to the presence of resistor R1 and capacitor C1, the voltage of node B can slowly decrease, and the voltage of node B can be determined by the voltage division of bias resistors Rb1 and R2. Generally, the resistance value of bias resistor Rb1 can be greater than the resistance value of bias resistor Rb2, such as 3 or 4 times the resistance value of bias resistor Rb2, so that the voltage of node B can be reliably reduced. The voltage drop at node B increases the impedance of bias transistors MN1 to MN4, causing the oscillation frequency of the ring oscillator to gradually decrease from the high frequency Fhi to the low frequency Flo, generating the required sweep signal X.

[0068] Optionally, in Figure 4 Based on this, further reference Figure 7 It can be seen that the state control unit 022 may include: a second filter and voltage regulator circuit 0221, an input buffer unit 0222, a logic processing unit 0223, and a switch control inverting unit 0224.

[0069] The second filter and voltage regulator circuit 0221 can be used to receive the sweep frequency control voltage Vx (i.e., Figure 6 The voltage at point A is shown, and the sweep frequency control voltage Vx is filtered and regulated.

[0070] The input buffer 0222 can be used to receive the sweep frequency control voltage Vx output by the second filter and voltage regulator circuit 0221, and output a reference signal Vref based on the received sweep frequency control voltage Vx.

[0071] The logic processing unit 0223 can receive the sweep frequency signal X and the reference signal Vref, and perform logic processing on the sweep frequency signal X and the reference signal Vref to output the switch control signal K1.

[0072] The switch control inverter 0224 can receive the frequency injection enable signal Fin-en, the switch control signal K1, and the reference signal Vref. In response to the switch control signal K1 and the reference signal Vref, it controls the output voltage of the switch control inverter 0224. In response to the frequency injection enable signal Fin-en, it controls the on / off state of the sweep frequency voltage-controlled oscillator 021 and the crystal oscillator 10 to control the output state of the sweep frequency signal X.

[0073] Accordingly, it can be seen that the second filter and voltage regulator circuit 0221 can be respectively connected with... Figure 6 The circuit shown is connected to node A and input buffer 0222. Input buffer 0222 can be connected to logic processing unit 0223 and switch control inverter 0224 respectively. Switch control inverter 0224 can be connected to timing control circuit 01 and crystal oscillator 10 respectively.

[0074] Optionally, in Figure 7 Based on this, further reference Figure 8 As can be seen, the second filter and voltage regulator circuit 0221 may include: a second resistor R2 and a second capacitor C2. The input buffer section 0222 may include: a buffer (abbreviated as Buf). The logic processing section 0223 may include: an AND gate circuit. The switch control inverting section 0224 may include: multiple second inverters INV2 connected in series, as well as a third switch T3 and a fourth switch T4.

[0075] The first end of the second resistor R2 can be connected to node A of the sweep frequency control voltage Vx output in the sweep frequency voltage-controlled oscillator 021. The second end of the second resistor R2 and the first end of the second capacitor C2 can both be connected to the input of the buffer Buf. The second end of the second capacitor C2 can be connected to the pull-down terminal (e.g., GND). The output of the buffer Buf can be connected to the first input of the AND gate circuit and the control terminal of the other second inverters INV2 except for the last second inverter INV2. The second input of the AND gate circuit can be connected to the output terminal Fout of the sweep frequency voltage-controlled oscillator 021 that outputs the sweep signal X. The output of the AND gate circuit can be connected to the input of the first second inverter INV2. The outputs of the last two series-connected second inverters INV2 (marked as VP and VN in the figure) can be connected to the crystal oscillator 10 via the third switch T3 and the fourth switch T4, respectively.

[0076] The voltage output from the output terminal of the second inverter INV2, which is connected in series with the last two inverters, can be the output voltage of the switch-controlled inverter 0224.

[0077] For example, such as Figure 8As shown, the switch control inverter 0224 includes three second inverters INV2 connected in series, labeled INV21, INV22, and INV23 respectively. Figure 8 The output of the buffer Buf is designated as node P, and the output of the AND gate is designated as node N. Thus, node P can be considered to be connected to the first input of the AND gate and the control terminals of the second inverters INV21 and INV22, respectively. The outputs of the second inverters INV22 and INV23 can be considered to correspond to VP and VN, respectively. The AND logic processing performed by the AND gate can mean that the output is only logic high 1 when all input signals are simultaneously logic high (1); the output is logic low 0 as long as one or more input signals are logic low (0). Of course, this is not limited to... Figure 8 The structure shown.

[0078] by Figure 8 Taking the structure shown as an example, the working principle of the state control machine 022 is explained as follows: First, it can be seen that the voltage of node A can slowly decrease over time, similar to the sweep signal X. Second, during the start-up phase, the frequency injection enable signal Fin-en can control the closing of switches T3 and T4, meaning that Fin-en can be enabled and opened first after power-on. At this time, the initial level of node A is high level 1. Correspondingly, the level of node P can also be controlled to be high level 1. Thus, the sweep signal X output by the sweep voltage-controlled oscillator 021 via Fout can be transmitted to the crystal oscillator 10 through the AND gate and the second inverters INV2 to INV3. Furthermore, as the voltage of node A continuously decreases, the sweep injection effect can be achieved, that is, sweep energy injection can be realized. When the voltage of node A decreases below the threshold voltage of the buffer Buf, the buffer Buf can output 0 at the output terminal, that is, the level of node P can become low level 0. Correspondingly, after AND logic processing by the AND gate, it can also output 0, that is, the level of node N can also become low level 0. In addition, the second inverters INV21 and INV22 can also be controlled to stop working. At this time, the outputs of VP and VN can be in a floating state, meaning VP and VN can be left unconnected. Correspondingly, the sweep frequency voltage-controlled oscillator loop 02 can be disconnected from the core circuit of the crystal oscillator 10. Furthermore, under the control of the frequency injection enable signal Fin-en, switches T3 and T4 can also be turned off, thereby completely disconnecting the sweep frequency voltage-controlled oscillator 021 from the crystal oscillator 10, so that the sweep frequency signal X generated by the sweep frequency voltage-controlled oscillator 021 is no longer transmitted to the crystal oscillator 10.

[0079] It can be understood that the threshold voltage of the buffer Buf can refer to the critical input voltage value that causes the output of the buffer Buf to switch. When the input voltage passes through this critical value from high to low or from low to high, the output of the buffer Buf will switch from one logic state to another. For example, from high level 1 to low level 0. Figure 8 The diagram also schematically shows the voltage waveform at each node in nodes A, P, and N, with the horizontal axis representing time t and the vertical axis representing voltage.

[0080] Optionally, combined Figure 1 It can also be seen that the crystal oscillator 10 described in the embodiments of this application may further include: an inverting amplifier INV0. Correspondingly, the amplitude control module 03 may be used to reduce the negative resistance of the inverting amplifier INV0 through negative feedback in response to the amplifier enable signal Amp-en, so as to limit the oscillation amplitude of the crystal oscillator 10.

[0081] Based on this, Figure 9 A schematic diagram of an amplitude control module 03 is shown. (Reference) Figure 9 It can be seen that the amplitude control module 03 may include: a control switch unit 031 and an amplifier control unit 032.

[0082] The control switch unit 031 can be used to receive the amplifier enable signal Amp-en and control the switching between the amplifier control unit 032 and the crystal oscillator 10 in response to the amplifier enable signal Amp-en.

[0083] For example, when the control switch unit 031 receives a high-level amplifier enable signal Amp-en, it can control the amplifier control unit 032 to turn on the crystal oscillator 10, and when it receives a low-level amplifier enable signal Amp-en, it can control the amplifier control unit 032 to disconnect from the crystal oscillator 10.

[0084] The amplifier control unit 032 can be used to reduce the bias current of the inverting amplifier INV0 through negative feedback when the crystal oscillator 10 is turned on, so as to limit the gain of the inverting amplifier INV0 and thereby reduce the negative resistance of the inverting amplifier INV0.

[0085] Optionally, in Figure 9 On this basis, Figure 10 A schematic diagram of a circuit structure including an amplitude control module 03 and a crystal oscillator 10 is shown. (Reference) Figure 10 It can be seen that the control switch unit 031 may include: a fifth switch T5. The amplifier control unit 032 may include: a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a third resistor R3, a fourth resistor R4, a third bias pair Bias3, and a fourth bias pair Bias4.

[0086] Both the third bias pair Bias3 and the fourth bias pair Bias4 may include a first type of transistor (e.g., MP) and a second type of transistor (e.g., MN) connected between the power supply terminal VDD and the pull-down terminal (e.g., GND).

[0087] The first terminal of the third capacitor C3 can be connected to the inverting amplifier INV0. The second terminal of the third capacitor C3 can be connected to the first terminal of the third resistor R3 via the fifth switch T5. The first terminal of the third resistor R3 can also be connected to the gate of the second type transistor included in the third bias pair Bias3. The second terminal of the third resistor R3, the first terminal of the fourth resistor R4, and the first terminal of the fourth capacitor C4 can all be connected to the connection node of the first type transistor and the second type transistor included in the third bias pair Bias3. The second terminal of the fourth resistor R4 and the first terminal of the fifth capacitor C5 can both be connected to the gate of the second type transistor included in the fourth bias pair Bias4. The second terminals of the fourth capacitor C4 and the fifth capacitor C5 can also both be connected to the pull-down terminal GND.

[0088] For distinction, the first type transistors MP included in the third bias pair Bias3 and the fourth bias pair Bias4 are labeled MP01 and MP02, respectively, and the second type transistors MN included in the third bias pair Bias3 and the fourth bias pair Bias4 are labeled MN01 and MN02, respectively. Specifically, the gate of transistor MP01 can receive the bias voltage VP1, the source of transistor MP01 can be connected to the power supply terminal VDD, the drain of transistor MP01 can be connected to the drain of transistor MN01, the gate of transistor MN01 can be connected to the fifth switch T5, and the source of transistor MN01 can be connected to ground GND. The gate of transistor MP02 can be connected to the gate of transistor MP03 in the crystal oscillator 10, the source of transistor MP02 can be connected to the power supply terminal VDD, the drain of transistor MP02 can be connected to the drain of transistor MN02, the gate of transistor MN02 can be connected to the second terminal of the fourth resistor R4 and the first terminal of the fifth capacitor C5, and the source of transistor MN02 can be connected to ground GND. Furthermore, the first terminal of the third resistor R3 can be connected to the connection node of transistors MP01 and MN01. The second terminal of the third resistor R3, the first terminal of the fourth resistor R4, and the first terminal of the fourth capacitor C4 can all be connected to the connection node of transistors MP01 and MN01.

[0089] also, Figure 10In this context, transistors MP03 and MN03 refer to the transistors included in the inverting amplifier INV0 within crystal oscillator 10. MN03 provides loop gain and a 180-degree phase shift, while MP03 provides current bias for MN03. Resistor Rb01 is the bias resistor in crystal oscillator 10 described earlier, providing bias for the inverting amplifier INV0. Capacitors CN and CP are the adjustable load capacitors in crystal oscillator 10 described earlier, with adjustable values. XN and XP can be external crystal oscillator access points, which can be connected via resistor R. Figure 1 The quartz crystal XTAL is shown. Transistors MP04 and MN04, MP05 and MN05 connected between the power supply terminal VDD and the ground terminal GND can be normally off transistors, providing electrostatic discharge (ESD) protection to ensure reliable operation of the crystal oscillator 10. For example, the gates of MP04 and MP05 can both receive a high level 1 to reliably turn off under the control of this high level 1; the gates of MN04 and MN05 can both receive a low level 0 to reliably turn off under the control of this low level 0. Additionally, capacitor C6, resistor R5, and transistors MP06 and MN06 connected between the power supply terminal VDD and the ground terminal GND can form an alternating current buffer (AC-Buf), which can be used to amplify and buffer the AC voltage output of the inverting amplifier INV0, such as amplifying the low-swing oscillation signal of OUTN to a swing from 0 to VDD. Transistors MP07 and MN07, connected between the power supply terminal VDD and the ground terminal GND, can form another amplification buffer to further amplify the voltage output of the AC buffer. This improves the output drive capability of the crystal oscillator 10. That is, in this embodiment, Figure 10 The switch T5, capacitors C3, C4, and C5, resistors R3 and R4, and MP01, MP02, MN01, and MN02 shown can form a negative feedback loop as amplitude control module 03. Of course, it is not limited to this. Figure 10 The structure shown.

[0090] by Figure 10 Taking the structure shown as an example, the working principle of the amplitude control module 03 is explained as follows: Before the oscillation amplitude of the crystal oscillator 10 reaches the target amplitude, that is, during the oscillation start-up stage, the timing control circuit 01 can output a low-level amplifier enable signal Amp-en to control switch T5 to turn off. After the oscillation amplitude of the crystal oscillator 10 reaches the target amplitude, that is, during the steady-state stage, the timing control circuit 01 can output a high-level amplifier enable signal Amp-en to control switch T5 to close, thereby establishing a connection between the negative feedback loop and the oscillation loop formed by the crystal oscillator 10. Under the negative feedback mechanism, the bias current provided by transistor MP03 in the inverting amplifier INV0 can be reduced, thereby limiting the gain of the inverting amplifier INV0 and reducing the negative resistance of the inverting amplifier INV0, preventing the oscillation swing of the crystal oscillator 10 from being too large, and thus preventing the overall power consumption of the circuit from increasing, thereby reducing power consumption.

[0091] Optionally, in conjunction with the above embodiments, Figure 11 A schematic diagram of the circuit structure of a crystal oscillator and its control circuit is also shown. Figure 6 The structure shown corresponds to Figure 11 The sweep frequency voltage-controlled oscillator 021 in the sweep frequency oscillation loop 02 shown is indicated by simplified symbols. Figure 8 The structure shown corresponds to Figure 11 The state control machine 022 in the frequency sweep oscillation loop 02 shown is... Figure 11 This is only shown schematically. Figure 8 For a complete structural reference of some components in the state control machine 022, please refer to the following. Figure 8 As shown. Figure 10 The structure shown corresponds to Figure 11 The amplitude control module 03 shown is... Figure 11 This is only shown schematically. Figure 10 For reference, see the complete structure of the amplifier control unit 032 in the amplitude control module 03. Figure 10 As shown in the above embodiments, this application provides a low-power circuit capable of rapid oscillation. By controlling frequency sweep energy injection, steady-state gain attenuation, and load capacitance, the oscillation time of a crystal oscillator such as a DCXO can be effectively reduced, i.e., the oscillation is accelerated, and the oscillation amplitude is stabilized after oscillation is completed, ultimately achieving a significant reduction in power consumption.

[0092] In summary, this application provides a control circuit for a crystal oscillator. In this control circuit, the timing control circuit and the frequency sweep oscillation loop can cooperate to inject frequency sweep energy during the crystal oscillator's start-up phase, rapidly exciting the crystal oscillator to a stable target amplitude. Furthermore, the timing control circuit and the amplitude control module can cooperate to limit the oscillation amplitude through negative feedback in the crystal oscillator's steady-state state, i.e., after reaching the stable target amplitude, thus achieving steady-state gain attenuation. In this way, the overall circuit's power consumption can be effectively reduced.

[0093] This application also provides a crystal oscillator circuit. For example... Figure 12 As shown, the crystal oscillator circuit includes: a crystal oscillator 10, and a control circuit 00 as described above.

[0094] The control circuit 00 can be connected to the crystal oscillator 10 to inject sweep frequency energy and attenuate steady-state gain into the crystal oscillator 10, thereby effectively reducing the overall circuit power consumption.

[0095] It is understandable that, since the crystal oscillator circuit has essentially the same technical effect as the control circuit of the crystal oscillator described above, the technical effect of the crystal oscillator circuit will not be described again here for the sake of brevity.

[0096] This application also provides an electronic device. For example... Figure 13 As shown, the electronic device includes: a load 100, and a crystal oscillator circuit 000 as described above.

[0097] The crystal oscillator circuit 000 can be connected to the load 100 to generate a clock signal and output it to the load 100 to drive the load 10 to work. Optionally, the load 10 can be, for example, a frequency and phase detector in a phase-locked loop.

[0098] It is understandable that, since the electronic device has essentially the same technical effect as the control circuit of the crystal oscillator described above, for the sake of brevity, the technical effect of the electronic device will not be described again here.

[0099] It is understood that the terminology used in the embodiments of this application is for explaining the embodiments of this application and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0100] For example, the use of words like "first," "second," "third," and similar terms does not indicate any order, quantity, or importance, but is merely used to distinguish different components. Similarly, words like "a" or "one" do not indicate a quantity limitation, but rather the presence of at least one. Words like "include" or "contain" mean that the element or object preceding "includes" covers the element or object listed after "includes" or "contains," and does not exclude other elements or objects. Words like "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Or" indicates that three relationships can exist; for example, A or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects have an "or" relationship.

[0101] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A control circuit for a crystal oscillator, characterized in that, The crystal oscillator is used to oscillate to generate a clock signal, and to stably output the clock signal when the oscillation amplitude reaches the target amplitude; the control circuit includes: The timing control circuit is used to output a frequency injection enable signal when the power is on, and to switch to an output amplifier enable signal when the oscillation amplitude of the crystal oscillator reaches the target amplitude. A frequency sweep oscillation loop is used to receive a frequency injection enable signal and, in response to the frequency injection enable signal, generate a frequency sweep signal whose frequency gradually decreases over time and output it to the crystal oscillator. When the frequency of the frequency sweep signal matches the natural frequency of the crystal in the crystal oscillator, energy is injected into the crystal oscillator to excite the crystal oscillator to quickly start oscillating to the target amplitude. An amplitude control module is used to receive an amplifier enable signal and, in response to the amplifier enable signal, limit the oscillation amplitude of the crystal oscillator through negative feedback to reduce the loop power consumption of the crystal oscillator.

2. The control circuit according to claim 1, characterized in that, The upper limit of the frequency of the sweep signal is greater than the inherent frequency of the crystal, and the lower limit of the frequency of the sweep signal is less than the inherent frequency of the crystal.

3. The control circuit according to claim 2, characterized in that, The upper limit of the frequency of the sweep signal is greater than twice the inherent frequency of the crystal, and the lower limit of the frequency of the sweep signal is less than half the inherent frequency of the crystal.

4. The control circuit according to any one of claims 1 to 3, characterized in that, The crystal oscillator further includes: an adjustable load capacitor; The timing control circuit is also used to adjust the capacitance value of the adjustable load capacitor based on the oscillation amplitude of the crystal oscillator, so that the capacitance value is positively correlated with the oscillation amplitude.

5. The control circuit according to claim 4, characterized in that, The timing control circuit is used to set the capacitance value of the adjustable load capacitor to a first capacitance value when the power is on, and to set the capacitance value of the adjustable load capacitor to a second capacitance value when the oscillation amplitude of the crystal oscillator reaches the target amplitude. The second capacitance value is greater than the first capacitance value.

6. The control circuit according to any one of claims 1 to 3, characterized in that, The timing control circuit is further configured to stop outputting the frequency injection enable signal when the frequency of the sweep signal matches the inherent frequency of the crystal, so as to instruct the sweep oscillation loop to stop generating the sweep signal. Furthermore, before the oscillation amplitude of the crystal oscillator reaches the target amplitude, the amplifier enable signal is prohibited from being output to disable the amplitude control module.

7. The control circuit according to any one of claims 1 to 3, characterized in that, The frequency sweep oscillation loop includes: a frequency sweep voltage-controlled oscillator and its state control unit; The frequency sweep voltage-controlled oscillator is used to receive the frequency injection enable signal and generate the frequency sweep signal and the frequency sweep control voltage in response to the frequency injection enable signal. The state control unit is used to receive the frequency injection enable signal, the frequency sweep signal, and the frequency sweep control voltage, and in response to the frequency injection enable signal, the frequency sweep signal, and the frequency sweep control voltage, control the on / off state of the frequency sweep voltage-controlled oscillator and the crystal oscillator to control the output state of the frequency sweep signal.

8. The control circuit according to claim 7, characterized in that, The sweep frequency voltage-controlled oscillator includes: an oscillation switch, a bias circuit, a ring oscillator, and a first filter and voltage regulation circuit. The oscillation switch is used to receive the frequency injection enable signal and control the on / off state of the bias circuit and the ring oscillator in response to the frequency injection enable signal. The bias circuit is used to provide bias to the ring oscillator when it is turned on. The ring oscillator is configured to operate under the control of the bias circuit to generate the sweep frequency signal and the sweep frequency control voltage. The first filtering and voltage regulation circuit is used to filter and regulate the frequency sweep control voltage.

9. The control circuit according to claim 7, characterized in that, The state control unit includes: a second filter and voltage regulator circuit, an input buffer, a logic processing unit, and a switch control inverting unit; The second filtering and voltage regulation circuit is used to receive the sweep frequency control voltage and to filter and regulate the sweep frequency control voltage. The input buffer is used to receive the sweep frequency control voltage output by the second filter and voltage regulator circuit, and output a reference signal based on the received sweep frequency control voltage. The logic processing unit is used to receive the sweep signal and the reference signal, and to perform logic processing on the sweep signal and the reference signal to output a switch control signal; The switch control inverting section is used to receive the frequency injection enable signal, the switch control signal, and the reference signal, and in response to the switch control signal and the reference signal, control the output voltage of the switch control inverting section, and in response to the frequency injection enable signal, control the on / off state of the sweep frequency voltage-controlled oscillator and the crystal oscillator, so as to control the output state of the sweep frequency signal.

10. The control circuit according to any one of claims 1 to 3, characterized in that, The crystal oscillator further includes: an inverting amplifier; The amplitude control module is used to reduce the negative resistance of the inverting amplifier through negative feedback in response to the amplifier enable signal, so as to limit the oscillation amplitude of the crystal oscillator.

11. The control circuit according to claim 10, characterized in that, The amplitude control module includes: a control switch section and an amplifier control section; The control switch is used to receive the amplifier enable signal and control the switching between the amplifier control unit and the crystal oscillator in response to the amplifier enable signal. The amplifier control unit is configured to reduce the bias current of the inverting amplifier through negative feedback when the crystal oscillator is turned on, thereby limiting the gain of the inverting amplifier and reducing the negative resistance of the inverting amplifier.

12. A crystal oscillator circuit, characterized in that, The crystal oscillation circuit includes: a crystal oscillator, and a control circuit as described in any one of claims 1 to 11.

13. An electronic device, characterized in that, The electronic device includes: a load, and a crystal oscillator circuit as described in claim 12.

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