Amplifier circuit, radio frequency front-end module and electronic device

Abstract

The application relates to the technical field of integrated circuit design, and discloses an amplifier circuit, an RF front-end module and electronic equipment. In the amplifier circuit: a main transconductance unit is connected with an input matching module, an adjustable bias module, a transistor unit and a source degeneration unit; the input matching module is used for realizing input matching; the adjustable bias module is used for outputting adjustable first and second bias voltages; an auxiliary transconductance unit is connected with the input matching module, the adjustable bias module, the main transconductance unit and the source degeneration unit; the first and second bias voltages can be dynamically adjusted, so that the proportional relationship between the transconductance of the auxiliary transconductance unit and the transconductance of the main transconductance unit is constant; the transistor unit is connected with an output matching module; the source degeneration unit is used for introducing current negative feedback; and the output matching module is used for realizing output matching. The application can keep the linearization offset relationship between the main transconductance unit and the auxiliary transconductance unit stable under different working conditions.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, specifically to amplifier circuits, radio frequency front-end modules, and electronic devices. Background Technology

[0002] One method for auxiliary transconductance cancellation is used to improve amplifier linearity. This method typically uses an auxiliary transistor to generate a third-order transconductance component opposite to that of the main amplifier transistor, thereby reducing the overall third-order nonlinearity. However, the cancellation conditions of this type of scheme are very sensitive to the operating point of the main amplifier transistor / auxiliary transistor, device size, inversion region, source degradation impedance, temperature, and power supply. Post-mass production PVT (Process, Voltage, Temperature) discrepancies can cause instability in the linearization cancellation relationship between the main amplifier transistor (main transconductance unit) and the auxiliary transistor (auxiliary transconductance unit), resulting in drift of the optimal IIP3 (Input Third Order Intercept Point). Summary of the Invention

[0003] This invention provides an amplifier circuit, an RF front-end module, and an electronic device to solve the problem of how to keep the linearization cancellation relationship between the main transconductance unit and the auxiliary transconductance unit stable under different PVT, frequency bands, and gain modes.

[0004] In a first aspect, the present invention provides an amplifier circuit, comprising: an input matching module, an adjustable bias module, an amplification module, and an output matching module; the amplification module is used to amplify signals and includes a main transconductance unit, an auxiliary transconductance unit, a transistor unit, and a source degradation unit; The control terminal of the main transconductance unit is connected to the first output terminal of the input matching module and the first output terminal of the adjustable bias module, respectively. The first terminal of the main transconductance unit is connected to the first terminal of the transistor unit, and the second terminal of the main transconductance unit is connected to the first terminal of the source degradation unit. The input terminal of the input matching module is used to input the signal to be processed. The input matching module is used to realize input matching. The adjustable bias module is used to output the first bias voltage and the second bias voltage. The control terminal of the auxiliary transconductance unit is connected to the second output terminal of the input matching module and the second output terminal of the adjustable bias module, respectively. The first terminal of the auxiliary transconductance unit is connected to the first terminal of the main transconductance unit, and the second terminal of the auxiliary transconductance unit is connected to the second terminal of the source degradation unit. The first bias voltage and the second bias voltage can be dynamically adjusted so that the ratio between the transconductance of the auxiliary transconductance unit and the transconductance of the main transconductance unit is constant. The control terminal of the transistor unit is used to connect the control voltage, and the second terminal of the transistor unit is connected to the first terminal of the output matching module. The third terminal of the source degradation unit is grounded, and the source degradation unit is used to introduce current negative feedback; The second terminal of the output matching module is used to connect to the working voltage, the output terminal of the output matching module is used to output the amplified signal, and the output matching module is used to achieve output matching.

[0005] In one optional implementation, the adjustable bias module forms a constant transconductance reference by outputting an adjustable first bias voltage and a second bias voltage, such that the transconductance of the main transconductance unit and the transconductance of the auxiliary transconductance unit satisfy the following relationship: gm1≈gm_ref; gm2≈A×gm_ref; gm_total = gm1 + B × gm2; Wherein, gm1 is the transconductance of the main transconductance unit, gm2 is the transconductance of the auxiliary transconductance unit, gm_ref is the constant transconductance reference, A is the auxiliary transconductance scaling factor, B is the weighting factor, and gm_total is the total transconductance, which is set to a constant value.

[0006] In one optional implementation, the adjustable bias module includes an adjustable transconductance current source, a current mirror unit, a first voltage generation unit, and a second voltage generation unit. The power supply terminal of the adjustable transconducting current source is connected to the power supply terminal of the current mirror unit and is used to input the working voltage. The current mirror terminal of the adjustable transconducting current source is connected to the current mirror terminal of the current mirror unit. The bias terminal of the adjustable transconducting current source is connected to the bias terminal of the current mirror unit. The first output terminal of the current mirror unit is connected to the input terminal of the first voltage generation unit, and the second output terminal of the current mirror unit is connected to the input terminal of the second voltage generation unit. The output terminal of the first voltage generation unit is connected to the control terminal of the main transconductance unit and the first output terminal of the input matching module, respectively. The output of the second voltage generation unit is connected to the control terminal of the auxiliary transconductance unit and the second output of the input matching module, respectively.

[0007] In one alternative implementation, the adjustable transconductance current source includes a first transistor, a second transistor, a first transistor unit, a second transistor unit, and a resistor unit. The first terminal of the first transistor is connected to the first terminal of the second transistor and the power supply terminal of the current mirror unit and is used to input the working voltage. The control terminal of the first transistor is connected to the control terminal of the second transistor, the second terminal of the first transistor, the first terminal of the first transistor unit, and the current mirror terminal of the current mirror unit. The second terminal of the second transistor is connected to the control terminal of the first transistor unit, the control terminal of the second transistor unit, the first terminal of the second transistor unit, and the bias terminal of the current mirror unit, respectively. The second terminal of the first transistor unit is connected to the first terminal of the resistor unit; The second terminal of the second transistor unit is grounded; The second terminal of the resistor sub-unit is grounded; The equivalent on-resistance of the second transistor unit and / or the resistance of the resistor subunit are adjustable.

[0008] In one alternative implementation, the resistor subunit includes several parallel sub-resistors, and a first controllable switch is connected in series on the circuit branch where each sub-resistor is located.

[0009] In one alternative implementation, the second transistor unit includes a plurality of first sub-transistors connected in parallel, and a second controllable switch is connected in series on the branch where the first or second terminal of each first sub-transistor is located.

[0010] In one alternative implementation, the current mirror unit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first terminal of the third transistor is connected to the first terminal of the fourth transistor and the power supply terminal of the adjustable transconducting current source and is used to apply the working voltage. The control terminal of the third transistor is connected to the control terminal of the fourth transistor and the current mirror terminal of the adjustable transconducting current source. The second terminal of the third transistor is connected to the first terminal of the fifth transistor. The second terminal of the fourth transistor is connected to the first terminal of the sixth transistor; The control terminal of the fifth transistor is connected to the control terminal of the sixth transistor and the bias terminal of the adjustable transconductance current source, respectively, and the second terminal of the fifth transistor is connected to the input terminal of the first voltage generation unit. The second terminal of the sixth transistor is connected to the input terminal of the second voltage generation unit.

[0011] In one alternative implementation, the first voltage generation unit includes a seventh transistor and an eighth transistor; The control terminal of the seventh transistor is connected to the first terminal of the seventh transistor, the control terminal of the eighth transistor, the first output terminal of the current mirror unit, the control terminal of the main transconductance unit, and the first output terminal of the input matching module, respectively. The second terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the second terminal of the eighth transistor, respectively, and grounded. The second voltage generation unit includes a ninth transistor and a tenth transistor; The control terminal of the ninth transistor is connected to the first terminal of the ninth transistor, the control terminal of the tenth transistor, the second output terminal of the current mirror unit, the control terminal of the auxiliary transconductance unit, and the second output terminal of the input matching module, respectively. The second terminal of the ninth transistor is connected to the first terminal of the tenth transistor and the second terminal of the tenth transistor, respectively, and grounded.

[0012] In one alternative implementation, the main transconductance unit includes several main transistors connected in parallel, and a third controllable switch is connected in series on the branch where the first or second end of each main transistor is located.

[0013] In one alternative implementation, the auxiliary transconductance unit includes several auxiliary transistors connected in parallel, and a fourth controllable switch is connected in series on the branch where the first or second terminal of each auxiliary transistor is located.

[0014] In one alternative implementation, the source degradation unit includes a first inductor and a second inductor; The first end of the first inductor is connected to the first end of the second inductor and the first end of the main transconducting unit, respectively; the second end of the first inductor is connected to the second end of the auxiliary transconducting unit. The second terminal of the second inductor is grounded.

[0015] In a second aspect, the present invention provides a radio frequency front-end module, including: an amplifier circuit according to the first aspect above or any corresponding embodiment thereof.

[0016] Thirdly, the present invention provides an electronic device comprising: a radio frequency front-end module according to the second aspect above or any corresponding embodiment thereof.

[0017] The technical solution provided by this invention has at least the following beneficial effects: The basic structure of a low-noise amplifier is constructed by connecting the control terminal of the main transconductance unit to the first output terminal of the input matching module and the first output terminal of the adjustable bias module, respectively; connecting the first terminal of the main transconductance unit to the first terminal of the transistor unit; connecting the second terminal of the main transconductance unit to the first terminal of the source degradation unit; grounding the third terminal of the source degradation unit; and connecting the second terminal of the transistor unit to the first terminal of the output matching module. Based on this, the basic structure of a low-noise amplifier is constructed by connecting the control terminal of the auxiliary transconductance unit to the second output terminal of the input matching module and the second output terminal of the adjustable bias module, respectively; and connecting the first terminal of the auxiliary transconductance unit to the main transconductance unit. The first end of the main transconductance unit and the second end of the auxiliary transconductance unit are connected to the second end of the source degradation unit, so that the transconductance of the main transconductance unit can be canceled by the auxiliary transconductance unit. At the same time, the first bias voltage and the second bias voltage are output by the adjustable bias module. Based on the dynamic adjustment of the first bias voltage and the second bias voltage, the ratio between the transconductance of the auxiliary transconductance unit and the transconductance of the main transconductance unit is kept constant. This allows the linear cancellation relationship between the main transconductance unit and the auxiliary transconductance unit to remain stable under different PVT, frequency bands and gain modes, effectively suppressing the drift of the optimal IIP3 point and exhibiting high linearity. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a structural block diagram of an amplifier circuit according to an embodiment of the present invention; Figure 2 This is a partial circuit schematic diagram of an amplifier circuit according to an embodiment of the present invention; Figure 3 This is a structural block diagram of an adjustable bias module according to an embodiment of the present invention; Figure 4 This is a first partial circuit schematic diagram of an adjustable bias module according to an embodiment of the present invention; Figure 5 This is a circuit schematic diagram of a resistor subunit according to an embodiment of the present invention; Figure 6 This is a circuit schematic diagram of the second transistor unit according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the second partial circuit of the adjustable bias module according to an embodiment of the present invention; Figure 8 This is a circuit schematic diagram of the main transconductor unit according to an embodiment of the present invention; Figure 9 This is a circuit schematic diagram of an auxiliary transconductance unit according to an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0022] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0023] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0024] In related technologies, common methods to improve the linearity of low-noise amplifiers include input attenuation, source negative feedback, increasing bias current, and switching gain levels. However, when using input attenuation, the useful signal is also attenuated, leading to a deterioration in the noise figure. When using source negative feedback, strong source degradation causes a decrease in gain, affecting input noise matching. Increasing bias current leads to increased power consumption, making it unsuitable for multi-level low-power receivers. When using gain level switching, simple gain switching cannot maintain a stable trade-off between noise, matching, and linearity. While there is a method using auxiliary transistors to cancel transconductance nonlinearity, the cancellation point of this method drifts with process technology, power supply, temperature, and frequency band. This invention provides an amplifier circuit that provides a first bias voltage and a second bias voltage to the main transconductance unit and the auxiliary transconductance unit respectively through an adjustable bias module. Based on the dynamic adjustment of the first bias voltage and the second bias voltage, the ratio between the transconductance of the auxiliary transconductance unit and the transconductance of the main transconductance unit is kept constant. This enables the linearization cancellation relationship between the main transconductance unit and the auxiliary transconductance unit to remain stable under different PVT, frequency bands and gain modes, effectively suppressing the drift of the optimal IIP3 point.

[0025] This embodiment provides an amplifier circuit, such as Figure 1 and Figure 2 It includes: an input matching module, an adjustable bias module, an amplification module and an output matching module; the amplification module is used to amplify the signal and includes a main transconductance unit M1A, an auxiliary transconductance unit M1B, a transistor unit M1C and a source degradation unit; The control terminal of the main transconductance unit M1A is connected to the first output terminal of the input matching module and the first output terminal of the adjustable bias module, respectively. The first terminal of the main transconductance unit M1A is connected to the first terminal of the transistor unit M1C. The second terminal of the main transconductance unit M1A is connected to the first terminal of the source degradation unit. The input terminal RFIN of the input matching module is used to input the signal to be processed. The input matching module is used to realize input matching. The adjustable bias module is used to output the first bias voltage Vb1 and the second bias voltage Vb2. The control terminal of the auxiliary transconductance unit M1B is connected to the second output terminal of the input matching module and the second output terminal of the adjustable bias module, respectively. The first terminal of the auxiliary transconductance unit M1B is connected to the first terminal of the main transconductance unit M1A, and the second terminal of the auxiliary transconductance unit M1B is connected to the second terminal of the source degradation unit. The first bias voltage Vb1 and the second bias voltage Vb2 can be dynamically adjusted so that the ratio between the transconductance of the auxiliary transconductance unit M1B and the transconductance of the main transconductance unit M1A remains constant. The control terminal of transistor unit M1C is used to connect the control voltage Vcs, and the second terminal of transistor unit M1C is connected to the first terminal of the output matching module. The third terminal of the source degradation unit is grounded, and the source degradation unit is used to introduce current negative feedback; The second terminal of the output matching module is used to connect to the working voltage VDD, and the output terminal RFOUT of the output matching module is used to output the amplified signal. The output matching module is used to achieve output matching.

[0026] Specifically, the input matching module can be built based on the input matching circuit in a conventional low-noise amplifier circuit. The adjustable bias module is configured with adjustable output, i.e., the first bias voltage Vb1 and the second bias voltage Vb2 are adjustable. The output matching module can be built based on the output matching circuit in a conventional low-noise amplifier circuit. The main transconductance unit M1A, the auxiliary transconductance unit M1B, and the transistor unit M1C can all be built based on MOSFETs, such as N-type MOSFETs. The source degradation unit can be in the form of a coupled inductor to realize feedback multiplexing between the main branch (the branch where the main transconductance unit M1A is located) and the auxiliary branch (the branch where the auxiliary transconductance unit M1B is located). The adjustable bias module forms a constant transconductance reference gm_ref by outputting an adjustable first bias voltage Vb1 and a second bias voltage Vb2, and ensures that the transconductance gm1 of the main transconductance unit M1A and the transconductance gm2 of the auxiliary transconductance unit M1B satisfy the following relationship: gm1≈gm_ref; gm2≈A×gm_ref, that is, gm2 / gm1≈A; gm_total = gm1 + B × gm2; Where A is the auxiliary transconductance ratio coefficient, B is the weighting coefficient, and gm_total is the total transconductance, which is set to a constant value.

[0027] It should be noted that by stabilizing the transconductance relationship between the main transconductance unit M1A and the auxiliary transconductance unit M1B using a constant transconductance reference gm_ref, the cancellation point drift can be suppressed. A can be determined by the fixed size ratio of the main transconductance unit M1A and the auxiliary transconductance unit M1B, as well as the bias voltages (first bias voltage Vb1 and second bias voltage Vb2). By adjusting the auxiliary transconductance strength through A, IIP3 can be optimized according to the mode. By controlling the total transconductance constantly, the gain variation between the high linearity mode and the low noise mode can be controlled. The ratio between the first bias voltage Vb1 and the second bias voltage Vb2 is adjustable. B can be determined by the signal distribution and output synthesis relationship between the main transconductance unit M1A and the auxiliary transconductance unit M1B, as well as the source degradation unit. For example, with a fixed PVT, if we do not consider the equivalent on-resistance of the main transconductance unit M1A and the auxiliary transconductance unit M1B, as well as the influence of the bias voltage, and assume that the size of the main transconductance unit M1A is 300u and the size of the auxiliary transconductance unit M1B is 30u, we can get A=10.

[0028] In one specific implementation, the input matching module may include an input inductor Lg, a first capacitor C1, and a second capacitor C2. The first capacitor C1 and the second capacitor C2, together with the input inductor Lg, form a resonant network to eliminate the imaginary part of the input impedance to achieve conjugate matching, while simultaneously offsetting the effects of transistor parasitic capacitance, optimizing the noise figure, and improving linearity. The output matching module may include an output inductor Ld, a series capacitor Cse, and a parallel capacitor Csh. The output inductor Ld, the series capacitor Cse, and the parallel capacitor Csh work together to achieve conjugate impedance matching to maximize power transfer. The series capacitor Cse is mainly used for DC blocking and impedance real part transformation, while the parallel capacitor Csh is mainly used for resonant tuning, capacitive load cancellation, and bandwidth control. Together, they achieve output conjugate matching to maximize power transfer and maintain linearity. A first resistor R1 can be set on the branch containing the first bias voltage Vb1, a second resistor R2 can be set on the branch containing the second bias voltage Vb2, and a third resistor R3 can be set on the branch containing the control voltage Vcs to suppress oscillation and adjust the switching speed. The control terminal of transistor unit M1C can be connected to a grounded third capacitor C3 to filter out high-frequency interference, prevent false turn-on, and suppress gate oscillation. The control voltage Vcs can be provided by the operating voltage VDD, or it can be provided by a low-dropout linear regulator at a fixed voltage.

[0029] The amplifier circuit provided in this embodiment is used to construct a high-linearity, low-noise amplifier. The basic structure of the low-noise amplifier is constructed by connecting the control terminal of the main transconductance unit M1A to the first output terminal of the input matching module and the first output terminal of the adjustable bias module, respectively; connecting the first terminal of the main transconductance unit M1A to the first terminal of the transistor unit M1C; connecting the second terminal of the main transconductance unit M1A to the first terminal of the source degradation unit; grounding the third terminal of the source degradation unit; and connecting the second terminal of the transistor unit M1C to the first terminal of the output matching module. Based on this, the basic structure of the low-noise amplifier is constructed by connecting the control terminal of the auxiliary transconductance unit M1B to the second output terminal of the input matching module and the second output terminal of the adjustable bias module, respectively; and connecting the first terminal of the auxiliary transconductance unit M1B to the first output terminal of the output matching module. The first terminal of the auxiliary transconductance unit M1B is connected to the first terminal of the main transconductance unit M1A, and the second terminal of the auxiliary transconductance unit M1B is connected to the second terminal of the source degradation unit. In this way, the transconductance of the main transconductance unit M1A can be canceled by the auxiliary transconductance unit M1B. At the same time, the first bias voltage Vb1 and the second bias voltage Vb2 are output through the adjustable bias module. Based on the dynamic adjustment of the first bias voltage Vb1 and the second bias voltage Vb2, the ratio between the transconductance of the auxiliary transconductance unit M1B and the transconductance of the main transconductance unit M1A is kept constant. This allows the linear cancellation relationship between the main transconductance unit M1A and the auxiliary transconductance unit M1B to remain stable under different PVT, frequency bands and gain modes, effectively suppressing the drift of the optimal IIP3 point and exhibiting high linearity characteristics.

[0030] In one alternative implementation, such as Figure 3 The adjustable bias module includes an adjustable transconductance current source, a current mirror unit, a first voltage generation unit, and a second voltage generation unit. The power supply terminal of the adjustable transconducting current source is connected to the power supply terminal of the current mirror unit and is used to connect to the working voltage VDD. The current mirror terminal of the adjustable transconducting current source is connected to the current mirror terminal of the current mirror unit. The bias terminal of the adjustable transconducting current source is connected to the bias terminal of the current mirror unit. The first output terminal of the current mirror unit is connected to the input terminal of the first voltage generation unit, and the second output terminal of the current mirror unit is connected to the input terminal of the second voltage generation unit. The output terminal of the first voltage generation unit is connected to the control terminal of the main transconductance unit M1A and the first output terminal of the input matching module, respectively. The output of the second voltage generation unit is connected to the control terminal of the auxiliary transconductance unit M1B and the second output of the input matching module, respectively.

[0031] Specifically, the adjustable transconductance current source can be optimized based on a conventional constant transconductance current source, and its transconductance is adjustable. The current mirror unit can adopt a conventional current mirror structure. Both the first and second voltage generation units can be constructed based on conventional transistors. The output of the second voltage generation unit is adjustable.

[0032] In practical implementation, an adjustable transconductance current source provides the original current Ib. The current mirror unit can replicate the original current Ib to generate a first bias current Ib1 and a second bias current Ib2, where Ib1≈Ib2. The first voltage generation unit generates the main bias voltage, i.e., the first bias voltage Vb1, based on the first bias current Ib1. The second voltage generation unit generates an auxiliary bias voltage, i.e., the second bias voltage Vb2, based on the second bias current Ib2. The specific value of the auxiliary bias voltage can be determined according to the auxiliary transconductance proportional coefficient A. The output second bias voltage Vb2 needs to make the transconductance gm2 of the auxiliary transconductance unit M1B close to A×gm1.

[0033] In one alternative implementation, such as Figure 4 The adjustable transconducting current source includes a first transistor M1, a second transistor M2, a first transistor unit Q10, a second transistor unit Q20, and a resistor subunit R10; The first terminal of the first transistor M1 is connected to the first terminal of the second transistor M2 and the power supply terminal of the current mirror unit, and is used to connect to the working voltage VDD. The control terminal of the first transistor M1 is connected to the control terminal of the second transistor M2, the second terminal of the first transistor M1, the first terminal of the first transistor unit Q10, and the current mirror terminal of the current mirror unit. The second terminal of the second transistor M2 is connected to the control terminal of the first transistor unit Q10, the control terminal of the second transistor unit Q20, the first terminal of the second transistor unit Q20, and the bias terminal of the current mirror unit, respectively. The second terminal of the first transistor unit Q10 is connected to the first terminal of the resistor subunit R10; The second terminal of the second transistor unit Q20 is grounded; The second terminal of resistor subunit R10 is grounded; The equivalent on-resistance of the second transistor unit Q20 and / or the resistance of the resistor subunit R10 are adjustable.

[0034] Specifically, the first transistor M1 and the second transistor M2 can be conventional transistors, such as P-type MOSFETs. The first transistor unit Q10 can be constructed from one or more transistors, for example, it can be constructed from one N-type MOSFET. The second transistor unit Q20 can be constructed from several transistors (such as N-type MOSFETs). The resistor subunit R10 can be constructed from several resistors.

[0035] In one specific implementation, when the equivalent on-resistance value of the second transistor unit Q20 needs to be adjustable, the second transistor unit Q20 can adopt a structure constructed by several transistors connected in parallel, and the equivalent on-resistance value can be adjusted by controlling the turn-on ratio of the transistors in the second transistor unit Q20.

[0036] In another specific implementation, when the resistance value of the resistor subunit R10 needs to be adjustable, the resistor subunit R10 can adopt a resistor matrix structure constructed by connecting several resistors in parallel, and the resistance value can be adjusted by controlling the number of resistors connected.

[0037] In one alternative implementation, such as Figure 5 The resistor subunit R10 includes several parallel sub-resistors, and a first controllable switch is connected in series on the circuit branch where each sub-resistor is located.

[0038] Specifically, the sub-resistors can be conventional resistors. The first controllable switch can be a conventional switching transistor. The sub-resistors in resistor sub-unit R10 can be represented by R11-R1n respectively. The first controllable switch in resistor sub-unit R10 can be represented by SW1_1-SW1_n respectively. n is an integer greater than 1.

[0039] In one alternative implementation, such as Figure 6 The second transistor unit Q20 includes several first sub-transistors connected in parallel, and a second controllable switch is connected in series on the branch where the first or second end of each first sub-transistor is located.

[0040] Specifically, the first sub-transistor can be a conventional N-type MOSFET. The second controllable switch can be a conventional switching transistor. The first sub-transistors of the second transistor unit Q20 can be represented by Q21-Q2m respectively. The second controllable switches in the second transistor unit Q20 can be represented by SW2_1-SW2_m respectively. m is an integer greater than 1.

[0041] In one alternative implementation, such as Figure 4 The current mirror unit includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The first terminal of the third transistor M3 is connected to the first terminal of the fourth transistor M4 and the power supply terminal of the adjustable transconducting current source, and is used to connect to the working voltage VDD. The control terminal of the third transistor M3 is connected to the control terminal of the fourth transistor M4 and the current mirror terminal of the adjustable transconducting current source. The second terminal of the third transistor M3 is connected to the first terminal of the fifth transistor M5. The second terminal of the fourth transistor M4 is connected to the first terminal of the sixth transistor M6; The control terminal of the fifth transistor M5 is connected to the control terminal of the sixth transistor M6 and the bias terminal of the adjustable transconductance current source, respectively. The second terminal of the fifth transistor M5 is connected to the input terminal of the first voltage generation unit. The second terminal of the sixth transistor M6 is connected to the input terminal of the second voltage generation unit.

[0042] Specifically, the third transistor M3 and the fourth transistor M4 can be conventional P-type MOSFETs. The fifth transistor M5 and the sixth transistor M6 can be conventional N-type MOSFETs. The third transistor M3 and the fifth transistor M5 are combined to form a current mirror, and the fourth transistor M4 and the sixth transistor M6 are combined to form another current mirror. The two current mirrors replicate the original current Ib of the adjustable transconductance current source into a first bias current Ib1 and a second bias current Ib2, respectively.

[0043] In one alternative implementation, such as Figure 7 The first voltage generation unit includes a seventh transistor M7 and an eighth transistor M8; The control terminal of the seventh transistor M7 is connected to the first terminal of the seventh transistor M7, the control terminal of the eighth transistor M8, the first output terminal of the current mirror unit, the control terminal of the main transconductance unit M1A, and the first output terminal of the input matching module, respectively. The second terminal of the seventh transistor M7 is connected to the first terminal of the eighth transistor M8 and the second terminal of the eighth transistor M8, respectively, and grounded. The second voltage generation unit includes a ninth transistor M9 and a tenth transistor M10; The control terminal of the ninth transistor M9 is connected to the first terminal of the ninth transistor M9, the control terminal of the tenth transistor M10, the second output terminal of the current mirror unit, the control terminal of the auxiliary transconductance unit M1B, and the second output terminal of the input matching module. The second terminal of the ninth transistor M9 is connected to the first terminal of the tenth transistor M10 and the second terminal of the tenth transistor M10 and grounded.

[0044] Specifically, transistors M7, M8, M9, and M10 can all be conventional N-type MOSFETs. Transistors M7 and M9 are transistors with different values, allowing for different first bias voltages Vb1 and Vb2 based on the first bias current Ib1 and the second bias current Ib2, respectively. The equivalent on-resistance of transistor M9 is adjustable.

[0045] In one alternative implementation, the ninth transistor M9 includes a plurality of second sub-transistors connected in parallel, and a sub-controllable switch is connected in series on the branch containing the first or second terminal of each second sub-transistor, as detailed in [reference needed]. Figure 6 The interconnections of the various components are constructed. The second sub-transistor can be an N-type MOSFET. The sub-controllable switch can be a conventional switching transistor. The turn-on ratio of the second sub-transistor in the ninth transistor M9 can be determined according to a preset auxiliary transconductance ratio coefficient A.

[0046] In one alternative implementation, such as Figure 8The main transconductor unit M1A includes several main transistors connected in parallel, and a third controllable switch is connected in series on the branch where the first or second end of each main transistor is located.

[0047] Specifically, the main transistor can be an N-type MOSFET. The third controllable switch can be a conventional switching transistor. The main transistors in the main transconductance unit M1A can be represented by M1A1-M1Ap respectively. The third controllable switches in the main transconductance unit M1A can be represented by SW3_1-SW3_p respectively. p is an integer greater than 1.

[0048] In one alternative implementation, such as Figure 9 The auxiliary transconductance unit M1B includes several auxiliary transistors connected in parallel, and a fourth controllable switch is connected in series on the branch where the first or second end of each auxiliary transistor is located.

[0049] Specifically, the auxiliary transistor can be an N-type MOSFET. The fourth controllable switch can be a conventional switching transistor. The auxiliary branch containing the auxiliary transconductance unit M1B can be turned on as needed, reducing auxiliary transistor noise and parasitic load in non-blocking scenarios, while also controlling the on-state ratio. The auxiliary transistors in the auxiliary transconductance unit M1B can be represented by M1B1-M1Bq respectively. The fourth controllable switch in the auxiliary transconductance unit M1B can be represented by SW4_1-SW4_q respectively. q is an integer greater than 1. The auxiliary transistor can be an N-type MOSFET. The fourth controllable switch can be a conventional switching transistor.

[0050] In one alternative implementation, such as Figure 2 The source degradation unit includes a first inductor Ls1 and a second inductor Ls2; The first end of the first inductor Ls1 is connected to the first end of the second inductor Ls2 and the first end of the main transconducting unit M1A, respectively; the second end of the first inductor Ls1 is connected to the second end of the auxiliary transconducting unit M1B. The second terminal of the second inductor Ls2 is grounded.

[0051] Specifically, the first inductor Ls1 and the second inductor Ls2 can be standard models suitable for low-noise amplifier design. The first inductor Ls1 and the second inductor Ls2 can form a coupled inductor through staggered or cross-layered configurations. The coupling coefficient can be determined through simulation, which not only introduces coupling impedance adjustment but also reduces the footprint. In practice, the simulation tool used can be the Cadence Spectre simulation platform, with the following simulation conditions: tt corner (Typical-Typical Corner); the default ambient temperature of 27°C; the operating frequency band set to 2.5 GHz-2.7 GHz; the scan step of 10 MHz; and the operating voltage VDD of 1.2 V. The target coupling coefficient range of the coupled inductor constructed from the first inductor Ls1 and the second inductor Ls2 is approximately 0.84-0.86. In this embodiment, the first inductor Ls1 and the second inductor Ls2 constitute the coupled inductor network at the input stage source end. The first inductor Ls1 is located between the source branches of the two input MOS transistors (i.e., the main transconductance unit M1A and the auxiliary transconductance unit M1B), and the second inductor Ls2 is connected to ground. By magnetically coupling the two inductors, the source degradation feedback is changed, thereby simultaneously affecting the input impedance, gain, and bandwidth. The technical solution provided in this embodiment is applicable to applications requiring high linearity and low noise amplifiers, such as sub6G.

[0052] This embodiment also provides a radio frequency front-end module, including the amplifier circuit described in the above embodiment.

[0053] Specifically, the amplifier circuit in the above embodiments is used to construct a high-linearity, low-noise amplifier based on constant transconductance ratio control. The RF front-end module in this embodiment integrates the amplifier circuit from the above embodiments. Relying on the amplifier circuit's core characteristics such as low noise, high linearity, and optimal IIP3-point drift suppression, it can achieve low-noise amplification under extremely weak signals while maintaining linearity without distortion under high interference environments. This balances receiver sensitivity with anti-blocking / anti-intermodulation capabilities, and can be directly applied to smartphones and mobile devices, Wi-Fi 6 / 6E / 7 routers and terminals, IoT and vehicle-to-everything (V2X) systems, satellite communications, and phased array systems.

[0054] This embodiment also provides an electronic device, including: the radio frequency front-end module in the above embodiment.

[0055] Specifically, the electronic device in this embodiment is equipped with the radio frequency front-end module described in the above embodiment. It is a signal processing electronic device for scenarios such as mobile terminals, Wi-Fi 6 / 6E / 7, Internet of Things and vehicle network, satellite communication and phased array system. Relying on the low noise amplification, linear distortion-free operation, and balanced receiving sensitivity and anti-blocking / anti-intermodulation capabilities of the radio frequency front-end module, it can achieve high sensitivity, high fidelity and high reliability wireless signal reception in complex electromagnetic environments, ensuring the core performance of the device under extreme communication distance, strong interference scenarios and high speed requirements.

[0056] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. An amplifier circuit, characterized in that, include: The system includes an input matching module, an adjustable bias module, an amplification module, and an output matching module. The amplification module is used to amplify the signal and includes a main transconductance unit, an auxiliary transconductance unit, a transistor unit, and a source degradation unit. The control terminal of the main transconductance unit is connected to the first output terminal of the input matching module and the first output terminal of the adjustable bias module, respectively. The first terminal of the main transconductance unit is connected to the first terminal of the transistor unit, and the second terminal of the main transconductance unit is connected to the first terminal of the source degradation unit. The input terminal of the input matching module is used to input the signal to be processed. The input matching module is used to realize input matching. The adjustable bias module is used to output the first bias voltage and the second bias voltage. The control terminal of the auxiliary transconductance unit is connected to the second output terminal of the input matching module and the second output terminal of the adjustable bias module, respectively. The first terminal of the auxiliary transconductance unit is connected to the first terminal of the main transconductance unit, and the second terminal of the auxiliary transconductance unit is connected to the second terminal of the source degradation unit. The first bias voltage and the second bias voltage can be dynamically adjusted so that the ratio between the transconductance of the auxiliary transconductance unit and the transconductance of the main transconductance unit is constant. The control terminal of the transistor unit is used to connect to the control voltage, and the second terminal of the transistor unit is connected to the first terminal of the output matching module. The third terminal of the source degradation unit is grounded, and the source degradation unit is used to introduce current negative feedback; The second terminal of the output matching module is used to connect to the working voltage, the output terminal of the output matching module is used to output an amplified signal, and the output matching module is used to achieve output matching.

2. The amplifier circuit according to claim 1, characterized in that, The adjustable bias module forms a constant transconductance reference by outputting adjustable first bias voltage and second bias voltage, and ensures that the transconductance of the main transconductance unit and the transconductance of the auxiliary transconductance unit satisfy the following relationship: gm1≈gm_ref; gm2≈A×gm_ref; gm_total = gm1 + B × gm2; Wherein, gm1 is the transconductance of the main transconductance unit, gm2 is the transconductance of the auxiliary transconductance unit, gm_ref is the constant transconductance reference, A is the auxiliary transconductance scaling factor, B is the weighting factor, and gm_total is the total transconductance, which is set to a constant value.

3. The amplifier circuit according to claim 1, characterized in that, The adjustable bias module includes an adjustable transconductance current source, a current mirror unit, a first voltage generation unit, and a second voltage generation unit. The power supply terminal of the adjustable transconducting current source is connected to the power supply terminal of the current mirror unit and is used to input the working voltage. The current mirror terminal of the adjustable transconducting current source is connected to the current mirror terminal of the current mirror unit. The bias terminal of the adjustable transconducting current source is connected to the bias terminal of the current mirror unit. The first output terminal of the current mirror unit is connected to the input terminal of the first voltage generation unit, and the second output terminal of the current mirror unit is connected to the input terminal of the second voltage generation unit. The output terminal of the first voltage generation unit is connected to the control terminal of the main transconductance unit and the first output terminal of the input matching module, respectively. The output terminal of the second voltage generation unit is connected to the control terminal of the auxiliary transconductance unit and the second output terminal of the input matching module, respectively.

4. The amplifier circuit according to claim 3, characterized in that, The adjustable transconducting current source includes a first transistor, a second transistor, a first transistor unit, a second transistor unit, and a resistor unit; The first terminal of the first transistor is connected to the first terminal of the second transistor and the power supply terminal of the current mirror unit and is used to input the working voltage. The control terminal of the first transistor is connected to the control terminal of the second transistor, the second terminal of the first transistor, the first terminal of the first transistor unit, and the current mirror terminal of the current mirror unit. The second terminal of the second transistor is connected to the control terminal of the first transistor unit, the control terminal of the second transistor unit, the first terminal of the second transistor unit, and the bias terminal of the current mirror unit, respectively. The second terminal of the first transistor unit is connected to the first terminal of the resistor subunit; The second terminal of the second transistor unit is grounded; The second terminal of the resistor sub-unit is grounded; The equivalent on-resistance of the second transistor unit and / or the resistance of the resistor subunit are adjustable.

5. The amplifier circuit according to claim 4, characterized in that, The resistor subunit includes several parallel sub-resistors, and a first controllable switch is connected in series on each circuit branch where the sub-resistor is located.

6. The amplifier circuit according to claim 4, characterized in that, The second transistor unit includes several first sub-transistors connected in parallel, and a second controllable switch is connected in series on the branch where the first or second end of each first sub-transistor is located.

7. The amplifier circuit according to claim 3, characterized in that, The current mirror unit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The first terminal of the third transistor is connected to the first terminal of the fourth transistor and the power supply terminal of the adjustable transconducting current source and is used to input the working voltage. The control terminal of the third transistor is connected to the control terminal of the fourth transistor and the current mirror terminal of the adjustable transconducting current source. The second terminal of the third transistor is connected to the first terminal of the fifth transistor. The second terminal of the fourth transistor is connected to the first terminal of the sixth transistor; The control terminal of the fifth transistor is connected to the control terminal of the sixth transistor and the bias terminal of the adjustable transconductance current source, respectively, and the second terminal of the fifth transistor is connected to the input terminal of the first voltage generation unit. The second terminal of the sixth transistor is connected to the input terminal of the second voltage generation unit.

8. The amplifier circuit according to claim 3, characterized in that, The first voltage generation unit includes a seventh transistor and an eighth transistor; The control terminal of the seventh transistor is connected to the first terminal of the seventh transistor, the control terminal of the eighth transistor, the first output terminal of the current mirror unit, the control terminal of the main transconductance unit, and the first output terminal of the input matching module, respectively. The second terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the second terminal of the eighth transistor, respectively, and grounded. The second voltage generation unit includes a ninth transistor and a tenth transistor; The control terminal of the ninth transistor is connected to the first terminal of the ninth transistor, the control terminal of the tenth transistor, the second output terminal of the current mirror unit, the control terminal of the auxiliary transconductance unit, and the second output terminal of the input matching module, respectively. The second terminal of the ninth transistor is connected to the first terminal of the tenth transistor and the second terminal of the tenth transistor, respectively, and grounded.

9. The amplifier circuit according to claim 1, characterized in that, The main transconductor unit includes several main transistors connected in parallel, and a third controllable switch is connected in series on the branch where the first or second end of each main transistor is located.

10. The amplifier circuit according to claim 1, characterized in that, The auxiliary transconductance unit includes several auxiliary transistors connected in parallel, and a fourth controllable switch is connected in series on the branch where the first or second end of each auxiliary transistor is located.

11. The amplifier circuit according to claim 1, characterized in that, The source degradation unit includes a first inductor and a second inductor; The first end of the first inductor is connected to the first end of the second inductor and the first end of the main transconducting unit, respectively; the second end of the first inductor is connected to the second end of the auxiliary transconducting unit. The second terminal of the second inductor is grounded.

12. A radio frequency front-end module, characterized in that, include: The amplifier circuit according to any one of claims 1 to 11.

13. An electronic device, characterized in that, include: The radio frequency front-end module as described in claim 12.

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