An ultra-wideband high power matching circuit and amplifier for standard power tubes

Abstract

The application discloses a kind of ultra-wideband high-power matching circuit and amplifier for standard power tube, it is related to power amplifier technical field, including the gold wire inductance group and input stabilization circuit being arranged in tube shell, input matching network and output matching network being arranged outside tube shell and input bias circuit and output bias circuit.Gold wire inductance group is connected between tube core and corresponding tube leg, and as the first stage inductive impedance conversion structure of tube shell outer matching network transition of tube core end equivalent impedance.The circuit described in the application cooperates through gold wire inductance group in package, input stabilization circuit and two-section type dielectric constant matching network outside package, realizes wideband impedance conversion, and considers output power, efficiency, stability and cost.

Description

Technical Field

[0001] This invention belongs to the field of power amplifiers, and in particular to an ultra-wideband high-power matching circuit and amplifier for standard power transistors. Background Technology

[0002] Ultra-wideband high-power amplifiers have wide applications in electronic interference, wireless communication, scientific research and production, and medical treatment.

[0003] Existing ultra-wideband high-power amplifiers mostly employ microwave monolithic integrated circuits (MMICs) or internal matching methods. Microwave monolithic integrated circuits have no discontinuous structures, resulting in high circuit fabrication precision and the ability to achieve very high operating frequencies and wide bandwidths. However, their disadvantages include low power output, high circuit losses, low efficiency, expensive manufacturing processes, and high cost per unit power. Internal matching methods use expensive semiconductor processes for the die, while the circuitry is fabricated using relatively inexpensive thin-film processes, making them less expensive than microwave monolithic integrated circuits. Internal matching methods can utilize multi-cell synthesis to increase output power, increase the thickness of the circuit substrate to reduce losses, and improve output efficiency. However, their disadvantages include more circuit discontinuities, and lower matching bandwidth and high-frequency performance compared to microwave monolithic integrated circuits.

[0004] Standard power transistors are the lowest-cost form of power amplifier and are widely used in high-power amplifier products. However, parasitic parameters of the transistor case, PCB dielectric fabrication processes, and insufficient Q values ​​of multilayer ceramic capacitors severely limit the design of ultra-wideband matching circuits. Ultra-wideband high-power circuits designed with standard power transistors are rare. Summary of the Invention

[0005] In view of the aforementioned existing problems, the present invention is proposed.

[0006] Therefore, the present invention provides an ultra-wideband high-power matching circuit for standard power transistors, thereby realizing an ultra-wideband high-power amplifier in the form of a low-cost standard power transistor and reducing the cost of the ultra-wideband high-power amplifier.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides an ultra-wideband high-power matching circuit for a standard power transistor, wherein the standard power transistor includes a casing, a die disposed within the casing, an input leg extending from the casing, and an output leg extending from the casing. The matching circuit comprises: a gold wire inductor group disposed within the casing, the gold wire inductor group being connected between the die and the corresponding leg, and serving as a first-stage inductive impedance transformation structure for transitioning the low impedance of the die to the matching network outside the casing; an input stabilization circuit disposed within the casing, connected between the input terminal and ground terminal of the die; and an input matching network disposed outside the casing and connected between the RF input terminal and the input leg, the input matching network comprising a second input matching segment and a first input matching segment sequentially arranged along the RF signal transmission direction, the first input matching segment being connected to the input leg, and the second input matching segment being connected to the RF input terminal, the first input matching segment comprising a stepped impedance microstrip transmission line structure composed of at least two input microstrip transmission line segments, and the second input matching segment comprising... The system includes at least one input microstrip transmission line segment, wherein the relative permittivity of the microwave PCB board used for the first input matching segment is greater than that of the microwave PCB board used for the second input matching segment; an output matching network, disposed outside the housing and connected between the output pin and the RF output terminal, the output matching network including a first output matching segment and a second output matching segment arranged sequentially along the RF signal transmission direction, the first output matching segment being connected to the output pin, and the second output matching segment being connected to the RF output terminal, the first output matching segment including a stepped impedance microstrip transmission line structure composed of at least two output microstrip transmission line segments, the second output matching segment including at least one output microstrip transmission line segment, and the relative permittivity of the microwave PCB board used for the first output matching segment being greater than that of the microwave PCB board used for the second output matching segment; an input bias circuit connected to an input-side node between the first input matching segment and the input pin; and an output bias circuit connected to an output-side node between the first output matching segment and the output pin.

[0008] In a preferred embodiment of the ultra-wideband high-power matching circuit for a standard power transistor according to the present invention, the first input matching section uses a microwave PCB board with a first input dielectric constant, the second input matching section uses a microwave PCB board with a second input dielectric constant, and the first input dielectric constant is not less than twice the second input dielectric constant; the first output matching section uses a microwave PCB board with a first output dielectric constant, the second output matching section uses a microwave PCB board with a second output dielectric constant, and the first output dielectric constant is not less than twice the second output dielectric constant; the first input matching section and the second input matching section, and the first output matching section and the second output matching section are electrically connected by bonding wires or soldered metal blocks, respectively.

[0009] As a preferred embodiment of the ultra-wideband high-power matching circuit for a standard power transistor according to the present invention, the input stabilization circuit includes a stabilizing resistor and a stabilizing capacitor connected in series. One end of the stabilizing resistor is connected to the input terminal of the transistor die, and one end of the stabilizing capacitor is grounded, so as to suppress low-frequency oscillation at the input terminal of the standard power transistor through a series RC branch.

[0010] As a preferred embodiment of the ultra-wideband high-power matching circuit for standard power transistors described in this invention, the gold wire inductor group includes an input-side gold wire inductor group and an output-side gold wire inductor group. The input-side gold wire inductor group is connected between the input terminal of the transistor and the input pin, and the output-side gold wire inductor group is connected between the output terminal of the transistor and the output pin.

[0011] As a preferred embodiment of the ultra-wideband high-power matching circuit for a standard power transistor according to the present invention, the first output matching section includes at least two output microstrip transmission lines connected in series along the radio frequency signal transmission direction, the second output matching section includes at least one output-side microstrip transmission line, and an output DC blocking capacitor is provided between the second output matching section and the radio frequency output terminal.

[0012] As a preferred embodiment of the ultra-wideband high-power matching circuit for a standard power transistor according to the present invention, the first input matching section includes at least two input microstrip transmission lines connected in series along the radio frequency signal transmission direction, the second input matching section includes at least one input-side microstrip transmission line, and an input DC blocking capacitor is provided between the second input matching section and the radio frequency input terminal.

[0013] As a preferred embodiment of the ultra-wideband high-power matching circuit for standard power transistors described in this invention, the second input matching segment includes at least two input microstrip transmission segments, and a parallel RC two-terminal network is connected in series between two adjacent input microstrip transmission segments. The parallel RC two-terminal network is composed of resistors and capacitors connected in parallel with each other, and is used to adjust the gain flatness and stability of the input matching network.

[0014] As a preferred embodiment of the ultra-wideband high-power matching circuit for a standard power transistor according to the present invention, the input bias circuit includes an input bias microstrip line branching from the input-side node, an input stabilizing resistor connected in series in the input bias microstrip line, a gate bias terminal connected to the end of the input bias microstrip line, and an input grounding capacitor connected between the gate bias terminal and the ground terminal; the output bias circuit includes an output bias microstrip line branching from the output-side node, a drain bias terminal connected to the end of the output bias microstrip line, and an output grounding capacitor connected between the drain bias terminal and the ground terminal.

[0015] As a preferred embodiment of the ultra-wideband high-power matching circuit for a standard power transistor according to the present invention, when the standard power transistor includes two symmetrically arranged dies, the input bias circuit and the output bias circuit each include two bias microstrip line branches symmetrically arranged relative to the corresponding synthesis node, and the end of each bias microstrip line branch is connected to the corresponding bias terminal and grounded through the corresponding grounding capacitor.

[0016] Secondly, the present invention provides an ultra-wideband high-power amplifier, including the ultra-wideband high-power matching circuit, and an RF input terminal and an RF output terminal connected to the ultra-wideband high-power matching circuit, wherein the standard power transistor is a GaN power transistor, and the input matching network and the output matching network are configured to enable the ultra-wideband high-power amplifier to operate in the 0.2 GHz to 2.5 GHz frequency band.

[0017] The beneficial effects of this invention are as follows: the gold wire inductor group inside the tube first transforms the equivalent impedance of the die end, which is lower than the external 50Ω port impedance, to an intermediate impedance. The first matching section with a high dielectric constant near the tube leg further completes the compact transformation of the low impedance region. The second matching section with a low dielectric constant near the external RF port then transforms the intermediate impedance to 50Ω and reduces transmission loss. The input stabilization circuit and the bias microstrip line with its end RF grounded via a capacitor, both located inside the tube, are used to suppress low-frequency or out-of-band oscillations. The above structure synergistically improves the matching capability, stability, and power efficiency over a wide bandwidth while maintaining the cost advantage of standard power transistor solutions. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a block diagram of an ultra-wideband high-power matching circuit disclosed in an embodiment of the present invention; Figure 2 This is a topology diagram of an ultra-wideband high-power matching circuit disclosed in an embodiment of the present invention; Figure 3 This is a schematic diagram of the dual-branch symmetrical structure of the output bias circuit in an embodiment of the present invention; Figure 4 A schematic diagram showing the addition of a debugging capacitor to the output matching circuit in an embodiment of the present invention; Figure 5 This is a schematic diagram of the dual-branch symmetrical structure of the input bias circuit in an embodiment of the present invention; Figure 6 The output power simulation test data of the power amplifier disclosed in the embodiments of the present invention; Figure 7 These are simulation test data of the drain efficiency of the power amplifier disclosed in the embodiments of the present invention.

[0020] In the diagram: 100, Input matching network; 110, First input matching segment; 120, Second input matching segment; 130, Input bias circuit; 200, Standard power transistor; 210, Die; 220, Case; 230, Input stabilization circuit; 300, Output matching network; 310, First output matching segment; 320, Second output matching segment; 330, Output bias circuit; VG, Gate bias terminal; VD, Drain bias terminal. Detailed Implementation

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0023] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0024] In this specification, "standard power transistor" refers to a packaged power device that uses a general-purpose discrete power transistor case and input / output pin configuration, and does not have a complete input matching network and a complete output matching network facing an external 50Ω port within the case; "ultra-wideband" refers to a continuous operating frequency band, and the ratio of the upper frequency limit to the lower frequency limit of this continuous operating frequency band is not less than 4; "high power" refers to an output power of not less than 49dBm under 50Ω load and continuous wave excitation conditions, where 49dBm corresponds to approximately 79.4W, which is in the 80W power range; "operating within a certain frequency band" means that when tested at frequency intervals not greater than 100MHz within this continuous frequency band, the continuous wave output power at each test frequency point is not less than 49dBm, and there is no continuous self-oscillation. Taking the 0.2GHz to 2.5GHz frequency band of this embodiment as an example, the ratio of the upper frequency limit to the lower frequency limit is 12.5, which meets the ultra-wideband determination criteria.

[0025] like Figure 1 and Figure 2 As shown, this embodiment provides an ultra-wideband high-power matching circuit for a standard power transistor. The standard power transistor 200 includes a housing 220, a die 210 disposed within the housing 220, an input pin extending from the housing 220, and an output pin extending from the housing 220. The ultra-wideband high-power matching circuit includes an input matching network 100, the standard power transistor 200, and an output matching network 300. The input matching network 100 is disposed outside the housing 220 and connected between the RF input terminal RFin and the input pin, while the output matching network 300 is disposed outside the housing 220 and connected between the output pin and the RF output terminal RFout.

[0026] When implementing this embodiment, the selected GaN die should provide a nonlinear large-signal model covering the target operating frequency band, or be able to perform source pull and load pull tests on the die's input pad reference plane and output pad reference plane respectively; for Figure 2 The dual-die structure shown should have a target output capacity of no less than 50W for each die under 28V drain power supply. The length, width, height, and relative positions of the die pads, housing cavity, input leads, and output leads are established using the structural drawings or 3D measurement results of the selected package. The number, diameter, horizontal span, arc height, and spacing between adjacent gold wires are input into the model according to the actual bonding structure, thus establishing a correspondence between the subsequent microstrip transmission line dimensions and the specific die and package structure.

[0027] The standard power transistor 200 includes a die 210, a housing 220, an input stabilization circuit 230, and a gold wire inductor group. The die 210 is a GaN die. The gold wire inductor group includes an input-side gold wire inductor group L2 and an output-side gold wire inductor group L1. The input-side gold wire inductor group L2 is connected between the input terminal and the input leg of the die 210, and the output-side gold wire inductor group L1 is connected between the output terminal and the output leg of the die 210. Each gold wire inductor group consists of 2 to 16 bonding wires with a diameter of 25μm to 50μm connected in parallel. The horizontal span between the two solder joints of a single bonding wire is 0.5mm to 2.0mm, the arc height can be 0.1mm to 0.5mm, and the equivalent inductance of the gold wire inductor group can be 0.15nH to 1.2nH. Figure 2 In the dual-die embodiment shown, each die uses four gold wires with a diameter of 25μm and a horizontal span of approximately 1.0mm on the input side, and eight gold wires with a diameter of 25μm and a horizontal span of approximately 0.8mm on the output side. The gold wire inductor array serves two purposes: firstly, it enables electrical interconnection between die 210 and its leads; secondly, it acts as a first-stage inductive impedance transformation structure, transitioning the die-end equivalent impedance (lower than the external 50Ω port impedance) to the external matching network, thus reducing the impedance transformation difficulty between the external input matching network 100 and the output matching network 300.

[0028] The input stabilization circuit 230 is disposed within the housing 220 and connected between the input terminal and the ground terminal of the die 210. Specifically, the input stabilization circuit 230 includes a stabilizing resistor R1 and a stabilizing capacitor C1 connected in series. One end of the stabilizing resistor R1 is connected to the input terminal of the die 210, and one end of the stabilizing capacitor C1 is grounded through the metal base of the housing. The stabilizing resistor R1 can be a ceramic film resistor with a resistance value of 10Ω to 50Ω; the stabilizing capacitor C1 can be a ceramic film capacitor or a metal oxide capacitor with a capacitance value of 22pF to 100pF. In a specific prototype, R1 is 30Ω, C1 is 47pF, the interconnection length between R1 and the die input terminal is no greater than 1.0mm, and the interconnection length between the C1 ground terminal and the ground terminal is no greater than 0.5mm. The input stabilization circuit 230 is used to form an out-of-band energy discharge path near the input terminal of the die 210 to suppress low-frequency or out-of-band oscillations. During simulation, an actual device model containing R1, C1 and parasitic inductance and resistance of the interconnect structure is used instead of an ideal lumped model. When the standard power transistor includes two or more dies, each die's input terminal is provided with an input stabilization branch consisting of a stabilizing resistor R1 and a stabilizing capacitor C1 connected in series. All input stabilization branches are collectively referred to as the input stabilization circuit 230.

[0029] The input matching network 100 includes a first input matching segment 110, a second input matching segment 120, and an input bias circuit 130. Along the RF signal transmission direction, the second input matching segment 120 is connected to the RF input terminal RFin, and the first input matching segment 110 is connected to the input pin. The first input matching segment 110 includes a stepped impedance microstrip transmission line structure composed of at least two series-connected input microstrip transmission line segments, and the second input matching segment 120 includes at least one input microstrip transmission line segment. The first input matching segment 110 uses a microwave PCB board with a first input dielectric constant, and the second input matching segment 120 uses a microwave PCB board with a second input dielectric constant. The first input dielectric constant is greater than the second input dielectric constant; preferably, the first input dielectric constant is not less than twice the second input dielectric constant.

[0030] In a preferred embodiment, the microwave PCB board of the first input matching section 110 has a relative permittivity of 9.5 to 11 and a thickness of 0.3 mm to 0.7 mm; the microwave PCB board of the second input matching section 120 has a relative permittivity of 2.8 to 4.0 and a thickness of 0.5 mm to 1.0 mm. More specifically, the first input matching section 110 can be fabricated using a microwave PCB board with a relative permittivity of 10.2 and a thickness of 0.508 mm, and the second input matching section 120 can be fabricated using a microwave PCB board with a relative permittivity of 3.5 and a thickness of 0.762 mm. The aforementioned relative permittivity is obtained using the same test method and test frequency.

[0031] The microwave PCBs of the first input matching section 110, the second input matching section 120, the first output matching section 310, and the second output matching section 320 are all provided with continuous metal ground planes, and the copper foil thickness is 35μm to 70μm; near 1GHz, the loss tangent of the board material is preferably not greater than 0.004. Grounding vias are provided along both sides of the microstrip transmission line and the transition edge of the two PCBs. The diameter of the grounding vias is 0.2mm to 0.4mm, and the center distance between adjacent grounding vias is not greater than 1.0mm, in order to reduce the grounding loop inductance and inter-board transition parasitics.

[0032] like Figure 2As shown, the first input matching section 110 includes multiple input microstrip transmission lines, such as TL12, TL13, and TL14, connected in series along the RF signal transmission direction. The second input matching section 120 includes multiple input-side microstrip transmission lines, such as TL15 and TL16, connected in series along the RF signal transmission direction. An input DC blocking capacitor C6 is provided between the second input matching section 120 and the RF input terminal RFin. The input DC blocking capacitor C6 is a multilayer ceramic capacitor with C0G or NPO dielectric. The first input matching section 110 and the second input matching section 120 are electrically connected by 2 to 6 parallel bonding wires or welded metal blocks. The distance between adjacent PCB edges is no greater than 0.5 mm, and the signal transition length of the bonding wires or welded metal blocks is no greater than 1.5 mm.

[0033] A parallel RC two-terminal network can also be configured in the second input matching section 120. Specifically, a parallel RC two-terminal network consisting of a resistor R3 and a capacitor C5 connected in parallel is connected in series between TL15 and TL16. The resistor R3 is a ceramic thin-film surface-mount resistor with a resistance of approximately 15Ω; the capacitor C5 is a multilayer ceramic capacitor with a C0G or NPO dielectric and a capacitance of approximately 27pF. The two terminals of the parallel RC two-terminal network are connected to TL15 and TL16 respectively, which is used to introduce frequency-dependent damping in the main input transmission path to improve gain flatness and stability.

[0034] The input bias circuit 130 is connected to the input-side node between the first input matching section 110 and the input pin. Specifically, the input bias circuit 130 includes an input bias microstrip line TL11 branching from the input-side node, an input stabilizing resistor R2 connected in series in the input bias microstrip line TL11, a gate bias terminal VG connected to the end of the input bias microstrip line TL11, and an input grounding capacitor C4 connected between the gate bias terminal VG and the ground terminal. This makes the end of TL11 have low RF impedance in the operating frequency band, and simultaneously feeds the gate bias voltage to the input terminal of the die 210 through TL11 and R2. The input stabilizing resistor R2 is a ceramic thin film surface mount resistor with a resistance of approximately 5.1Ω; the equivalent capacitance of the input grounding capacitor C4 is above 400pF, and in a specific prototype, it is composed of 82pF and 390pF C0G or NPO capacitors connected in parallel. The capacitor bank is no more than 2.0mm away from the gate bias terminal VG and grounded through at least two grounding vias. The input bias circuit 130 and the first input matching section 110 are integrated on the same high dielectric constant microwave PCB board to provide gate bias, reduce out-of-band low-end gain, and improve stability and gain flatness.

[0035] The output matching network 300 includes a first output matching section 310, a second output matching section 320, and an output bias circuit 330. Along the RF signal transmission direction, the first output matching section 310 is connected to the output pin, and the second output matching section 320 is connected to the RF output terminal RFout. The first output matching section 310 includes a stepped impedance microstrip transmission line structure composed of at least two series-connected output microstrip transmission line segments, and the second output matching section 320 includes at least one output microstrip transmission line segment. The first output matching section 310 uses a microwave PCB board with a first output dielectric constant, and the second output matching section 320 uses a microwave PCB board with a second output dielectric constant. The first output dielectric constant is greater than the second output dielectric constant; preferably, the first output dielectric constant is not less than twice the second output dielectric constant.

[0036] In a preferred embodiment, the microwave PCB board of the first output matching section 310 has a relative permittivity of 9.5 to 11 and a thickness of 0.3 mm to 0.7 mm; the microwave PCB board of the second output matching section 320 has a relative permittivity of 2.8 to 4.0 and a thickness of 0.5 mm to 1.0 mm. More specifically, the first output matching section 310 can be fabricated using a microwave PCB board with a relative permittivity of 10.2 and a thickness of 0.508 mm, and the second output matching section 320 can be fabricated using a microwave PCB board with a relative permittivity of 3.5 and a thickness of 0.762 mm. The aforementioned relative permittivity is obtained using the same testing method and frequency as the input matching network.

[0037] like Figure 2 As shown, the first output matching section 310 includes multiple output microstrip transmission lines, such as TL2 to TL9, connected in series along the RF signal transmission direction. The second output matching section 320 includes at least one output-side microstrip transmission line, such as TL10. An output DC blocking capacitor C3 is provided between the second output matching section 320 and the RF output terminal RFout. The output DC blocking capacitor C3 is a multilayer ceramic capacitor with C0G or NPO dielectric, with an equivalent capacitance of approximately 20pF and a rated DC withstand voltage of not less than 100V. The first output matching section 310 and the second output matching section 320 are electrically connected by 2 to 6 parallel bonding wires or soldered metal blocks. The distance between adjacent PCB edges is not greater than 0.5mm, and the signal transition length of the bonding wires or soldered metal blocks is not greater than 1.5mm.

[0038] The output bias circuit 330 is connected to the output-side node between the first output matching section 310 and the output pin. Specifically, the output bias circuit 330 includes an output bias microstrip line TL1 branching from the output-side node, a drain bias terminal VD connected to the end of the output bias microstrip line TL1, and an output grounding capacitor C2 connected between the drain bias terminal VD and the ground terminal. This ensures that the end of TL1 has low RF impedance within the operating frequency band, while simultaneously feeding the drain bias voltage into the output terminal of die 210 via TL1. The equivalent capacitance of the output grounding capacitor C2 is 400pF or higher. In a specific prototype, it is composed of 82pF and 390pF C0G or NPO capacitors connected in parallel. The capacitor bank is no more than 2.0mm away from the drain bias terminal VD and grounded through at least two grounding vias. The output bias circuit 330 and the first output matching section 310 are integrated on the same high-dielectric-constant microwave PCB board to provide drain bias, improve output matching, and reduce out-of-band low-side gain.

[0039] by Figure 2 Taking the dual-die, 28V GaN power amplifier shown as an example, the first input matching section 110 and the first output matching section 310 use microwave PCB boards with a relative permittivity of 10.2 and a thickness of 0.508mm, while the second input matching section 120 and the second output matching section 320 use microwave PCB boards with a relative permittivity of 3.5 and a thickness of 0.762mm. One feasible dimension for each microstrip transmission line segment is as follows, all dimensions are conductor pattern length × width in mm, excluding pads: TL1 10.0 × 0.30, TL2 3.0 × 5.0, TL3 3.5 × 4.0, TL4 4.0 × 3.2, TL5 4.5 × 2.6, TL6 5.0 × 2.0, TL7 5.5 × 1.5, TL8 6.0 × 1.0, TL9 6.0 × 0.60, TL10 8.0 × 1.70, TL11 8.0 × 0.30, TL12 3.5 × 2.8, TL13 4.5 × 1.8, TL14 5.5 × 0.90, TL15 7.0 × 2.4, TL16 8.0 × 1.70; the dimensional tolerance of the conductor pattern is preferably controlled within ±0.05 mm.

[0040] In the specific prototype described above, R1 is 30Ω, R2 is 5.1Ω, R3 is 15Ω, C1 is 47pF, the equivalent capacitance of C2 and C4 is approximately 470pF, C3 is 20pF, C5 is 27pF, and C6 is 47pF. R2 is preferably a thin-film resistor in a 0402 or smaller package, and R3 is preferably an RF power thin-film resistor or an equivalent resistance formed by multiple resistors connected in parallel. C3, C5, and C6 are preferably C0G or NPO capacitors in a 0402 or smaller package. C3 is composed of multiple high-Q capacitors connected in parallel or in series-parallel configurations, and the package size is determined based on the RF current, equivalent series resistance, and temperature rise of each capacitor. C2 and C4 are composed of 82pF and 390pF capacitors connected in parallel, respectively. During simulation and layout optimization, the equivalent series resistance, equivalent series inductance, self-resonance characteristics, pads, and ground vias of the capacitors are all included in the model.

[0041] In this embodiment, the radio frequency (RF) signal is input from the RF input terminal RFin, passes through the input DC blocking capacitor C6 to the second input matching section 120, and then passes through the first input matching section 110, the input pin, and the input-side gold wire inductor group L2 to the die 210. After the die 210 amplifies the RF signal, the amplified RF signal passes through the output-side gold wire inductor group L1 and the output pin to the first output matching section 310, and then passes through the second output matching section 320 and the output DC blocking capacitor C3 to be output from the RF output terminal RFout. This forms a continuous ultra-wideband impedance matching path from the RF input terminal RFin to the RF output terminal RFout.

[0042] In this embodiment, the input-side gold wire inductor group L2 and the output-side gold wire inductor group L1 first transform the equivalent impedance of the die end (below 50Ω) to the intermediate impedance of the leg reference surface. The first input matching section 110 and the first output matching section 310 are located in the low-impedance region near the leg. Using a microwave PCB board with a higher relative permittivity can shorten the physical length required to achieve the same electrical length and reduce the circuit size. The second input matching section 120 and the second output matching section 320 are located in the region near the external 50Ω port. Using a microwave PCB board with a lower relative permittivity can obtain a more reasonable microstrip linewidth near 50Ω and lower transmission loss. The die end impedance, leg intermediate impedance, and inter-board intermediate impedance mentioned in this specification are all complex impedances at the corresponding reference surface. During optimization, both the real and imaginary parts are calculated simultaneously. 20Ω to 35Ω refers to the preferred range of the real part of the intermediate impedance. The imaginary part converges to zero by adjusting the gold wire equivalent inductance and the electrical length of the microstrip transmission line. By sequentially performing multi-stage transformations of "die-end complex impedance - leg-intermediate complex impedance - inter-board intermediate complex impedance - 50Ω port impedance", the transformation ratio of a single-stage matching network can be reduced and the input-output matching effect over a wide bandwidth can be improved.

[0043] Specifically, the ultra-wideband high-power matching circuit of this embodiment can be applied to dual-die GaN power amplifiers from 0.2GHz to 2.5GHz. The drain operating voltage can be 28V, and the gate bias can be adjusted to a total static drain current of approximately 0.6A. During testing, the power amplifier is mounted on a metal heat sink at a temperature of 25±5℃. A 50Ω signal source and a 50Ω load are connected to the RF input and RF output terminals, respectively. A continuous wave signal is used, and the input power is adjusted to within the range of 36dBm to 38dBm at each test frequency. The test results are adjusted after deducting losses from input and output cables and connectors. Drain efficiency is calculated as the ratio of output RF power to drain DC input power. Figure 6 and Figure 7 The data shown indicates that, within the frequency range of 0.2 GHz to 2.5 GHz, the continuous wave output power is no less than 49 dBm, approximately 80 W, and the drain efficiency is no less than 45%. The typical output power is approximately 100 W, and the typical drain efficiency is approximately 50%. Stability can be verified by disconnecting the RF input signal and applying a phase scan with a VSWR of no more than 2:1 to the source and load terminals, with the condition being the absence of continuous self-oscillation.

[0044] like Figure 3 As shown, in the dual-die combined structure, the output bias circuit 330 adopts a dual-branch symmetrical structure. Two output bias microstrip lines TL1 are symmetrically arranged with respect to the output combining node of the two dies. The ends of each output bias microstrip line TL1 are connected to the drain bias terminal VD, and grounded through the corresponding output grounding capacitor C2. The two drain bias terminals VD are connected to the same drain bias power supply, ensuring that both dies receive the same drain bias voltage. This improves the symmetry of the output bias feed and reduces the impact of the bias structure on output matching consistency.

[0045] like Figure 4 As shown, in another embodiment, at least one of the first output matching section 310 and the second output matching section 320 has a grounded tuning capacitor, such as tuning capacitors C7, C8, and C9, located at a predetermined position in the microstrip circuit. The tuning capacitors are multilayer ceramic capacitors with C0G or NPO dielectric. In a specific tuning example, C7, C8, and C9 are 1.2 pF, 0.8 pF, and 1.0 pF, respectively. By setting grounded tuning capacitors, the local equivalent capacitance of the output matching network 300 can be corrected during physical tuning, thereby improving output power, VSWR, or efficiency. The location and capacitance value of the tuning capacitors can be determined based on the target frequency band, die equivalent impedance, relative permittivity of the substrate, and measured matching results.

[0046] like Figure 5As shown, in the dual-die synthesis structure, the input bias circuit 130 adopts a dual-branch symmetrical structure. Two input bias microstrip lines TL11 are symmetrically arranged with respect to the input synthesis node of the two dies. Each input bias microstrip line TL11 has a series input stabilizing resistor R2. The ends of each input bias microstrip line TL11 are connected to the gate bias terminal VG, and are grounded through the corresponding input grounding capacitor C4. The two gate bias terminals VG are connected to the same adjustable gate bias power supply, ensuring that both dies receive the same gate bias voltage. This improves the consistency of the input bias feed and enhances input stability and gain flatness.

[0047] In other embodiments, the number of output microstrip transmission segments in the first output matching section 310 is not limited to... Figure 2 The eight shown can be set to other numbers depending on the target frequency band, die output impedance, and board parameters; the number of microstrip transmission line segments on the output side of the second output matching section 320 is not limited to... Figure 2 The single input microstrip transmission segment shown can also be configured as multiple serial segments. The number of input microstrip transmission segments in the first input matching segment 110 is not limited to... Figure 2 The number of microstrip transmission segments on the input side in the three shown in the second input matching segment 120 is not limited to... Figure 2 Both shown can be adjusted according to the target working bandwidth and matching requirements.

[0048] In other embodiments, the length, width, and spacing of the microstrip transmission line segments of the first input matching segment 110, the second input matching segment 120, the first output matching segment 310, and the second output matching segment 320 can be determined by microwave circuit simulation or three-dimensional electromagnetic field simulation based on the target operating frequency band, the equivalent impedance of the die input and output, the equivalent inductance value of the gold wire inductor group, the relative permittivity of the microwave PCB board, and the board thickness. It can also be corrected by combining the grounding debugging capacitor during prototype debugging.

[0049] A repeatable design flow includes: First, setting the die input pad and output pad as the source pull reference plane and load pull reference plane, respectively. Based on the nonlinear large-signal model of the selected die or source pull and load pull tests, the target source complex impedance and target load complex impedance, expressed in the form of R+jX, are obtained at 0.2GHz, 0.5GHz, 1.0GHz, 1.5GHz, 2.0GHz, and 2.5GHz, respectively. The load impedance is selected with the output power of a single die not less than 46dBm, and the drain efficiency is maximized among the candidate impedances that meet this output power requirement. After the dual-die output is synthesized by the gold wire inductor group on the output side and the output matching network, the continuous wave output power at the RF output terminal is not less than 49dBm as the pass condition for the whole device. The source impedance is selected with the condition of satisfying input stability and maximizing power gain. Secondly, a three-dimensional electromagnetic model was established, including the actual geometric dimensions of the die pads, the housing cavity, the input leads, the output leads, and the bonding wires. By adjusting the number, diameter, horizontal span, and arc height of the wires, the complex impedance at the die end was transformed to the intermediate complex impedance of the lead reference surface. Thirdly, the first matching segment with high dielectric constant was optimized to ensure the real part of the intermediate complex impedance was within the range of 20Ω to 35Ω and the imaginary part converged to zero. Then, the second matching segment with low dielectric constant was optimized to ensure the external RF port was close to 50Ω within the target frequency band. Finally, the S-parameter models of the actual resistors and capacitors were jointly simulated with the electromagnetic model. Output power, drain efficiency, input / output VSWR, and small-signal stability were checked at frequency intervals not exceeding 100MHz within the target frequency band. A continuous wave output power of not less than 49dBm and the absence of continuous self-oscillation were used as the pass condition, and minor corrections were made using capacitors C7, C8, C9, or corresponding adjustment capacitors.

[0050] In other embodiments, the standard power transistor 200 is not limited to a dual-die composite structure, but can also be a single-die structure, a four-die composite structure, or other multi-die composite structures. Correspondingly, the input matching network 100 and the output matching network 300 are adjusted from a dual-path composite form to a single-path composite form, a four-path composite form, or other multi-path composite forms, and the number of gold wires and the microstrip linewidth are reset according to the current of each branch. The above adjustments do not change the basic concept of this invention to achieve ultra-wideband high-power matching through the coordinated action of the gold wire inductor group inside the casing, the two-stage heterodielectric constant input-output matching network outside the casing, and the bias microstrip line.

[0051] In other embodiments, the operating frequency band of the present invention can also be adjusted to a continuous frequency band of 0.2 GHz to 2 GHz, 0.5 GHz to 2.5 GHz, or other upper and lower frequency ratios not less than 4, depending on device characteristics and application requirements. For different frequency bands, the die input and output equivalent impedances should be re-obtained, and each structural parameter should be recalculated and verified in the order of the gold wire inductance group inside the die, the high dielectric constant first matching segment near the lead, and the low dielectric constant second matching segment near the port.

[0052] In other embodiments, the input bias circuit 130 and the output bias circuit 330 may be supplemented with additional resistors, decoupling capacitors, or additional microstrip lines according to stability and bias feed requirements. The number, diameter, horizontal span, and arc height of the gold wires in the input-side gold wire inductor group L2 and the output-side gold wire inductor group L1 can be adjusted according to the number of dies, the lead layout, and the required equivalent inductance, but they are still set between the dies and the corresponding leads and serve as the first-stage inductive impedance transformation structure.

[0053] The specific values ​​in the above embodiments, such as relative permittivity, board thickness, microstrip transmission line segment size, gold wire size, resistance value, capacitance value, operating voltage, output power, and operating frequency band, are all used to illustrate the preferred embodiments of the present invention. Those skilled in the art can adjust the number of microstrip transmission lines, segment size, connection method, number of dies, operating frequency band, or bias circuit configuration within the scope of the technical concept and feasible parameters described in the specification, based on the equivalent impedance and power rating of the specific die.

[0054] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An ultra-wideband high-power matching circuit for a standard power transistor, the standard power transistor comprising a housing, a die disposed within the housing, an input pin extending from the housing, and an output pin extending from the housing, characterized in that, The matching circuit includes: The gold wire inductor group disposed inside the tube shell is connected between the die and the corresponding leg, and serves as the first-stage inductive impedance transformation structure for the transition from the low impedance of the die to the matching network outside the tube shell. The input stabilization circuit, located inside the housing, is connected between the input terminal and the ground terminal of the die. An input matching network is disposed outside the housing and connected between the RF input terminal and the input pin. The input matching network includes a second input matching segment and a first input matching segment arranged sequentially along the RF signal transmission direction. The first input matching segment is connected to the input pin, and the second input matching segment is connected to the RF input terminal. The first input matching segment includes a stepped impedance microstrip transmission line structure composed of at least two input microstrip transmission line segments. The second input matching segment includes at least one input microstrip transmission line segment. The relative permittivity of the microwave PCB board used in the first input matching segment is greater than that of the microwave PCB board used in the second input matching segment. An output matching network is disposed outside the tube housing and connected between the output tube leg and the RF output terminal. The output matching network includes a first output matching segment and a second output matching segment arranged sequentially along the RF signal transmission direction. The first output matching segment is connected to the output tube leg, and the second output matching segment is connected to the RF output terminal. The first output matching segment includes a stepped impedance microstrip transmission line structure composed of at least two output microstrip transmission line segments. The second output matching segment includes at least one output microstrip transmission line segment. The relative permittivity of the microwave PCB board used in the first output matching segment is greater than that of the microwave PCB board used in the second output matching segment. An input bias circuit is connected to the input-side node between the first input matching segment and the input pin; An output bias circuit is connected to the output-side node between the first output matching segment and the output pin.

2. The ultra-wideband high-power matching circuit for standard power transistors as described in claim 1, characterized in that: The first input matching segment uses a microwave PCB board with a first input dielectric constant, the second input matching segment uses a microwave PCB board with a second input dielectric constant, and the first input dielectric constant is not less than twice the second input dielectric constant; The first output matching section uses a microwave PCB board with a first output dielectric constant, the second output matching section uses a microwave PCB board with a second output dielectric constant, and the first output dielectric constant is not less than twice the second output dielectric constant; the first input matching section and the second input matching section, as well as the first output matching section and the second output matching section, are electrically connected by bonding wires or welding metal blocks, respectively.

3. The ultra-wideband high-power matching circuit for standard power transistors as described in claim 1, characterized in that: The input stabilization circuit includes a stabilizing resistor and a stabilizing capacitor connected in series. One end of the stabilizing resistor is connected to the input terminal of the die, and one end of the stabilizing capacitor is grounded, so as to suppress low-frequency oscillation at the input terminal of the standard power transistor through a series RC branch.

4. The ultra-wideband high-power matching circuit for standard power transistors as described in claim 1, characterized in that: The gold wire inductor group includes an input-side gold wire inductor group and an output-side gold wire inductor group. The input-side gold wire inductor group is connected between the input terminal of the die and the input pin, and the output-side gold wire inductor group is connected between the output terminal of the die and the output pin.

5. The ultra-wideband high-power matching circuit for standard power transistors as described in claim 1, characterized in that: The first output matching section includes at least two output microstrip transmission lines connected in series along the radio frequency signal transmission direction, the second output matching section includes at least one output end-side microstrip transmission line, and an output DC blocking capacitor is provided between the second output matching section and the radio frequency output end.

6. The ultra-wideband high-power matching circuit for standard power transistors as described in claim 1, characterized in that: The first input matching segment includes at least two input microstrip transmission lines connected in series along the radio frequency signal transmission direction, the second input matching segment includes at least one input-side microstrip transmission line, and an input DC blocking capacitor is provided between the second input matching segment and the radio frequency input terminal.

7. The ultra-wideband high-power matching circuit for a standard power transistor as described in claim 6, characterized in that: The second input matching segment includes at least two input microstrip transmission segments. A parallel RC two-terminal network is connected in series between two adjacent input microstrip transmission segments. The parallel RC two-terminal network is composed of resistors and capacitors connected in parallel with each other and is used to adjust the gain flatness and stability of the input matching network.

8. The ultra-wideband high-power matching circuit for standard power transistors as described in claim 1, characterized in that: The input bias circuit includes an input bias microstrip line branching from the input-side node, an input stabilizing resistor connected in series in the input bias microstrip line, a gate bias terminal connected to the end of the input bias microstrip line, and an input grounding capacitor connected between the gate bias terminal and the ground terminal, so that the end of the input bias microstrip line has low radio frequency impedance in the operating frequency band. The output bias circuit includes an output bias microstrip line branching from the output side node, a drain bias terminal connected to the end of the output bias microstrip line, and an output grounding capacitor connected between the drain bias terminal and the ground terminal, so that the end of the output bias microstrip line has low radio frequency impedance in the operating frequency band.

9. The ultra-wideband high-power matching circuit for a standard power transistor as described in claim 8, characterized in that: When the standard power transistor includes two symmetrically arranged dies, the input bias circuit includes two input bias microstrip line branches symmetrically arranged relative to the input combining node of the two dies, and the output bias circuit includes two output bias microstrip line branches symmetrically arranged relative to the output combining node of the two dies. The end of each input bias microstrip line branch is connected to the gate bias terminal and grounded through the corresponding input grounding capacitor, and the end of each output bias microstrip line branch is connected to the drain bias terminal and grounded through the corresponding output grounding capacitor.

10. An ultra-wideband high-power amplifier, characterized in that, Includes an ultra-wideband high-power matching circuit as described in any one of claims 1 to 9, and an RF input terminal and an RF output terminal connected to the ultra-wideband high-power matching circuit, wherein the standard power transistor is a GaN power transistor, and the input matching network and the output matching network are configured to enable the ultra-wideband high-power amplifier to operate in the 0.2 GHz to 2.5 GHz frequency band.

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