An integrated crosstalk suppression circuit for SiC MOSFETs

Abstract

The application discloses an integrated crosstalk suppression circuit for SiC MOSFET, which comprises a swing rate detection module, a gate-source voltage detection module and a control and driving module; the detection input end of the swing rate detection module is coupled to the drain of the SiC MOSFET through a high-pass network, directly detects the change direction of the drain-source voltage and correspondingly generates a swing rate judgment signal to identify the switch transient corresponding to the positive or negative crosstalk; the gate-source voltage detection module detects whether the positive abnormal change of the gate-source voltage occurs and outputs a detection signal; and the control and driving module controls the clamping transistor NM1 integrated in the chip to realize the rapid discharge of the crosstalk current according to the logic combination result of the swing rate judgment signal, the gate-source voltage detection signal and an external PWM signal. The application has the advantages of fast response speed, high integration degree, avoidance of additional loss and the like, and can simultaneously suppress the positive and negative crosstalk.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an integrated crosstalk suppression circuit for SiC MOSFETs. Background Technology

[0002] SiCMOSFETs (Silicon Carbide Field Effect Transistors) have advantages such as fast switching speed, high voltage withstand and low conduction loss, but their extremely high drain-source voltage change rate will be coupled to the gate through the gate-drain Miller capacitance.

[0003] In applications such as half-bridge, when another power device in the same bridge arm switches at high speed, the gate of the SiCMOSFET in the off state may experience a positive spike, causing false turn-on, or it may experience a large negative spike, exceeding the device's allowable negative gate voltage range, thereby reducing system reliability.

[0004] Existing crosstalk suppression schemes mainly include increasing the negative gate voltage during turn-off, reducing the turn-off loop impedance, increasing the gate-source capacitance, and setting up active auxiliary branches. However, their drawbacks are as follows: increasing the negative gate voltage during turn-off requires additional or increased negative power supply and corresponding level conversion circuitry; increasing the gate-source capacitance increases gate charge, switching delay, and drive losses; while adding additional gate capacitors during partial switching phases, or using transistors, diodes, and capacitors to form auxiliary branches to establish a low-impedance path from the gate to the negative power supply during specific periods can reduce crosstalk spikes, it usually requires additional components, timing control, and PCB routing. Some Miller clamping schemes also require waiting for the gate-source voltage to reach a set threshold before acting, resulting in a relatively delayed response time. Therefore, there is a need for an integrated crosstalk suppression circuit that does not rely on further increasing the negative gate voltage or fixing the gate capacitance, but can directly detect the rise and fall of drain-source voltage and promptly establish a low-impedance discharge path. Summary of the Invention

[0005] The present invention was made in view of the above-mentioned problems, and its object is to provide an integrated crosstalk suppression circuit for SiCMOSFET.

[0006] The objective of this invention is achieved through the following technical solution: This invention provides an integrated crosstalk suppression circuit for SiCMOSFETs, comprising: a slew rate detection module, a gate-source voltage detection module, and a control and drive module; The detection input terminal of the slew rate detection module is coupled to the drain of the SiCMOSFET through a high-pass network to directly detect the direction of change of the drain-source voltage, and generates a detection signal according to the direction of change. Based on the detection signal, a slew rate determination signal is output to identify the switching transients that cause positive or negative crosstalk. The input terminal of the gate-source voltage detection module is used to couple to the gate of the SiCMOSFET to detect whether there is a positive abnormal change in the gate-source voltage of the SiCMOSFET, and outputs a gate-source voltage detection signal. The control and drive module is used to receive the slew rate determination signal, the gate-source voltage detection signal and the external PWM signal, and determine the current crosstalk state based on the logical combination result of the three, and control the state of the clamping transistor NM1 inside the circuit. When the clamping transistor NM1 is turned on, a low-impedance path is established between the gate of the SiCMOSFET and the negative power supply VEE; when the clamping transistor NM1 is turned off, the gate driver's normal control over the SiCMOSFET is restored.

[0007] Further: The slew rate detection module includes: a positive edge detection branch for detecting the rising edge of the drain-source voltage, a negative edge detection branch for detecting the falling edge of the drain-source voltage, and an OR gate OR3 for combining the outputs of the two branches to form the slew rate determination signal; The positive edge detection branch and the negative edge detection branch acquire drain-source voltage change information through the same detection input terminal, and output valid levels through OR gate OR1 and OR gate OR2 respectively. The valid levels output by the two branches are combined by OR gate OR3 to form a slew rate determination signal.

[0008] Further: The positive edge detection branch includes resistors R2 and R3, transistor Q1, PMOS transistor MP1, inverter INV1, first delay chain, and OR gate OR1; The detection input terminal is connected to the base of transistor Q1 via resistor R2. The emitter of transistor Q1 is grounded. The collector of transistor Q1 is connected to one end of resistor R3 and the gate of PMOS transistor MP1. The drain of PMOS transistor MP1 is connected to both the input of inverter INV1 and the input of the first delay chain. The output of inverter INV1 and the output of the first delay chain are respectively connected to the two inputs of OR gate OR1. The negative edge detection branch includes resistors R2, R4, and R5, transistors Q2 and Q3, PMOS transistor MP2, inverter INV2, second delay chain, and OR gate OR2. The detection input terminal is connected to the base of transistor Q2 via resistor R2. The emitter of transistor Q2 is grounded. The collector of transistor Q2 is connected to one end of resistor R4 and the base of transistor Q3. The collector of transistor Q3 is connected to one end of resistor R5 and the gate of PMOS transistor MP2. The drain of PMOS transistor MP2 is connected to both the input of inverter INV2 and the input of the second delay chain. The output of inverter INV2 and the output of the second delay chain are respectively connected to the two inputs of OR gate OR2.

[0009] Furthermore: the gate-source voltage detection module includes comparators CMP1 and CMP2, as well as resistor R6 and capacitor C2; The gate-source voltage detection terminal VGS is connected to the non-inverting input terminal of the comparator CMP1 and one end of the resistor R6; the other end of the resistor R6 is connected to one end of the capacitor C2 and the inverting input terminal of the comparator CMP2; the other end of the capacitor C2 is grounded; the inverting input terminal of the comparator CMP1 and the non-inverting input terminal of the comparator CMP2 are grounded. The output terminals of comparator CMP1 and comparator CMP2 are respectively connected to the control and drive module.

[0010] Furthermore: the control and drive module includes inverters INV3 and INV4, AND gates AND1 and AND2, OR gate OR4, and a two-stage complementary buffer drive stage composed of PMOS transistor MP3, NMOS transistor NM2, PMOS transistor MP4 and NMOS transistor NM3; The output of OR gate OR3, the output of comparator CMP1, and the PWM input are respectively connected to the three inputs of AND gate AND1; the output of comparator CMP1 is also connected to the first input of AND gate AND2 via inverter INV3; the output of comparator CMP2 is connected to the second input of AND gate AND2; and the PWM input is also connected to the third input of AND gate AND2 via inverter INV4. The outputs of AND gate AND1 and AND gate AND2 are respectively connected to the two inputs of OR gate OR4; the output of OR gate OR4 is connected to the input of the two complementary buffer drive stages, and the output of the two complementary buffer drive stages is connected to the gate of clamp transistor NM1.

[0011] Furthermore: the output terminal of the OR gate OR4 is simultaneously connected to the gate of the PMOS transistor MP3 and the gate of the NMOS transistor NM2; the source of the PMOS transistor MP3 is connected to the positive power supply VDD, the source of the NMOS transistor NM2 is connected to the negative power supply VEE, and the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor NM2 to form a first buffer node; The first buffer node is connected to the gate of the PMOS transistor MP4 and the gate of the NMOS transistor NM3. The source of the PMOS transistor MP4 is connected to the positive power supply VDD, the source of the NMOS transistor NM3 is connected to the negative power supply VEE, and the drain of the PMOS transistor MP4 is connected to the drain of the NMOS transistor NM3 to form a second buffer node. The second buffer node is connected to the gate of the clamping transistor NM1.

[0012] Furthermore, the drain of the clamping transistor NM1 is used to connect to the gate node between the gate of the SiCMOSFET and the external gate resistor, and its source is connected to the negative power supply VEE.

[0013] Furthermore: the high-pass network coupling is composed of C1 and resistor R1; the capacitor C1 is connected between the drain and the detection input terminal, and the resistor R1 is connected between the detection input terminal and ground.

[0014] In summary, the beneficial effects of the present invention are as follows: 1. The slew rate detection module, gate-source voltage detection module, control and drive module, and clamping transistor NM1 are all integrated into the chip, reducing PCB area and system complexity.

[0015] 2. The high-pass network formed by capacitor C1 and resistor R1 in the slew rate detection module is directly coupled to the drain of the SiCMOSFET, directly detecting the rate of change of drain-source voltage. The response speed is extremely fast, ahead of the appearance of crosstalk spikes.

[0016] 3. In the slew rate detection module, each edge detection branch utilizes a combination of inverters (INV1 / INV2) and delay chains, along with OR gates (OR1 / OR2), to form an edge pulse generation circuit. This structure can generate an effective pulse with controllable width at the instant the dv / dt change begins, rather than a continuous level, ensuring that the detection signal has high timeliness and accurately indicates the occurrence window of crosstalk transients.

[0017] 4. Two independent edge detection branches are set up in the slew rate detection module—positive edge detection branch and negative edge detection branch, which simultaneously takes into account the suppression of both positive and negative crosstalk.

[0018] 5. The slew rate determination signal, the gate-source voltage detection signal (from the comparison result of CMP1 / CMP2), and the external PWM signal are logically combined and determined by the control and drive module to avoid malfunctions during normal switching.

[0019] 6. The clamping transistor NM1 is turned on only during crosstalk transients (within the effective duration of the slew rate detection pulse), establishing a low-impedance discharge path between the gate and the negative power supply VEE, providing a fast discharge path for crosstalk current and avoiding additional losses. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this drawing or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this drawing. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the circuit structure of the present invention; Figure 2 This is a schematic diagram of the working state connection of the present invention.

[0022] The purpose, features, and advantages of this accompanying drawing will be further explained in conjunction with the embodiments and with reference to the accompanying drawing. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments provided by this invention without inventive effort are within the scope of protection of this invention.

[0024] Obviously, the accompanying drawings described below are merely some examples or embodiments of the present invention. Those skilled in the art can apply the present invention to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this invention, modifications to design, manufacturing, or production based on the technical content disclosed in this invention are merely conventional technical means and should not be construed as insufficient disclosure of the present invention.

[0025] Unless otherwise specified, all embodiments and optional embodiments of the present invention can be combined with each other to form new technical solutions.

[0026] Unless otherwise specified, all technical features and optional technical features of this invention can be combined to form new technical solutions.

[0027] Unless otherwise specified, all steps of the present invention may be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, the mention that the method may also include step (c) indicates that step (c) may be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.

[0028] Unless otherwise specified, the terms "comprising" and "including" as used in this invention can be open-ended or closed-ended. For example, "comprising" and "including" can mean that other components not listed may also be included, or that only the listed components may be included.

[0029] Unless otherwise specified, the term "or" is inclusive in this invention. For example, the phrase "A or B" means "A, B, or both A and B". More specifically, the condition "A or B" is satisfied by any of the following conditions: A is true (or exists) and B is false (or does not exist); A is false (or does not exist) and B is true (or exists); or both A and B are true (or exist).

[0030] Please see Figures 1 to 2 : Figure 1 The circuit structure diagram of the present invention includes: a slew rate detection module (the area represented by 10), a gate-source voltage detection module (20), and a control and drive module (30). Please see Figure 2This is a connection diagram of the present invention during operation. The connection relationship is as follows: the detection input terminal (IN) of the slew rate detection module is coupled to the drain of the SiC MOSFET through a high-pass network (composed of R1 and C1) to directly detect the rising and falling changes of the drain-source voltage, and generates a rising edge detection signal or a falling edge detection signal according to the direction of the drain-source voltage change. After being synthesized by the logic inside the slew rate detection module, a slew rate determination signal is output to identify the switching transients that cause positive or negative crosstalk; the input terminal of the gate-source voltage detection module is coupled to the gate of the SiC MOSFET to detect the SiC... The system detects whether the gate-source voltage of the MOSFET exhibits a positive abnormal change and outputs a gate-source voltage detection signal. The control and drive module receives the slew rate determination signal, the gate-source voltage detection signal, and the external PWM signal. Based on the logical combination of these three signals, it determines the current crosstalk state and controls the internal clamping transistor NM1 to turn on or off. When clamping transistor NM1 is on, a low-impedance path is established between the gate of the SiC MOSFET and the negative power supply VEE, providing a fast discharge path for the crosstalk current. When clamping transistor NM1 is off, the gate driver restores normal control of the SiC MOSFET.

[0031] The drain of clamping transistor NM1 is connected to the gate node between the gate of the SiCMOSFET and the external gate resistor, and its source is connected to the negative power supply VEE. When clamping transistor NM1 is turned on, the low-impedance path formed between the gate node and the negative power supply VEE provides a discharge path for the gate crosstalk current during crosstalk transients. After the slew rate detection pulse ends, clamping transistor NM1 is turned off, and the gate driver resumes normal control of the SiCMOSFET.

[0032] Specifically: The slew rate detection module, as shown in the figure, includes a positive edge detection branch (resistors R2, R3, transistor Q1, PMOS transistor MP1, inverter INV1, first delay chain, and OR gate OR1) for detecting the rising edge of the drain-source voltage, a negative edge detection branch (R2, R4, R5, transistors Q2, Q3, PMOS transistor MP2, inverter INV2, second delay chain, and OR gate OR2) for detecting the falling edge of the drain-source voltage, and an OR gate OR3 for combining the outputs of the two branches into a slew rate determination signal; The positive edge detection branch and the negative edge detection branch acquire drain-source voltage change information through the same detection input terminal. When a rapid rise or fall occurs at the detection input terminal, they output effective levels through OR gate OR1 and OR gate OR2 respectively. Finally, the slew rate determination signal is output by OR gate OR3. This design uses two independent branches to capture the rising and falling edges of dv / dt respectively, ensuring that the drain-source voltage can be accurately identified regardless of which direction the sudden change is in (corresponding to the turn-off / turn-on process), thus fully covering both positive and negative crosstalk scenarios. The specific structure of the positive edge detection branch is as follows: the detection input terminal is connected to the base of transistor Q1 via resistor R2, the emitter of transistor Q1 is grounded, the collector of transistor Q1 is connected to one end of resistor R3 and the gate of PMOS transistor MP1; the drain of PMOS transistor MP1 is connected to both the input of inverter INV1 and the input of the first delay chain, and the output of inverter INV1 and the output of the first delay chain are respectively connected to the two inputs of OR gate OR1; the specific structure of the negative edge detection branch is as follows: the detection input terminal is connected to the base of transistor Q2 via resistor R2, the emitter of transistor Q2 is grounded, and the collector of transistor Q2 is connected to one end of resistor R4 and the base of transistor Q3. The collector of transistor Q3 is connected to one end of resistor R5 and the gate of PMOS transistor MP2. The drain of PMOS transistor MP2 is connected to both the input of inverter INV2 and the input of the second delay chain. The output of inverter INV2 and the output of the second delay chain are respectively connected to the two inputs of OR gate OR2. This design uses transistors and PMOS transistors to convert analog voltage changes into digital pulses. An edge pulse generation circuit is constructed using a delay chain, inverter, and OR gate (outputting a valid pulse at the moment the change begins) to ensure that the detection signal precedes the peak value of crosstalk, providing sufficient time for clamping action. The cascading of transistors Q2 / Q3 is used to realize the polarity reversal and amplification of the negative edge.

[0033] The gate-source voltage detection module includes comparators CMP1 and CMP2, as well as resistor R6 and capacitor C2. The gate-source voltage detection terminal VGS is connected to the non-inverting input terminal of comparator CMP1 and one end of resistor R6. The other end of resistor R6 is connected to one end of capacitor C2 and the inverting input terminal of comparator CMP2. The other end of capacitor C2 is grounded. The inverting input terminal of comparator CMP1 and the non-inverting input terminal of comparator CMP2 are grounded. The output terminals of comparator CMP1 and comparator CMP2 are connected to the control and drive module, forming two channels. The comparison results are used together to determine whether the gate-source voltage has a positive abnormal change, so as to logically confirm the detection result of the slew rate detection module and avoid malfunctions during normal drive conversion. In this design, CMP1 detects whether VGS exceeds the ground potential positively (a positive spike appears); CMP2 detects whether VGS is still in the abnormal range after RC filtering (providing a certain degree of noise immunity / delay judgment). The two comparison results are used together as confirmation signals to form an "AND" logic with the slew rate detection signal to avoid false clamping due to simple dv / dt interference at the normal PWM switching edge.

[0034] The control and drive module includes inverters INV3 and INV4, AND gates AND1 and AND2, OR gate OR4, and a two-stage complementary buffer drive stage composed of PMOS transistor MP3, NMOS transistor NM2, PMOS transistor MP4, and NMOS transistor NM3. The output of OR gate OR3, the output of comparator CMP1, and the PWM input are respectively connected to the three inputs of AND gate AND1. The output of comparator CMP1 is also connected to the first input of AND gate AND2 via inverter INV3. The output of comparator CMP2 is connected to the second input of AND gate AND2. The PWM input is also connected to the third input of AND gate AND2 via inverter INV4. The outputs of AND gate AND1 and AND gate AND2 are respectively connected to the two inputs of OR gate OR4. The output of OR gate OR4 is connected to the inputs of the two-stage complementary buffer drive stage, and the outputs of the two-stage complementary buffer drive stage are connected to the gate of clamp transistor NM1 to quickly switch the conduction state of clamp transistor NM1. In this design, AND1 is responsible for the "positive crosstalk scenario" (effective slew rate + CMP1 reports a positive anomaly + PWM is in the off state); AND2 is responsible for the "negative crosstalk scenario" (slew rate valid + CMP2 confirmation + PWM is in the on state); the two-stage logic is combined through OR4 to ensure that the correct trigger signal can be output in both positive and negative crosstalk windows; two-stage buffer drive stages are introduced to provide sufficient gate charging and discharging current for the subsequent NM1; In this design, the output of OR4 is connected to the gates of both PMOS transistor MP3 and NMOS transistor NM2. The source of PMOS transistor MP3 is connected to the positive power supply VDD, and the source of NMOS transistor NM2 is connected to the negative power supply VEE. The drains of PMOS transistor MP3 and NMOS transistor NM2 are connected to form a first buffer node, which is also connected to the gates of PMOS transistor MP4 and NMOS transistor NM3. The source of PMOS transistor MP4 is connected to the positive power supply VDD, and the source of NMOS transistor NM3 is connected to the negative power supply VEE. The drains of PMOS transistor MP4 and NMOS transistor NM3 are connected to form a second buffer node, which is connected to the gate of clamping transistor NM1. This design uses a cascaded (two-stage) CMOS push-pull structure, which significantly improves the peak charging and discharging current of the gate capacitor of clamping transistor NM1 compared to a single-stage inverter. This greatly shortens the turn-on / turn-off delay of NM1, ensuring that NM1 can react and recover quickly in nanosecond-level crosstalk transients.

[0035] It should be noted that the present invention is not limited to the above-described embodiments. The above embodiments are merely examples, and any embodiments that have the same structure and perform the same effects as the technical concept within the scope of the present invention are included within the scope of the present invention. Furthermore, various modifications that can be conceived by those skilled in the art to the embodiments, and other ways of constructing by combining some of the constituent elements of the embodiments, without departing from the spirit of the present invention, are also included within the scope of the present invention.

Claims

1. An integrated crosstalk suppression circuit for SiC MOSFETs, characterized in that, include: Slew rate detection module, gate-source voltage detection module, and control and drive module; The detection input terminal of the slew rate detection module is coupled to the drain of the SiCMOSFET through a high-pass network to directly detect the direction of change of the drain-source voltage, and generates a detection signal according to the direction of change. Based on the detection signal, a slew rate determination signal is output to identify the switching transients that cause positive or negative crosstalk. The input terminal of the gate-source voltage detection module is used to couple to the gate of the SiCMOSFET to detect whether there is a positive abnormal change in the gate-source voltage of the SiCMOSFET, and outputs a gate-source voltage detection signal. The control and drive module is used to receive the slew rate determination signal, the gate-source voltage detection signal and the external PWM signal, and determine the current crosstalk state based on the logical combination result of the three, and control the state of the clamping transistor NM1 inside the circuit. When the clamping transistor NM1 is turned on, a low-impedance path is established between the gate of the SiCMOSFET and the negative power supply VEE; when the clamping transistor NM1 is turned off, the gate driver's normal control over the SiCMOSFET is restored.

2. The integrated crosstalk suppression circuit for SiC MOSFET according to claim 1, characterized in that, The slew rate detection module includes: a positive edge detection branch for detecting the rising edge of the drain-source voltage, a negative edge detection branch for detecting the falling edge of the drain-source voltage, and an OR gate OR3 for combining the outputs of the two branches to form the slew rate determination signal. The positive edge detection branch and the negative edge detection branch acquire drain-source voltage change information through the same detection input terminal, and output valid levels through OR gate OR1 and OR gate OR2 respectively. The valid levels output by the two branches are combined by OR gate OR3 to form a slew rate determination signal.

3. The integrated crosstalk suppression circuit for SiC MOSFETs according to claim 2, characterized in that, The positive edge detection branch includes resistors R2 and R3, transistor Q1, PMOS transistor MP1, inverter INV1, first delay chain, and OR gate OR1. The detection input terminal is connected to the base of transistor Q1 via resistor R2. The emitter of transistor Q1 is grounded. The collector of transistor Q1 is connected to one end of resistor R3 and the gate of PMOS transistor MP1. The drain of PMOS transistor MP1 is connected to both the input of inverter INV1 and the input of the first delay chain. The output of inverter INV1 and the output of the first delay chain are respectively connected to the two inputs of OR gate OR1. The negative edge detection branch includes resistors R2, R4, and R5, transistors Q2 and Q3, PMOS transistor MP2, inverter INV2, second delay chain, and OR gate OR2. The detection input terminal is connected to the base of transistor Q2 via resistor R2. The emitter of transistor Q2 is grounded. The collector of transistor Q2 is connected to one end of resistor R4 and the base of transistor Q3. The collector of transistor Q3 is connected to one end of resistor R5 and the gate of PMOS transistor MP2. The drain of PMOS transistor MP2 is connected to both the input of inverter INV2 and the input of the second delay chain. The output of inverter INV2 and the output of the second delay chain are respectively connected to the two inputs of OR gate OR2.

4. The integrated crosstalk suppression circuit for SiC MOSFET according to claim 1, characterized in that, The gate-source voltage detection module includes comparators CMP1 and CMP2, as well as resistor R6 and capacitor C2. The gate-source voltage detection terminal VGS is connected to the non-inverting input terminal of the comparator CMP1 and one end of the resistor R6; the other end of the resistor R6 is connected to one end of the capacitor C2 and the inverting input terminal of the comparator CMP2; the other end of the capacitor C2 is grounded; the inverting input terminal of the comparator CMP1 and the non-inverting input terminal of the comparator CMP2 are grounded. The output terminals of comparator CMP1 and comparator CMP2 are respectively connected to the control and drive module.

5. The integrated crosstalk suppression circuit for SiC MOSFETs according to claim 1, characterized in that, The control and drive module includes inverters INV3 and INV4, AND gates AND1 and AND2, OR gate OR4, and a two-stage complementary buffer drive stage composed of PMOS transistor MP3, NMOS transistor NM2, PMOS transistor MP4 and NMOS transistor NM3. The output of OR gate OR3, the output of comparator CMP1, and the PWM input are respectively connected to the three inputs of AND gate AND1; the output of comparator CMP1 is also connected to the first input of AND gate AND2 via inverter INV3; the output of comparator CMP2 is connected to the second input of AND gate AND2; and the PWM input is also connected to the third input of AND gate AND2 via inverter INV4. The outputs of AND gate AND1 and AND gate AND2 are respectively connected to the two inputs of OR gate OR4; the output of OR gate OR4 is connected to the input of the two complementary buffer drive stages, and the output of the two complementary buffer drive stages is connected to the gate of clamp transistor NM1.

6. The integrated crosstalk suppression circuit for SiC MOSFETs according to claim 5, characterized in that, The output of the OR gate OR4 is simultaneously connected to the gate of the PMOS transistor MP3 and the gate of the NMOS transistor NM2; the source of the PMOS transistor MP3 is connected to the positive power supply VDD, the source of the NMOS transistor NM2 is connected to the negative power supply VEE, and the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor NM2 to form a first buffer node. The first buffer node is connected to the gate of the PMOS transistor MP4 and the gate of the NMOS transistor NM3. The source of the PMOS transistor MP4 is connected to the positive power supply VDD, the source of the NMOS transistor NM3 is connected to the negative power supply VEE, and the drain of the PMOS transistor MP4 is connected to the drain of the NMOS transistor NM3 to form a second buffer node. The second buffer node is connected to the gate of the clamping transistor NM1.

7. The integrated crosstalk suppression circuit for SiC MOSFET according to claim 1, characterized in that, The drain of the clamping transistor NM1 is connected to the gate node between the gate of the SiCMOSFET and the external gate resistor, and its source is connected to the negative power supply VEE.

8. The integrated crosstalk suppression circuit for SiC MOSFETs according to claim 1, characterized in that, The high-pass network coupling is composed of C1 and resistor R1; the capacitor C1 is connected between the drain and the detection input terminal, and the resistor R1 is connected between the detection input terminal and ground.

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