A high-voltage motor driving level conversion circuit

Abstract

The application provides a high-voltage motor driving level conversion circuit, and belongs to the technical field of high-voltage motor driving, comprising: the level conversion module comprises a bias current input end, an output state feedback end and a lock signal output end; the bias current input end of the control lock module is connected with a current source, and the bias current is input through the current source; the output state feedback end of the control lock module is connected with the output end of the level conversion module; the lock signal output end of the control lock module is connected with the adjusting end of the level conversion module; the level conversion module is used for converting the input low-voltage pulse signal into a high-voltage domain level signal; the control lock module responds to the current source current, the output state signal and the voltage of the adjusting end of the level conversion module. Therefore, the upper tube opening lock circuit and the under-voltage protection circuit in the control lock module can use a narrow pulse width, which can flip stably in the 600V high-voltage domain and also reduce the power consumption of the level conversion circuit.

Description

Technical Field

[0001] This invention belongs to the field of high voltage motor drive technology, and specifically relates to a high voltage motor drive level conversion circuit. Background Technology

[0002] In fields such as power electronics, industrial control, and new energy vehicles, the motor drive system serves as the core execution unit, and its performance directly determines the operating efficiency and reliability of the equipment. The high-side drive circuit, as a key component of the motor drive system, is responsible for controlling the on / off state of the high-side power switching transistors. Its operating voltage range often needs to cover high-voltage scenarios above 600V to meet the driving requirements of high-power, high-voltage motors.

[0003] The level conversion circuit is the core module of the high-side drive circuit. Its function is to convert low-voltage control signals (such as the logic level output by the MCU) into drive levels adapted to the high-voltage power switches. In high-voltage scenarios, the power consumption of the power switches increases significantly. For structures using charge pumps, this will increase the difficulty of charge pump design. For capacitor-pumped structures, it will greatly reduce the pumping duration, limiting the application range of this structure.

[0004] Furthermore, in high-voltage applications above 600V, the high-side drive circuit faces a severe undervoltage risk. When the high-side supply voltage falls below the threshold, the power switch cannot conduct normally, potentially leading to abnormal motor operation, switch damage, or even failure of the entire drive system. In existing technologies, high-side undervoltage protection typically requires additional detection circuitry and protection modules. This not only increases circuit complexity and cost but may also reduce the timeliness and accuracy of protection response due to coordination issues between modules, further impacting the reliability of the motor drive system.

[0005] Therefore, developing a level conversion circuit that is simple in structure, highly reliable, and has both low power consumption and high-side undervoltage protection to meet the motor drive requirements of high voltage domains above 600V has become an urgent technical problem to be solved in the field of power electronics. Summary of the Invention

[0006] In view of the problems that existing high-side drive circuits require additional detection circuits and protection modules, resulting in complex circuits, high power consumption, and low applicability, this invention proposes a high-voltage motor drive level conversion circuit. Compared with traditional level conversion circuits, this circuit has lower power consumption, integrates undervoltage protection devices, has a simple circuit structure, stable and reliable conversion, and can be applied to high voltage domains such as 600V.

[0007] This application provides a high-voltage motor drive level conversion circuit, including:

[0008] The control includes a locking module and a level conversion module; the level conversion module includes a bias current input terminal, an output status feedback terminal, and a locking signal output terminal.

[0009] The bias current input terminal of the control lock module is connected to a current source, and the bias current is connected through the current source;

[0010] The output status feedback terminal of the control locking module is connected to the output terminal of the level conversion module;

[0011] The locking signal output terminal of the control locking module is connected to the adjustment terminal of the level conversion module; the level conversion module is used to convert the input low-voltage pulse signal into a high-voltage level signal; the control locking module responds to the current source current, the output status signal, and the voltage of the adjustment terminal of the level conversion module, and is used to lock the output state of the level conversion module after the level conversion module completes a level conversion.

[0012] Preferably, the control locking module includes: a current mirror bias circuit, the input of which is connected to the current source, for providing a stable bias current to the subsequent circuit;

[0013] The upper transistor turn-on locking circuit is connected to the output of the current mirror bias circuit and is used to generate an instantaneous drive signal when the level conversion triggers the upper power transistor to turn on.

[0014] A lock signal generation circuit has its input terminal connected to the output terminal of the upper tube lock-on circuit and the output terminal of the level conversion module, and its output terminal connected to the output status feedback terminal and the lock signal output terminal, respectively, for generating and maintaining the lock signal.

[0015] The upper transistor opening and locking circuit is used to adjust the two power transistors so that the power upper transistor can be kept constantly open by the subsequent circuit.

[0016] Preferably, the current mirror bias circuit includes: a common-gate current mirror composed of a first P-tube PM1 and a second P-tube PM2, and a common-gate current mirror composed of a first N-tube NM1, a second N-tube NM2, and an eleventh N-tube NM11; the output of the current source is connected to the drain of the first N-tube NM1.

[0017] The source of the first P-type transistor PM1 is connected to the power supply BST, and the first P-type transistor PM1 and the second P-type transistor PM2 are connected to the same gate, with the gate and drain of the first P-type transistor PM1 connected.

[0018] The drain of the first P transistor PM1 is also connected to the drain of the eleventh N transistor NM11. The gate of the eleventh N transistor NM11 is connected to the reference voltage VREF. The source of the eleventh N transistor NM11 is connected to the drain of the second N transistor NM2. The source of the second N transistor NM2 is grounded. The second N transistor NM2 and the first N transistor NM1 are connected to the same gate, and the drain of the first N transistor NM1 is connected to the gate. The source of the first N transistor NM1 is grounded.

[0019] The source of the second P-type transistor PM2 is connected to the power supply BST, the drain of the second P-type transistor PM2 is connected to the drain of the third N-type transistor NM3, the drain of the third N-type transistor NM3 is connected to the gate, and the source of the third N-type transistor NM3 is connected to the floating ground terminal SH.

[0020] Preferably, the upper tube opening locking circuit includes:

[0021] The third P-tube PM3, the tenth N-tube NM10, and the fourth P-tube PM4;

[0022] The source of the third P-type transistor PM3 is connected to the power supply BST, and the gate of the third P-type transistor PM3 is connected to the P4 node of the drain of the second P-type transistor PM2; the drain of the third P-type transistor PM3 and the gate of the fourth P-type transistor PM4 are connected to the P3 node.

[0023] The drain of the tenth N transistor NM10 is connected to node P3, the gate of the tenth N transistor NM10 is connected to node P4, which is the drain of the second P transistor PM2, and the source of the tenth N transistor NM10 is connected to the floating ground terminal SH.

[0024] The source of the fourth P-type transistor PM4 is connected to the power supply BST, the drain of the fourth P-type transistor PM4 is connected to the drain of the fourth N-type transistor NM4, and the source of the fourth N-type transistor NM4 is connected to the floating ground terminal SH.

[0025] Preferably, the locking signal generation circuit further includes:

[0026] The fifth N-tube NM5, the seventh N-tube NM7, and the fourth N-tube NM4;

[0027] The drain of the fifth N-transistor NM5 is connected to the P5 node of the drain of the fourth P-transistor PM4, and the gate of the fifth N-transistor NM5 is connected to the gate of the fourth N-transistor NM4; the source of the fifth N-transistor NM5 is connected to the drain of the seventh N-transistor NM7.

[0028] The gate of the seventh N transistor NM7 is connected to the output terminal of the first inverter INV1, and the source and drain of the seventh N transistor NM7 are also connected.

[0029] Preferably, the locking signal generation circuit further includes:

[0030] The sixth N-tube, NM6, and the fifth P-tube, PM5;

[0031] The gate of the sixth N-channel transistor NM6 is connected to node P5, and the source of the sixth N-channel transistor NM6 is connected to the floating ground terminal SH.

[0032] The source of the fifth P-type transistor PM5 is connected to the power supply EST, the gate of the fifth P-type transistor PM5 is connected to the common gate point of the first P-type transistor PM1 and the second P-type transistor PM2, and the drain of the fifth P-type transistor PM5 is connected to the drain of the sixth N-type transistor NM6.

[0033] Preferably, the locking signal generation circuit further includes:

[0034] The sixth P-tube PM6, the seventh P-tube PM7, the eighth N-tube NM8, and the first inverter INV1;

[0035] The drain of the fifth P-type transistor PM5 and the sixth N-type transistor NM6 is connected to the drain of the ninth N-type transistor NM9. The gate of the ninth N-type transistor NM9 is connected to the B terminal of the control lock-up module. The source of the ninth N-type transistor NM9 is connected to the floating ground terminal SH. The drain of the ninth N-type transistor NM9 is connected to the input terminal of the second inverter INV2.

[0036] The source of the sixth P-type transistor PM6 is connected to the power supply BST, the gate of the sixth P-type transistor PM6 is connected to the output terminal of the second inverter INV2 and the input terminal of the first inverter INV1, the drain of the sixth P-type transistor PM6 is connected to the gate of the seventh P-type transistor PM7, and the drain of the sixth P-type transistor PM6 serves as the C terminal.

[0037] The output of the first inverter INV1 is connected to the gate of the eighth N transistor NM8 and the gate of the seventh N transistor NM7. The source of the seventh P transistor PM7 is connected to the power supply BST, the drain of the seventh P transistor PM7 is connected to the drain of the eighth N transistor NM8, and the source of the eighth N transistor NM8 is grounded at SH.

[0038] Preferably, the locking signal generation circuit further includes:

[0039] Third inverter INV3 and fourth inverter INV4;

[0040] The third inverter INV3 and the fourth inverter INV4 are connected in reverse parallel, and the first end of the parallel connection is connected to the drain of the seventh P-type transistor PM7 and the eighth N-type transistor NM8, and the second end of the parallel connection is used as point B.

[0041] Preferably, the level conversion module includes:

[0042] The eighth P-tube PM8, the ninth P-tube PM9, the twelfth N-tube NM12, the thirteenth N-tube NM13, the first resistor R1, and the second resistor R2;

[0043] The source of the eighth P-type transistor PM8 is connected to the power supply BST, the gate of the eighth P-type transistor PM8 is connected to the drain of the ninth P-type transistor PM9, and the drain of the eighth P-type transistor PM8 is connected to the first terminal of the first resistor R1 and to the gate of the ninth P-type transistor PM9.

[0044] The second end of the first resistor R1 is connected to the drain of the twelfth N transistor NM12, the gate of the twelfth N transistor NM12 is connected to the input signal INN, and the source of the twelfth N transistor NM12 is grounded.

[0045] The source of the ninth P-type transistor PM9 is connected to the power supply BST, the gate of the ninth P-type transistor PM9 is connected to the drain of the eighth P-type transistor PM8, and the drain of the ninth P-type transistor PM9 is connected to the first end of the second resistor R2 and to the gate of the eighth P-type transistor PM8.

[0046] The second end of the second resistor R2 is connected to the drain of the thirteenth N transistor NM13, the gate of the thirteenth N transistor NM13 is connected to the input signal INP, and the source of the thirteenth N transistor NM13 is grounded.

[0047] Preferably, the level conversion module further includes:

[0048] Fourteenth N-tube NM14, fifteenth N-tube NM15, tenth P-tube PM10 and eleventh P-tube PM11;

[0049] The drain of the fourteenth N transistor NM14 is connected to the P2 node led out from the drain of the ninth P transistor PM9, and the gate and source of the fourteenth N transistor NM14 are connected and connected to the floating ground terminal SH.

[0050] The drain of the fifteenth N transistor NM15 is connected to the P1 node led out from the drain of the eighth P transistor PM8, and the gate and source of the fifteenth N transistor NM15 are connected and connected to the floating ground terminal SH.

[0051] The source of the tenth P-type transistor PM10 is connected to the power supply BST, and the gate of the tenth P-type transistor PM10 is connected to the P1 node and the drain of the fifteenth N-type transistor NM15.

[0052] The drain of the tenth P-tube PM10 is connected to the drain of the eleventh P-tube PM11; the drains of the tenth P-tube PM10 and the eleventh P-tube PM11 are connected to a node as the output terminal.

[0053] The gate of the eleventh P-type transistor PM11 is connected to the P2 node and the drain of the fourteenth N-type transistor NM14. The drain of the eleventh P-type transistor PM11 is connected to the floating ground terminal SH.

[0054] The gate of the eleventh P-type transistor PM11 is also connected to the first end of the second resistor R2, which in turn connects to the C terminal of the control lock module.

[0055] The beneficial effects of this invention are as follows: Based on the above technical solution, this application includes a control locking module and a level conversion module; the level conversion module includes a bias current input terminal, an output status feedback terminal, and a lock signal output terminal; the bias current input terminal of the control locking module is connected to a current source, and a bias current is input through the current source; the output status feedback terminal of the control locking module is connected to the output terminal of the level conversion module; the lock signal output terminal of the control locking module is connected to the adjustment terminal of the level conversion module; the level conversion module is used to convert the input low-voltage pulse signal into a high-voltage level signal; the control locking module responds to the current of the current source, the output status signal, and the voltage of the adjustment terminal of the level conversion module, and is used to lock the output state of the level conversion module after the level conversion module completes one level conversion. Therefore, by controlling the upper transistor to enable the locking circuit in the control locking module, a narrow pulse width can be used, ensuring accurate and stable switching in 600V or other high-voltage domains while reducing the power consumption of the level conversion circuit, reducing the complexity of the high-voltage motor drive circuit, and improving the reliability and applicability of the circuit.

[0056] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description and the drawings. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 The topology diagram of the control locking module in an embodiment of this application is shown;

[0059] Figure 2 A topology diagram of the level conversion module in an embodiment of this application is shown. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," "longitudinal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings.

[0062] This application provides a high-voltage motor drive level conversion circuit, including:

[0063] The control includes a locking module and a level conversion module; the level conversion module includes a bias current input terminal, an output status feedback terminal, and a locking signal output terminal.

[0064] The bias current input terminal of the control lock module is connected to a current source, and the bias current is connected through the current source;

[0065] The output status feedback terminal of the control locking module is connected to the output terminal of the level conversion module;

[0066] The locking signal output terminal of the control locking module is connected to the adjustment terminal of the level conversion module; the level conversion module is used to convert the input low-voltage pulse signal into a high-voltage level signal; the control locking module responds to the current source current, the output status signal, and the voltage of the adjustment terminal of the level conversion module, and is used to lock the output state of the level conversion module after the level conversion module completes a level conversion.

[0067] Preferably, the control locking module includes: a current mirror bias circuit, the input of which is connected to the current source, for providing a stable bias current to the subsequent circuit;

[0068] The upper transistor turn-on locking circuit is connected to the output of the current mirror bias circuit and is used to generate an instantaneous drive signal when the level conversion triggers the upper power transistor to turn on.

[0069] A lock signal generation circuit has its input terminal connected to the output terminal of the upper tube lock-on circuit and the output terminal of the level conversion module, and its output terminal connected to the output status feedback terminal and the lock signal output terminal, respectively, for generating and maintaining the lock signal.

[0070] The upper transistor opening and locking circuit is used to adjust the two power transistors so that the power upper transistor can be kept constantly open by the subsequent circuit.

[0071] Specifically, preferably, the current mirror bias circuit includes: a common-gate current mirror composed of a first P-tube PM1 and a second P-tube PM2, and a common-gate current mirror composed of a first N-tube NM1, a second N-tube NM2, and an eleventh N-tube NM11; the output of the current source is connected to the drain of the first N-tube NM1.

[0072] The source of the first P-type transistor PM1 is connected to the power supply BST, and the first P-type transistor PM1 and the second P-type transistor PM2 are connected to the same gate, with the gate and drain of the first P-type transistor PM1 connected.

[0073] The drain of the first P transistor PM1 is also connected to the drain of the eleventh N transistor NM11. The gate of the eleventh N transistor NM11 is connected to the reference voltage VREF. The source of the eleventh N transistor NM11 is connected to the drain of the second N transistor NM2. The source of the second N transistor NM2 is grounded. The second N transistor NM2 and the first N transistor NM1 are connected to the same gate, and the drain of the first N transistor NM1 is connected to the gate. The source of the first N transistor NM1 is grounded.

[0074] The source of the second P-type transistor PM2 is connected to the power supply BST, the drain of the second P-type transistor PM2 is connected to the drain of the third N-type transistor NM3, the drain of the third N-type transistor NM3 is connected to the gate, and the source of the third N-type transistor NM3 is connected to the floating ground terminal SH.

[0075] Specifically, the upper tube opening locking circuit includes:

[0076] The third P-tube PM3, the tenth N-tube NM10, and the fourth P-tube PM4;

[0077] The source of the third P-type transistor PM3 is connected to the power supply BST, and the gate of the third P-type transistor PM3 is connected to the P4 node of the drain of the second P-type transistor PM2; the drain of the third P-type transistor PM3 and the gate of the fourth P-type transistor PM4 are connected to the P3 node.

[0078] The drain of the tenth N transistor NM10 is connected to node P3, the gate of the tenth N transistor NM10 is connected to node P4, which is the drain of the second P transistor PM2, and the source of the tenth N transistor NM10 is connected to the floating ground terminal SH.

[0079] The source of the fourth P-type transistor PM4 is connected to the power supply BST, the drain of the fourth P-type transistor PM4 is connected to the drain of the fourth N-type transistor NM4, and the source of the fourth N-type transistor NM4 is connected to the floating ground terminal SH.

[0080] Specifically, preferably, the locking signal generation circuit further includes:

[0081] The fifth N-tube NM5, the seventh N-tube NM7, and the fourth N-tube NM4;

[0082] The drain of the fifth N-transistor NM5 is connected to the P5 node of the drain of the fourth P-transistor PM4, and the gate of the fifth N-transistor NM5 is connected to the gate of the fourth N-transistor NM4; the source of the fifth N-transistor NM5 is connected to the drain of the seventh N-transistor NM7.

[0083] The gate of the seventh N transistor NM7 is connected to the output terminal of the first inverter INV1, and the source and drain of the seventh N transistor NM7 are also connected.

[0084] Preferably, the locking signal generation circuit further includes:

[0085] The sixth N-tube, NM6, and the fifth P-tube, PM5;

[0086] The gate of the sixth N-channel transistor NM6 is connected to node P5, and the source of the sixth N-channel transistor NM6 is connected to the floating ground terminal SH.

[0087] The source of the fifth P-type transistor PM5 is connected to the power supply EST, the gate of the fifth P-type transistor PM5 is connected to the common gate point of the first P-type transistor PM1 and the second P-type transistor PM2, and the drain of the fifth P-type transistor PM5 is connected to the drain of the sixth N-type transistor NM6.

[0088] Preferably, the locking signal generation circuit further includes:

[0089] The sixth P-tube PM6, the seventh P-tube PM7, the eighth N-tube NM8, and the first inverter INV1;

[0090] The drain of the fifth P-type transistor PM5 and the sixth N-type transistor NM6 is connected to the drain of the ninth N-type transistor NM9. The gate of the ninth N-type transistor NM9 is connected to the B terminal of the control lock-up module. The source of the ninth N-type transistor NM9 is connected to the floating ground terminal SH. The drain of the ninth N-type transistor NM9 is connected to the input terminal of the second inverter INV2.

[0091] The source of the sixth P-type transistor PM6 is connected to the power supply BST, the gate of the sixth P-type transistor PM6 is connected to the output terminal of the second inverter INV2 and the input terminal of the first inverter INV1, the drain of the sixth P-type transistor PM6 is connected to the gate of the seventh P-type transistor PM7, and the drain of the sixth P-type transistor PM6 serves as the C terminal.

[0092] The output of the first inverter INV1 is connected to the gate of the eighth N transistor NM8 and the gate of the seventh N transistor NM7. The source of the seventh P transistor PM7 is connected to the power supply BST, the drain of the seventh P transistor PM7 is connected to the drain of the eighth N transistor NM8, and the source of the eighth N transistor NM8 is grounded at SH.

[0093] Preferably, the locking signal generation circuit further includes:

[0094] Third inverter INV3 and fourth inverter INV4;

[0095] The third inverter INV3 and the fourth inverter INV4 are connected in reverse parallel, and the first end of the parallel connection is connected to the drain of the seventh P-type transistor PM7 and the eighth N-type transistor NM8, and the second end of the parallel connection is used as point B.

[0096] The control and locking module in this application will be described in detail below with reference to the accompanying drawings.

[0097] As an optional implementation method, such as Figure 1 As shown, the control locking module includes PMOS devices PM1, PM2, PM3, PM4, PM5, PM6, PM7, NMOS devices NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, high-voltage NMOS device NM11, PNP devices Q1, Q2, and inverters INV1, INV2, INV3, INV4.

[0098] It should be noted that conventional abbreviations can be used to refer to PMOS and NMOS devices in this application. The alphanumeric combination in this specification refers to conventional devices. For example, PM1 represents the first P-type transistor, i.e., the position of the P-type MOS transistor in the figure; NM1 represents the first N-type transistor, i.e., the position of the N-type MOS transistor in the figure.

[0099] In the control lockout module, the source terminal of NM1 is grounded, and its gate terminal is connected to the drain terminal of NM1 and the gate terminal of NM2, and is input through terminal A; the source terminal of NM2 is grounded, and its drain terminal is the source terminal of NM11; the gate terminal of NM11 is connected to the reference VREF, and its drain terminal is connected to the drain and gate terminals of PM1, PM2, and PM5; the source terminal of PM1 is connected to BST; the source terminal of PM2 is connected to BST, and its drain terminal is connected to the gate terminals of PM5, PM3, PM10, NM3, and NM4; the source terminal of PM3 is connected to BST, and its drain terminal is connected to the drain terminal of NM10 and the gate terminal of PM4; the source terminal of NM10 is connected to floating ground SH; the source terminal of NM3 is connected to floating ground SH, and its gate terminal is connected to the gate terminal of NM4 and the gate terminal of NM5; the source terminal of PM4 is connected to BST, and its drain terminal is connected to the drain terminal of NM4, the drain terminal of NM5, the gate terminal of NM6, and Q2. The base and collector of NM4 are connected; the source of NM4 is connected to the floating ground SH; the emitter of Q2 is connected to the base and collector of Q1; the emitter of Q1 is connected to BST; the source of NM5 is connected to the drain of NM7; the gate of NM7 is connected to the output of inverter INV1 and the gate of NM8; the source of NM8 is connected to the floating ground SH, the drain of NM8 is connected to the drain of PM7, the input of inverter INV3 and the output of inverter INV4; the output of inverter INV3 and the input of inverter INV4 are connected together, and the output is B. Inverters INV3 and INV4 form a latch; the source of PM7 is connected to BST, and the gate of PM7 is connected to the drain and C of PM6; the source of PM6 is connected to BST, and the gate of PM6 is connected to the input of inverter INV1 and the output of inverter INV2; the drain of gate 6 of NM9 is connected to the floating ground SH; the source of PM5 is connected to BST. The gate terminal of NM9 is connected to terminal B, the source terminal is connected to floating ground SH, and the drain terminal is connected to the input of inverter INV2, the drain terminal of NM6, and the drain terminal of PM5.

[0100] In some specific implementations, the second P-tube PM2, the third P-tube PM3, the fourth P-tube PM4, the third N-tube NM3, and the tenth N-tube NM10 constitute the upper transistor turn-on latching circuit. When the input pulse arrives, the power upper transistor turns on, causing both SH and BST to rise. During the rise, the current of PM2 increases, pulling the P4 node high. This pulls the P4 node low through PM3 and NM10, which in turn pulls the P5 node high through PM4, thus keeping the power upper transistor constantly on through the subsequent circuit. It can be seen that SH and BST begin to change (i.e., the power upper transistor is on, and the lower transistor is off). Even if the input pulse width signal is turned off, the system will force the upper transistor to remain on, continuing the low-to-high transition. That is, the input control signal pulse width can be less than the power output transition time. For 600V or other high-voltage domains, the power output typically takes a long time to complete one transition. This structure can use a narrow pulse width, ensuring accurate and stable transitions while reducing the power consumption of the level conversion circuit.

[0101] In another embodiment, see Figure 2The level conversion module includes:

[0102] The eighth P-tube PM8, the ninth P-tube PM9, the twelfth N-tube NM12, the thirteenth N-tube NM13, the first resistor R1, and the second resistor R2;

[0103] The source of the eighth P-type transistor PM8 is connected to the power supply BST, the gate of the eighth P-type transistor PM8 is connected to the drain of the ninth P-type transistor PM9, and the drain of the eighth P-type transistor PM8 is connected to the first terminal of the first resistor R1 and to the gate of the ninth P-type transistor PM9.

[0104] The second end of the first resistor R1 is connected to the drain of the twelfth N transistor NM12, the gate of the twelfth N transistor NM12 is connected to the input signal INN, and the source of the twelfth N transistor NM12 is grounded.

[0105] The source of the ninth P-type transistor PM9 is connected to the power supply BST, the gate of the ninth P-type transistor PM9 is connected to the drain of the eighth P-type transistor PM8, and the drain of the ninth P-type transistor PM9 is connected to the first end of the second resistor R2 and to the gate of the eighth P-type transistor PM8.

[0106] The second end of the second resistor R2 is connected to the drain of the thirteenth N transistor NM13, the gate of the thirteenth N transistor NM13 is connected to the input signal INP, and the source of the thirteenth N transistor NM13 is grounded.

[0107] Specifically, the level conversion module further includes:

[0108] The fourteenth N-tube NM14 and the fifteenth N-tube NM15;

[0109] The drain of the fourteenth N transistor NM14 is connected to the P2 node led out from the drain of the ninth P transistor PM9, and the gate and source of the fourteenth N transistor NM14 are connected and connected to the floating ground terminal SH.

[0110] The drain of the fifteenth N-transistor NM15 is connected to the P1 node derived from the drain of the eighth P-transistor PM8, and the gate and source of the fifteenth N-transistor NM15 are connected to the floating ground terminal SH.

[0111] Specifically, the level conversion module further includes:

[0112] Tenth P-tube PM10 and eleventh P-tube PM11;

[0113] The source of the tenth P-type transistor PM10 is connected to the power supply BST, and the gate of the tenth P-type transistor PM10 is connected to the P1 node and the drain of the fifteenth N-type transistor NM15.

[0114] The drain of the tenth P-tube PM10 is connected to the drain of the eleventh P-tube PM11; the drains of the tenth P-tube PM10 and the eleventh P-tube PM11 are connected to a node as the output terminal.

[0115] The gate of the eleventh P-type transistor PM11 is connected to the P2 node and the drain of the fourteenth N-type transistor NM14. The drain of the eleventh P-type transistor PM11 is connected to the floating ground terminal SH.

[0116] The gate of the eleventh P-type transistor PM11 is also connected to the first end of the second resistor R2, which in turn connects to the C terminal of the control lock module.

[0117] The level conversion module in this application will be described in detail below with reference to the accompanying drawings.

[0118] As an optional implementation method, such as Figure 2 As shown, the level conversion circuit module includes PMOS devices PM8, PM9, PM10, and PM11, NMOS devices NM14 and NM15, high-voltage NMOS devices NM12 and NM13, current source I1, first resistor R1, and second resistor R2.

[0119] The gate of NM12 is connected to the input INN, the source is grounded, and the drain is connected to one end of resistor R1; the other end of R1 is connected to the gate of PM9, the drain of PM8, the gate of PM10, and the drain of NM15; the gate of PM8 is connected to the drain of PM9, the gate of PM11, the drain of NM14, the C terminal of control module X1, one end of resistor R2, and the source is connected to BST; the other end of resistor R2 is connected to the drain of NM13; the source of PM9 is connected to BST; the gate and source of NM15 are connected to floating ground SH; the gate and source of NM14 are connected to floating ground SH; the source of PM10 is connected to BST, the drain is connected to the source of PM11, the B terminal of control module X1, and outputs OUT; the drain of PM11 is connected to floating ground SH; the source of NM13 is grounded, and the gate is connected to the input INP; the current source I1 is connected to the A terminal of control module X1.

[0120] The level conversion circuit is mainly used for high-side level conversion in motor drive chips. Compared with traditional level conversion circuits, it has lower power consumption, thereby reducing the burden on the charge pump and pump voltage capacitor. Its core idea is that the input of the level conversion circuit is a pulse signal, and the other end is normally off. Within the pulse signal time range, the on or off signal is locked by a latch, thereby ensuring that the power output of the subsequent stage completes the low-to-high or high-to-low conversion. Since the input is a pulse signal, the main circuit of the level conversion circuit only consumes power during the pulse width process. Especially when the level conversion circuit operates in a high voltage domain such as 600V, the power consumption is greatly reduced.

[0121] The basic principle of the level conversion circuit in this application is as follows: Figure 2As shown, when the input pulse width of NM12 is met and the input of NM13 is constantly low, the output of node P1 in the left branch is low, the output of node P2 in the right branch is high, and LST outputs a high level, turning off the power transistor. The output stage begins to change from high to low, and then both NM12 and NM13 are turned off. During this process, SH leads BST to go low. Because NM12 and NM13 are turned off, the voltages of nodes P1 and P2 decrease with the decrease of BST, but because the charge they contain is discharged by PM8 and PM9, these nodes remain at a high level. At this time, as long as the X1 module latches the OUT output high value during the high-to-low transition, the high-to-low transition can be completed normally.

[0122] When NM13 is pulse width and NM12 is low, node P2 in the right branch goes low, node P1 in the left branch goes high, and OUT outputs a low level, driving the subsequent driver stage to turn on the power transistor. The output stage transitions from low to high, and then both NM12 and NM13 turn off. During this process, SH, along with BST, transitions from low to high. Because NM12 and NM13 are off, the voltages of nodes P1 and P2 increase with SH. Since their charge is injected by NM14 and NM15, these nodes are at a low level, and OUT outputs high, driving the subsequent driver stage to turn off the power transistor. If module X1 is locked at a low level, the low-to-high transition can be completed normally.

[0123] As can be seen, as long as the control locking module can lock the signal during the low-to-high or high-to-low transition, level conversion can be completed. The control locking module mainly has three working modes: 1. Level conversion to achieve low-to-high, driving the subsequent power transistor to turn on; 2. Level conversion to achieve high-to-low, driving the subsequent power transistor to turn off; 3. After the power transistor is turned on, it performs undervoltage detection and protection for the power transistor. The working principle of the control module X1 is as follows:

[0124] Power transistor turn-on: The control module X1 is powered by the high-voltage device NM11. During the boost process, SH and BST go high, and the PM1 current increases accordingly, exceeding the current I1 supplied through port A. This process raises node P4, thus turning off PM3. Node P3 is clamped to SH by NM10. When node P4 is high, NM10 is turned on, clamping node P3 low. Without this device, node P3 would be floating. PM4 turns on, raising node P5, causing node P6 to output low, resulting in a low OUT output and turning on the power transistor. When SH and BST no longer change, the PM1 current decreases to the current source I1, causing P4 to decrease. NM10 can only handle a small current, and P3 goes high.

[0125] Power transistor turn-off: When BST and SH change from high to low, OUT is high, the right branch P8 node is high, OUT pulls P6 to 0, the latch input is left floating, and the latch outputs high at all times.

[0126] This circuit is used in the high-side level conversion circuit of motor drive. Through innovative low-power architecture and control module, it significantly reduces static and dynamic power consumption while ensuring the correctness of conversion. At the same time, the circuit achieves undervoltage protection function by simply adding two additional transistors in the control module. The circuit structure is simple and can be used for high-voltage applications using only ordinary low-voltage devices and ordinary high-voltage MOS devices corresponding to 600V or other voltage domains.

[0127] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A high-voltage motor drive level conversion circuit, characterized in that, include: Control locking module and level conversion module; The level conversion module includes a bias current input terminal, an output status feedback terminal, and a lock signal output terminal; The bias current input terminal of the control lock module is connected to a current source, and the bias current is connected through the current source; The output status feedback terminal of the control locking module is connected to the output terminal of the level conversion module; The locking signal output terminal of the control locking module is connected to the adjustment terminal of the level conversion module; The level conversion module is used to convert the input low-voltage pulse signal into a high-voltage level signal; The control locking module responds to the current source current, the output status signal, and the adjustment terminal voltage of the level conversion module, and is used to lock the output state of the level conversion module after the level conversion module completes a level conversion.

2. The circuit according to claim 1, characterized in that, The control locking module includes: a current mirror bias circuit, the input of which is connected to the current source to provide a stable bias current for the subsequent circuit. The upper transistor turn-on locking circuit is connected to the output of the current mirror bias circuit and is used to generate an instantaneous drive signal when the level conversion triggers the upper power transistor to turn on. A lock signal generation circuit has its input terminal connected to the output terminal of the upper tube lock-on circuit and the output terminal of the level conversion module, and its output terminal connected to the output status feedback terminal and the lock signal output terminal, respectively, for generating and maintaining the lock signal. The upper transistor opening and locking circuit is used to adjust the two power transistors so that the power upper transistor can be kept constantly open by the subsequent circuit.

3. The circuit according to claim 2, characterized in that, The current mirror bias circuit includes: a common-gate current mirror composed of a first P-tube PM1 and a second P-tube PM2, and a common-gate current mirror composed of a first N-tube NM1, a second N-tube NM2, and an eleventh N-tube NM11; the output of the current source is connected to the drain of the first N-tube NM1. The source of the first P-type transistor PM1 is connected to the power supply BST, and the first P-type transistor PM1 and the second P-type transistor PM2 are connected to the same gate, with the gate and drain of the first P-type transistor PM1 connected. The drain of the first P transistor PM1 is also connected to the drain of the eleventh N transistor NM11. The gate of the eleventh N transistor NM11 is connected to the reference voltage VREF. The source of the eleventh N transistor NM11 is connected to the drain of the second N transistor NM2. The source of the second N transistor NM2 is grounded. The second N transistor NM2 and the first N transistor NM1 are connected to the same gate, and the drain of the first N transistor NM1 is connected to the gate. The source of the first N transistor NM1 is grounded. The source of the second P-type transistor PM2 is connected to the power supply BST, the drain of the second P-type transistor PM2 is connected to the drain of the third N-type transistor NM3, the drain of the third N-type transistor NM3 is connected to the gate, and the source of the third N-type transistor NM3 is connected to the floating ground terminal SH.

4. The circuit according to claim 2, characterized in that, The upper tube opening locking circuit includes: The third P-tube PM3, the tenth N-tube NM10, and the fourth P-tube PM4; The source of the third P-type transistor PM3 is connected to the power supply BST, and the gate of the third P-type transistor PM3 is connected to the P4 node of the drain of the second P-type transistor PM2; the drain of the third P-type transistor PM3 and the gate of the fourth P-type transistor PM4 are connected to the P3 node. The drain of the tenth N transistor NM10 is connected to node P3, the gate of the tenth N transistor NM10 is connected to node P4, which is the drain of the second P transistor PM2, and the source of the tenth N transistor NM10 is connected to the floating ground terminal SH. The source of the fourth P-type transistor PM4 is connected to the power supply BST, the drain of the fourth P-type transistor PM4 is connected to the drain of the fourth N-type transistor NM4, and the source of the fourth N-type transistor NM4 is connected to the floating ground terminal SH.

5. The circuit according to claim 1, characterized in that, The locking signal generation circuit further includes: The fifth N-tube NM5, the seventh N-tube NM7, and the fourth N-tube NM4; The drain of the fifth N-transistor NM5 is connected to the P5 node of the drain of the fourth P-transistor PM4, and the gate of the fifth N-transistor NM5 is connected to the gate of the fourth N-transistor NM4; the source of the fifth N-transistor NM5 is connected to the drain of the seventh N-transistor NM7. The gate of the seventh N transistor NM7 is connected to the output terminal of the first inverter INV1, and the source and drain of the seventh N transistor NM7 are also connected.

6. The circuit according to claim 5, characterized in that, The locking signal generation circuit further includes: The sixth N-tube, NM6, and the fifth P-tube, PM5; The gate of the sixth N-channel transistor NM6 is connected to node P5, and the source of the sixth N-channel transistor NM6 is connected to the floating ground terminal SH. The source of the fifth P-type transistor PM5 is connected to the power supply EST, the gate of the fifth P-type transistor PM5 is connected to the common gate point of the first P-type transistor PM1 and the second P-type transistor PM2, and the drain of the fifth P-type transistor PM5 is connected to the drain of the sixth N-type transistor NM6.

7. The circuit according to claim 6, characterized in that, The locking signal generation circuit further includes: The sixth P-tube PM6, the seventh P-tube PM7, the eighth N-tube NM8, and the first inverter INV1; The drain of the fifth P-type transistor PM5 and the sixth N-type transistor NM6 is connected to the drain of the ninth N-type transistor NM9. The gate of the ninth N-type transistor NM9 is connected to the B terminal of the control lock-up module. The source of the ninth N-type transistor NM9 is connected to the floating ground terminal SH. The drain of the ninth N-type transistor NM9 is connected to the input terminal of the second inverter INV2. The source of the sixth P-type transistor PM6 is connected to the power supply BST, the gate of the sixth P-type transistor PM6 is connected to the output terminal of the second inverter INV2 and the input terminal of the first inverter INV1, the drain of the sixth P-type transistor PM6 is connected to the gate of the seventh P-type transistor PM7, and the drain of the sixth P-type transistor PM6 serves as the C terminal. The output of the first inverter INV1 is connected to the gate of the eighth N transistor NM8 and the gate of the seventh N transistor NM7. The source of the seventh P transistor PM7 is connected to the power supply BST, the drain of the seventh P transistor PM7 is connected to the drain of the eighth N transistor NM8, and the source of the eighth N transistor NM8 is grounded at SH.

8. The circuit according to claim 7, characterized in that, The locking signal generation circuit further includes: Third inverter INV3 and fourth inverter INV4; The third inverter INV3 and the fourth inverter INV4 are connected in reverse parallel, and the first end of the parallel connection is connected to the drain of the seventh P-type transistor PM7 and the eighth N-type transistor NM8, and the second end of the parallel connection is used as point B.

9. The circuit according to claim 1, characterized in that, The level conversion module includes: The eighth P-tube PM8, the ninth P-tube PM9, the twelfth N-tube NM12, the thirteenth N-tube NM13, the first resistor R1, and the second resistor R2; The source of the eighth P-type transistor PM8 is connected to the power supply BST, the gate of the eighth P-type transistor PM8 is connected to the drain of the ninth P-type transistor PM9, and the drain of the eighth P-type transistor PM8 is connected to the first terminal of the first resistor R1 and to the gate of the ninth P-type transistor PM9. The second end of the first resistor R1 is connected to the drain of the twelfth N transistor NM12, the gate of the twelfth N transistor NM12 is connected to the input signal INN, and the source of the twelfth N transistor NM12 is grounded. The source of the ninth P-type transistor PM9 is connected to the power supply BST, the gate of the ninth P-type transistor PM9 is connected to the drain of the eighth P-type transistor PM8, and the drain of the ninth P-type transistor PM9 is connected to the first end of the second resistor R2 and to the gate of the eighth P-type transistor PM8. The second end of the second resistor R2 is connected to the drain of the thirteenth N transistor NM13, the gate of the thirteenth N transistor NM13 is connected to the input signal INP, and the source of the thirteenth N transistor NM13 is grounded.

10. The circuit according to claim 9, characterized in that, The level conversion module further includes: Fourteenth N-tube NM14, fifteenth N-tube NM15, tenth P-tube PM10 and eleventh P-tube PM11; The drain of the fourteenth N transistor NM14 is connected to the P2 node led out from the drain of the ninth P transistor PM9, and the gate and source of the fourteenth N transistor NM14 are connected and connected to the floating ground terminal SH. The drain of the fifteenth N transistor NM15 is connected to the P1 node led out from the drain of the eighth P transistor PM8, and the gate and source of the fifteenth N transistor NM15 are connected and connected to the floating ground terminal SH. The source of the tenth P-type transistor PM10 is connected to the power supply BST, and the gate of the tenth P-type transistor PM10 is connected to the P1 node and the drain of the fifteenth N-type transistor NM15. The drain of the tenth P-tube PM10 is connected to the drain of the eleventh P-tube PM11; the drains of the tenth P-tube PM10 and the eleventh P-tube PM11 are connected to a node as the output terminal. The gate of the eleventh P-type transistor PM11 is connected to the P2 node and the drain of the fourteenth N-type transistor NM14. The drain of the eleventh P-type transistor PM11 is connected to the floating ground terminal SH. The gate of the eleventh P-type transistor PM11 is also connected to the first end of the second resistor R2, which in turn connects to the C terminal of the control lock module.

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