A digital isolator with high common mode rejection

Abstract

The application relates to the field of digital isolators, in particular to a digital isolator with high common-mode anti-interference degree, a rail-to-rail amplifier comprising a filtering module, an input pair tube module and a folding operational amplifier, the input pair tube module comprising MOS tubes P1, P2 and N1, N2, a common-mode voltage VCM1 being input to the gate of the MOS tube P1, the gate of the MOS tube P2 and the gate of the MOS tube N1, and the gate of the MOS tube N2; the front-end filtering module filters low-frequency noise of an input signal, when positive common-mode interference occurs, the MOS tube N1 and the MOS tube N2 are turned on, and the demodulation amplifier keeps the amplification function; when negative common-mode interference occurs, the MOS tube P1 and the MOS tube P2 are turned on, the demodulation amplifier keeps the amplification function, and the purpose of keeping normal signal transmission without reducing the capacitance value of the isolation module is achieved.

Description

Technical Field

[0001] This invention relates to the field of digital isolators, and more specifically to a digital isolator with high common-mode immunity. Background Technology

[0002] A digital isolator is a core electronic device that can transmit digital signals between circuits at different potentials while blocking direct current paths and achieving electrical isolation. A digital isolator mainly consists of a transmitter and a receiver, relying on internal capacitive coupling, magnetic coupling, and other technologies to build an isolation barrier. These typically include capacitive isolation using silicon dioxide as the dielectric, magnetic isolation based on a micro-transformer structure, GMR / TMR magnetoresistive coupling, RF coupling, and other technical paths. The signal completes the transmission process through a complete flow: input buffering, encoding and modulation, passing through the isolation barrier, demodulation and decoding, and output driving. Low-frequency signals are further modulated by PWM before passing through the isolation layer. Compared to traditional optocouplers, it relies on semiconductor technology and has significant advantages such as high transmission speed (up to Gbps), no LED aging issues, longer lifespan, lower power consumption, and higher integration. It is gradually replacing traditional optocouplers as the mainstream isolation solution.

[0003] Existing digital isolators typically use NMOS input pairs for their demodulation amplifiers. When there is positive common-mode interference, the common-mode voltage rises, approaching the power supply voltage. Because it's an NMOS input, the amplifier still functions normally, and the chip operates correctly. However, when there is negative common-mode interference, the common-mode voltage drops, potentially falling close to ground. This causes the NMOS input pairs to cut off, the amplifier loses its amplification function, and the chip fails. To improve the common-mode immunity of digital isolators, current technology typically minimizes the values ​​of high-voltage isolation capacitors and bias resistors in the signal path to reduce the impact of common-mode interference. However, if the values ​​of these capacitors and resistors are too small, the chip's noise immunity decreases, affecting normal signal transmission and leading to abnormal chip function. Summary of the Invention

[0004] The purpose of this invention is to provide a digital isolator with high common-mode immunity, aiming to improve the problem of poor common-mode immunity and noise immunity of conventional digital isolators.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A digital isolator with high common-mode interference immunity includes a primary-side chip, an isolation capacitor module, and a secondary-side chip connected in series. The secondary chip includes a demodulation amplifier, an envelope comparator, and an output driver module connected in series. The demodulation amplifier includes a rail-to-rail amplifier, a fully differential amplifier, and a source follower connected in series. The rail-to-rail amplifier includes a filter module, an input transistor module, and a folded operational amplifier. The input transistor module includes MOSFETs P1, P2, N1, and N2. A common-mode voltage VCM1 is input to the gates of MOSFETs P1, P2, N1, and N2. A common-mode voltage VCM2 is input to the fully differential amplifier. The output terminal of the isolation capacitor module is electrically connected to the filter module. After filtering by the filter module, the differential signal INA is output to the gate of MOS transistor P1 and the gate of MOS transistor N1, and the differential signal INB is output to the gate of MOS transistor P2 and the gate of MOS transistor N2. The tail current source is input to the source of MOS transistor P1, the source of MOS transistor P2, the source of MOS transistor N1 and the source of MOS transistor N2. The drains of MOS transistor P1, P2, N1 and N2 are all electrically connected to the folded operational amplifier. The output terminal of the folded operational amplifier is electrically connected to the input terminal of the fully differential amplifier.

[0006] Furthermore, the folded operational amplifier includes MOS transistors P4, P5, N4, and N5, and resistors R5, R6, R12, and R13. The power supply VDD is input to one end of resistor R5 and one end of resistor R6. The external bias voltage VBP2 is input to the gate of MOSFET P4 and the gate of MOSFET P5. The external bias voltage VBN2 is input to the gate of MOSFET N4 and the gate of MOSFET N5. The drain of MOSFET N1 is electrically connected to the other end of resistor R5 and the source of MOSFET P4; the drain of MOSFET N2 is electrically connected to the other end of resistor R6 and the source of MOSFET P5; the drain of MOSFET P1 is electrically connected to the source of MOSFET N5 and one end of resistor R13; the drain of MOSFET P2 is electrically connected to the source of MOSFET N4 and one end of resistor R12; the drains of MOSFET P4 and MOSFET N4 are electrically connected as the first output terminal to the first input terminal of the fully differential amplifier; the drains of MOSFET P5 and MOSFET N5 are electrically connected as the second output terminal to the second input terminal of the fully differential amplifier. The other ends of resistor R12 and resistor R13 are both grounded.

[0007] Furthermore, the rail-to-rail amplifier also includes MOSFET P3, MOSFET N3, and resistors R3 and R4; The common-mode voltage VCM1 is input to one end of resistor R3 and one end of resistor R4. The other end of resistor R4 is electrically connected to the gate of MOSFET N1 and the gate of MOSFET P1. The other end of resistor R3 is electrically connected to the gate of MOSFET N2 and the gate of MOSFET P2. Power supply VDD is input to the source of MOSFET P3, external bias voltage VBP1 is input to the gate of MOSFET P3, and external bias voltage VBN1 is input to the gate of MOSFET N3; the drain of MOSFET P3 is electrically connected to the source of MOSFET P1 and the source of MOSFET P2, and the drain of MOSFET N3 is electrically connected to the source of MOSFET N1 and the source of MOSFET N2. The source of the MOS transistor N3 is grounded.

[0008] Furthermore, the filtering module includes resistors R1 and R2, and capacitors C6 and C7; The first output terminal of the isolation capacitor module is electrically connected to one end of resistor R1 and one end of capacitor C6; the second output terminal of the isolation capacitor module is electrically connected to one end of resistor R2 and one end of capacitor C7; the other end of capacitor C6 is electrically connected to the gate of MOSFET N1 and the gate of MOSFET P1; and the other end of capacitor C7 is electrically connected to the gate of MOSFET N2 and the gate of MOSFET P2. The other ends of resistor R1 and resistor R2 are both grounded.

[0009] Furthermore, the isolation capacitor module includes high-voltage isolation capacitor CHV1, high-voltage isolation capacitor CHV2, high-voltage isolation capacitor CHV3 and high-voltage isolation capacitor CHV4; One end of the high-voltage isolation capacitor CHV2 is electrically connected to one end of the high-voltage isolation capacitor CHV1, and the other end of the high-voltage isolation capacitor CHV2 is electrically connected to one end of the resistor R1 and one end of the capacitor C6. One end of the high-voltage isolation capacitor CHV4 is electrically connected to one end of the high-voltage isolation capacitor CHV3, and the other end of the high-voltage isolation capacitor CHV4 is electrically connected to one end of the resistor R2 and one end of the capacitor C7.

[0010] Furthermore, the fully differential amplifier includes MOSFETs P10, P11, N6, N7, and N13, resistors R7, R8, R9, R10, R14, and R15, and capacitors C8 and C9. The power supply VDD is input to the source of MOSFET P10, the source of MOSFET P11, one end of capacitor C8, and one end of capacitor C9. The external bias voltage VBN1 is input to the gate of MOSFET N13. The common-mode voltage VCM2 is input to one end of resistor R14 and one end of resistor R15. The first output terminal of the folded operational amplifier and the other end of resistor R14 are both electrically connected to the gate of MOSFET N6. The second output terminal of the folded operational amplifier and the other end of resistor R14 are both electrically connected to the gate of MOSFET N7. The gate of MOSFET P10 is electrically connected to the other end of capacitor C8 and one end of resistor R7. The drain of MOSFET P10 is electrically connected to the drain of MOSFET N6 and one end of resistor R8, and serves as the first output terminal connected to the source follower. The gate of MOSFET P11 is electrically connected to the other end of capacitor C9 and one end of resistor R9. The drain of MOSFET P11 is electrically connected to the drain of MOSFET N7 and one end of resistor R10, and serves as the second output terminal connected to the source follower. The other end of resistor R7 is electrically connected to the other end of resistor R8, and serves as the third output terminal connected to the source follower. The other end of resistor R9 is electrically connected to the other end of resistor R10, and serves as the fourth output terminal connected to the source follower. The source of MOS transistor N6 and the source of MOS transistor N7 are both electrically connected to the drain of MOS transistor N13, and the source of MOS transistor N13 is grounded.

[0011] Furthermore, the source follower includes MOSFETs N9, N10, N11, N12, N14, and N15, and resistor R11; Power supply VDD is input to the drains of MOSFETs N9, N10, N11, and N12; the first output terminal of the fully differential amplifier is electrically connected to the gate of MOSFET N9, the second output terminal is electrically connected to the gate of MOSFET N10, the third output terminal is electrically connected to the gate of MOSFET N11, and the fourth output terminal is electrically connected to the gate of MOSFET N12; an external bias voltage VBN1 is input to the gates of MOSFETs N14 and N15. The source of MOSFET N9 is electrically connected to one end of resistor R11 and the source of MOSFET N10. The source of MOSFET N11 is electrically connected to the source of MOSFET N12 and the drain of MOSFET N15, and is electrically connected to the envelope comparator as the first output terminal. The other end of resistor R11 is electrically connected to the drain of MOSFET N14, and is electrically connected to the envelope comparator as the second output terminal. The sources of both MOS transistor N14 and MOS transistor N15 are grounded.

[0012] Furthermore, the envelope comparator includes a current source I2, MOSFETs P14, P15, P16, P17, P18, P19, P20, P21, and MOSFETs N18, N19, N20, N21, N22, N23, N24, N25, N26, and N27; Power supply VDD is input to the sources of MOSFETs P14, P15, P16, P17, P18, P19, P20, and P21; the first output terminal of the source follower is electrically connected to the gate of MOSFET N18 and the gate of MOSFET N21, and the second output terminal of the source follower is electrically connected to the gate of MOSFET N19 and the gate of MOSFET N20. The gate of MOSFET P14 is electrically connected to the gate and drain of MOSFET P15, the gate of MOSFET P16, the gate of MOSFET P17, the gate and drain of MOSFET N22, the gate of MOSFET N23, the gate of MOSFET N24, and the gate of MOSFET N25. The drain of MOSFET P14 is electrically connected to the negative terminal of current source I2. The drain of MOSFET P16 is electrically connected to the drain of MOSFET N18 and the drain of MOSFET N19. The source of MOSFET N18 is electrically connected to the source of MOSFET N20 and the drain of MOSFET N23. The source of MOSFET N19 is electrically connected to the source of MOSFET N21 and the drain of MOSFET N24. The drain of MOSFET P17 is electrically connected to the gate and drain of MOSFET P18, the gate of MOSFET P19, the drain of MOSFET N20, and the drain of MOSFET N21. The drain of MOSFET P19 is electrically connected to the gate of MOSFET P20, the gate of MOSFET N26, and the drain of MOSFET N25. The drains of MOSFET P20 and MOSFET N26 are both electrically connected to the gates of MOSFET P21 and MOSFET N27. The drains of MOSFET P21 and MOSFET N27 serve as output terminals to output the signal CMP_OUT to the output driver module. The positive terminal of current source I2, the source of MOSFET N22, the source of MOSFET N23, the source of MOSFET N24, the source of MOSFET N25, the source of MOSFET N26, and the source of MOSFET N27 are all grounded.

[0013] Furthermore, the aspect ratio of MOS transistor N18 is the same as that of MOS transistor N19, and the aspect ratio of MOS transistor N20 is the same as that of MOS transistor N21; the aspect ratios of MOS transistor N18 and MOS transistor N19 are both greater than the aspect ratios of MOS transistor N20 and N21.

[0014] Furthermore, the primary-side chip includes a modulation drive module and an oscillator. The input signal INPUT is input to the modulation drive module. The output terminal of the oscillator is electrically connected to the modulation drive module, and the output terminal of the modulation drive module is electrically connected to the input terminal of the isolation capacitor module.

[0015] By adopting the above technical solution, the present invention has the following advantages compared with the prior art: The front-end filtering module filters out low-frequency noise from the input signal. When positive common-mode interference occurs, the voltage values ​​of the differential signals INA and INB rise rapidly, MOSFETs P1 and P2 are cut off, while MOSFETs N1 and N2 are turned on, and the demodulation amplifier maintains its amplification function. When negative common-mode interference occurs, the voltage values ​​of the differential signals INA and INB drop rapidly, MOSFETs N1 and N2 are cut off, while MOSFETs P1 and P2 are turned on, and the demodulation amplifier maintains its amplification function. This achieves the goal of maintaining normal signal transmission without reducing the capacitance value of the isolation module. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the digital isolator with high common-mode interference immunity described in this invention; Figure 2 This is a circuit diagram of a demodulation amplifier with a high common-mode immunity digital isolator as described in this invention; Figure 3 This is the envelope comparator circuit diagram of the digital isolator with high common-mode immunity described in this invention; Figure 4 This is a modulation and demodulation principle diagram of the digital isolator with high common-mode interference immunity described in this invention.

[0017] Explanation of reference numerals in the attached figures: 1. Primary-side chip; 11. Modulation driver module; 12. Oscillator; 2. Isolation capacitor module; 3. Secondary side chip; 31. Demodulation amplifier; 311. Rail-to-rail amplifier; 312. Fully differential amplifier; 313. Source follower; 32. Envelope comparator; 33. Output driver module. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] Additionally, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are all based on the orientation or positional relationship shown in the accompanying drawings. They are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element of the present invention must have a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0020] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.

[0021] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example

[0022] Please refer to Figure 1-4As shown, this embodiment provides a digital isolator with high common-mode interference immunity, including a primary-side chip 1, an isolation capacitor module 2, and a secondary-side chip 3 connected in series. The secondary-side chip 3 includes a demodulation amplifier 31, an envelope comparator 32, and an output driver module 33 connected in series. The demodulation amplifier 31 includes a rail-to-rail amplifier 311, a fully differential amplifier 312, and a source follower 313 connected in series. The rail-to-rail amplifier 311 includes a filter module, an input transistor module, and a folded operational amplifier. The input transistor module includes MOSFETs P1, P2, N1, and N2. A common-mode voltage VCM1 is input to the gates of MOSFETs P1, P2, N1, and N2. A common-mode voltage VCM2 is input to the fully differential amplifier 312. The output of isolation capacitor module 2 is electrically connected to the filter module. After filtering, the filter module outputs a differential signal INA to the gates of MOSFET P1 and MOSFET N1, and a differential signal INB to the gates of MOSFET P2 and MOSFET N2. The tail current source is input to the sources of MOSFET P1, MOSFET P2, MOSFET N1, and MOSFET N2. The drains of MOSFET P1, MOSFET P2, MOSFET N1, and MOSFET N2 are all electrically connected to the folded operational amplifier. The output of the folded operational amplifier is electrically connected to the input of the fully differential amplifier 312.

[0023] The front-end filtering module filters out low-frequency noise from the input signal. When positive common-mode interference occurs, the voltage values ​​of the differential signals INA and INB rise rapidly, MOSFETs P1 and P2 are turned off, while MOSFETs N1 and N2 are turned on, and the demodulation amplifier 31 maintains its amplification function. When negative common-mode interference occurs, the voltage values ​​of the differential signals INA and INB drop rapidly, MOSFETs N1 and N2 are turned off, while MOSFETs P1 and P2 are turned on, and the demodulation amplifier 31 maintains its amplification function, thus achieving the goal of maintaining normal signal transmission without reducing the capacitance value of the isolation module.

[0024] Please refer to Figure 1 and Figure 2As shown, specifically, the primary-side chip 1 includes a modulation drive module 11 and an oscillator 12. The input signal INPUT is input to the modulation drive module 11. The output terminal of the oscillator 12 is electrically connected to the modulation drive module 11, and the output terminal of the modulation drive module 11 is electrically connected to the input terminal of the isolation capacitor module 2. The isolation capacitor module 2 includes high-voltage isolation capacitors CHV1, CHV2, CHV3, and CHV4. One end of high-voltage isolation capacitor CHV2 is electrically connected to one end of high-voltage isolation capacitor CHV1, and the other end of high-voltage isolation capacitor CHV2 is electrically connected to one end of resistor R1 and one end of capacitor C6 of the filter module. One end of high-voltage isolation capacitor CHV4 is electrically connected to one end of high-voltage isolation capacitor CHV3, and the other end of high-voltage isolation capacitor CHV4 is electrically connected to one end of resistor R2 and one end of capacitor C7 of the filter module.

[0025] The modulation drive module 11 modulates the input signal INPUT. The isolation capacitor module 2 transmits the signal and withstands the voltage difference between the primary-side chip 1 and the secondary-side chip 3. The primary-side chip 1 demodulates the signal to restore the primary-side input signal. Specifically, the oscillator 12 generates a high-frequency carrier wave and outputs it to the modulation drive module 11. The modulation drive module 11 drives the high-voltage isolation capacitor to modulate the carrier signal carrying the input information into two signals with opposite phases, which are then transmitted to the secondary-side chip 3 through the high-voltage capacitor to achieve modulation of the input signal. The demodulation amplifier 31 amplifies the signal transmitted by the high-voltage isolation capacitor and, together with the envelope comparator 32, demodulates the signal to restore the input signal level. The output drive module 33 further buffers and amplifies the demodulated signal.

[0026] Please refer to Figure 2As shown, specifically, the folded operational amplifier includes MOSFETs P4, P5, N4, and N5, and resistors R5, R6, R12, and R13. Power supply VDD is input to one end of resistor R5 and one end of resistor R6. External bias voltage VBP2 is input to the gates of MOSFETs P4 and P5, and external bias voltage VBN2 is input to the gates of MOSFETs N4 and N5. The drain of MOSFET N1 is electrically connected to the other end of resistor R5 and the source of MOSFET P4. The drain of MOSFET N2 is electrically connected to the other end of resistor R6 and the source of MOSFET P5. The drain of MOSFET P1 is electrically connected to the source of MOSFET N5 and one end of resistor R13. The drain of MOSFET P2 is electrically connected to the source of MOSFET N4 and one end of resistor R12. The drains of MOSFET P4 and MOSFET N4 are electrically connected to the first input terminal of the fully differential amplifier 312 as the first output terminal, and the drains of MOSFET P5 and MOSFET N5 are electrically connected to the second input terminal of the fully differential amplifier 312 as the second output terminal; the other ends of resistor R12 and resistor R13 are both grounded.

[0027] Furthermore, the rail-to-rail amplifier 311 also includes MOSFETs P3 and N3, and resistors R3 and R4. A common-mode voltage VCM1 is input to one end of resistor R3 and one end of resistor R4. The other end of resistor R4 is electrically connected to the gates of MOSFETs N1 and P1, and the other end of resistor R3 is electrically connected to the gates of MOSFETs N2 and P2. A power supply VDD is input to the source of MOSFET P3, an external bias voltage VBP1 is input to the gate of MOSFET P3, and an external bias voltage VBN1 is input to the gate of MOSFET N3. The drain of MOSFET P3 is electrically connected to the sources of MOSFETs P1 and P2, and the drain of MOSFET N3 is electrically connected to the sources of MOSFETs N1 and N2. The source of MOSFET N3 is grounded.

[0028] The filtering module includes resistors R1 and R2, and capacitors C6 and C7. The first output terminal of the isolation capacitor module 2 is electrically connected to one end of resistor R1 and one end of capacitor C6; the second output terminal of the isolation capacitor module 2 is electrically connected to one end of resistor R2 and one end of capacitor C7; the other end of capacitor C6 is electrically connected to the gates of MOSFET N1 and MOSFET P1; the other end of capacitor C7 is electrically connected to the gates of MOSFET N2 and MOSFET P2; the other ends of resistors R1 and R2 are both grounded.

[0029] MOSFETs P1 and P2, along with MOSFETs N1 and N2, form input pairs. MOSFETs P3 and N3 serve as tail current sources for the two input pairs, respectively. Resistors R1 and R2, along with capacitors C6 and C7, constitute a high-pass filter to remove low-frequency noise. The common-mode voltage VCM1 provides the common-mode voltage to the input pairs through resistors R3 and R4, ensuring a suitable operating point for the input pairs.

[0030] When positive common-mode interference occurs, the common-mode current flows through isolation capacitor module 2 into resistors R1 and R2, generating voltages across them and causing a sudden increase in the voltage across resistors R1 and R2. Since the voltages across capacitors C6 and C7 cannot change abruptly, the differential signals INA and INB follow this sudden increase. If the common-mode rate of change is large, the common-mode current is large, resulting in a significant increase in the voltages of the differential signals INA and INB. When the voltages of the differential signals INA and INB reach a certain level, the PMOS input pair transistors P1 and P2 are turned off, but the NMOS input pair transistors N1 and N2 remain on, and the demodulation amplifier 31 continues its amplification function.

[0031] When negative common-mode interference occurs, the common-mode current flows out through resistor R3, capacitor C7, high-voltage isolation capacitors CHV3 and CHV4, and resistor R4, capacitor C6, high-voltage isolation capacitors CHV2 and CHV1. The common-mode current generates a voltage drop across resistors R3 and R4, causing the differential signals INA and INB to drop. If the common-mode rate of change is large, the common-mode current is large, resulting in a large drop in the voltage of the differential signals INA and INB. When the voltage drops to a certain level, the NMOS input pair transistors N1 and N2 are turned off, but the PMOS input pair transistors P1 and P2 remain on, so the amplifier still has amplification function.

[0032] In summary, regardless of whether the common-mode change is positive or negative, the demodulation amplifier 31 is in normal working condition, and the chip is working normally.

[0033] Specifically, the fully differential amplifier 312 includes MOSFETs P10, P11, N6, N7, and N13, resistors R7, R8, R9, R10, R14, and R15, and capacitors C8 and C9.

[0034] Power supply VDD is input to the source of MOSFET P10, the source of MOSFET P11, one end of capacitor C8, and one end of capacitor C9. External bias voltage VBN1 is input to the gate of MOSFET N13. Common-mode voltage VCM2 is input to one end of resistor R14 and one end of resistor R15. The first output terminal of the folded op-amp and the other end of resistor R14 are both electrically connected to the gate of MOSFET N6. The second output terminal of the folded op-amp and the other end of resistor R14 are both electrically connected to the gate of MOSFET N7. In this embodiment, the drains of MOSFET P4 and MOSFET N4 are both electrically connected to the gate of MOSFET N6, and the drains of MOSFET P5 and MOSFET N5 are both electrically connected to the gate of MOSFET N7.

[0035] The gate of MOSFET P10 is electrically connected to the other end of capacitor C8 and one end of resistor R7. The drain of MOSFET P10 is electrically connected to the drain of MOSFET N6 and one end of resistor R8, and serves as the first output terminal connected to source follower 313. The gate of MOSFET P11 is electrically connected to the other end of capacitor C9 and one end of resistor R9. The drain of MOSFET P11 is electrically connected to the drain of MOSFET N7 and one end of resistor R10, and serves as the second output terminal connected to source follower 313. The other end of resistor R7 is electrically connected to the other end of resistor R8, and serves as the third output terminal connected to source follower 313. The other end of resistor R9 is electrically connected to the other end of resistor R10, and serves as the fourth output terminal connected to source follower 313. The sources of MOSFETs N6 and N7 are both electrically connected to the drain of MOSFET N13, and the source of MOSFET N13 is grounded. The first output terminal outputs the X signal, the second output terminal outputs the Y signal, the third output terminal outputs the M signal, and the fourth output terminal outputs the N signal. The X and Y signals are filtered by RC, and their amplitudes are larger when a carrier signal is received. The M and N signals are filtered by RC, and their amplitudes are smaller.

[0036] Specifically, the source follower 313 includes MOSFETs N9, N10, N11, N12, N14, and N15, and resistor R11. Power supply VDD is input to the drains of MOSFETs N9, N10, N11, and N12. The first output terminal of the fully differential amplifier 312 is electrically connected to the gate of MOSFET N9, that is, the drain of MOSFET P10 is electrically connected to the gate of MOSFET N9. The second output terminal of the fully differential amplifier 312 is electrically connected to the gate of MOSFET N10, and the drain of MOSFET P11 is electrically connected to the gate of MOSFET N10. The third output terminal of the fully differential amplifier 312 is electrically connected to the gate of MOSFET N11, and the other end of resistor R7 is electrically connected to the gate of MOSFET N11. The fourth output terminal of the fully differential amplifier 312 is electrically connected to the gate of MOSFET N12, and the other end of resistor R9 is electrically connected to the gate of MOSFET N12. An external bias voltage VBN1 is input to the gates of MOSFETs N14 and N15. The source of MOSFET N9 and one end of resistor R11 are electrically connected to the source of MOSFET N10. The source of MOSFET N11 is electrically connected to the source of MOSFET N12 and the drain of MOSFET N15, and is electrically connected to envelope comparator 32 as the first output terminal; the other end of resistor R11 is electrically connected to the drain of MOSFET N14, and is electrically connected to envelope comparator 32 as the second output terminal; the sources of MOSFET N14 and MOSFET N15 are both grounded.

[0037] In a static state, the voltages at points X, Y, M, and N are the same, so the voltage at point Q is lower than the voltage at point P by Is*R11. In a dynamic state, since the signal amplitudes at points X and Y are larger than those at points M and N, the voltage at point Q is made higher than the voltage at point P by adjusting the value of resistor R11. This creates two different states: in the static state, the voltage at point P is higher than the voltage at point Q; in the dynamic state, the voltage at point Q is higher than the voltage at point P. The difference in voltage between points P and Q represents different input states, which are then processed by subsequent circuitry to reconstruct the input signal.

[0038] Please refer to Figure 3As shown, the envelope comparator 32 includes a current source I2, MOSFETs P14, P15, P16, P17, P18, P19, P20, P21, and N18, N19, N20, N21, N22, N23, N24, N25, N26, and N27. Power supply VDD is input to the sources of MOSFETs P14, P15, P16, P17, P18, P19, P20, and P21. The first output terminal of source follower 313 is electrically connected to the gates of MOSFET N18 and MOSFET N21. Specifically, the source of MOSFET N11 and the source of MOSFET N12 output a P signal to the gates of MOSFET N18 and MOSFET N21. The second output terminal of source follower 313 is electrically connected to the gates of MOSFET N19 and MOSFET N20, and the other end of resistor R11 outputs a Q signal to the gates of MOSFET N19 and MOSFET N20.

[0039] The gate of MOSFET P14 is electrically connected to the gate and drain of MOSFET P15, the gate of MOSFET P16, the gate of MOSFET P17, the gate and drain of MOSFET N22, the gate of MOSFET N23, the gate of MOSFET N24, and the gate of MOSFET N25. The drain of MOSFET P14 is electrically connected to the negative terminal of current source I2. The drain of MOSFET P16 is electrically connected to the drain of MOSFET N18 and the drain of MOSFET N19. The source of MOSFET N18 is electrically connected to the source of MOSFET N20 and the drain of MOSFET N23. The source of MOSFET N19 is electrically connected to the source of MOSFET N21 and the drain of MOSFET N24. The drain of MOSFET P17 is electrically connected to the gate and drain of MOSFET P18, the gate of MOSFET P19, the drain of MOSFET N20, and the drain of MOSFET N21. The drain of MOSFET P19 is electrically connected to the gate of MOSFET P20, the gate of MOSFET N26, and the drain of MOSFET N25. The drains of MOSFET P20 and MOSFET N26 are both electrically connected to the gates of MOSFET P21 and MOSFET N27. The drains of MOSFET P21 and MOSFET N27 serve as output terminals, outputting the signal CMP_OUT to the output driver module 33. The positive terminal of current source I2, the source of MOSFET N22, the source of MOSFET N23, the source of MOSFET N24, the source of MOSFET N25, the source of MOSFET N26, and the source of MOSFET N27 are all grounded.

[0040] Furthermore, the aspect ratio of MOSFET N18 is the same as that of MOSFET N19, and the aspect ratio of MOSFET N20 is the same as that of MOSFET N21; the aspect ratios of MOSFET N18 and MOSFET N19 are both greater than the aspect ratios of MOSFET N20 and MOSFET N21.

[0041] In the static state, because the voltage at point P is higher than the voltage at point Q, the current flowing through MOSFETs N20 and N21 is relatively small, resulting in a relatively small current flowing through MOSFET P18. The current mirrored to MOSFET P19 is less than the current flowing through MOSFET N25. After being buffered and amplified by MOSFETs P20, N26, P21, and N27, the signal CMP_OUT is low. In the dynamic state, because the voltage at point Q is higher than the voltage at point P, the current flowing through MOSFETs N20 and N21 increases, as does the current flowing through MOSFET P18. The current mirrored to MOSFET P19 is greater than the current flowing through MOSFET N25. After being buffered and amplified by MOSFETs P20, N26, P21, and N27, the signal CMP_OUT outputs a high level.

[0042] In this embodiment, the output drive module 33, the modulation drive module 11, and the oscillator 12 are all conventional modules and will not be described in detail here. Please refer to... Figure 4 As shown, attached Figure 4 This is a schematic diagram of the modulation and demodulation principle of the digital isolator disclosed in this embodiment, provided in the appendix. Figure 4 It can be seen that when the input signal is low, the voltage at point P is higher than the voltage at point Q; when the input signal is high, the voltage at point Q is higher than the voltage at point P. The voltages at points P and Q are then used by the subsequent envelope comparator 32 to reconstruct the input signal. When common-mode interference occurs, the differential input signal of the demodulation amplifier 31 decreases. When positive common-mode interference occurs, the common-mode input voltage of the demodulation amplifier 31 increases; when negative common-mode interference occurs, the common-mode input voltage of the demodulation amplifier 31 decreases.

[0043] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A digital isolator with high common-mode interference immunity, characterized in that, It includes a primary-side chip, an isolation capacitor module, and a secondary-side chip connected in series. The secondary chip includes a demodulation amplifier, an envelope comparator, and an output driver module connected in series. The demodulation amplifier includes a rail-to-rail amplifier, a fully differential amplifier, and a source follower connected in series. The rail-to-rail amplifier includes a filter module, an input transistor module, and a folded operational amplifier. The input transistor module includes MOSFETs P1, P2, N1, and N2. A common-mode voltage VCM1 is input to the gates of MOSFETs P1, P2, N1, and N2. A common-mode voltage VCM2 is input to the fully differential amplifier. The output terminal of the isolation capacitor module is electrically connected to the filter module. After filtering by the filter module, the differential signal INA is output to the gate of MOS transistor P1 and the gate of MOS transistor N1, and the differential signal INB is output to the gate of MOS transistor P2 and the gate of MOS transistor N2. The tail current source is input to the source of MOS transistor P1, the source of MOS transistor P2, the source of MOS transistor N1 and the source of MOS transistor N2. The drains of MOS transistor P1, P2, N1 and N2 are all electrically connected to the folded operational amplifier. The output terminal of the folded operational amplifier is electrically connected to the input terminal of the fully differential amplifier.

2. The digital isolator with high common-mode interference immunity according to claim 1, characterized in that, The folded operational amplifier includes MOSFETs P4, P5, N4, and N5, and resistors R5, R6, R12, and R13. The power supply VDD is input to one end of resistor R5 and one end of resistor R6. The external bias voltage VBP2 is input to the gate of MOSFET P4 and the gate of MOSFET P5. The external bias voltage VBN2 is input to the gate of MOSFET N4 and the gate of MOSFET N5. The drain of MOSFET N1 is electrically connected to the other end of resistor R5 and the source of MOSFET P4; the drain of MOSFET N2 is electrically connected to the other end of resistor R6 and the source of MOSFET P5; the drain of MOSFET P1 is electrically connected to the source of MOSFET N5 and one end of resistor R13; the drain of MOSFET P2 is electrically connected to the source of MOSFET N4 and one end of resistor R12; the drains of MOSFET P4 and MOSFET N4 are electrically connected as the first output terminal to the first input terminal of the fully differential amplifier; the drains of MOSFET P5 and MOSFET N5 are electrically connected as the second output terminal to the second input terminal of the fully differential amplifier. The other ends of resistor R12 and resistor R13 are both grounded.

3. The digital isolator with high common-mode interference immunity according to claim 1, characterized in that, The rail-to-rail amplifier also includes MOSFETs P3 and N3, and resistors R3 and R4. The common-mode voltage VCM1 is input to one end of resistor R3 and one end of resistor R4. The other end of resistor R4 is electrically connected to the gate of MOSFET N1 and the gate of MOSFET P1. The other end of resistor R3 is electrically connected to the gate of MOSFET N2 and the gate of MOSFET P2. Power supply VDD is input to the source of MOSFET P3, external bias voltage VBP1 is input to the gate of MOSFET P3, and external bias voltage VBN1 is input to the gate of MOSFET N3; the drain of MOSFET P3 is electrically connected to the source of MOSFET P1 and the source of MOSFET P2, and the drain of MOSFET N3 is electrically connected to the source of MOSFET N1 and the source of MOSFET N2. The source of the MOS transistor N3 is grounded.

4. The digital isolator with high common-mode interference immunity according to claim 1, characterized in that, The filtering module includes resistors R1 and R2, and capacitors C6 and C7. The first output terminal of the isolation capacitor module is electrically connected to one end of resistor R1 and one end of capacitor C6; the second output terminal of the isolation capacitor module is electrically connected to one end of resistor R2 and one end of capacitor C7; the other end of capacitor C6 is electrically connected to the gate of MOSFET N1 and the gate of MOSFET P1; and the other end of capacitor C7 is electrically connected to the gate of MOSFET N2 and the gate of MOSFET P2. The other ends of resistor R1 and resistor R2 are both grounded.

5. The digital isolator with high common-mode interference immunity according to claim 4, characterized in that, The isolation capacitor module includes high-voltage isolation capacitor CHV1, high-voltage isolation capacitor CHV2, high-voltage isolation capacitor CHV3 and high-voltage isolation capacitor CHV4; One end of the high-voltage isolation capacitor CHV2 is electrically connected to one end of the high-voltage isolation capacitor CHV1, and the other end of the high-voltage isolation capacitor CHV2 is electrically connected to one end of the resistor R1 and one end of the capacitor C6. One end of the high-voltage isolation capacitor CHV4 is electrically connected to one end of the high-voltage isolation capacitor CHV3, and the other end of the high-voltage isolation capacitor CHV4 is electrically connected to one end of the resistor R2 and one end of the capacitor C7.

6. The digital isolator with high common-mode interference immunity according to claim 1, characterized in that, The fully differential amplifier includes MOSFETs P10, P11, N6, N7, and N13, resistors R7, R8, R9, R10, R14, and R15, and capacitors C8 and C9. The power supply VDD is input to the source of MOSFET P10, the source of MOSFET P11, one end of capacitor C8, and one end of capacitor C9. The external bias voltage VBN1 is input to the gate of MOSFET N13. The common-mode voltage VCM2 is input to one end of resistor R14 and one end of resistor R15. The first output terminal of the folded operational amplifier and the other end of resistor R14 are both electrically connected to the gate of MOSFET N6. The second output terminal of the folded operational amplifier and the other end of resistor R14 are both electrically connected to the gate of MOSFET N7. The gate of MOSFET P10 is electrically connected to the other end of capacitor C8 and one end of resistor R7. The drain of MOSFET P10 is electrically connected to the drain of MOSFET N6 and one end of resistor R8, and serves as the first output terminal connected to the source follower. The gate of MOSFET P11 is electrically connected to the other end of capacitor C9 and one end of resistor R9. The drain of MOSFET P11 is electrically connected to the drain of MOSFET N7 and one end of resistor R10, and serves as the second output terminal connected to the source follower. The other end of resistor R7 is electrically connected to the other end of resistor R8, and serves as the third output terminal connected to the source follower. The other end of resistor R9 is electrically connected to the other end of resistor R10, and serves as the fourth output terminal connected to the source follower. The source of MOS transistor N6 and the source of MOS transistor N7 are both electrically connected to the drain of MOS transistor N13, and the source of MOS transistor N13 is grounded.

7. The digital isolator with high common-mode interference immunity according to claim 1, characterized in that, The source follower includes MOSFETs N9, N10, N11, N12, N14, and N15, and resistor R11; Power supply VDD is input to the drains of MOSFETs N9, N10, N11, and N12; the first output terminal of the fully differential amplifier is electrically connected to the gate of MOSFET N9, the second output terminal is electrically connected to the gate of MOSFET N10, the third output terminal is electrically connected to the gate of MOSFET N11, and the fourth output terminal is electrically connected to the gate of MOSFET N12; an external bias voltage VBN1 is input to the gates of MOSFETs N14 and N15. The source of MOSFET N9 is electrically connected to one end of resistor R11 and the source of MOSFET N10. The source of MOSFET N11 is electrically connected to the source of MOSFET N12 and the drain of MOSFET N15, and is electrically connected to the envelope comparator as the first output terminal. The other end of resistor R11 is electrically connected to the drain of MOSFET N14, and is electrically connected to the envelope comparator as the second output terminal. The sources of both MOS transistor N14 and MOS transistor N15 are grounded.

8. The digital isolator with high common-mode interference immunity according to claim 1, characterized in that, The envelope comparator includes a current source I2, MOSFETs P14, P15, P16, P17, P18, P19, P20, P21, and MOSFETs N18, N19, N20, N21, N22, N23, N24, N25, N26, and N27. Power supply VDD is input to the sources of MOSFETs P14, P15, P16, P17, P18, P19, P20, and P21; the first output terminal of the source follower is electrically connected to the gate of MOSFET N18 and the gate of MOSFET N21, and the second output terminal of the source follower is electrically connected to the gate of MOSFET N19 and the gate of MOSFET N20. The gate of MOSFET P14 is electrically connected to the gate and drain of MOSFET P15, the gate of MOSFET P16, the gate of MOSFET P17, the gate and drain of MOSFET N22, the gate of MOSFET N23, the gate of MOSFET N24, and the gate of MOSFET N25. The drain of MOSFET P14 is electrically connected to the negative terminal of current source I2. The drain of MOSFET P16 is electrically connected to the drain of MOSFET N18 and the drain of MOSFET N19. The source of MOSFET N18 is electrically connected to the source of MOSFET N20 and the drain of MOSFET N23. The source of MOSFET N19 is electrically connected to the source of MOSFET N21 and the drain of MOSFET N24. The drain of MOSFET P17 is electrically connected to the gate and drain of MOSFET P18, the gate of MOSFET P19, the drain of MOSFET N20, and the drain of MOSFET N21. The drain of MOSFET P19 is electrically connected to the gate of MOSFET P20, the gate of MOSFET N26, and the drain of MOSFET N25. The drains of MOSFET P20 and MOSFET N26 are both electrically connected to the gates of MOSFET P21 and MOSFET N27. The drains of MOSFET P21 and MOSFET N27 serve as output terminals to output the signal CMP_OUT to the output driver module. The positive terminal of current source I2, the source of MOSFET N22, the source of MOSFET N23, the source of MOSFET N24, the source of MOSFET N25, the source of MOSFET N26, and the source of MOSFET N27 are all grounded.

9. The digital isolator with high common-mode interference immunity according to claim 8, characterized in that, The aspect ratio of MOS transistor N18 is the same as that of MOS transistor N19, and the aspect ratio of MOS transistor N20 is the same as that of MOS transistor N21; the aspect ratios of MOS transistor N18 and MOS transistor N19 are both greater than the aspect ratios of MOS transistor N20 and N21.

10. The digital isolator with high common-mode interference immunity according to claim 1, characterized in that, The primary-side chip includes a modulation drive module and an oscillator. The input signal INPUT is input to the modulation drive module. The output terminal of the oscillator is electrically connected to the modulation drive module. The output terminal of the modulation drive module is electrically connected to the input terminal of the isolation capacitor module.

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