FPGA-based demodulation reliability quantification phase-locked amplification system and method

Abstract

The application discloses a demodulation reliability quantification phase-locked amplification system and method based on FPGA, which quantifies the locking quality and stability into a determinable index which can be reported through reliability score, so that the host computer can make consistent comparison and evaluation on the measuring performance in different situations. In the transient process or strong interference environment, the user or the later algorithm can filter the unreliable data in real time according to the index, so that the robustness of the measuring instrument in the complex working condition is greatly improved. The system is characterized in that it comprises a DC removal module, an I / Q mixing module, a CIC filter module, a FIR low-pass filter module, a CORDIC operation module, an amplitude scaling module, an external reference tracking module, an online self-calibration module, a reliability score module and a communication output module.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing and measurement instrument technology, specifically to an FPGA-based demodulation reliability quantization lock-in amplification system and method. Background Technology

[0002] Lock-in amplifiers typically output amplitude and phase values, lacking an objective quantitative description of the current demodulation state (such as whether it is stably locked or whether convergence is complete). In actual measurements, external reference frequencies may change abruptly, input signals may fluctuate, and environmental noise may increase sharply, all of which can temporarily render the demodulation results unreliable. The host computer cannot directly determine the reliability of the current measurement value based solely on the amplitude and phase data, thus affecting subsequent analysis. Summary of the Invention

[0003] This invention provides a demodulation reliability quantification lock-in amplifier system and method based on FPGA, which solves the problem of the lack of objective quantification output of demodulation result quality in existing digital lock-in amplifiers.

[0004] The technical solution of the present invention is as follows:

[0005] An FPGA-based demodulation reliability quantization phase-locked amplifier system is characterized by comprising a DC-DC de-energizing module, an external reference tracking module, and a communication output module. One end of the DC-DC de-energizing module is connected to the input signal, and the other end is connected to the first input terminals of a first mixer module and a second mixer module, respectively. One end of the external reference tracking module is connected to an external reference signal, and the other end is connected to the second input terminals of both the first and second mixer modules, respectively. The output terminal of the first mixer module is connected to the first input terminal of a CORDIC arithmetic module via a first CIC filter module and a first FIR low-pass filter module, respectively. The output terminal of the second mixer module is connected to the second input terminal of the CORDIC arithmetic module via a second CIC filter module and a second FIR low-pass filter module, respectively. The output terminal of the CORDIC arithmetic module is connected to the first input terminal of an amplitude scaling module, and the second input terminal of the amplitude scaling module is connected to a self-calibration module. The communication output module is connected to the output terminal of the amplitude scaling module, a reliability scoring module, and a host computer module, respectively.

[0006] The self-calibration module is an online self-calibration module that includes a floating-point divider. The floating-point divider calculates the self-calibration coefficients, and the online self-calibration module writes the self-calibration coefficients back to the amplitude scaling module. It also provides a calibration completion flag or a calibration coefficient validity flag to the reliability scoring module. The reliability scoring module calculates a quantized reliability score based on the stability of the external reference signal, the stability of the reference frequency, the phase error statistics, and the amplitude window consistency index, and transmits the reliability score to the host computer module.

[0007] The reliability score is synthesized by weighting multiple signal scores reflecting the demodulation state, and the reliability score ranges from 0 to 255.

[0008] The multiple signal scores reflecting the demodulation status include: S lock S freq S phase , and S amp S lock It is an external reference stable score, S freq It is a frequency stability score, S phase It is the phase stability score, S amp It is an amplitude consistency score.

[0009] Including the following expressions:

[0010] ,

[0011] Where K is the self-calibration coefficient. This is the known amplitude of the internal digital reference sine wave signal that is at the same frequency as the external reference signal and is used as the input demodulation link in calibration mode. It is an amplitude estimate formed based on N valid amplitude samples in the input signal, where N is a positive integer.

[0012] Including the following expressions:

[0013] ,

[0014] Where S is the reliability score, S lock It is an external reference stable score, S freq It is a frequency stability score, S phase It is the phase stability score, S amp It is an amplitude consistency score, where ω1 and ω2 are both weighting coefficients.

[0015] The FPGA-based demodulation reliability quantization phase-locked amplification method is characterized by employing the aforementioned FPGA-based demodulation reliability quantization phase-locked amplification system.

[0016] The advantages of this invention compared to the prior art are:

[0017] This invention presents an FPGA-based demodulation reliability quantification phase-locked amplification system and method. By quantifying lock-in quality and stability into reportable deterministic indicators through reliability scoring, it facilitates consistent comparative evaluation of measurement performance under different conditions by the host computer. In transient processes or environments with strong interference, users or subsequent algorithms can use this information to filter unreliable data in real time, significantly improving the robustness of the measuring instrument under complex operating conditions. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the FPGA-based demodulation reliability quantization phase-locked amplifier system implementing the present invention. FPGA stands for Field Programmable Gate Array. Figure 1 The FPGA in the system includes a DC-DC de-energizing module, an external reference tracking module, and a communication output module. The DC-DC de-energizing module is connected to the input signal (i.e., the signal under test), the external reference tracking module is connected to the external reference signal, and the communication output module is connected to the host computer module.

[0019] Figure 2 This is the flowchart of the FPGA-based demodulation reliability quantization phase-locked amplification method of the present invention. Figure 2 The process includes: Step 1, self-calibrating K (K is the self-calibration coefficient, calculated by the floating-point divider in the online self-calibration module, and K is written back to the amplitude scaling module and a calibration completion flag or a valid calibration coefficient flag is provided to the reliability scoring module); Step 2, the external reference tracking module performs external reference tracking, generating orthogonal reference signals with the same frequency as the external reference signal, which are then connected to the demodulation link and the reliability scoring module respectively; Step 3, the demodulation link transmits the state variables to the reliability scoring module and the host computer respectively; Step 4, the reliability scoring module calculates the quantized reliability score based on the external reference stability, reference frequency stability, phase error statistics, and amplitude window consistency index, and transmits the reliability score to the host computer.

[0020] The reference numerals in the attached diagrams are explained as follows: 1-DC converter module; 2-Mixer module (including a first mixer module and a second mixer module, the first mixer module receiving the output signal from the DC converter module and the 90-degree phase-shifted signal from the external reference tracking module, the second mixer module receiving the output signal from the DC converter module and the output signal from the external reference tracking module); 3-CIC filter module (including a first CIC filter module and a second CIC filter module, the first CIC filter module receiving the first I / Q mixed signal from the first mixer module, the second CIC filter module receiving the second I / Q mixed signal from the second mixer module, CIC stands for Cascaded Integrator Comb Filter, I / Q stands for In-phase / Quadrature); 4-FIR low-pass filter module (including a first FIR low-pass filter module and a second FIR low-pass filter module, the first FIR low-pass filter module connected to the first CIC filter module, the second FIR low-pass filter module connected to the second CIC filter module, FIR stands for Finite Impulse Response); 5- CORDIC computation module (CORDIC stands for Coordinate Rotation Digital Computer); 6-Amplitude scaling module; 7-Communication output module; 8-External reference tracking module; 9-Self-calibration module (self-calibration K); 10-Reliability scoring module; 11-Host computer module. Detailed Implementation

[0021] The following is in conjunction with the attached diagram ( Figures 1-2 The present invention will be described in conjunction with the examples.

[0022] Figure 1 This is a schematic diagram of the FPGA-based demodulation reliability quantization lock-in amplifier system for implementing the present invention. Figure 2 This is a flowchart illustrating the FPGA-based demodulation reliability quantization phase-locked amplification method of the present invention. (Reference) Figures 1 to 2As shown, the FPGA-based demodulation reliability quantization phase-locked amplifier system includes a DC-DC de-amplifier module 1, an external reference tracking module 8, and a communication output module 7. One end of the DC-DC de-amplifier module is connected to the input signal, and the other end is connected to the first input terminal of the first mixer module (belonging to mixer module 2) and the first input terminal of the second mixer module (belonging to mixer module 2). One end of the external reference tracking module 8 is connected to an external reference signal, and the other end is connected to the second input terminal of the first mixer module and the second input terminal of the second mixer module. The output terminal of the first mixer module passes through a first CIC filter module (belonging to CIC filter module 3) and a first FIR low-pass filter in sequence. The filtering module (belonging to the FIR low-pass filter module 4) is connected to the first input terminal of the CORDIC operation module 5. The output terminal of the second mixer module is connected to the second input terminal of the CORDIC operation module 5 in sequence through the second CIC filter module (belonging to the CIC filter module 3) and the second FIR low-pass filter module (belonging to the FIR low-pass filter module 4). The output terminal of the CORDIC operation module 5 is connected to the first input terminal of the amplitude scaling module 6. The second input terminal of the amplitude scaling module 6 is connected to the self-calibration module 9. The communication output module 7 is connected to the output terminal of the amplitude scaling module 6, the reliability scoring module 10, and the host computer module 11.

[0023] The self-calibration module 9 is an online self-calibration module containing a floating-point divider. The floating-point divider calculates the self-calibration coefficients, and the online self-calibration module writes the self-calibration coefficients back to the amplitude scaling module 6 and transmits them to the reliability scoring module 10. The reliability scoring module 10 calculates a quantized reliability score based on the stability of the external reference signal, the stability of the reference frequency, the phase error statistics, and the amplitude window consistency index, and transmits the reliability score to the host computer module 11.

[0024] The reliability score is synthesized by weighting multiple signal scores reflecting the demodulation state, and the reliability score ranges from 0 to 255.

[0025] The multiple signal scores reflecting the demodulation status include: S lock S freq S phase , and S amp S lock It is an external reference stable score, S freq It is a frequency stability score, S phase It is the phase stability score, S amp It is an amplitude consistency score.

[0026] Including the following expressions:

[0027] ,

[0028] Where K is the self-calibration coefficient, A ref The amplitude of the sinusoidal reference signal is known. It is an amplitude estimate formed based on N valid amplitude samples in the input signal, where N is a positive integer.

[0029] Including the following expressions:

[0030] ,

[0031] Where S is the reliability score, S lock It is an external reference stable score, S freq It is a frequency stability score, S phase It is the phase stability score, S amp It is an amplitude consistency score, where ω1 and ω2 are both weighting coefficients.

[0032] The FPGA-based demodulation reliability quantization phase-locked amplification method includes the above-mentioned FPGA-based demodulation reliability quantization phase-locked amplification system.

[0033] This invention relates to a phase-locked amplifier system and method for demodulation reliability quantification based on FPGA (Field-Programmable Gate Array). Conventional digital lock-in amplifiers are mostly used to obtain amplitude and phase outputs, which are prone to misjudgment when the external reference frequency changes abruptly or the signal jumps, and lack objective evaluation indicators for the reliability of the current demodulated data. The method of this invention proposes a demodulation reliability quantification method, which extracts internal state variables such as reference lock stability, frequency control word increment, phase error, and estimated stability to construct a reliability score in the range of 0 to 255. This method can quantify the lock demodulation quality and stability into reportable indicators without changing the core demodulation principle, providing real-time signal quality judgment basis for host computer processing, and effectively reducing the measurement misjudgment rate in transient processes or strong interference environments.

[0034] A phase-locked amplifier system and method for demodulation reliability quantization based on FPGA (Field-Programmable Gate Array) includes a DC-DC removal module, an I / Q mixing module (I / Q, In-phase / Quadrature), a CIC filter module (Cascaded Integrator Comb Filter), a FIR low-pass filter module (Finite Impulse Response), a CORDIC computation module (Coordinate Rotation Digital Computer), an amplitude scaling module, an external reference tracking module, an online self-calibration module, a reliability scoring module, and a communication output module. The external reference tracking module generates an orthogonal reference signal with the same frequency as the reference signal and connects it to the demodulation link. The reliability scoring module calculates the quantized reliability score based on the system's internal external reference stability, reference frequency stability, phase error statistics, and amplitude window consistency index.

[0035] The amplitude scaling module is used to scale the demodulation results using the calibration coefficients obtained from the self-calibration module to eliminate link gain.

[0036] The external reference tracking module counts the periods of the external reference TTL signal (TTL, transistor-transistor logic) and calculates the DDS fundamental frequency control word PINC (DDS is a direct digital frequency synthesizer, and PINC is the frequency control word). PINC determines the phase step of the DDS phase accumulator in each clock cycle, thus completing a coarse measurement of the reference frequency. Fine-tuning of the phase error is performed by continuously adjusting PINC through an internal PI loop (PI stands for proportional-integral, P is proportional, and I is integral). When the system detects that it has just entered the locked state and the phase error is less than a set threshold, the external reference tracking module performs a one-time compensation on the DDS phase offset control word POFF. POFF applies a fixed phase offset to the DDS output reference signal to eliminate the small steady-state phase error remaining after PI adjustment. The system configures the DDS via the data bus using the dynamically updated PINC and POFF parameters at high frequency, ultimately generating sine and cosine reference signals with the same frequency as the external signal.

[0037] The aforementioned online self-calibration module is used to calculate the link gain. It isolates the external signal under test from the input selector and switches to an internal signal with a known amplitude (A). ref), a sinusoidal reference signal, execute a calibration process; the calibration process comprises: setting the number of valid samples to be discarded at the output end of the low-pass filtering module to remove transients, then collecting N valid amplitude samples and using the Median-of-N algorithm to obtain a robust amplitude estimate A est ), where N is a positive integer, calculating the self-calibration coefficient K via a floating-point divider according to the following formula, and writing it back to the amplitude scaling module.

[0038] ,

[0039] where K is the self-calibration coefficient, A ref is the known amplitude of the sinusoidal reference signal, and A est is the amplitude estimate.

[0040] The reliability scoring module is synthesized by weighting a plurality of signal scores reflecting the demodulation state, comprising: an external reference stability score S lock , a frequency stability score S freq , a phase stability score S phase and an amplitude consistency score S amp , to calculate a reliability score ranging from 0 to 255.

[0041] The phase stability score S phase uses a piecewise comparison of the root mean square with a first threshold E1 and a second threshold E2 (where E1<E2) as the criterion, and the dual thresholds E1 and E2 are set in a multiple proportional manner based on the baseline root mean square of the device in an interference-free background noise environment.

[0042] The amplitude consistency score S amp is generated based on the steady-state convergence degree of the demodulated amplitude estimate: in a known signal calibration mode, it is determined whether the amplitude falls into a preset absolute target window [A min , A max ; in an unknown signal measurement mode, it is determined whether the local variance of the amplitude within a sliding statistical window is lower than a preset fluctuation threshold; after the amplitude meets the steady-state convergence condition of the corresponding mode and maintains for a set time, S amp takes the highest score; when deviating from the convergence condition, points are deducted in segments according to the magnitude of the deviation or variance.

[0043] The communication output module adopts a Universal Asynchronous Receiver-Transmitter (UART) or other digital communication interface, which is configured to encapsulate the amplitude, phase and state information into a frame format with a fixed byte length for outward transmission, wherein the state information frame at least comprises the reliability score generated under the current demodulation state.

[0044] An FPGA-based adaptive time constant switching and demodulation reliability quantization phase-locked amplifier technology includes DC removal, I / Q mixing, CIC filter module, FIR low-pass filter, CORDIC operation module, amplitude scaling module, external reference tracking module, online self-calibration module, reliability scoring module, and communication output module.

[0045] The specific implementation steps are as follows:

[0046] (1) The present invention relates to a digital lock-in amplifier with quality quantization deployed on an FPGA. After the system is powered on, the measurement gate enable terminal is pulled low because the external reference is not yet stable. The system first initiates the online self-calibration process: the input selector cuts off the external signal under test channel and injects a known amplitude A into the link. ref The internal digital reference sine wave is used. After the signal passes through mixing, CIC filtering, and low-pass filtering, the self-calibration controller first discards the first few valid samples at the output to filter out transients, waiting for the internal shift register of the filter to be filled; then, it continuously acquires N valid amplitude samples, and performs a median selection algorithm (such as Median-of-5) through a hardware sorting circuit to remove occasional jump points and obtain a robust amplitude estimate A. est Finally, the normalization coefficients are calculated using the internal divider.

[0047] (2) After self-calibration, an external input signal is connected. The external reference tracking module counts the period of the external TTL reference pulse in real time and calculates the basic frequency control word PINC to complete the coarse frequency measurement. At the same time, the internal PI regulator continuously fine-tunes the frequency control word based on the phase error. When it detects that it has just entered the locked state and the phase error meets the set locking threshold, it performs a one-time step compensation on POFF in the phase offset register to eliminate the small steady-state error remaining in the PI regulation. The system configures the dynamically updated PINC and POFF to the DDS via the internal data bus, and finally generates sine and cosine reference signals with the same frequency and phase as the external reference signal and connects them to the demodulation link.

[0048] (3) After the input signal is sampled by the ADC, it enters the FPGA. First, it undergoes DC removal processing, and then it is mixed with the quadrature reference signal generated by the external reference tracking module to obtain I and Q signals. The mixing result is downsampled by the CIC filter and then sent to the FIR low-pass filter to extract the DC component. Finally, the amplitude and phase are calculated by the CORDIC algorithm. The amplitude result is output after scaling.

[0049] (4) The external reference tracking module calculates the fundamental frequency control word (PINC) of the DDS by counting the period of the external TTL reference signal, thus completing the coarse frequency measurement. Simultaneously, the internal PI loop continuously fine-tunes the PINC based on the phase error, achieving fine phase-locked looping. When the system detects that it has just entered the locked state and the phase error is less than the set threshold, a one-time step compensation is performed on the POFF in the phase offset register inside the DDS to eliminate the small steady-state error remaining from the PI adjustment, reduce the fixed phase deviation after locking, and shorten the time required for the demodulated output to enter a stable state. Finally, sine and cosine reference signals with the same frequency as the external TTL signal are generated.

[0050] (5) The reliability scoring module does not rely on external measurement channels. It extracts the state variables within the phase-locked demodulation link to construct a reliability score (S) ranging from 0 to 255. The score is synthesized from the following signal scores:

[0051] Locked sub-score S lock Extract the reference signal stability (ref_stable) flag output by the external reference tracking module. If ref_stable is 1, then S... lock It is 1 if it is true, otherwise it is 0.

[0052] Frequency stability score S freq Extract the frequency control word difference between adjacent time steps to obtain the frequency control word increment ΔPINC:

[0053] ,

[0054] The frequency stability is determined by combining the preset threshold PINC_TH. When the frequency control word increment ΔPINC is less than the threshold PINC_TH, S... freq It is 1 if it is true, otherwise it is 0.

[0055] Phase stability score S phase Based on the root mean square (RMS) phase error from the internal statistical window, a piecewise linear deduction evaluation is performed using dual thresholds [E1, E2]. E1 is set to 1.5 to 3 times the RMS of natural phase jitter caused by background noise under ideal locking conditions. If the error is within this range, it indicates that the system is in perfect tracking condition, and a full score of 255 is given. E2 is usually set to 3 to 6 times the RMS of natural phase jitter. If it exceeds this value, it indicates that the phase error has far exceeded the random disturbance of normal noise, and the system is likely experiencing frequency abrupt changes or signal loss. In this case, an extremely low score or even 0 points is given.

[0056] Amplitude Consistency Score ampBased on the steady-state convergence of the demodulated amplitude estimate, the following is determined: whether the local variance of the amplitude within the sliding statistical window is lower than a preset fluctuation threshold; when the amplitude meets the steady-state convergence condition of the corresponding mode and is maintained for a set time, S... amp The highest score of 255 is taken; when the convergence condition is deviated from, points are deducted in segments according to the magnitude of the deviation or variance. The reliability scoring formula is as follows:

[0057] ,

[0058] ω1 and ω2 are both weighting coefficients.

[0059] like Figure 1 As shown, this invention is a digital lock-in amplifier with demodulation reliability quantification. The signal under test enters the FPGA and first undergoes DC component removal processing by the DC removal module 1. Then, it is I / Q mixed with the sine and cosine reference signals generated by the external reference tracking module in the mixing module 2 to obtain two quadrature baseband signals. The mixed I / Q signals are then sequentially passed through the CIC filter module 3 and the FIR low-pass filter module 4 to filter out high-frequency components and extract the DC component. They are then sent to the CORDIC calculation module 5 to calculate the amplitude and phase. The amplitude result is scaled in the amplitude scaling module 6 with the self-calibration coefficients calculated by the self-calibration module 9 to form the final demodulated output. Simultaneously, the external reference tracking module 8 generates a DDS reference signal based on the TTL reference signal and provides a synchronization reference for the mixing module. The reliability scoring module 10 extracts indicators from internal states such as reference lock state, PINC change, phase error, and amplitude stability to generate a reliability score, which, along with the amplitude and phase results, is sent to the host computer module 11 via the communication output module 7.

[0060] like Figure 2 As shown, the specific implementation steps of this invention are as follows:

[0061] (1) After the system is powered on, the system first starts the online self-calibration process: the input selection module shields the external ADC sampling data and selects the internal digital reference sine wave as the demodulation link input, injecting a digital reference sine wave of known amplitude into the link. After the signal is mixed, CIC filtered, FIR filtered, and CORDIC calculated, the self-calibration controller first discards the first DISCARD_NUM valid amplitude samples after the calibration mode is started, so that they do not participate in the subsequent amplitude statistics (DISCARD_NUM is the preset or configurable number of transient discarded samples); then, N amplitude samples are continuously collected, and the median selection (Median-of-5) is performed through the hardware sorting circuit to remove occasional jump points; finally, the self-calibration coefficient K is calculated using the internal floating-point divider. Thus, the calibration of the overall proportional gain error of the two links inside the system is completed.

[0062] (2) After self-calibration is completed, an external input signal is connected. The external reference tracking module 8 counts the external TTL reference pulses in real time and calculates the reference frequency control word. At the same time, the PI regulator adjusts the fine frequency control word according to the phase error. When the error meets the locking threshold, a one-time differential compensation is performed on POFF in the internal phase offset register of the DDS to complete the signal synchronization.

[0063] (3) The reliability scoring module 10 extracts the state variables within the phase-locked demodulation link to construct a reliability score (S) ranging from 0 to 255. The score is synthesized from the following signal scores:

[0064] Locked sub-score S lock Extract the reference signal stability (ref_stable) flag output by the external reference tracking module. If ref_stable is 1, then S... lock It is 1 if it is true, otherwise it is 0.

[0065] Frequency stability score S freq Extract the frequency control word difference between adjacent time steps to obtain the frequency control word increment ΔPINC:

[0066] ,

[0067] The frequency stability is determined by combining the preset threshold PINC_TH. When the frequency control word increment ΔPINC is less than the threshold PINC_TH, S... freq It is 1 if it is true, otherwise it is 0.

[0068] Phase stability score S phase Based on the root mean square (RMS) phase error from the internal statistical window, a piecewise linear deduction evaluation is performed using dual thresholds [E1, E2]. E1 is set to 1.5 to 3 times the RMS of natural phase jitter caused by background noise under ideal locking conditions. If the error is within this range, it indicates that the system is in perfect tracking condition, and a full score of 255 is given. E2 is usually set to 3 to 6 times the RMS of natural phase jitter. If it exceeds this value, it indicates that the phase error has far exceeded the random disturbance of normal noise, and the system is likely experiencing frequency abrupt changes or signal loss. In this case, an extremely low score or even 0 points is given.

[0069] Amplitude Consistency Score amp Based on the steady-state convergence of the demodulated amplitude estimate, the following is determined: whether the local variance of the amplitude within the sliding statistical window is lower than a preset fluctuation threshold; when the amplitude meets the steady-state convergence condition of the corresponding mode and is maintained for a set time, S... amp The highest score of 255 is taken; when the convergence condition is deviated from, points are deducted in segments according to the magnitude of the deviation or variance. The reliability scoring formula is as follows:

[0070] ,

[0071] ω1 and ω2 are both weighting coefficients.

[0072] (4) Throughout the entire operation cycle, the communication module encapsulates the amplitude and S into a fixed-byte frame format and sends it to the host computer. Based on this quantization score, the host computer can extract the amplitude data and understand the demodulation link status without needing to understand the complex waveforms inside the FPGA.

[0073] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A FPGA-based demodulation reliability quantization lock-in amplifier system, characterized in that, The system includes a DC-DC de-energizing module, an external reference tracking module, and a communication output module. One end of the DC-DC de-energizing module is connected to the input signal, and the other end is connected to the first input terminal of the first mixer module and the first input terminal of the second mixer module. One end of the external reference tracking module is connected to an external reference signal, and the other end is connected to the second input terminal of the first mixer module and the second input terminal of the second mixer module. The output terminal of the first mixer module is connected to the first input terminal of the CORDIC arithmetic module through a first CIC filter module and a first FIR low-pass filter module. The output terminal of the second mixer module is connected to the second input terminal of the CORDIC arithmetic module through a second CIC filter module and a second FIR low-pass filter module. The output terminal of the CORDIC arithmetic module is connected to the first input terminal of the amplitude scaling module. The second input terminal of the amplitude scaling module is connected to a self-calibration module. The reliability scoring module is connected to the external reference tracking module, the CORDIC arithmetic module, and the amplitude scaling module, respectively, and is used to obtain the external reference lock status, frequency control word change, phase error statistics, and demodulation amplitude statistics, and generate a reliability score corresponding to the current demodulation result based on the status quantities. The communication output module is connected to the output of the amplitude scaling module, the reliability scoring module, and the host computer module, respectively.

2. The FPGA-based demodulation reliability quantization lock-in amplifier system according to claim 1, characterized in that, The self-calibration module is an online self-calibration module containing a floating-point divider. The floating-point divider calculates the self-calibration coefficients, which are then written back to the amplitude scaling module. The module provides a calibration completion flag or a valid calibration coefficient flag to the reliability scoring module. If calibration is incomplete or the calibration coefficients are invalid, the reliability score is set to zero or marked as invalid. The reliability scoring module calculates a quantized reliability score based on the stability of the external reference signal, the stability of the reference frequency, the phase error statistics, and the amplitude window consistency index, and transmits the reliability score to the host computer module.

3. The FPGA-based demodulation reliability quantization lock-in amplifier system according to claim 2, characterized in that, The reliability score is synthesized by weighting multiple signal scores reflecting the demodulation state, and the reliability score ranges from 0 to 255.

4. The FPGA-based demodulation reliability quantization lock-in amplifier system according to claim 3, characterized in that, The multiple signal scores reflecting the demodulation status include: S lock S freq S phase , and S amp S lock It is an external reference stable score, S freq It is a frequency stability score, S phase It is the phase stability score, S amp It is an amplitude consistency score.

5. The FPGA-based demodulation reliability quantization lock-in amplifier system according to claim 1, characterized in that, Including the following expressions: ， Where K is the self-calibration coefficient. In calibration mode, the known amplitude of the internal digital reference sine wave signal with the same frequency as the reference signal is input to the demodulation link. It is an amplitude estimate formed based on N valid amplitude samples in the input signal, where N is a positive integer.

6. The FPGA-based demodulation reliability quantization lock-in amplifier system according to claim 1, characterized in that, Including the following expressions: ， Where S is the reliability score, S lock It is an external reference stable score, S freq It is a frequency stability score, S phase It is the phase stability score, S amp It is an amplitude consistency score, where ω1 and ω2 are both weighting coefficients.

7. An FPGA-based demodulation reliability quantization phase-locked amplification method, including: Periodic measurement and phase tracking are performed on an external reference signal to generate two orthogonal reference signals with the same frequency as the external reference signal; The input signal is mixed with the two orthogonal reference signals respectively, and then decimation filtering, low-pass filtering and amplitude-phase calculation are performed in sequence to obtain the current demodulation amplitude and demodulation phase. Acquire the external reference lock status, frequency control word change, phase error statistics, and demodulation amplitude statistics; An external reference stability score and a frequency stability score are generated based on the external reference lock state and frequency control word change. A phase stability score and an amplitude consistency score are generated based on the phase error statistics and demodulation amplitude statistics. The external reference stability score, frequency stability score, phase stability score, and amplitude consistency score are combined to generate a reliability score corresponding to the current demodulation amplitude and demodulation phase. The demodulation amplitude, demodulation phase, and reliability score are then correlated and output.

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