delta-sigma loop filter with input feedforward

Abstract

Various embodiments of the invention relate to delta-sigma loop filters with input feedforward. A delta-sigma loop filter can include a first integrator and a quantizer having an input coupled to an output of the first integrator. The delta-sigma loop filter can also include a first summing node having an output coupled to an input of the first integrator. Further, the delta-sigma loop filter can include a feedforward path from an input of the delta-sigma loop filter to a first input of the first summing node. The delta-sigma loop filter can also include a first feedback path from an output of the quantizer to a second input of the first summing node.

Description

[0001] This application is a divisional application of the patent application filed on April 25, 2019, with international application number PCT / US2019 / 029216, Chinese application number 201980030789.6, and entitled "Δ-Σ loop filter with input feedforward".

[0002] Priority Statement

[0003] This patent application claims the benefit of U.S. Provisional Application No. 62 / 669,131, entitled “DELTA-SIGMA LOOP FILTER WITH INPUT FEEDFORWARD AND RELATED SYSTEMS, METHODS ANDDEVICES,” filed May 9, 2018, pursuant to 35 USC §119(e), and the benefit of U.S. Patent Application Serial No. 16 / 149,746, entitled “DELTA-SIGMA LOOP FILTERS WITH INPUT FEEDFORWARD,” filed October 2, 2018, which also claims priority to U.S. Provisional Application Serial No. 62 / 669,131, the contents and disclosures of which are hereby incorporated herein by reference in their entirety. Technical Field

[0004] This disclosure relates in its entirety to Δ-Σ loop filters, and more specifically, to analog-to-digital converters including Δ-Σ loop filters with input feedforward. Background Technology

[0005] Analog-to-digital converters (ADCs) are used in wireless communications to convert analog radio frequency (RF) signals into digital signals. An ADC may include an RF front end that includes an RF filter that rejects unwanted frequencies and passes through the desired frequencies (i.e., the "passband"), and typically allows compatibility with one or more communication protocols, such as Bluetooth, Bluetooth Low Energy (BLE), wireless, near field communication (NFC), etc.

[0006] Δ-Σ modulation is a technique used to encode analog signals (such as analog RF signals) into digital signals. Unlike the quantizer used in conventional ADCs that encode the absolute value of the signal (which introduces quantization error noise into the encoded digital signal), Δ-Σ modulation encodes the variations in the signal (i.e., the Δ of the signal). For example, a conventional Δ-Σ ADC can encode an analog signal using high-frequency Δ-Σ modulation, and then apply a filter to form a higher resolution but lower sample frequency digital output. Δ-Σ modulation is particularly useful in communication systems because it achieves higher transmission efficiency by transmitting only the changes in value between consecutive samples rather than the actual sample values. Attached Figure Description

[0007] Although this disclosure concludes with claims that specifically point out and clearly claim protection for particular embodiments, the various features and advantages of the embodiments within the scope of this disclosure can be more readily identified by the following description when read in conjunction with the accompanying drawings, in which: Figure 1A An exemplary second-order feedback Δ-Σ loop filter is shown; Figure 1B An exemplary second-order feedforward Δ-Σ loop filter is shown; Figure 1C An exemplary second-order enhanced feedforward Δ-Σ loop filter is shown; Figure 2 This is a block diagram illustrating exemplary Δ-Σ analog-to-digital converters (ADCs) according to various embodiments of the present disclosure; Figure 3 An exemplary second-order Δ-Σ loop filter according to one or more embodiments of the present disclosure is shown; Figure 4 An exemplary third-order Δ-Σ loop filter according to various embodiments of the present disclosure is shown; Figure 5 Exemplary Δ-Σ loop filters, including in-phase channels and positive traffic channels, as well as cross-coupled paths, are shown according to various embodiments of the present disclosure.

[0008] Figure 6A An exemplary second-order Δ-Σ loop filter including an in-phase channel and a positive traffic channel is shown according to various embodiments of the present disclosure; Figure 6B Another exemplary second-order Δ-Σ loop filter, including an in-phase channel and a positive traffic channel, is shown according to various embodiments of the present disclosure; Figure 7 Multiple curves are shown, illustrating the zero-point locations used for feedback zero-point optimization and orthogonal zero-point optimization; Figure 8Exemplary programmable second-order Δ-Σ loop filters including in-phase channels and positive-current channels are shown according to various embodiments of the present disclosure; Figure 9 Another exemplary programmable second-order Δ-Σ loop filter, including an in-phase channel and a positive traffic channel, is shown according to various embodiments of the present disclosure; Figure 10 An exemplary switched capacitor network according to one or more embodiments of the present disclosure is shown.

[0009] Figure 11A Exemplary devices including a programmable receiver according to various embodiments of the present disclosure are shown; Figure 11B Another exemplary device including a programmable receiver is shown according to various embodiments of the present disclosure; Figure 12 A top-level on-chip system was demonstrated; and Figure 13 An exemplary top-level system-on-chip including a Δ-Σ analog-to-digital converter is shown according to various embodiments of the present disclosure. Detailed Implementation

[0010] The various embodiments disclosed herein relate to loop filters, and more specifically, to Δ-Σ loop filters with input feedforward. According to some embodiments, the loop filter can be configured as a low-pass and / or quadrature Δ-Σ analog-to-digital converter (ADC). In at least some embodiments, the Δ-Σ loop filter can be configured to add feedforward at a summing node coupled to the input of the final integrator. In these and other embodiments, the final integrator has an output coupled to the input of a quantizer (notably, a summing node at the input of the quantizer is not required, thus reducing power consumption).

[0011] Furthermore, according to some embodiments, the receiver may include a configurable ADC comprising at least one Δ-Σ loop filter. In these and other embodiments, the receiver may be configured to switch between zero-IF and low-IF operation. In at least one embodiment, the bandwidth center frequency of the ADC may be programmed via one or more coefficients of one or more coupling paths of the loop filter, which allows the center frequency of the ADC to be adjusted (e.g., adjusted from zero to an intermediate frequency).

[0012] Compared to conventional Δ-Σ loop filters, Δ-Σ loop filters according to the various embodiments disclosed herein can reduce hardware requirements (e.g., reduce the number of amplifiers), and therefore the various embodiments can provide power and / or area savings that are superior to conventional devices.

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and specific embodiments in which this disclosure may be practiced are shown by way of example. These embodiments are described in sufficient detail to enable those skilled in the art to practice this disclosure. However, it should be understood that while the detailed description and specific examples indicate examples of embodiments of this disclosure, they are given by way of example only and not by way of limitation. Various substitutions, modifications, additions, rearrangements, or combinations thereof may be made within the scope of this disclosure and will be apparent to those skilled in the art.

[0014] In accordance with common practice, the various features shown in the accompanying drawings may not be drawn to scale. The illustrations presented herein are not intended to be actual views of any particular device (e.g., apparatus, system, etc.) or method, but are merely representations illustrating various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily expanded or reduced for clarity. Furthermore, some figures may be simplified for clarity. Thus, the figures may not show all components of a given device or all operations of a particular method.

[0015] The information and signals described herein can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout this specification can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. For clarity of presentation and description, some figures may show signals as single signals. Those skilled in the art will understand that signals may represent bus signals, wherein the bus may have various bit widths, and this disclosure can be implemented on any number of data signals comprising single data signals.

[0016] It should be understood that any reference to elements in this document using names such as "first," "second," etc., does not limit the number or order of these elements unless such limitation is explicitly stated. Rather, these names are used herein as a convenient way to distinguish two or more elements or two or more instances of a single element. Therefore, a reference to a first element and a second element does not imply that only two elements can be used, or that the first element must somehow precede the second element. Moreover, unless otherwise stated, a group of elements may include one or more elements. Similarly, elements sometimes referred to in the singular may also include one or more instances of the element.

[0017] As used in this article, an "Nth-order" loop filter refers to the number of integrator stages in a loop filter. For example, "first-order", "second-order" and "third-order" Δ-Σ loop filters refer to Δ-Σ loop filters with a single integrator stage, two integrator stages and three integrator stages, respectively.

[0018] Examples of Δ-Σ loop filters used in conventional ADCs include feedback Δ-Σ loop filters, feedforward Δ-Σ loop filters, and what is referred to herein as an enhanced feedforward Δ-Σ loop filter.

[0019] Figure 1A A conventional second-order feedback Δ-Σ loop filter 100 is illustrated. The loop filter 100 is configured to receive an input signal 101 at a first summing node 102, where a feedback signal 103 from a first feedback path 104 is subtracted from the input signal 101. The feedback signal 103 is the output signal of a primary feedback digital-to-analog converter (DAC) 106, which outputs a reference voltage based on the 'low' or 'high' output of a quantizer 108. The output signal from the first summing node 102 is fed to the input of a first loop integrator 110. The output signal of the first loop integrator 110 is fed to a summing node 112, where a feedback signal 113 from a second feedback path 116 is subtracted from the output signal of the first loop integrator 110. The feedback signal 113 is the output signal of a secondary feedback DAC 118, which outputs a reference voltage based on the output of the quantizer 108. The output signal of the second summing node 112 is sent to the second loop integrator 114, and the output signal of the second loop integrator 114 is sent to the quantizer 108. Each of the feedback signals 103 and 113 is amplified (e.g., through gain stages 120 and 122) at the input of the first summing node 102 and the input of the second summing node 112, respectively. This is known to the inventors of this disclosure. Figure 1A One drawback of the feedback Δ-Σ loop shown is that the loop integrator has more stringent design requirements because the gain stages (e.g., gain stages 120 and 122) at summing nodes 102 and 112 have large swing and linear (gain) requirements.

[0020] Figure 1BA conventional second-order feedforward Δ-Σ loop filter 130 is shown. The loop filter 130 is configured to receive the input signal 131 at a first summing node 132, where the feedback signal 133 from the feedback path 134 is subtracted from the input signal 131. The feedback signal 133 is the output signal of a primary DAC 136, which outputs a reference voltage based on the output of a quantizer 138. The output signal of the first summing node 132 is fed to a first loop integrator 140, and the output signal of the first loop integrator 140 is fed to a second loop integrator 142. The output signal of the first loop integrator 140 is also fed to a second summing node 144 via the feedforward path 146. The input signal 131 is also fed to the second summing node 144 via the second feedforward path 148. At the summing node 144, the input signal 131 and the output signal of the first loop integrator 140 are subtracted from the output signal of the second loop integrator 142. The output signal of the second summing node 144 is then fed to the quantizer 138.

[0021] Figure 1B Several drawbacks of the illustrated Δ-Σ loop filter 130 are known to the inventors of this disclosure. First, with Figure 1A Compared to the feedback Δ-Σ loop filter 100 shown, the Δ-Σ loop filter 130 includes an additional gain stage at the summing node (e.g., gain stages 150 and / or 152, which may include optical transconductance amplifiers (OTA)). The gain stages at summing nodes 132 and 144 impose some gain and swing requirements on loop integrators 140 and 142. Furthermore, this design can impose tight timing requirements on the adder circuitry. Finally, there is an additional load (sometimes a significant one) at the outputs of loop integrators 140 and summing node 132.

[0022] Figure 1C A conventional second-order enhanced feedforward Δ-Σ loop filter 160 is shown. During the operation of the loop filter 160, the signals of the two feedforward paths 162 and 164 are subtracted from the output signal of the first loop integrator 166 (i.e., at the summing node 168), and the output signal of the summing node 168 is fed to the second loop integrator 170. One disadvantage known to the inventors of this disclosure regarding the feedforward Δ-Σ loop filter 160 is that the completion time at the feedforward path 164 can complicate the setup of the loop integrator, and therefore timing constraints may be affected.

[0023] The various embodiments disclosed herein generally relate to ADCs with Δ-Σ loop filters, which, in addition to having other beneficial effects and advantages, may not suffer from some or all of the defects and disadvantages of conventional ADCs with Δ-Σ loop filters, such as Figure 1A , Figure 1B and Figure 1C The drawbacks and disadvantages shown are addressed. In some implementations, an input feedforward path and a second feedback path can be selected such that the summing node is coupled to the input of the final integrator, rather than to the input of the quantizer (e.g., see [link to implementation]). Figure 1B And therefore, the noise transfer function (NTF) and / or signal transfer function (STF) remain unchanged. It is noteworthy that the second-order Δ-Σ NTF with two zeros at DC (direct current, therefore no frequency variation) can be derived as a discrete-time (z-domain) form of (1-z-1)². At DC, z⁻¹ can be 1. With Figure 1A The STF of a feedback Δ-Σ loop, similar to the conventional loop filter 130 shown, can be z⁻². Figure 1B and Figure 1C In the conventional feedforward system shown: STF can be 1.

[0024] Although various embodiments of this disclosure are described as second-order or third-order input-feedforward Δ-Σ loop filters, these principles can be extended to any order (e.g., fourth, fifth, sixth, etc.). For various second-order embodiments, the load on the first integrator can be approximately one-third that of the conventional feedforward loop filter described above. Furthermore, with... Figure 1C Unlike the conventional feedforward Δ-Σ loop filter 160 shown, this one has little or no (unreasonable) completion time on the critical feedforward path. Furthermore, the second-order implementation can have fewer gain stages (e.g., amplifiers), which relaxes design requirements compared to the conventional loop filter described above. For various third-order implementations, fewer gain stages may be required compared to a conventional feedforward third-order loop filter, and the total load added at the input of the final integrator and the outputs of the first and second integrators may be less.

[0025] Some embodiments of this disclosure relate to ADCs and various input-feedforward Δ-Σ loop filters including one or more quadrature integrators. Quadrature integrators provide more efficient noise shaping (e.g., a beneficial effect of 10+ dB in Q-noise shaping) compared to feedback zero-point optimization (in a low-pass Δ-Σ modulator), where the output of the second integrator can be fed back to the input of the first integrator. In both cases, the NTF zeros are shifted from DC within the frequency band. However, in a quadrature Δ-Σ ADC, both zeros are in the signal band, and in the case of a low-pass Δ-Σ with zero-point optimization, one zero can be selectively placed in the signal band, and one zero can be placed in the image band.

[0026] Figure 2This is a block diagram illustrating a device 200 including a Δ-Σ ADC 202 according to various embodiments of the present disclosure. The Δ-Σ ADC 202 includes an RF front-end 204 and a digital filter 206. The Δ-Σ ADC, more specifically the RF front-end 204, may include one or more loop filters and / or modulators disclosed herein. In some embodiments, the Δ-Σ ADC 202 is operatively coupled to, or may be part of, a radio component 208. For example, the Δ-Σ ADC 202 may be used in a receiver for, for example, wireless communication, and in at least one embodiment, the ADC 202 may be part of a system-on-a-chip (SoC) including other components.

[0027] Discrete transforms, illustrating how discrete-time signals can be represented in the complex frequency domain during operation, are shown in the numerous figures used in describing embodiments of this disclosure. Those skilled in the art will understand that while embodiments of this disclosure include discrete transforms, such transforms do not limit the generality of the architecture described herein. Furthermore, the inclusion of discrete transforms is not intended to indicate that operation necessarily infringes upon any of the claims disclosed herein.

[0028] Figure 3 A second-order Δ-Σ loop filter 300 according to one or more embodiments of the present disclosure is shown. In some embodiments, the loop filter 300 may be included within a Δ-Σ modulator and / or a Δ-Σ ADC, and / or implemented as a Δ-Σ modulator and / or a Δ-Σ ADC.

[0029] The loop filter 300, configured to receive input signal 301, includes a summing node 305, a first integrator 306, a summing node 310, a second integrator 312, and a quantizer 314. As shown, the output of summing node 305 is operatively coupled to the input of the first integrator 306, and the output of the first integrator 306 is operatively coupled to the input of summing node 310 via a delay element 308. The delay element 308 may be configured to implement the delay via, for example, a switched capacitor circuit. The output of summing node 310 is operatively coupled to the input of the second integrator 312, and the output of the second integrator 312 is operatively coupled to the input of the quantizer 314.

[0030] The loop filter 300 also includes a feedforward path 302 that is operatively coupled to the input of the loop filter 300 and the input of the summing node 310. The feedforward path 302 includes an element 304 and a gain stage (e.g., OTA) 324.

[0031] Furthermore, the loop filter 300 includes a feedback path 316 that is operationally coupled to the output of the quantizer 314 and the input of the summing node 310. Feedback path 316 includes a DAC 309 and a gain stage (e.g., OTA) 328. The loop filter 300 also includes a feedback path 320 that is operationally coupled to the output of the quantizer 314 and the input of the summing node 305. Feedback path 320 includes a DAC 322 and a gain stage (e.g., OTA) 326.

[0032] Feedback path 316 and feedback path 320 can be characterized by the same discrete transformation coefficients, or they can be characterized by different discrete transformation coefficients.

[0033] During the intended operation of the loop filter 300, the summing node 305 may receive the input signal 301 and a first feedback signal 321 from the feedback path 320. The summing node 305 may subtract the feedback signal 321 from the input signal 301, and the output signal of the summing node 305 may be transmitted to the first integrator 306. Furthermore, the input signal 301 may be transmitted via the feedforward path 302 to the second summing node 310, which may subtract the input signal 301 and the feedback signal 315 from the feedback path 316 from the output signal of the first integrator 306. The output signal of the second summing node 310 may be transmitted to the second integrator 312, and the output signal of the second integrator 312 may be transmitted to the quantizer 314 (e.g., a comparator and latch).

[0034] According to some implementation schemes, the load on the first integrator 306 can be approximately one-third of that of the conventional feedforward loop filter described above. Furthermore, with... Figure 1C Unlike the conventional feedforward Δ-Σ loop filter 160 shown, it has little or no (unreasonable) completion time on path 308.

[0035] Figure 4 An exemplary third-order Δ-Σ loop filter 400 according to various embodiments of the present disclosure is shown. In some embodiments, the loop filter 400 may be included within a Δ-Σ modulator and / or a Δ-Σ ADC, and / or implemented as a Δ-Σ modulator and / or a Δ-Σ ADC.

[0036] The loop filter 400 includes summing nodes 420, 424, and 428, integrators 422, 426, and 430, and a quantizer 432. As shown, the output of summing node 420 is operatively coupled to the input of a first integrator 422, and the output of the first integrator 422 is operatively coupled to the input of summing node 424. The output of summing node 424 is operatively coupled to the input of a second integrator 426, and the output of the second integrator 426 is operatively coupled to summing node 428 via a delay element 452. The delay element 452 can be configured to implement the delay via, for example, a switched capacitor circuit. Additionally, the output of summing node 428 is operatively coupled to the input of a third integrator 430, and the output of the third integrator 430 is operatively coupled to the input of the quantizer 432.

[0037] The loop filter 400 also includes feedforward paths 402, 404, and 406. Feedforward path 402 is operatively coupled to the input of the loop filter 400 and the input of the summing node 428, and includes element 414 and a gain stage (e.g., OTA) 448. Feedforward path 404 is operatively coupled to the input of the loop filter 400 and the input of the summing node 428, and includes element 416 and a gain stage (e.g., OTA) 446. Feedforward path 406 is operatively coupled to the input of the loop filter 400 and the input of the summing node 424, and includes element 418 and a gain stage (e.g., OTA) 444.

[0038] The loop filter 400 also includes feedback paths 408, 410, and 412. Feedback path 408 is coupled between the output of quantizer 432 and summing node 420, and includes a DAC 409 and a gain stage (e.g., OTA) 440. Feedback path 410 is operatively coupled between the output of quantizer 432 and the input of summing node 424, and includes a DAC 411 and a gain stage (e.g., OTA) 442. Feedback path 412 is operatively coupled between the output of quantizer 432 and the input of summing node 428, and includes a DAC 413 and a gain stage (e.g., OTA) 450. One or more of feedback paths 408, 410, and 412 may be characterized by the same coefficients, or each of feedback paths 408, 410, and 412 may be characterized by different coefficients. In some implementations, DAC 409, DAC 411 and / or DAC 413 may determine the feedback gain and / or loop zeros and poles of the associated path.

[0039] During the intended operation of the loop filter 400, the summing node 420 may receive the input signal 401 and the feedback signal 458 from the feedback path 408. The summing node 420 may subtract the feedback signal 458 from the input signal 401, and the output signal of the summing node 420 may be transmitted to the integrator 422. The output signal of the integrator 422 may be transmitted to the summing node 424. Furthermore, the input signal 401 may be transmitted via feedforward paths 402, 404, and 406. Feedforward path 402 may transmit a feedforward signal 423 to the summing node 428, feedforward path 404 may transmit a feedforward signal 425 to the summing node 428, and feedforward path 406 may transmit a feedforward signal 427 to the summing node 424.

[0040] Summing node 424 can subtract feedforward signal 427 and feedback signal 460 from the output of first integrator 422, and the output of summing node 424 can be transmitted to integrator 426. The output of integrator 426 can be transmitted to summing node 428 via delay element 452. Summing node 428 can subtract feedforward signal 423, feedforward signal 425 and feedback signal 462 from the output of integrator 426, and the output of summing node 428 can be transmitted to integrator 430. The output of integrator 430 can be transmitted to quantizer 432, and the output of quantizer 432 can be transmitted via feedback paths 408, 410 and 412.

[0041] As shown in the figure, the first integrator 422 and the second integrator 426 may not receive the input of the loop filter 400, and in at least some embodiments, the main function of the first integrator 422 and the second integrator 426 may be to process quantization noise.

[0042] According to some embodiments, the loop filter may be included within an orthogonal Δ-Σ modulator (more specifically, an orthogonal Δ-Σ loop filter) and / or implemented as an orthogonal Δ-Σ modulator (more specifically, an orthogonal Δ-Σ loop filter). More specifically, in some embodiments, the orthogonal Δ-Σ loop filter may be implemented via one or more cross-coupled paths operatively coupled to two channels of the loop filter. Furthermore, as described more fully below, in some embodiments, the one or more coupling paths of the loop filter may be configurable and / or programmable.

[0043] Figure 5 An orthogonal Δ-Σ loop filter 500 according to various embodiments of the present disclosure is shown. The Δ-Σ loop filter 500 includes an in-phase channel (“I-channel”) 502 and an orthogonal channel (“Q-channel”) 504. Each of the I-channel 502 and the Q-channel 504 includes multiple integrator stages (e.g., Figure 5(The first and second stages are shown). Furthermore, the loop filter 500 includes coupling paths 506, 508, 510, and 512. I-channel 502 and Q-channel 504 may each include a loop filter (such as any loop filter disclosed herein) or another loop filter. Furthermore, as disclosed more fully below, one or more of the cross-coupling paths 506, 508, 510, and 512 can be characterized by coefficients. Furthermore, as described more fully below, one or more cross-coupling paths 506, 508, 510, and 512 can be enabled and disabled, and / or the coefficients of one or more cross-coupling paths 506, 508, 510, and 512 can be programmable.

[0044] According to some implementations, the output of a stage of I channel 502 (e.g., at the input of a quantizer) may be coupled to the input of a corresponding stage of Q channel 504 (e.g., at the input of a summing node). Furthermore, the output of a stage of Q channel 504 (e.g., at the input of a quantizer) may be coupled to the input of a corresponding stage of I channel 502 (e.g., at the input of a summing node). Additionally, in some implementations, the output of a stage of I channel 502 (e.g., a second stage) (e.g., at the input of a quantizer) may be coupled to the input of another stage of I channel 502 (e.g., a first stage) (e.g., at the input of a summing node). Furthermore, the output of a stage of Q channel 504 (e.g., a second stage) (e.g., at the input of a quantizer) may be coupled to the input of another stage of Q channel 504 (e.g., a first stage) (e.g., at the input of a summing node).

[0045] More specifically, as shown in the figure, coupling path 506 is operatively coupled between the output of the first stage of I-channel 502 (e.g., at the input of the quantizer) and the input of the first stage of Q-channel 504 (e.g., at the input of the summing node), and coupling path 508 is operatively coupled between the output of the first stage of Q-channel 504 (e.g., at the input of the quantizer) and the input of the first stage of I-channel 502 (e.g., at the input of the summing node). Furthermore, coupling path 510 is operatively coupled between the output of the second stage of I-channel 502 (e.g., at the input of the quantizer) and the input of the second stage of Q-channel 504 (e.g., at the input of the summing node), and coupling path 512 is operatively coupled between the output of the second stage of Q-channel 504 (e.g., at the input of the quantizer) and the input of the second stage of I-channel 502 (e.g., at the input of the summing node).

[0046] Furthermore, as shown in the figure, coupling path 514 is operatively coupled between the output of the second stage of I-channel 502 (e.g., at the input of the quantizer) and the input of the first stage of I-channel 502 (e.g., at the input of the summing node). Additionally, coupling path 516 is operatively coupled between the output of the second stage of Q-channel 504 (e.g., at the input of the quantizer) and the input of the first stage of Q-channel 504 (e.g., at the input of the summing node).

[0047] Although the Δ-Σ loop filter 500 is shown as a two-stage loop filter, embodiments of this disclosure are not limited thereto, and the Δ-Σ loop filter may include any number of stages. For example, in an embodiment where the loop filter includes three stages, the output of the third stage of the I-channel (e.g., at the input of the quantizer) may be coupled to the input of the third stage of the Q-channel (e.g., at the input of the summing node), and the output of the third stage of the Q-channel (e.g., at the input of the quantizer) may be coupled to the input of the third stage of the I-channel (e.g., at the input of the summing node).

[0048] Figure 6A A second-order orthogonal Δ-Σ loop filter 600 according to various embodiments of the present disclosure is illustrated. The loop filter 600 may include an in-phase channel (“I-channel”) 602 and an orthogonal channel (“Q-channel”) 642. The I-channel 602 includes summing nodes 604 and 608, integrators 606 and 610, a delay element 611, and a quantizer 612. The I-channel 602 also includes a feedforward path 616, a feedback path 618, and a feedback path 620. The Q-channel 642 includes summing nodes 644 and 648, integrators 646 and 650, a delay element 651, and a quantizer 652. The Q-channel 642 also includes a feedforward path 656, a feedback path 658, and a feedback path 660. In addition, I channel 602 includes gain stages (e.g., OTA) 624, 625, 626, 627, 628 and 629, and Q channel 604 includes gain stages (e.g., OTA) 664, 665, 666, 667, 668 and 669.

[0049] In some implementations, each of integrators 606, 610, 646, and 650 may include an orthogonal integrator. In these implementations, orthogonality may be achieved via cross-coupling paths 680, 682, 684, and 686. More specifically, the output of integrator 606 may be coupled to summing node 644 via coupling path 680, the output of integrator 610 may be coupled to summing node 648 via coupling path 684, the output of integrator 646 may be coupled to summing node 604 via coupling path 682, and the output of integrator 650 may be coupled to summing node 608 via coupling path 686.

[0050] During the intended operation of the loop filter 600, the summing node 604 may receive the input signal 601_I, the feedback signal 630 from the feedback path 620, and the signal 690 (i.e., the signal via the cross-coupling path 682). The summing node 604 may subtract the feedback signal 630 and the signal 690 from the input signal 601_I, and the output signal of the summing node 604 may be transmitted to the integrator 606. The output signal of the integrator 606 may be transmitted to the summing node 608 via the delay element 611. Furthermore, the input signal 601_I may be transmitted via the feedforward path 616, which may transmit the feedforward signal 632 to the summing node 608. The feedback signal 634, transmitted via the feedback path 618, may also be transmitted to the summing node 608.

[0051] Summing node 608 can subtract feedforward signal 632, feedback signal 634, and signal 692 (i.e., signals via cross-coupling path 686) from the output of first integrator 606, and the output signal of summing node 608 can be transmitted to integrator 610. The output of integrator 610 can be transmitted to quantizer 612, and the output signal of quantizer 612 can be transmitted via feedback paths 618 and 620.

[0052] Furthermore, summing node 644 can receive input signal 601_Q, feedback signal 670 from feedback path 660, and signal 691 (i.e., signals via cross-coupling path 680). Summing node 644 can subtract feedback signal 670 and signal 691 from input signal 601_Q, and the output signal of summing node 644 can be transmitted to integrator 646. The output signal of integrator 646 can be transmitted to summing node 648 via delay element 651. Additionally, input signal 601_Q can be transmitted via feedforward path 656, which can transmit feedforward signal 672 to summing node 648. Feedback signal 674 transmitted via feedback path 658 can also be transmitted to summing node 648.

[0053] Summing node 648 can subtract feedforward signal 672, feedback signal 674, and signal 693 (i.e., signals via cross-coupling path 684) from the output of first integrator 646, and the output signal of summing node 648 can be transmitted to integrator 650. The output of integrator 650 can be transmitted to quantizer 652, and the output signal of quantizer 652 can be transmitted via feedback paths 658 and 660.

[0054] Figure 6B Another exemplary second-order Δ-Σ loop filter 600' according to various embodiments of the present disclosure is shown. The filter 600', which can be implemented as, for example, a Δ-Σ modulator and / or a Δ-Σ ADC, is similar to... Figure 6A The loop filter 600' includes feedforward paths 702 and 704, each with a coefficient e. The loop filter 600' also includes feedback paths 706, 708, 710, and 712, each with a coefficient d. While these paths may have a relatively small impact in the low-IF / zero-IF case, feedforward paths 702 and 704 also eliminate the first integrator (e.g., integrators 606 and 646, see...). Figure 6A The input signal at the output of the integrator. In at least some embodiments, the quadrature integrator may have a transfer function z⁻¹ / (1-z⁻¹(1+d+cj)), so the integrator zeros may be at z=1+d+cj.

[0055] Figure 7 Curves 750 and 752 are shown, illustrating orthogonal zero-point optimization (e.g., as...). Figure 6A and Figure 6B How can (as shown) be optimized compared to low-pass zero-point (e.g., as shown)? Figure 3 and Figure 4 A more effective example is shown below. As described above, and referring to curve 752, in quadrature zero optimization, there are two zeros 754 in the signal band. In contrast, as shown by curve 750, in low-pass zero optimization, there are two zeros 756—one zero in the signal band and one zero in the image band. In some implementations, low-pass zero optimization can provide, for example, a beneficial effect of 3-dB from I+Q, and quadrature zero optimization can provide higher-order noise shaping from I+Q (e.g., a beneficial effect of 10+dB in terms of Q noise shaping).

[0056] Other embodiments of this disclosure relate to programmable receivers. More specifically, according to some embodiments, the programmable receiver may include a loop filter that can be configured and / or reconfigured between low-pass Δ-Σ or quadrature Δ-Σ by enabling and / or disabling one or more coefficients of one or more coupling paths of the loop filter. Furthermore, in some embodiments, the bandwidth center frequency (e.g., the bandwidth center frequency of the receiver including loop filter 600) can be programmed by programming one or more coefficients of one or more coupling paths. Therefore, in these and other embodiments, a receiver including a configurable ADC (e.g., loop filter 600) can switch between zero-IF operation and low-IF operation with minimal hardware requirements.

[0057] Figure 8 Embodiments of a second-order Δ-Σ loop filter 800 according to various embodiments of the present disclosure are shown. In some embodiments, the loop filter 800 may be included within a Δ-Σ modulator and / or a Δ-Σ ADC, and / or implemented as a Δ-Σ modulator and / or a Δ-Σ ADC. The loop filter 800 is similar to... Figure 6A The loop filter 600. However, the loop filter 800 also includes a feedback path 810 from the output of the integrator 610 to the input of the summing node 604. The loop filter 800 also includes a feedback path 820 from the output of the integrator 650 to the input of the summing node 644. Feedback path 810 and feedback path 820 may each be referred to herein as variable gain paths.

[0058] In some embodiments, the loop filter 800 can be configured by enabling / disabling one or more of cross-coupling paths 680, 682, 684, and 686 and / or variable gain paths 810 and 820. The loop filter may include or be part of a configurable ADC and / or a configurable receiver. In at least one embodiment, the cross-coupling paths can be enabled / disabled by configuring gain on the paths. For example, in low-pass mode, zero-point optimization (for noise shaping) can be achieved by enabling coefficient D of variable gain paths 810 and 820 and / or programming coefficient D, for example, via one or more control signals. Furthermore, for example, in quadrature mode, paths 810 and 820 can be disabled, and paths 680, 682, 684, and 686 can be enabled, and the bandwidth center frequency can be adjusted by programming coefficient C. Therefore, in at least one embodiment, the loop filter 800 can be used to implement a configurable receiver. Furthermore, the receiver can be programmed to function as a Zero-IF or Low-IF receiver by configuring the loop filter 800 to operate in low-pass or quadrature mode. Additionally, the configurable receiver can be configured for zero-point optimization by enabling variable gain paths 810 and 820 when cross-coupling paths 680, 682, 684, and 686 are disabled.

[0059] Figure 9 Another second-order Δ-Σ loop filter 900 according to various embodiments of the present disclosure is shown. According to some embodiments, the loop filter 900 can be implemented in a configurable receiver, wherein the polarity of one or more cross-coupled IQ paths can be changed. The loop filter 900 is similar to... Figure 8 The filter 900 includes a loop filter 800; however, the filter 900 also includes multiplexers 902, 904, 906, and 908, which enable (e.g., in response to one or more control signals received at one or more of the multiplexers 902, 904, 906, and 908) to switch the polarity of the cross-coupling coefficients C of the cross-coupling paths 922, 924, 926, and 928. Switching the polarity of one or more of the cross-coupling paths 922, 924, 926, and 928 enables a transition from the signal band to the image band, and vice versa.

[0060] It is worth noting that there exists a... Figure 9The Δ-Σ loop filter 900 shown enables at least four levels of programming / configuration. Programming levels include, but are not limited to: (1) enabling / disabling quadrature / low-pass mode; (2) switching between signal and image bands by selecting the polarity of the bandwidth center frequency; (3) in low-pass mode, zero-point optimization by enabling / disabling one or more variable gain paths; and (4) in quadrature mode, programming the ADC bandwidth center frequency by configuring one or more cross-coupling coefficients. In at least one embodiment, the loop filter (e.g., Figure 5 500 loop filter Figure 6A Loop filter 600, loop filter 600' of filter 6B, Figure 8 800 loop filter and Figure 9 One or more programming levels of the loop filter 900 can be set via a selection unit, which may include [missing information - likely related to a specific filter or feature]. Figure 11A and Figure 11B The illustrated implementation requires relatively little hardware. The selection unit may include, for example, only a configurable state machine, a switched capacitor network, logic, or any other suitable selection unit.

[0061] Figure 10 An exemplary switched capacitor network 1000 according to one or more embodiments of the present disclosure is illustrated. The switched capacitor network 1000 may be configured (e.g., via one or more switches S) to enable a quadrature Δ-Σ ADC (e.g., Figure 9 The loop filter 900 shown is programmed in one or more dimensions (e.g., four dimensions).

[0062] For example, the quad control signal Quad can be programmed in quadrature mode (e.g., enabling one or more paths including coefficient C). Furthermore, the LP_zero signal can enable feedback from the second integrator (e.g., integrator 610 and / or integrator 650) in low-pass mode for zero-point optimization (e.g., enabling one or more paths including coefficient D). For example, setting LP_zero and Quad to zero allows for low-pass mode configuration of the loop filter (e.g., ...). Figure 9 The loop filter (900) does not require zero-point optimization. (Signal Gain_ctrl) <n:0>This allows for gain programming of one or more paths, including coefficients C and / or D, in both quadrature and low-pass modes. Signal band + and band - allow for changing the polarity in quadrature mode (e.g., selecting between positive and negative signal bands).

[0063] As disclosed herein, one advantage of the various implementations of the Δ-Σ ADC loop filter is the selectability of either the positive or negative signal bandwidth center frequency. Furthermore, according to various implementations, the configurable receiver can switch to the image band to compensate for local oscillator surges by selecting between a mode using the positive signal bandwidth center frequency and a mode using the negative signal bandwidth center frequency.

[0064] Figure 11 illustrates an embodiment of system 1100 according to various embodiments of the present disclosure. System 1100 includes a configurable receiver 1102, wherein I and Q channels 1104 can be swapped (e.g., before I and Q signals are received at ADC 1105). In at least some embodiments, multiplexer 1106 can receive one or more control signals 1107, and in response thereto, I and Q channels 1104 can be swapped. Figure 11B An embodiment of a system 1110 including a configurable receiver 1112 is shown, wherein the frequency of a local oscillator (LO) signal 1114 received at the receiver 1112 is adjustable.

[0065] In low-power RF applications (such as Bluetooth Low Energy ("BLE")), quadrature null optimization may be more efficient than low-pass null optimization, where the receiver is low-IF (the center of the signal bandwidth is offset from zero frequency) and nulls in the image band are inefficient. The following will combine... Figure 11A and Figure 11B This paper discusses the beneficial effects and advantages of configurable receivers that implement one or more embodiments of orthogonal Δ-Σ ADC loop filters. For example, in low-power applications, power may be reduced by only 1 / 2 or 2 / 3, while some performance degradation may occur.

[0066] Figure 12 A top-level system-on-chip (SoC) 1200, as understood by the inventors of this disclosure, is shown. The top-level SoC includes a wireless receiver 1202 having a composite analog filter 1204 (e.g., Berkeley packet filter) and a medium-resolution ADC 1206 (e.g., successive approximation register ADC).

[0067] Figure 13 A top-level SoC 1250 according to various embodiments of the present disclosure is illustrated. As shown, the SoC 1250 includes an analog module 1252, a digital module 1254, a modem 1256, and a microcontroller 1258. For example, in some embodiments, the analog module 1252, the digital module 1254, and the modem 1256 may include or be part of a radio component 1260.

[0068] Analog module 1252, which may include an analog RF module, includes a Δ-Σ ADC 1270. For example, ADC 1270 may include one or more loop filters arranged according to one or more embodiments of the present disclosure. For example, ADC 1270 may include... Figure 3 300 loop filter Figure 4 400 loop filter Figure 5 500 loop filter Figure 6A 600 loop filter Figure 6B 600' loop filter Figure 8 800 loop filter and Figure 9 The loop filter 900. The output of the Δ-Σ ADC 1270 can be coupled to the digital filter 1272 of the digital module 1254.

[0069] It is worth noting that, Figure 12 The composite analog filter 1204 was replaced with Figure 13 The digital filter 1272 and the Δ-Σ ADC 1270. Therefore, in at least these embodiments, filtering can be applied from the high-power analog domain (…). Figure 12 Move to the lower power digital domain ( Figure 13 Furthermore, the higher resolution Δ-Σ ADC 1270 achieves improved dynamic range, with a proportional reduction in filtering (and elimination of unnecessary filter blocks preceding the ADC 1206, such as...). Figure 12 (As shown). The reduced power consumption makes the various embodiments described herein particularly suitable for low-power RF applications, and is compatible with... Figure 12 Compared to the receiver 1202 shown, it can improve the signal quantization noise ratio (SNQR).

[0070] Various embodiments of this disclosure eliminate the need for a summing gain stage (e.g., an amplifier) ​​in the input feedforward path of the Δ-Σ loop filter. Furthermore, various embodiments retain the beneficial effect of having input feedforward in the Δ-Σ loop filter without adding an additional summing gain stage (e.g., an OTA). Some embodiments may not require a timing-critical path in the feedforward architecture. Moreover, unlike other feedforward Δ-Σ loop filters, various embodiments may not increase the load on the first integrator.

[0071] Various implementations can be applied to multi-order (e.g., second-order, third-order, etc.) Δ-Σ loop filters, and some implementations can be extended to orthogonal Δ-Σ loop filters and low-pass Δ-Σ loop filters. Furthermore, some implementations can reduce Δ-Σ loop power (e.g., by approximately 1 / 3) by eliminating the summing gain stage (e.g., an amplifier), reducing the first integrator (e.g., ... Figure 3 Integrator 306 Figure 4 Integrator 422, Figure 6A The load of integrator 606 and / or integrator 646) and / or avoid timing critical paths.

[0072] For example, in one specific implementation, the Δ-Σ ADC can exhibit a signal-to-noise ratio (SNDR) of 67 dB, utilize a bandwidth of approximately 2 MHz, and consume approximately 0.5 mW (I+Q) of power. Furthermore, in this implementation, the factor of quality (FOM) can be approximately 35 f J / conv. Additionally, the oversampling ratio can be approximately 15+, the receiver area can be <1 mm², the filtering before the ADC can be relatively small, and the number of operational amplifiers and DACs per channel can be, for example, two or three. Furthermore, in some implementations, for quadrature implementations, handshaking can occur between the ADC I and Q channels.

[0073] The embodiments disclosed herein are not limited to a specific RF topology, and the embodiments specifically envisioned herein can be used with a range of RF topologies. As non-limiting examples, these include topologies based on IEEE 802.15.4 technical standards (such as ZigBee, ISA100.11a, WirelessHART, SNAP, and Threading); low-power topologies based on Bluetooth Low Energy, ANT, ANT+, and low-rate wireless personal area networks; WiFi topologies; and topologies that include or are backward compatible with the foregoing, such as those based on Bluetooth 5.0.

[0074] Those skilled in the art will understand that a wireless receiver implementing one or more embodiments of this disclosure can be used to communicate using unlicensed frequencies including 2.4 GHz, 3.5 GHz, and 5 GHz and across a variety of spectrums, such as spectrum allocated for commercial communication services, including very low frequencies (about 3 kHz to 30 kHz), low frequencies (about 30 to 300 kHz), medium frequencies (about 300 kHz to 3,000 kHz), and high frequencies (about 3 MHz to 30 MHz), very high frequencies (about 30 MHz to 300 MHz), extra-high frequencies (about 300 MHz to 3000 MHz), ultra-high frequencies (about 3 GHz to 30 GHz), and extremely high frequencies (about 30 GHz to 300 GHz).

[0075] As used in this disclosure, the terms "module" or "component" can refer to a specific hardware implementation configured to perform actions of a module or component and / or software object or software routine that can be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, etc.) of a computing system. In some implementations, the different components, modules, engines, and services described in this disclosure can be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0076] Terms used in this disclosure, and especially in the appended claims (e.g., the body of the appended claims), are generally intended to be "open" terms (e.g., the term "comprising" should be interpreted as "including but not limited to", the term "having" should be interpreted as "at least having", the term "comprising" should be interpreted as "including but not limited to", etc.).

[0077] Furthermore, if a specific number of introduced claim statements are anticipated, such an intent will be explicitly stated in the claims, and without such statements, no such intent exists. For example, to aid understanding, the appended claims may contain the use of introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be construed as implying that a claim statement introduced by the indefinite article "a" or "an" limits any particular claim containing such an introduced claim statement to an embodiment containing only one such statement, even when the same claim includes the introductory phrase "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and / or "an" can be interpreted as referring to "at least one" or "one or more"); the same applies to the use of definite articles for introducing claim statements.

[0078] Furthermore, even when specific numbers of the introduced claim statements are explicitly listed, those skilled in the art will recognize that such statements should be interpreted as referring to at least the number listed (e.g., in the absence of other modifiers, the basic expression "two statements" means at least two statements or two or more statements). Moreover, in cases where conventions such as "at least one of A, B, and C" or "one or more of A, B, and C" are used, such constructions are generally intended to include only A, only B, only C, both A and B, both A and C, both B and C, or all three A, B, and C, etc.

[0079] Furthermore, any separate word or phrase presenting two or more additional terms, whether in the specification, claims, or drawings, should be understood to include the possibility of including one of the terms, either of the two terms, or both of the two terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0080] Additional non-limiting embodiments of this disclosure include: Implementation Scheme 1: An apparatus comprising: an analog module including a Δ-Σ analog-to-digital converter (ADC), the Δ-Σ ADC including: a first integrator; a quantizer having an input coupled to an output of the first integrator; a first summing node having an output coupled to an input of the first integrator; a feedforward path from an input of the Δ-Σ ADC to a first input of the first summing node; and a first feedback path from an output of the quantizer to a second input of the first summing node; a digital module including a digital filter coupled to an output of the Δ-Σ ADC; and a modem coupled to an output of the digital module.

[0081] Implementation Scheme 2: According to the device described in Implementation Scheme 1, the Δ-Σ ADC further includes: a second summing node having a first input terminal coupled to the input terminal of the Δ-Σ ADC; and a second quantizer having an input terminal coupled to the output terminal of the second summing node and an output terminal coupled to the third input terminal of the first summing node.

[0082] Implementation Scheme 3: The device according to any one of Implementation Schemes 1 and 2, wherein the Δ-Σ ADC further includes a second feedback path, the second feedback path extending from the output of the quantizer to the second input of the second summing node.

[0083] Implementation Scheme 4: The device according to any one of Implementation Schemes 1 to 3, wherein the first feedback path and the second feedback path are each characterized by different coefficients.

[0084] Implementation Scheme 5: The device according to any one of Implementation Schemes 1 to 4, wherein the second summing node is configured to: receive the input signal of the Δ-Σ ADC; subtract the signal of the second feedback path from the input signal to generate an output signal; and transmit the output signal to the second integrator.

[0085] Implementation Scheme 6: The device according to any one of Implementation Schemes 1 to 5, wherein the first summing node is configured to: receive an input signal from the second integrator; subtract the signal of the first feedback path and the signal of the feedforward path from the input signal to generate an output signal; and transmit the output signal to the first integrator.

[0086] Implementation Scheme 7: The device according to any one of Implementation Schemes 1 to 6 further includes a delay element coupled to a third input terminal of the first summing node.

[0087] Implementation Scheme 8: The device according to any one of Implementation Schemes 1 to 7 further includes a microcontroller coupled to the modem.

[0088] Implementation Scheme 9: An analog-to-digital converter (ADC) including a Δ-Σ loop filter, the Δ-Σ loop filter comprising: a first integrator; a first summing node having a first input coupled to the output of the first integrator; a second integrator having an input coupled to the output of the first summing node; a quantizer having an input coupled to the output of the second integrator; an input feedforward path from the input of the Δ-Σ loop filter to a second input of the first summing node; a first feedback path from the output of the quantizer to a third input of the first summing node; a second summing node having a first input coupled to the input of the Δ-Σ loop filter and an output coupled to the input of the first integrator; and a second feedback path from the output of the quantizer to the second input of the second summing node.

[0089] Implementation Scheme 10: The ADC according to Implementation Scheme 9, wherein the second summing node is configured to generate an output signal based on the signal of the second feedback path and the signal at the input of the Δ-Σ loop filter.

[0090] Implementation Scheme 11: An ADC according to any one of Implementation Schemes 9 and 10, wherein the first summing node is configured to generate an output signal based on the signal from the first feedback path, the signal from the first integrator, and the signal from the input feedforward path.

[0091] Implementation Scheme 12: The ADC according to any one of Implementation Schemes 9 to 11 further includes a delay element coupled between the first integrator and the first summing node.

[0092] Implementation Scheme 13: The ADC according to any one of Implementation Schemes 9 to 12, wherein the first feedback path includes a digital-to-analog converter (DAC) and the first feedback path is characterized by a first coefficient, and the second feedback path includes a DAC and the second feedback path is characterized by a different second coefficient.

[0093] Implementation Scheme 14: The ADC according to any one of Implementation Schemes 9 to 13, wherein each of the first feedback path, the second feedback path and the input feedforward path includes an amplifier coupled to an associated summing node.

[0094] Implementation Scheme 15: An analog-to-digital converter (ADC) including a Δ-Σ loop filter, the Δ-Σ loop filter comprising: a first summing node having a first input terminal coupled to an input terminal of the Δ-Σ loop filter; a first integrator having an input terminal coupled to an output terminal of the first summing node; a second summing node having a first input terminal coupled to an output terminal of the first integrator; a second integrator having an input terminal coupled to an output terminal of the second summing node; and a third summing node having an input terminal coupled to an output terminal of the first summing node. The following components are described: a first input terminal of the output terminal of a dual integrator; a third integrator having an input terminal coupled to the output terminal of the third summing node; a quantizer having an input terminal coupled to the output terminal of the third integrator; a first input feedforward path from the input terminal of the Δ-Σ loop filter to the second input terminal of the second summing node; a first feedback path from the output terminal of the quantizer to the second input terminal of the first summing node; and a second feedback path from the output terminal of the quantizer to the third input terminal of the second summing node.

[0095] Implementation Scheme 16: According to the ADC of Implementation Scheme 15, the Δ-Σ loop filter further includes a second input feedforward path, the second input feedforward path extending from the input end of the Δ-Σ loop filter to the second input end of the third summing node.

[0096] Implementation Scheme 17: According to any one of Implementation Schemes 15 and 16, the Δ-Σ loop filter further includes a third input feedforward path, the third input feedforward path extending from the input terminal of the Δ-Σ loop filter to the third input terminal of the third summing node.

[0097] Implementation Scheme 18: According to any one of Implementation Schemes 15 to 17, the Δ-Σ loop filter further includes a third feedback path, the third feedback path extending from the output of the quantizer to the fourth input of the third summing node.

[0098] Implementation Scheme 19: The ADC according to any one of Implementation Schemes 15 to 18, wherein the first feedback path, the second feedback path and the third feedback path are each characterized by different coefficients.

[0099] Implementation Scheme 20: The ADC according to any one of Implementation Schemes 15 to 19 further includes a delay element coupled between the output of the second integrator and the first input of the third summing node.

[0100] Implementation Scheme 21: An analog-to-digital converter (ADC) includes: a first channel configured to receive an in-phase signal and including a first Δ-Σ loop filter; and a second channel configured to receive a quadrature signal and including a second Δ-Σ loop filter; each of the first Δ-Σ loop filter and the second Δ-Σ loop filter includes: a first integrator; a quantizer having an input coupled to an output of the first integrator; a first summing node having an output coupled to an input of the first integrator; a feedforward path from an input of the Δ-Σ loop filter to a first input of the first summing node; and a first feedback path from an output of the quantizer to a second input of the first summing node.

[0101] Implementation Scheme 22: According to the ADC of Implementation Scheme 21, each of the first Δ-Σ loop filter and the second Δ-Σ loop filter further includes: a second summing node having a first input coupled to the input of the Δ-Σ loop filter; a second integrator having an input coupled to the output of the second summing node and an output coupled to a third input of the first summing node; and a second feedback path from the output of the quantizer to a second input of the second summing node.

[0102] Implementation Scheme 23: The ADC according to any one of Implementation Schemes 21 and 22 further includes: a first path, the first path coupling the output of the first integrator of the first Δ-Σ loop filter to a third input of the second summing node of the second Δ-Σ loop filter; a second path, the second path coupling the output of the first integrator of the second Δ-Σ loop filter to a third input of the second summing node of the first Δ-Σ loop filter; a third path, the third path coupling the output of the second integrator of the first Δ-Σ loop filter to a fourth input of the first summing node of the second Δ-Σ loop filter; and a fourth path, the fourth path coupling the output of the second integrator of the second Δ-Σ loop filter to a fourth input of the first summing node of the first Δ-Σ loop filter.

[0103] Implementation Scheme 24: The ADC according to any one of Implementation Schemes 21 to 23, wherein at least one of the first path, the second path, the third path and the fourth path includes a multiplexer for switching the polarity of the coefficients of the associated path.

[0104] Implementation Scheme 25: An ADC according to any one of Implementation Schemes 21 to 24, wherein: each of the first path, the second path, the third path, and the fourth path includes programmable coefficients; and each of the first path, the second path, the third path, and the fourth path is configured to be in one of an enabled state and a disabled state.

[0105] Implementation Scheme 26: The ADC according to any one of Implementation Schemes 21 to 25 further includes: a fifth path, the fifth path coupling the output of the first integrator of the first Δ-Σ loop filter to the fourth input of the second summing node of the first Δ-Σ loop filter; and a sixth path, the sixth path coupling the output of the first integrator of the second Δ-Σ loop filter to the third input of the second summing node of the second Δ-Σ loop filter.

[0106] Implementation Scheme 27: An ADC according to any one of Implementation Schemes 21 to 26, wherein: each of the fifth path and the sixth path includes programmable coefficients; and each of the fifth path and the sixth path is configured to be in one of an enabled state and a disabled state.

[0107] Implementation Scheme 28: The ADC according to any one of Implementation Schemes 21 to 27 further includes: a fifth path, the fifth path coupling the input terminal of the first Δ-Σ loop filter to the fifth input terminal of the first summing node of the second Δ-Σ loop filter; and a sixth path, the sixth path coupling the input terminal of the second Δ-Σ loop filter to the fifth input terminal of the first summing node of the first Δ-Σ loop filter.

[0108] Implementation Scheme 29: The ADC according to any one of Implementation Schemes 21 to 28 further includes: a seventh path, the seventh path coupling the output of the second integrator of the first Δ-Σ loop filter to the third input of the second summing node of the first Δ-Σ loop filter; and an eighth path, the eighth path coupling the output of the first integrator of the first Δ-Σ loop filter to the sixth input of the first summing node of the first Δ-Σ loop filter; a ninth path, the ninth path coupling the output of the second integrator of the second Δ-Σ loop filter to the third input of the second summing node of the second Δ-Σ loop filter; and a tenth path, the tenth path coupling the output of the first integrator of the second Δ-Σ loop filter to the sixth input of the first summing node of the second Δ-Σ loop filter.

[0109] Implementation Scheme 30: An apparatus comprising: an analog module including a Δ-Σ analog-to-digital converter (ADC), the Δ-Σ ADC including a plurality of channels, each channel including: a first integrator; a first summing node having a first input coupled to an input of a Δ-Σ loop filter and an output coupled to an input of the first integrator; a second summing node having a first input coupled to an output of the first integrator; a second integrator having an input coupled to an output of the second summing node; a quantizer having an input coupled to an output of the second integrator; an input feedforward path from the input of the Δ-Σ loop filter to a second input of the second summing node; a first feedback path from the output of the quantizer to a third input of the second summing node; and a second feedback path from the output of the quantizer to the second input of the first summing node; a digital module including a digital filter coupled to an output of the Δ-Σ ADC; and a modem coupled to an output of the digital module.

[0110] Implementation Scheme 31: The device according to Implementation Scheme 30, wherein the first summing node is configured to generate an output signal based on the signal of the second feedback path and the signal at the input of the Δ-Σ loop filter.

[0111] Implementation Scheme 32: The device according to any one of Implementation Schemes 30 and 31, wherein the second summing node is configured to generate an output signal based on the signal from the first feedback path, the signal from the first integrator, and the signal from the input feedforward path.

[0112] Implementation Scheme 33: The device according to any one of Implementation Schemes 30 to 32 further includes a switched capacitor network coupled to the Δ-Σ ADC and configured to program the Δ-Σ ADC.

[0113] Implementation Scheme 34: An orthogonal Δ-Σ analog-to-digital converter (ADC) includes: a first channel and a second channel, the first channel being configured to receive an in-phase signal and the second channel being configured to receive a quadrature signal, each of the first channel and the second channel including: a first integrator; a first summing node having a first input coupled to an input of the channel and an output coupled to an input of the first integrator; a second summing node having a first input coupled to an output of the first integrator; a second integrator having an input coupled to an output of the second summing node; a quantizer having an input coupled to an output of the second integrator; an input feedforward path from an input of the Δ-Σ loop filter to a second input of the second summing node; and at least one feedback path from an output of the quantizer coupled to at least one of the first summing node and the second summing node.

[0114] Implementation Scheme 35: The orthogonal Δ-Σ ADC according to Implementation Scheme 34, wherein the at least one feedback path includes: a first feedback path, the first feedback path extending from the output of the quantizer to the third input of the second summing node; and a second feedback path, the second feedback path extending from the output of the quantizer to the second input of the first summing node.

[0115] Implementation Scheme 36: An orthogonal Δ-Σ ADC according to any one of Implementation Schemes 34 and 35, wherein each of the first channel and the second channel includes a third feedback path from the output of the second integrator to the first summing node.

[0116] Implementation Scheme 37: An orthogonal Δ-Σ ADC according to any one of Implementation Schemes 34 to 36, wherein the third feedback path includes programmable coefficients.

[0117] Implementation Scheme 38: The orthogonal Δ-Σ ADC according to any one of Implementation Schemes 34 to 37 further includes a first cross-coupling path, the first cross-coupling path coupling the output of the first integrator of the first channel to the second summing node of the second channel; a second cross-coupling path, the second cross-coupling path coupling the output of the first integrator of the second channel to the second summing node of the first channel; a third cross-coupling path, the third cross-coupling path coupling the output of the second integrator of the first channel to the first summing node of the second channel; and a fourth cross-coupling path, the fourth cross-coupling path coupling the output of the second integrator of the second channel to the first summing node of the first channel.

[0118] Implementation Scheme 39: An orthogonal Δ-Σ ADC according to any one of Implementation Schemes 34 to 38, wherein at least one of the first cross-coupling path, the second cross-coupling path, the third cross-coupling path, and the fourth cross-coupling path includes a programmable gain.

[0119] Implementation Scheme 40: An orthogonal Δ-Σ ADC according to any one of Implementation Schemes 34 to 39, wherein at least one of the first cross-coupled path, the second cross-coupled path, the third cross-coupled path, and the fourth cross-coupled path includes a multiplexer for switching the polarity of coefficients of the associated path.

[0120] Implementation Scheme 41: An analog-to-digital converter, comprising: an input terminal configured to receive an analog signal; and a first selectable channel and a second selectable channel, each of the first selectable channel and the second selectable channel comprising a Δ-Σ loop filter, wherein the first selectable channel is configured to receive an analog signal from the input terminal, and the second selectable channel is configured to receive another analog signal from the input terminal that is 90 degrees out of phase with the analog signal.

[0121] Implementation Scheme 42: A circuit comprising: a first filter circuit configured for a first polarity input signal; a second filter circuit configured for a second polarity input signal; and a cross-coupling circuit configured to operatively couple the first filter circuit and the second filter circuit.

[0122] Implementation Scheme 43: According to the circuit of Implementation Scheme 42, wherein the cross-coupling circuit is configured to: operatively couple the input of the quantizer of the first filter circuit to the input feedforward path of the second filter circuit, and operatively couple the input of the quantizer of the second filter circuit to the input feedforward path of the first filter circuit.

[0123] Implementation Scheme 44: The circuit according to any one of Implementation Schemes 42 and 43, wherein the cross-coupling circuit is configured to: operatively couple the output of the intermediate integrator of the first filter circuit to a summing node at the input of the intermediate integrator of the second filter circuit; and operatively couple the output of the intermediate integrator of the second filter circuit to a summing node at the input of the intermediate integrator of the first filter circuit.

[0124] Implementation Scheme 45: The circuit according to any one of Implementation Schemes 43 to 44 further includes: a first variable gain path, the first variable gain path extending from the input terminal of the quantizer of the first filter circuit to the summing node at the input terminal of the intermediate integrator of the first filter circuit; and a second variable gain path, the second variable gain path extending from the input terminal of the quantizer of the second filter circuit to the summing node at the input terminal of the intermediate integrator of the second filter circuit.

[0125] Implementation Scheme 46: The circuit according to any one of Implementation Schemes 42 to 45, wherein the gain of the first variable gain path and the gain of the second variable gain path are configurable.

[0126] Implementation Scheme 47: A radio frequency receiver includes: an analog-to-digital converter; and control circuitry operatively coupled to the analog-to-digital converter and configured to change one or more operating characteristics of the analog-to-digital converter in response to a plurality of selection circuits.

[0127] Implementation Scheme 48: The receiver according to Implementation Scheme 47, wherein the control circuit is a switched capacitor network, and one or more of the plurality of selection circuits are capacitors.

[0128] Implementation Scheme 49: The receiver according to Implementation Schemes 47 and 48, wherein the one or more operating characteristics include one or more operating modes and one or more operating parameters.

[0129] Implementation Scheme 50: A receiver according to any one of Implementation Schemes 47 to 49, wherein the one or more operating modes include orthogonal mode, low-pass mode, low-pass zero-point optimized mode, and combinations thereof.

[0130] Implementation Scheme 51: A receiver according to any one of Implementation Schemes 47 to 50, wherein one or more operating parameters include the center frequency bandwidth of the analog-to-digital converter.

[0131] Implementation Scheme 52: The receiver according to any one of Implementation Schemes 47 to 51, wherein the one or more operating modes include a zero intermediate frequency mode and a low intermediate frequency mode.

[0132] Implementation Scheme 53: The receiver according to any one of Implementation Schemes 47 to 52 further includes a digital filter, the digital filter being operatively coupled to the output of the analog-to-digital converter.

[0133] Any characterization of something as 'typical,' 'conventional,' or 'known' in this disclosure does not necessarily mean that the thing is disclosed in the prior art or understood in the prior art regarding the aspects discussed. Nor does it necessarily mean that it is well-known, readily understood, or routinely used in the relevant field.

[0134] While the invention has been described herein with reference to certain illustrated embodiments, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, numerous additions, deletions, and modifications may be made to the illustrated and described embodiments without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being included within the scope of the invention as contemplated by the inventors.

Claims

1. An orthogonal Δ-Σ analog-to-digital converter (ADC), the orthogonal Δ-Σ analog-to-digital converter (ADC) comprising a loop filter, the loop filter comprising: In-phase (I) channel and quadrature (Q) channel, each of the I channel and the Q channel comprising: The first summing node has a first input terminal coupled to the input terminal of the corresponding channel; A first integrator, the first integrator having an input coupled to the output of the first summing node; The second summing node has a first input terminal coupled to the output terminal of the first integrator; A second integrator, the second integrator having an input coupled to the output of the second summing node; A third summing node, the third summing node having a first input terminal coupled to the output terminal of the second integrator; A third integrator, the third integrator having an input coupled to the output of the third summing node; and A quantizer having an input that is directly coupled to the output of the third integrator; Multiple cross-coupling paths, each corresponding to a stage of the I channel and the Q channel, are characterized by a coefficient C that is programmable to adjust the bandwidth center frequency of the loop filter.

2. The orthogonal Δ-Σ ADC as described in claim 1, wherein, Each of the I-channel and the Q-channel further includes at least one input feedforward path from the input of the respective channel to the input of the second summing node or the third summing node, the at least one input feedforward path being configured to adjust the signal transfer function (STF) of the loop filter in the absence of a summing node between the third integrator and the quantizer.

3. The orthogonal Δ-Σ ADC as described in claim 1, wherein, Each of the I channel and the Q channel further includes: A first feedback path from the output of the quantizer to the second input of the first summing node; and The second feedback path from the output of the quantizer to the input of the second summing node.

4. The orthogonal Δ-Σ ADC as described in claim 3, wherein, Each of the I channel and the Q channel further includes a third feedback path from the output of the quantizer to the input of the third summing node.

5. The orthogonal Δ-Σ ADC as described in claim 1, wherein, The multiple cross-coupling paths include: The first cross-coupling path couples the output of the first integrator of the I channel to the input of the summing node of the Q channel. The second cross-coupling path couples the output of the first integrator of the Q channel to the input of the summing node of the I channel; A third cross-coupling path, which couples the output of the second integrator in the I channel to the input of the summing node in the Q channel; and The fourth cross-coupling path couples the output of the second integrator of the Q channel to the input of the summing node of the I channel.

6. The orthogonal Δ-Σ ADC as described in claim 5, further comprising: The fifth cross-coupling path couples the output of the third integrator of the I channel to the input of the third summing node of the Q channel. as well as The sixth cross-coupling path couples the output of the third integrator of the Q channel to the input of the third summing node of the I channel.

7. The orthogonal Δ-Σ ADC of claim 1, wherein the plurality of cross-coupling paths provide at least 10 dB improvement in quantization noise shaping relative to the corresponding feedback zero-optimized configuration.

8. The orthogonal Δ-Σ ADC of claim 1, further comprising a delay element coupled between the output of the second integrator in at least one of the I channel and the Q channel and the first input of the third summing node.

9. A programmable Δ-Σ loop filter, comprising: In-phase (I) channel and quadrature (Q) channel, each of the I channel and the Q channel includes a first integrator, a second integrator and a third integrator connected in series via a first summing node, a second summing node and a third summing node; Multiple cross-coupling paths, each characterized by a programmable coefficient C, couple the corresponding levels of the I and Q channels; Multiple variable gain feedback paths, each characterized by a coefficient D, couple the output of the corresponding integrator to the first summing node of the corresponding channel; as well as The loop filter is configurable in one of the following options: In orthogonal mode, the cross-coupling path is enabled, and the bandwidth center frequency is adjustable via the coefficient C. In low-pass mode, the cross-coupling path is disabled and zero-point optimization is performed through the variable gain feedback path with the coefficient D.

10. The programmable Δ-Σ loop filter of claim 9, wherein each of the I channel and the Q channel further includes a quantizer having an input directly coupled to the output of the third integrator, without a summing node in between.

11. The programmable Δ-Σ loop filter of claim 9, wherein each of the I channel and the Q channel further includes at least one input feedforward path from the input of the respective channel to the input of the third summing node.

12. A configurable Δ-Σ loop filter, comprising: In-phase (I) channel and quadrature (Q) channel, each of the I channel and the Q channel includes a first integrator, a second integrator and a third integrator connected in series via a first summing node, a second summing node and a third summing node; Multiple cross-coupling paths, wherein the multiple cross-coupling paths couple corresponding levels of the I channel and the Q channel, and each cross-coupling path is characterized by a cross-coupling coefficient; as well as Multiple multiplexers, each coupled to a corresponding cross-coupling path and configured to select between the positive and negative polarities of the cross-coupling coefficients in response to a control signal, thereby switching the loop filter between the signal band and the image band.

13. The configurable Δ-Σ loop filter of claim 12, further comprising a plurality of variable gain feedback paths, each variable gain feedback path being characterized by a coefficient D, selectively enabling zero-point optimization of the noise transfer function when the loop filter is configured in low-pass mode.

14. The configurable Δ-Σ loop filter of claim 12, wherein the loop filter is configurable across four dimensions: (i) enabling or disabling quadrature mode to low-pass mode; (ii) switching between signal and image bands via the plurality of multiplexers; (iii) enabling or disabling zero-point optimization via a variable feedback path; and (iv) programming the bandwidth center frequency via the cross-coupling coefficient.

15. The configurable Δ-Σ loop filter of claim 14, further comprising a switched capacitor network including a plurality of switches configured to implement the four dimensions via a control signal including an orthogonal mode signal, a zero-point optimization signal, a gain control signal, and a bandwidth selection signal.

16. An apparatus comprising: A configurable receiver includes a Δ-Σ analog-to-digital converter (ADC) including a loop filter having an in-phase (I) channel and a quadrature (Q) channel, each of the I channel and the Q channel including a first integrator, a second integrator, and a third integrator coupled in series via a summing node, the I channel and the Q channel being coupled via a cross-coupling path characterized by programmable coefficients; A multiplexer configured to switch I and Q channels in response to a control signal to compensate for local oscillator (LO) surges; as well as A digital module coupled to the output of the configurable receiver.

17. The device of claim 16, wherein the configurable receiver is switchable between a zero-IF mode and a low-IF mode, wherein in the zero-IF mode the loop filter operates in a low-pass mode and in the low-IF mode the loop filter operates in a quadrature mode.

18. The device of claim 16, wherein each of the I channel and the Q channel further includes a quantizer having an input directly coupled to the output of the third integrator, without a summing node between the third integrator and the quantizer.

19. The device of claim 16, further comprising a system-on-a-chip (SoC), the SoC including the configurable receiver, the digital module, the modem, and the microcontroller.

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