BFSK and BPSK dual-mode transmitter with N-path filter and control method thereof

Abstract

The application discloses a BFSK and BPSK dual-mode transmitter with an N-path filter and a control method thereof. The transmitter comprises a high-frequency clock source, a frequency divider, a low-pass filter, an N-path filter, a multiplexer, a modulation unit and an output driving stage. The low-pass filter and the N-path filter are respectively used for filtering a high-frequency clock signal to obtain a low-frequency filtered signal and a high-frequency filtered signal. The multiplexer is used for determining a working mode of the transmitter according to a mode selection signal and a data input signal, and determining a current phase output combination in combination with the data input signal, so as to output the low-frequency filtered signal as a low-frequency selection signal. The modulation unit is used for outputting a modulation signal according to the high-frequency filtered signal and the low-frequency selection signal. The embodiment of the application can realize dual-mode output of BFSK and BPSK, reduce the circuit complexity, area and power consumption of the transmitter, and improve the quality of the output signal. The application can be widely applied in the field of wireless communication technology.

Description

Technical Field

[0001] This application relates to the field of wireless communication technology, and in particular to a dual-mode transmitter with N-path filter for BFSK and BPSK and its control method. Background Technology

[0002] Low-power wireless transmitters are commonly used in implantable biomedical devices, wearable sensors, and small IoT nodes. These devices are typically powered by small-capacity batteries or energy harvesting circuits, and their antenna size, chip area, and on-chip passive components are also limited. Therefore, transmitters must not only meet requirements for output frequency, transmit power, and spectral purity, but also minimize static and switching power consumption. In these applications, the transmitter architecture itself often determines the system's power consumption and feasibility more than the specifications of individual modules.

[0003] BFSK typically uses PLL frequency hopping to generate different frequencies, and BFSP also requires a PLL to provide an inverted signal with low phase noise. Existing low-power BFSK transmitters usually only focus on switching between two frequency points, making it difficult to directly provide 0° / 180° phase modulation capability at the same frequency. When the system requires phase modulation or needs to cooperate with a coherent receiver, the applicability of a single BFSK architecture is limited.

[0004] While it is theoretically easy to implement dual-mode functionality using independent BFSK and BPSK links, it would increase power consumption and area by adding mixers, phase switching circuits, buffer stages, and output selection switches. This is not conducive to low-power scenarios such as implantable biomedical devices, wearable sensors, and small IoT nodes.

[0005] Furthermore, existing solutions typically focus more on the spectral specifications of the final RF output, while neglecting the handling of near-end spurious signals in the high-frequency clock path before modulation. For transmitters that use a combination of high-frequency clock fH and low-frequency signal fL for modulation, spurious signals near fH±fL present before modulation will be shifted again during modulation, forming parasitic frequencies close to the target signal.

[0006] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0007] The main objective of this application is to propose a dual-mode BFSK and BPSK transmitter with an N-path filter and its control method. The dual-mode output of BFSK and BPSK can be achieved through the same circuit structure, which reduces the circuit complexity, area and power consumption of the transmitter, while improving the quality of the output signal.

[0008] To achieve the above objectives, one aspect of this application proposes a dual-mode BFSK and BPSK transmitter with an N-path filter, comprising a high-frequency clock source, a frequency divider, a low-pass filter, an N-path filter, a multiplexer, a modulation unit, and an output driver stage. The frequency divider and the N-path filter are both connected to the high-frequency clock source, and both the frequency divider and the multiplexer are connected to the low-pass filter. The multiplexer, the N-path filter, and the output driver stage are all connected to the modulation unit. The high-frequency clock source outputs a high-frequency clock signal. The frequency divider divides the high-frequency clock signal to output a low-frequency clock signal. The low-pass filter filters the low-frequency clock signal to output a low-frequency filtered signal. The N-path filter filters the high-frequency clock signal to output a high-frequency filtered signal. The multiplexer receives a mode selection signal and a data input signal, and determines the current transmitter operating mode based on the mode selection signal. The formula and the data input signal determine the current phase output combination. The multiplexer is also used to output the low-frequency filtered signal as a low-frequency selection signal according to the current phase output combination. The modulation unit is used to output a modulation signal according to the high-frequency filtered signal and the low-frequency selection signal. The output driver stage is used to amplify the modulation signal and output it. The current transmitter operating mode is BFSK mode or BPSK mode. The current phase output combination is one of a first phase combination, a second phase combination, and a third phase combination. When the current transmitter operating mode is BFSK mode, the current phase output combination is the first phase combination or the second phase combination. When the current transmitter operating mode is BPSK mode, the current phase output combination is the first phase combination or the third phase combination. The phase change direction of the first phase combination is opposite to the phase change direction of the second phase combination. Each phase of the first phase combination is out of phase with the corresponding phase of the third phase combination.

[0009] In some embodiments, the high-frequency clock source includes a phase-locked loop (PLL), which includes a phase-frequency discriminator, a charge pump, a loop low-pass filter, and a voltage-controlled oscillator (VCO).

[0010] In some embodiments, the frequency of the high-frequency clock signal is 480MHz, and the frequency divider is specifically used to divide the high-frequency clock signal by 48 to output the low-frequency clock signal with a frequency of 10MHz.

[0011] In some embodiments, the low-frequency filtered signal includes a 0° low-frequency phase signal, a 90° low-frequency phase signal, a 180° low-frequency phase signal, and a 270° low-frequency phase signal.

[0012] In some embodiments, the mode selection signal is a first mode signal or a second mode signal, the data input signal is a first data signal or a second data signal, and the multiplexer is specifically used for: When the mode selection signal is the first mode signal and the data input signal is the first data signal, the current transmitter operating mode is determined to be the BFSK mode, and the current phase output combination is determined to be the first phase combination; When the mode selection signal is the first mode signal and the data input signal is the second data signal, the current transmitter operating mode is determined to be the BFSK mode, and the current phase output combination is determined to be the second phase combination; When the mode selection signal is the second mode signal and the data input signal is the first data signal, the current transmitter operating mode is determined to be the BPSK mode, and the current phase output combination is determined to be the first phase combination; When the mode selection signal is the second mode signal and the data input signal is the second data signal, the current transmitter operating mode is determined to be the BPSK mode, and the current phase output combination is determined to be the third phase combination.

[0013] In some embodiments, the multiplexer includes a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, and the multiplexer is further specifically used for: When the current phase output combination is the first phase combination, the 180° low-frequency phase signal, the 270° low-frequency phase signal, the 0° low-frequency phase signal, and the 90° low-frequency phase signal are output through the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal respectively to obtain the low-frequency selection signal; When the current phase output combination is the second phase combination, the 270° low-frequency phase signal, the 180° low-frequency phase signal, the 90° low-frequency phase signal, and the 0° low-frequency phase signal are output through the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal, respectively, to obtain the low-frequency selection signal; When the current phase output combination is the third phase combination, the 0° low-frequency phase signal, the 90° low-frequency phase signal, the 180° low-frequency phase signal, and the 270° low-frequency phase signal are output through the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal, respectively, to obtain the low-frequency selection signal.

[0014] In some embodiments, the modulation signal is one of a first mixed modulation signal, a second mixed modulation signal, and a third mixed modulation signal. When the current phase output combination corresponding to the low-frequency selection signal is the first phase combination, the modulation signal is the first mixed modulation signal, and the frequency of the first mixed modulation signal is 490MHz. When the current phase output combination corresponding to the low-frequency selection signal is the second phase combination, the modulation signal is the second mixed modulation signal, and the frequency of the second mixed modulation signal is 470MHz. When the current phase output combination corresponding to the low-frequency selection signal is the third phase combination, the modulation signal is the third mixed modulation signal, and the frequency of the third mixed modulation signal is 490MHz. Furthermore, the first mixed modulation signal and the third mixed modulation signal are 180° out of phase.

[0015] In some embodiments, the N-path filter includes a differential input terminal, a differential output terminal, and four filtering paths. Each filtering path includes an input-side switching unit, an energy storage capacitor, and an output-side switching unit. The differential input terminal is connected to the input-side switching unit. Both the input-side switching unit and the output-side switching unit are connected to the first terminal of the energy storage capacitor. The output-side switching unit is connected to the differential output terminal. The second terminal of the energy storage capacitor is grounded.

[0016] In some embodiments, the N-path filter is further configured to receive a first control signal, a second control signal, a third control signal, and a fourth control signal. The first control signal, the second control signal, the third control signal, and the fourth control signal are multi-phase control signals with phases staggered sequentially. The first control signal, the second control signal, the third control signal, and the fourth control signal are respectively used to control the on and off states of the input-side switching unit and the output-side switching unit in the corresponding filtering path.

[0017] To achieve the above objectives, another aspect of this application proposes a control method for a BFSK and BPSK dual-mode transmitter with an N-path filter, which is used to implement the aforementioned BFSK and BPSK dual-mode transmitter. The method includes the following steps: A high-frequency clock signal is output through the high-frequency clock source; The high-frequency clock signal is divided by the frequency divider to output a low-frequency clock signal; The low-pass filter is used to filter the low-frequency clock signal to output a low-frequency filtered signal. The high-frequency clock signal is filtered by the N-path filter to output a high-frequency filtered signal; The multiplexer receives a mode selection signal and a data input signal, determines the current transmitter operating mode based on the mode selection signal, and determines the current phase output combination based on the current transmitter operating mode and the data input signal. The multiplexer outputs the low-frequency filtered signal as a low-frequency selected signal according to the current phase output combination. The modulation unit outputs a modulation signal based on the high-frequency filtered signal and the low-frequency selection signal. The modulated signal is amplified and output through the output driver stage; Wherein, the current transmitter operating mode is BFSK mode or BPSK mode, and the current phase output combination is one of a first phase combination, a second phase combination, and a third phase combination. When the current transmitter operating mode is BFSK mode, the current phase output combination is either the first phase combination or the second phase combination. When the current transmitter operating mode is BPSK mode, the current phase output combination is either the first phase combination or the third phase combination. The phase change direction of the first phase combination is opposite to the phase change direction of the second phase combination, and each phase of the first phase combination is out of phase with the corresponding phase of the third phase combination.

[0018] The embodiments of this application include at least the following beneficial effects: This application provides a dual-mode BFSK and BPSK transmitter with an N-path filter and its control method. This scheme obtains a low-frequency filtered signal from a high-frequency clock signal through a frequency divider and a low-pass filter, and outputs the low-frequency filtered signal as a low-frequency selection signal with different phase combinations through a multiplexer. This allows the same modulation unit to switch between BFSK and BPSK modes without the need for an additional BPSK transmission link, reducing the number of independent modulation links and lowering the complexity of the circuit structure, chip area, and power consumption. At the same time, the N-path filter is located between the high-frequency clock source and the modulation unit, which can suppress spurious components in the high-frequency clock path before the high-frequency clock signal enters the modulation unit, thereby reducing the impact of spurious components in the high-frequency clock path on the final transmitted signal spectrum quality and improving the output stability and communication quality of the dual-mode transmitter. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the overall structure of a dual-mode BFSK and BPSK transmitter with an N-path filter provided in an embodiment of this application; Figure 2 This is a circuit schematic diagram of the multiplexer provided in the embodiments of this application; Figure 3 This is a circuit schematic diagram of the N-path filter provided in an embodiment of this application; Figure 4 This is an example of the output spectrum of a 470MHz modulated signal from a dual-mode BFSK and BPSK transmitter with an N-path filter in BFSK mode, as provided in this application embodiment. Figure 5 This is an example of the output spectrum of a 490MHz modulated signal from a dual-mode BFSK and BPSK transmitter with an N-path filter in BFSK mode, as provided in this application embodiment. Figure 6 This is a time-domain waveform diagram of the output signal corresponding to the two data states in BPSK mode of a dual-mode BFSK and BPSK transmitter with an N-path filter provided in an embodiment of this application. Figure 7 This is a comparison diagram showing the effect of the N-path filter provided in this application in filtering out 10MHz spurious components in a high-frequency clock signal; Figure 8 This is a flowchart illustrating the steps of a control method for a dual-mode BFSK and BPSK transmitter with an N-path filter, as provided in an embodiment of this application. Detailed Implementation To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0021] The terminology used in the embodiments of the present invention will be explained below.

[0022] BFSK (Binary Frequency Shift Keying): uses two different frequencies to represent binary data 0 and 1 respectively.

[0023] BPSK (Binary Phase Shift Keying): Represents binary data using two phase states that are 180° out of phase at the same carrier frequency.

[0024] PLL (Phase-Locked Loop): Used to generate the high-frequency clock or carrier signal required by the transmitter.

[0025] MUX (Multiplexer): Selects one or a group of signals from multiple inputs for output based on control signals.

[0026] DATA (Data Input Signal): The binary data to be sent, which controls the output frequency or output phase in different modes.

[0027] MODE (Mode Selection Signal): Used to select whether the transmitter operates in BFSK or BPSK mode.

[0028] The concept of the present invention will now be explained in conjunction with the background art.

[0029] Low-power wireless transmitters are commonly used in implantable biomedical devices, wearable sensors, and small IoT nodes. These devices are typically powered by small-capacity batteries or energy harvesting circuits, and their antenna size, chip area, and on-chip passive components are also limited. Therefore, transmitters must not only meet requirements for output frequency, transmit power, and spectral purity, but also minimize static and switching power consumption. In these applications, the transmitter architecture itself often determines the system's power consumption and feasibility more than the specifications of individual modules.

[0030] BFSK typically uses PLL frequency hopping to generate different frequencies, while BFSP also requires a PLL to provide an inverted signal with low phase noise. Recent IEEE research on low-power transmitters shows that existing solutions generally focus on architecture-level power reduction. For example, they utilize low-frequency polyphase signals combined with high-frequency clocks to generate the target frequency, employ edge synthesizers or digital power amplifiers to reduce the number of analog RF modules, or use injection locking, direct modulation of the local oscillator, etc., to reduce the power consumption of frequency synthesis and modulation links. A common feature of these methods is minimizing the number of independent RF links and multiplexing or merging modulation, frequency synthesis, and drive functions.

[0031] Existing low-power BFSK transmitters typically only focus on switching between two frequency points, making it difficult to directly provide 0° / 180° phase modulation capabilities at the same frequency. When the system requires phase modulation or needs to cooperate with a coherent receiver, the applicability of a single BFSK architecture is limited.

[0032] While it is theoretically easy to implement dual-mode functionality using independent BFSK and BPSK links, it would increase power consumption and area by adding mixers, phase switching circuits, buffer stages, and output selection switches. This is not conducive to low-power scenarios such as implantable biomedical devices, wearable sensors, and small IoT nodes.

[0033] Existing solutions typically focus more on the spectral performance of the final RF output, while neglecting the handling of near-end spurious signals in the high-frequency clock path before modulation. For transmitters using a combination of high-frequency clock fH and low-frequency signal fL for modulation, spurious signals near fH±fL present before modulation will be shifted again during modulation, forming parasitic frequencies close to the target signal. Therefore, the technical problem to be solved by the embodiments of the present invention is to achieve BFSK / BPSK dual-mode output while making maximum use of the existing low-power BFSK transmitter hardware resources; at the same time, to suppress spurious signals in the high-frequency clock path before modulation, reducing the impact of clock path spurious signals on the final transmit spectrum and phase modulation quality.

[0034] To achieve dual-mode BFSK / BPSK output while maximizing the reuse of existing low-power BFSK transmitter hardware resources, and to reduce the impact of clock path spurs on the final transmit spectrum and phase modulation quality by suppressing spurs on the high-frequency clock path before modulation, this application provides a dual-mode BFSK / BPSK transmitter with an N-path filter and its control method. Without adding a complete independent BPSK transmit link, it utilizes the existing high-frequency clock and low-frequency polyphase signal in the original BFSK transmitter. By changing the selection relationship of the low-frequency phase, the same modulation path can simultaneously operate in both BFSK and BPSK modes. Furthermore, an N-path filter is added after the high-frequency clock to filter out 10MHz spurs from the clock, improving communication quality.

[0035] Figure 1 This is a schematic diagram of the overall structure of a dual-mode BFSK and BPSK transmitter with an N-path filter provided in an embodiment of this application. (Refer to...) Figure 1This invention provides a dual-mode BFSK and BPSK transmitter with an N-path filter, comprising a high-frequency clock source, a frequency divider, a low-pass filter, an N-path filter, a multiplexer, a modulation unit, and an output driver stage. The frequency divider and the N-path filter are both connected to the high-frequency clock source, and both the frequency divider and the multiplexer are connected to the low-pass filter. The multiplexer, the N-path filter, and the output driver stage are all connected to the modulation unit. The high-frequency clock source outputs a high-frequency clock signal. The frequency divider divides the high-frequency clock signal to output a low-frequency clock signal. The low-pass filter filters the low-frequency clock signal and outputs a low-frequency filtered signal. The N-path filter filters the high-frequency clock signal and outputs a high-frequency filtered signal. The multiplexer receives a mode selection signal and a data input signal, and determines the current transmitter operating mode based on the mode selection signal. The formula and data input signal determine the current phase output combination. The multiplexer is also used to output the low-frequency filtered signal as a low-frequency selected signal according to the current phase output combination. The modulation unit is used to output the modulation signal according to the high-frequency filtered signal and the low-frequency selected signal. The output driver stage is used to amplify the modulation signal and output it. The current transmitter operating mode is BFSK mode or BPSK mode. The current phase output combination is one of the first phase combination, the second phase combination and the third phase combination. When the current transmitter operating mode is BFSK mode, the current phase output combination is the first phase combination or the second phase combination. When the current transmitter operating mode is BPSK mode, the current phase output combination is the first phase combination or the third phase combination. The phase change direction of the first phase combination is opposite to the phase change direction of the second phase combination. Each phase of the first phase combination is out of phase with the corresponding phase of the third phase combination.

[0036] In some embodiments, the high-frequency clock source includes a phase-locked loop (PLL), which includes a phase-frequency discriminator, a charge pump, a loop low-pass filter, and a voltage-controlled oscillator (VCO).

[0037] In some embodiments, the frequency of the high-frequency clock signal is 480MHz, and the frequency divider is specifically used to divide the high-frequency clock signal by 48 to output a low-frequency clock signal with a frequency of 10MHz.

[0038] In some embodiments, the low-frequency filtered signal includes a 0° low-frequency phase signal, a 90° low-frequency phase signal, a 180° low-frequency phase signal, and a 270° low-frequency phase signal.

[0039] Specifically, in this embodiment, the overall structure of the transmitter can be as follows: Figure 1 As shown, refer to Figure 1REF represents the reference input signal. The high-frequency clock source can include a phase-locked loop (PLL), which specifically includes a PFD (Phase Frequency Detector), a CP (Charge Pump), a loop LPF (Low-Pass Filter), and a VCO (Voltage-Controlled Oscillator). The PFD compares the phase or frequency difference between REF and the feedback signal; the CP and loop LPF adjust the control signal based on the comparison result; and the VCO generates a high-frequency clock signal under the control signal. Figure 1 In this context, Divide represents a frequency divider, 4 Path Filter represents an N-path filter containing four filtering paths, MUX represents a multiplexer, Mixer represents a modulation unit, and PA (Power Amplifier) ​​represents a power amplifier, which is the output driver stage in this embodiment.

[0040] Reference Figure 1 In this embodiment, after the high-frequency clock source outputs a high-frequency clock signal, the high-frequency clock signal is split into two paths. One path enters a frequency divider, which performs frequency division to obtain a low-frequency clock signal. The low-frequency clock signal then enters a low-pass filter, forming a low-frequency filtered signal. For example, the high-frequency clock signal can be 480MHz, and the frequency divider can divide the 480MHz high-frequency clock signal by 48 to obtain a 10MHz low-frequency clock signal. The low-frequency filtered signal can further include a 0° low-frequency phase signal, a 90° low-frequency phase signal, a 180° low-frequency phase signal, and a 270° low-frequency phase signal to provide a base signal for different subsequent phase combinations.

[0041] Another path of the high-frequency clock signal enters the N-path filter. The N-path filter is set between the high-frequency clock source and the modulation unit. It is used to filter the spurious components in the high-frequency clock path before the high-frequency clock signal enters the modulation unit and outputs a high-frequency filtered signal.

[0042] The multiplexer receives MODE and DATA, where MODE represents the mode selection signal, used to determine whether the transmitter is currently operating in BFSK or BPSK mode, and DATA represents the data input signal, used to indicate the binary data to be transmitted. In this embodiment, the multiplexer determines whether the transmitter is currently operating in BFSK or BPSK mode based on MODE, and further determines the phase output combination to be used based on DATA.

[0043] Simultaneously, after receiving the low-frequency filtered signal, the multiplexer can select the corresponding phase signal from multiple low-frequency phase signals according to the current transmitter operating mode and data input signal, and output a low-frequency selection signal according to the current phase output combination. After receiving the high-frequency filtered signal and the low-frequency selection signal, the modulation unit generates a modulation signal based on the two. The current phase output combination may include a first phase combination, a second phase combination, and a third phase combination.

[0044] Specifically, when the transmitter operates in BFSK mode, the multiplexer can select between a first phase combination and a second phase combination based on DATA. The phase transitions of the first and second phase combinations are opposite, so the corresponding low-frequency selection signals input to the modulation unit can cause the modulation unit to output modulation signals of different frequencies, achieving BFSK modulated data transmission. When the transmitter operates in BPSK mode, the multiplexer can select between a first phase combination and a third phase combination based on DATA. The phases in the first phase combination are out of phase with the corresponding phases in the third phase combination. Therefore, the corresponding low-frequency selection signals input to the modulation unit can cause the modulation unit to output modulation signals with the same frequency but a 180° phase difference, thus achieving BPSK modulated data transmission. Subsequently, the output driver stage amplifies the modulation signal, enabling it to be used as the transmit signal and output to the subsequent output matching network.

[0045] It can be understood that this embodiment obtains a low-frequency filtered signal from the high-frequency clock signal through a frequency divider and a low-pass filter, and outputs the low-frequency filtered signal as a low-frequency selection signal with different phase combinations through a multiplexer. This allows the same modulation unit to switch between BFSK and BPSK modes without the need for an additional BPSK transmit link, reducing the number of independent modulation links and lowering the complexity of the circuit structure, chip area, and power consumption. Simultaneously, the N-path filter, located between the high-frequency clock source and the modulation unit, can suppress spurious components in the high-frequency clock path before the high-frequency clock signal enters the modulation unit, thereby reducing the impact of spurious components in the high-frequency clock path on the final transmitted signal spectral quality and improving the output stability and communication quality of the dual-mode transmitter.

[0046] In some embodiments, the mode selection signal is a first mode signal or a second mode signal, the data input signal is a first data signal or a second data signal, and the multiplexer is specifically used for: When the mode selection signal is the first mode signal and the data input signal is the first data signal, the current transmitter operating mode is determined to be BFSK mode, and the current phase output combination is determined to be the first phase combination; When the mode selection signal is the first mode signal and the data input signal is the second data signal, the current transmitter operating mode is determined to be BFSK mode, and the current phase output combination is determined to be the second phase combination; When the mode selection signal is the second mode signal and the data input signal is the first data signal, the current transmitter operating mode is determined to be BPSK mode, and the current phase output combination is determined to be the first phase combination; When the mode selection signal is the second mode signal and the data input signal is the second data signal, the current transmitter operating mode is determined to be BPSK mode, and the current phase output combination is determined to be the third phase combination.

[0047] In some embodiments, the multiplexer includes a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, and the multiplexer is further specifically used for: When the current phase output combination is the first phase combination, the first output terminal, the second output terminal, the third output terminal and the fourth output terminal respectively output 180° low frequency phase signal, 270° low frequency phase signal, 0° low frequency phase signal and 90° low frequency phase signal to obtain the low frequency selection signal; When the current phase output combination is the second phase combination, the 270° low-frequency phase signal, 180° low-frequency phase signal, 90° low-frequency phase signal and 0° low-frequency phase signal are output through the first output terminal, the second output terminal, the third output terminal and the fourth output terminal respectively, to obtain the low-frequency selection signal; When the current phase output combination is the third phase combination, the 0° low-frequency phase signal, 90° low-frequency phase signal, 180° low-frequency phase signal and 270° low-frequency phase signal are output through the first output terminal, the second output terminal, the third output terminal and the fourth output terminal respectively, to obtain the low-frequency selection signal.

[0048] In some embodiments, the modulation signal is one of a first mixed modulation signal, a second mixed modulation signal, and a third mixed modulation signal. When the current phase output combination corresponding to the low-frequency selection signal is the first phase combination, the modulation signal is the first mixed modulation signal with a frequency of 490MHz. When the current phase output combination corresponding to the low-frequency selection signal is the second phase combination, the modulation signal is the second mixed modulation signal with a frequency of 470MHz. When the current phase output combination corresponding to the low-frequency selection signal is the third phase combination, the modulation signal is the third mixed modulation signal with a frequency of 490MHz. Furthermore, the first mixed modulation signal and the third mixed modulation signal are 180° out of phase.

[0049] Specifically, in this embodiment, referring to Figure 2 The multiplexer can receive four low-frequency phase signals, i.e. Figure 2 The 0°, 90°, 180°, and 270° low-frequency phase signals on the left are rearranged according to MODE and DATA to achieve different phase combinations. Figure 2 In the diagram, Va, Vb, Vc, and Vd correspond to the first, second, third, and fourth output terminals of the multiplexer, respectively. Figure 2 The D1, D1N, D2, and D2N signals in the upper right corner are switch control signals generated by MODE and DATA, where N represents the inverting control signal.

[0050] For example, when MODE is the first mode signal (i.e., "1"), the transmitter operates in BFSK mode. At this time, the multiplexer switches between a first phase combination and a second phase combination based on DATA. When DATA is the first data signal (i.e., binary "0"), the multiplexer uses the first phase combination, and Va, Vb, Vc, and Vd output 180°, 270°, 0°, and 90° low-frequency phase signals, respectively, forming the low-frequency selection signal corresponding to the first phase combination. When DATA is the second data signal (i.e., binary "1"), Va, Vb, Vc, and Vd output 270°, 180°, 90°, and 0° low-frequency phase signals, respectively, forming the low-frequency selection signal corresponding to the second phase combination. The phase transition directions of the first and second phase combinations are opposite. These two different low-frequency selection signals, when input to the modulation unit, can cause the modulation unit to output modulation signals of different frequencies. Specifically, the first phase combination can correspond to a first hybrid modulation signal of 490MHz, and the second phase combination can correspond to a second hybrid modulation signal of 470MHz, thereby enabling different data states to be represented by different frequencies in BFSK mode.

[0051] When MODE is the second mode signal (i.e., "0"), the transmitter operates in BPSK mode. At this time, the multiplexer switches between the first and third phase combinations based on DATA. When DATA is the first data signal (i.e., binary "0"), the multiplexer also uses the first phase combination, with Va, Vb, Vc, and Vd outputting 180°, 270°, 0°, and 90° low-frequency phase signals, respectively. When DATA is the second data signal (i.e., binary "1"), the multiplexer uses the third phase combination, with Va, Vb, Vc, and Vd outputting 0°, 90°, 180°, and 270° low-frequency phase signals, respectively, to form the third phase combination. Since each phase in the third phase combination is out of phase relative to its corresponding phase in the first phase combination (i.e., 180° phase difference), when both are input to the modulation unit, the modulation unit outputs modulated signals with the same frequency but opposite phases. Specifically, the first phase combination can correspond to the first hybrid modulation signal of 490MHz, and the third phase combination can correspond to the third hybrid modulation signal of 490MHz but with a phase difference of 180° from the first hybrid modulation signal, thereby realizing the representation of different data states by different frequencies in BFSK mode.

[0052] It can be recognized that this embodiment changes the output combination of four low-frequency phase signals by using a multiplexer, enabling the same modulation unit to switch between BFSK mode and BPSK mode without having to set up separate BFSK modulation links and BPSK modulation links, which helps to reduce the circuit complexity, area and power consumption of the transmitter.

[0053] In some embodiments, the N-path filter includes a differential input terminal, a differential output terminal, and four filtering paths. Each filtering path includes an input-side switching unit, an energy storage capacitor, and an output-side switching unit. The differential input terminal is connected to the input-side switching unit, and both the input-side and output-side switching units are connected to the first terminal of the energy storage capacitor. The output-side switching unit is connected to the differential output terminal, and the second terminal of the energy storage capacitor is grounded.

[0054] In some embodiments, the N-path filter is further configured to receive a first control signal, a second control signal, a third control signal, and a fourth control signal. The first control signal, the second control signal, the third control signal, and the fourth control signal are multi-phase control signals with phases staggered sequentially. The first control signal, the second control signal, the third control signal, and the fourth control signal are respectively used to control the on and off states of the input-side switching unit and the output-side switching unit in the corresponding filtering path.

[0055] Specifically, in this embodiment, referring to Figure 3 An N-path filter can be a four-path filter. Figure 3In the diagram, VINP and VINN represent the positive and negative terminals of the differential input, respectively; VOUTP and VOUTN represent the positive and negative terminals of the differential output, respectively; and S1, S2, S3, and S4 represent the first, second, third, and fourth control signals, respectively. The phase relationship of S1-S4 is as follows: Figure 3 As shown in the upper right corner, each filter path includes an input-side switching unit, an energy storage capacitor, and an output-side switching unit. The input-side switching unit is connected between the differential input and the energy storage capacitor, and the output-side switching unit is connected between the energy storage capacitor and the differential output. One end of the energy storage capacitor is connected to both the input-side and output-side switching units, and the other end is grounded. Therefore, when a corresponding control signal activates a filter path, the high-frequency clock signal can be transmitted to the energy storage capacitor via the input-side switching unit and output to the differential output via the output-side switching unit.

[0056] Since this embodiment achieves modulation through the combination of a high-frequency clock signal and a low-frequency clock signal—for example, by combining a 480MHz high-frequency clock signal and a 10MHz low-frequency clock signal to obtain the corresponding modulated output—spurious components in the high-frequency clock signal that are 10MHz off-frequency relative to the master clock frequency will have a significant impact on the subsequent modulation process. That is, if 10MHz of spurious components already exist in the high-frequency clock signal before it enters the modulation unit, these spurious components may participate in mixing during subsequent modulation, thus affecting the spectral quality of the final output signal. Therefore, this embodiment sets an N-path filter after the high-frequency clock source and before the modulation unit to specifically filter out the 10MHz frequency offset spurious components in the high-frequency clock signal.

[0057] During operation, S1, S2, S3, and S4 sequentially control the conduction of the four filter paths according to their phase order, allowing the high-frequency clock signal to enter the corresponding filter path in different time slices. The energy storage capacitor stores charge on the input signal during the conduction period of the corresponding path and, together with the equivalent resistance of the switch, forms an RC filter, thereby suppressing spurious components in the high-frequency clock signal that deviate from the target frequency. The filtered high-frequency clock signal is then output from the differential output terminal as the high-frequency filter signal required for subsequent modulation. In addition, when the N-path filter is connected to the PLL, an inverter chain needs to be added before and after the N-path filter to form a drive circuit.

[0058] It can be recognized that the dual-switch structure formed by the input-side switch unit and the output-side switch unit in conjunction with the energy storage capacitor in this embodiment can effectively achieve isolation between the input and output terminals compared with the structure that only sets a switch on one side. At the same time, the dual-switch structure has a better transfer function curve than the single-switch structure, and the stopband is less affected by the switch resistor, which is more conducive to filtering out spurious components in the high-frequency clock signal and improving the spectral quality of the output signal.

[0059] The beneficial effects of this embodiment will be further explained below with reference to experimental data.

[0060] Figure 4 This is the output spectrum of the 470MHz modulated signal in BFSK mode. Figure 5 This is the output spectrum of the 490MHz modulated signal in BFSK mode. Figure 6 This shows the time-domain waveforms of the output signals corresponding to the two data states in BPSK mode. (Refer to...) Figure 4 and Figure 5 In BFSK mode, the transmitter can output a 470MHz or 490MHz modulated signal based on the data input signal, referencing... Figure 6 In BPSK mode, the transmitter can output two modulated signals with the same frequency but a phase difference of 180°. Therefore, this embodiment can achieve dual-mode output of BFSK and BPSK modes through the same transmitter architecture, thereby reducing the setting of independent modulation links and reducing circuit complexity, area and power consumption.

[0061] Figure 7 A comparison chart showing the effectiveness of an N-path filter in removing 10MHz spurious components from a high-frequency clock signal, referencing... Figure 7 Before passing through the N-path filter, the spurious signal at a frequency offset of 10MHz is -17dBc. After passing through the N-path filter and then through the inverter chain for shaping, the frequency offset at 10MHz is -63dBc, which is a significant improvement and enhances the output spectrum quality of the adjusted signal.

[0062] Please see Figure 8 This application also provides a control method for a BFSK and BPSK dual-mode transmitter with an N-path filter, for implementation using the aforementioned BFSK and BPSK dual-mode transmitter. The method includes the following steps: S101, Outputs a high-frequency clock signal through a high-frequency clock source; S102. The high-frequency clock signal is divided by a frequency divider to output a low-frequency clock signal; S103. The low-frequency clock signal is filtered by a low-pass filter to output a low-frequency filtered signal. S104. The high-frequency clock signal is filtered through an N-path filter to output a high-frequency filtered signal. S105. Receive the mode selection signal and data input signal through the multiplexer, determine the current transmitter operating mode based on the mode selection signal, and determine the current phase output combination based on the current transmitter operating mode and the data input signal; S106. The low-frequency filtered signal is output as a low-frequency selected signal according to the current phase output combination through the multiplexer; S107. The modulation unit outputs a modulation signal based on the high-frequency filtered signal and the low-frequency selection signal. S108. The modulated signal is amplified and output through the output driver stage; The current transmitter operating mode is either BFSK or BPSK. The current phase output combination is one of the first phase combination, the second phase combination, and the third phase combination. When the current transmitter operating mode is BFSK, the current phase output combination is either the first phase combination or the second phase combination. When the current transmitter operating mode is BPSK, the current phase output combination is either the first phase combination or the third phase combination. The phase change direction of the first phase combination is opposite to that of the second phase combination. Each phase of the first phase combination is out of phase with the corresponding phase of the third phase combination.

[0063] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0064] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0065] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0066] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between units may be electrical, mechanical, or other forms.

[0067] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0068] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0069] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0070] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A dual-mode transmitter for BFSK and BPSK with an N-path filter, characterized in that, The transmitter includes a high-frequency clock source, a frequency divider, a low-pass filter, an N-path filter, a multiplexer, a modulation unit, and an output driver stage. The frequency divider and the N-path filter are both connected to the high-frequency clock source. The frequency divider and the multiplexer are both connected to the low-pass filter. The multiplexer, the N-path filter, and the output driver stage are all connected to the modulation unit. The high-frequency clock source outputs a high-frequency clock signal. The frequency divider divides the high-frequency clock signal to output a low-frequency clock signal. The low-pass filter filters the low-frequency clock signal to output a low-frequency filtered signal. The N-path filter filters the high-frequency clock signal to output a high-frequency filtered signal. The multiplexer receives a mode selection signal and a data input signal, determines the current transmitter operating mode based on the mode selection signal, and determines the current phase output combination based on the current transmitter operating mode and the data input signal. The multiplexer is also used to output the low-frequency filtered signal as a low-frequency selected signal according to the current phase output combination. The modulation unit is used to output a modulated signal according to the high-frequency filtered signal and the low-frequency selected signal. The output driver stage is used to amplify the modulated signal and output it. The current transmitter operating mode is BFSK mode or BPSK mode. The current phase output combination is one of a first phase combination, a second phase combination, and a third phase combination. When the current transmitter operating mode is BFSK mode, the current phase output combination is the first phase combination or the second phase combination. When the current transmitter operating mode is BPSK mode, the current phase output combination is the first phase combination or the third phase combination. The phase change direction of the first phase combination is opposite to the phase change direction of the second phase combination. Each phase of the first phase combination is out of phase with the corresponding phase of the third phase combination.

2. The dual-mode BFSK and BPSK transmitter with an N-path filter according to claim 1, characterized in that, The high-frequency clock source includes a phase-locked loop (PLL), which includes a phase-frequency discriminator, a charge pump, a loop low-pass filter, and a voltage-controlled oscillator (VCO).

3. A dual-mode BFSK and BPSK transmitter with an N-path filter according to claim 1, characterized in that, The high-frequency clock signal has a frequency of 480MHz, and the frequency divider is specifically used to divide the high-frequency clock signal by 48 to output the low-frequency clock signal with a frequency of 10MHz.

4. A dual-mode BFSK and BPSK transmitter with an N-path filter according to claim 3, characterized in that, The low-frequency filtered signals include 0° low-frequency phase signals, 90° low-frequency phase signals, 180° low-frequency phase signals, and 270° low-frequency phase signals.

5. A dual-mode BFSK and BPSK transmitter with an N-path filter according to claim 4, characterized in that, The mode selection signal is a first mode signal or a second mode signal, the data input signal is a first data signal or a second data signal, and the multiplexer is specifically used for: When the mode selection signal is the first mode signal and the data input signal is the first data signal, the current transmitter operating mode is determined to be the BFSK mode, and the current phase output combination is determined to be the first phase combination; When the mode selection signal is the first mode signal and the data input signal is the second data signal, the current transmitter operating mode is determined to be the BFSK mode, and the current phase output combination is determined to be the second phase combination; When the mode selection signal is the second mode signal and the data input signal is the first data signal, the current transmitter operating mode is determined to be the BPSK mode, and the current phase output combination is determined to be the first phase combination; When the mode selection signal is the second mode signal and the data input signal is the second data signal, the current transmitter operating mode is determined to be the BPSK mode, and the current phase output combination is determined to be the third phase combination.

6. A dual-mode BFSK and BPSK transmitter with an N-path filter according to claim 5, characterized in that, The multiplexer includes a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, and the multiplexer is further specifically used for: When the current phase output combination is the first phase combination, the 180° low-frequency phase signal, the 270° low-frequency phase signal, the 0° low-frequency phase signal, and the 90° low-frequency phase signal are output through the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal respectively to obtain the low-frequency selection signal; When the current phase output combination is the second phase combination, the 270° low-frequency phase signal, the 180° low-frequency phase signal, the 90° low-frequency phase signal, and the 0° low-frequency phase signal are output through the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal, respectively, to obtain the low-frequency selection signal; When the current phase output combination is the third phase combination, the 0° low-frequency phase signal, the 90° low-frequency phase signal, the 180° low-frequency phase signal, and the 270° low-frequency phase signal are output through the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal, respectively, to obtain the low-frequency selection signal.

7. A dual-mode BFSK and BPSK transmitter with an N-path filter according to claim 6, characterized in that, The modulation signal is one of a first mixed modulation signal, a second mixed modulation signal, and a third mixed modulation signal. When the current phase output combination corresponding to the low-frequency selection signal is the first phase combination, the modulation signal is the first mixed modulation signal, and the frequency of the first mixed modulation signal is 490MHz. When the current phase output combination corresponding to the low-frequency selection signal is the second phase combination, the modulation signal is the second mixed modulation signal, and the frequency of the second mixed modulation signal is 470MHz. When the current phase output combination corresponding to the low-frequency selection signal is the third phase combination, the modulation signal is the third mixed modulation signal, and the frequency of the third mixed modulation signal is 490MHz. Furthermore, the first mixed modulation signal and the third mixed modulation signal are 180° out of phase.

8. A dual-mode BFSK and BPSK transmitter with an N-path filter according to claim 1, characterized in that, The N-path filter includes a differential input terminal, a differential output terminal, and four filtering paths. Each filtering path includes an input-side switching unit, an energy storage capacitor, and an output-side switching unit. The differential input terminal is connected to the input-side switching unit. Both the input-side switching unit and the output-side switching unit are connected to the first terminal of the energy storage capacitor. The output-side switching unit is connected to the differential output terminal. The second terminal of the energy storage capacitor is grounded.

9. A dual-mode BFSK and BPSK transmitter with an N-path filter according to claim 8, characterized in that, The N-path filter is also used to receive a first control signal, a second control signal, a third control signal, and a fourth control signal. The first control signal, the second control signal, the third control signal, and the fourth control signal are multi-phase control signals with their phases staggered sequentially. The first control signal, the second control signal, the third control signal, and the fourth control signal are respectively used to control the on and off states of the input-side switch unit and the output-side switch unit in the corresponding filter path.

10. A control method for a BFSK and BPSK dual-mode transmitter with an N-path filter, used to implement a BFSK and BPSK dual-mode transmitter as described in any one of claims 1 to 9, characterized in that, Includes the following steps: A high-frequency clock signal is output through the high-frequency clock source; The high-frequency clock signal is divided by the frequency divider to output a low-frequency clock signal; The low-pass filter is used to filter the low-frequency clock signal to output a low-frequency filtered signal. The high-frequency clock signal is filtered by the N-path filter to output a high-frequency filtered signal; The multiplexer receives a mode selection signal and a data input signal, determines the current transmitter operating mode based on the mode selection signal, and determines the current phase output combination based on the current transmitter operating mode and the data input signal. The multiplexer outputs the low-frequency filtered signal as a low-frequency selected signal according to the current phase output combination. The modulation unit outputs a modulation signal based on the high-frequency filtered signal and the low-frequency selection signal. The modulated signal is amplified and output through the output driver stage; Wherein, the current transmitter operating mode is BFSK mode or BPSK mode, and the current phase output combination is one of a first phase combination, a second phase combination, and a third phase combination. When the current transmitter operating mode is BFSK mode, the current phase output combination is either the first phase combination or the second phase combination. When the current transmitter operating mode is BPSK mode, the current phase output combination is either the first phase combination or the third phase combination. The phase change direction of the first phase combination is opposite to the phase change direction of the second phase combination, and each phase of the first phase combination is out of phase with the corresponding phase of the third phase combination.

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