A digital signal processing system of a transceiving multiplexing architecture and a design method thereof

Abstract

The application belongs to the technical field of electronic signal processing, and particularly relates to a digital signal processing system of a transceiving multiplexing architecture and a design method thereof. The digital signal processing system can realize a multi-phase filtering channelization receiver and a transmitter on the basis of resources, increase a few selection control resources, and simultaneously realize the channelization receiver and the transmitter. In actual engineering application, the digital signal processing system has strong practicability and can be applied to unmanned aerial reconnaissance interference payloads and other miniaturized electronic platforms which are strictly limited in volume, weight and power consumption.

Description

Technical Field

[0001] This application belongs to the field of electronic signal processing technology, specifically relating to a digital signal processing system with a transmit / receive multiplexing architecture and its design method. Background Technology

[0002] Miniaturized platforms, such as electronic systems on drones, often face extremely stringent size, weight, and power consumption (SWaP) constraints, making the integration of reconnaissance and jamming an important development direction.

[0003] With the development of chip technology, the emergence of RFSoC (Radio Frequency System-on-Chip) has provided a new hardware solution for miniaturized electronic systems. RFSoC integrates multiple high-speed ADCs, DACs, FPGA programmable logic, and ARM processors onto a single chip, significantly reducing system size and power consumption. It also alleviates the interface costs and potential synchronization problems introduced by data interaction when the transmit and receive devices are on different chips.

[0004] However, with the continuous development of modern radar technology, the radar operating frequency band is constantly expanding, and the sampling rate of ADC and DAC devices is getting higher and higher. For RFSoCs applied in complex scenarios, it is not easy to achieve parallel multi-target reconnaissance and jamming processing of multiple broadband radio frequency signals on a single chip. It requires the design of extremely intensive and efficient algorithms and system architectures.

[0005] Multiphase filtering digital channelization technology can simultaneously and uniformly divide the instantaneous bandwidth into multiple sub-bandwidths through a single multiphase filtering and DFT / IDFT transformation, enabling full-probability reception of signals within the instantaneous bandwidth. It possesses multi-signal parallel processing capabilities and can significantly save computational resources compared to traditional digital up-conversion technology. Existing research, patents CN113608181A ("Radar Signal Reconnaissance and Multi-Target Jamming Method and System Based on Digital Channelization") and CN114488034A ("An Integrated Device and Method for Passive Detection and Reconnaissance Jamming") both employ digital channelization reception and digital channelization transmission reconstruction technology in their integrated reconnaissance and jamming systems. However, the problem remains that the digital channelization reception module and the digital channelization transmission reconstruction module are two independent processing modules, each occupying independent logic resources, leaving room for further compression of these logic resources.

[0006] Existing technologies have not effectively solved the problem of integrated closed-loop processing of broadband reconnaissance and jamming in applications with extremely limited SWaP constraints, such as RFSoC platforms and UAVs. Therefore, this application is proposed. Summary of the Invention

[0007] The purpose of this application is to provide a digital signal processing system with a transceiver multiplexing architecture and its design method. It designs a compact integrated reconnaissance and jamming processing system. Based on the integration of parameter measurement and transmission signal generation modules within a unified architecture, it achieves a complete reconnaissance and jamming closed loop with efficient utilization of hardware resources through an integrated multiphase filtering channelized transceiver design method. It is suitable for RFSoC platforms and UAV-borne miniaturized platforms.

[0008] The technical solution of this application is:

[0009] A digital signal processing system with a transmit / receive multiplexing architecture, comprising:

[0010] High-speed ADC, high-speed DAC, digital channelized transceiver multiplexing module, parameter measurement module, guided channel selection and interference timing control module, signal storage and playback module, and transmitted signal generation module;

[0011] The high-speed ADC samples the intermediate frequency signal after downconversion from the broadband RF front-end and outputs the broadband digital intermediate frequency signal to the digital channelized transceiver multiplexing module.

[0012] The digital channelization transceiver multiplexing module realizes time-division multiplexing of receiving channelization and transmitting channelization reconstruction through data flow direction control signals: In the receiving state, the broadband digital intermediate frequency signal is decomposed by polyphase, branched filtering and DFT operation to obtain the output of each sub-band channel; in the transmitting state, the sub-band interference signals output by the transmitting signal generation module are reconstructed into broadband digital intermediate frequency signals after IDFT operation and polyphase synthesis.

[0013] The parameter measurement module performs pulse time-domain parameter measurement and frequency measurement on the output of each sub-band channel, and generates pulse descriptor information for each detected pulse;

[0014] The channel selection and interference timing control module selects effective interference channels from all sub-band channels and generates working timing signals for the digital channelized transceiver multiplexing module, storage and playback module, and transmission signal generation module according to the interference strategy.

[0015] The signal storage and playback module stores and plays signals within the effective interference channel according to the working timing control signal and interference strategy;

[0016] The signal generation module generates interference signals for each sub-band based on the working timing control signal and the interference strategy;

[0017] The high-speed DAC converts the reconstructed broadband digital intermediate frequency signal into an analog intermediate frequency signal, which is then up-converted and amplified by the broadband radio frequency front end before being transmitted by the antenna.

[0018] According to at least one embodiment of this application, in the digital signal processing system of the above-described transceiver multiplexing architecture, a sorting and identification module is configured to receive pulse descriptor information, sort the pulse descriptor information, perform pulse deinterleaving and radiation source sorting, identify radiation source type and threat level, and an interference decision module is configured to generate interference strategy.

[0019] According to at least one embodiment of this application, in the digital signal processing system of the above-described transceiver multiplexing architecture, the digital channelized transceiver multiplexing module is implemented using a polyphase filtering and DFT / IDFT structure, including a polyphase decomposition unit, a branch filter bank, a DFT / IDFT operation unit, and a polyphase synthesis unit.

[0020] According to at least one embodiment of this application, in the digital signal processing system of the above-described transceiver multiplexing architecture, the transceiver time-division multiplexing cycle of the digital channelized transceiver multiplexing module is determined by the working timing control signal, the receiving processing and the transmitting processing are executed alternately, and the receiving path and the transmitting path share the same set of polyphase filtering and DFT / IDFT hardware resources.

[0021] According to at least one embodiment of this application, in the digital signal processing system of the above-described transceiver multiplexing architecture, the parameter measurement module performs parallel processing on the output of each sub-band channel, including detection, time of arrival measurement, pulse width measurement, carrier frequency measurement, and bandwidth measurement.

[0022] According to at least one embodiment of this application, in the digital signal processing system of the above-described transceiver multiplexing architecture, the transmit signal generation module adopts digital radio frequency storage technology, and performs delay superposition and frequency modulation processing on the stored data of each sub-band channel according to the interference pattern and parameters during the effective period of the interference transmit gate.

[0023] A design method for a digital signal processing system with a transceiver multiplexing architecture, used for designing a digital channelized transceiver multiplexing module in the aforementioned digital signal processing system with a transceiver multiplexing architecture, comprising:

[0024] S1. Determine the structure of traditional receivers and transmitters;

[0025] S2. Determine the structure of the digital channelized receiver and transmitter;

[0026] S3. Extract the shared module between the digital channelization receiver and transmitter;

[0027] S4. Add a digital channelized receiver and transmitter data selection module to add input data selection control function to the shared module.

[0028] According to at least one embodiment of this application, in the above-described digital signal processing system design method for a transceiver multiplexing architecture, in S1, the sampling rate fs, the number of channels K, the channel center frequency position fk, the decimation / interpolation factor M, and the filter order N are determined according to design requirements, and K=FM, N+1=PK, F, M, N, and P are positive integers, and the calculation parameters F=2 and P=6 are taken to make the operating parameters of the receiver and the transmitter the same.

[0029] According to at least one embodiment of this application, in the above-described digital signal processing system design method for a transceiver multiplexing architecture, in step S2, the structures of the channelized receiver and transmitter are derived. The channelized receiver includes an input adjustment module, a DFT / IDFT module, a polyphase filtering module, and a coefficient adjustment module; the channelized transmitter includes a coefficient adjustment module, a DFT / IDFT module, a polyphase filtering module, a data combining module, and an output adjustment module.

[0030] According to at least one embodiment of this application, in the above-described digital signal processing system design method for a transceiver multiplexing architecture, in step S3, the shared modules of the digital channelized receiver and transmitter are extracted, including a DFT / IDFT module, a polyphase filtering module, and a coefficient adjustment module;

[0031] In S4, a digital channelized receiver and transmitter data selection module is added, including an input adjustment module, a data combining module, and an output adjustment module;

[0032] Based on the indication marks of the digital channelized receiver and transmitter, the connection order of each module is adjusted, and the input data selection of the DFT / IDFT module, polyphase filter module, and coefficient adjustment module is controlled to realize the receiving and transmitting functions on the same set of hardware.

[0033] This application has at least the following beneficial technical effects:

[0034] This paper presents a digital signal processing system with a transmit / receive multiplexing architecture and its design method. It can realize a channelized receiver and transmitter simultaneously with minimal selection and control resources on the basis of implementing a multiphase filtered channelized receiver and transmitter. It has strong practicality in practical engineering applications and can be applied to UAV-borne reconnaissance and jamming payloads and other miniaturized electronic platforms with strict limitations on size, weight and power consumption. It is particularly suitable for integrated electronic systems that need to realize broadband reconnaissance and multi-target jamming at the same time. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the module connection relationship and data flow of the digital signal processing system with the transmit / receive multiplexing architecture provided in the embodiments of this application;

[0036] Figure 2This is a schematic diagram of the digital channelized transceiver multiplexing module design method provided in the embodiments of this application;

[0037] Figure 3 This is a schematic diagram of the structure of the digital channelized receiver provided in the embodiments of this application;

[0038] Figure 4 This is a schematic diagram of the structure of the digital channelized transmitter provided in the embodiments of this application;

[0039] Figure 5 This is a common structure diagram of the multiphase filtered channelized receiver and transmitter provided in the embodiments of this application;

[0040] Figure 6 This is a time-frequency diagram of the input signal provided in an embodiment of this application;

[0041] Figure 7 This is a time-frequency diagram of the output signal provided in an embodiment of this application.

[0042] To better illustrate this embodiment, some content in the accompanying drawings may be omitted, enlarged, or reduced. They are for illustrative purposes only and should not be construed as limiting the scope of this application. Detailed Implementation

[0043] To make the technical solution and advantages of this application clearer, the technical solution of this application will be described in a clearer and more complete manner below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only some embodiments of this application, and are only used to explain this application, not to limit this application. It should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, and other related parts can be referred to the general design.

[0044] Furthermore, unless otherwise defined, the technical or scientific terms used in this application description shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The word "comprising" as used in this application description indicates that the concept preceding the word encompasses the concepts listed following the word and their equivalents, without excluding other related concepts.

[0045] Furthermore, the terms indicating location used in the description of this application are only used to indicate relative directions or positional relationships. When the absolute position of the described object changes, its relative positional relationship may also change accordingly. It should also be noted that, unless otherwise explicitly specified and limited, terms such as "installation" and "connection" used in the description of this application should be interpreted broadly. For example, a connection can be a fixed connection or a detachable connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand its specific meaning in this application according to the specific circumstances.

[0046] A digital signal processing system with a transceiver multiplexing architecture is disclosed. This system is an integrated reconnaissance and jamming processing system based on a digital channel transceiver multiplexing architecture, suitable for RFSoC platforms and UAV-borne miniaturized platform electronic systems. It can be deployed in UAV-borne reconnaissance and jamming payloads. The system includes a high-speed ADC, a high-speed DAC, a digital channelized transceiver multiplexing module, a parameter measurement module, a guided channel selection and jamming timing control module, a signal storage and playback module, and a transmitted signal generation module. Figure 1 As shown.

[0047] The high-speed ADC samples the intermediate frequency signal after downconversion from the broadband RF front end. The sampling rate can be configured according to the system bandwidth requirements to obtain a broadband digital intermediate frequency signal, and outputs the broadband digital intermediate frequency signal to the digital channelized transceiver multiplexing module.

[0048] The digital channelized transceiver multiplexing module is the core functional module, which is implemented using polyphase filtering and DFT / IDFT structures, including polyphase decomposition units, branch filter banks, DFT / IDFT operation units, and polyphase synthesis units.

[0049] The digital channelization transceiver multiplexing module realizes time-division multiplexing of receive channelization and transmit channelization reconstruction through data flow direction control signals: In the receive state, the broadband digital intermediate frequency signal is decomposed by polyphase, branched filtering and DFT operation to obtain the output of each sub-band channel; in the transmit state, the sub-band interference signals output by the transmit signal generation module are reconstructed into broadband digital intermediate frequency signals after IDFT operation and polyphase synthesis.

[0050] The time-division multiplexing cycle of the digital channelized transceiver multiplexing module is determined by the working timing control signal. Receive processing and transmit processing are executed alternately. The receive path and transmit path share the same set of polyphase filtering and DFT / IDFT hardware resources, such as... Figure 5 As shown, the same set of polyphase filtering and DFT / IDFT resources are used for both transmission and reception through data selection control. The broadband digital intermediate frequency signal is decomposed by polyphase, branched filtering, and DFT to output the channel data of each sub-band. The interference signals of each sub-band are reconstructed into broadband digital intermediate frequency signals after IDFT and polyphase synthesis.

[0051] The parameter measurement module performs pulse time-domain parameter measurement and frequency measurement on the output of each sub-band channel, and performs parallel processing on the output of each sub-band channel, including detection, time of arrival measurement, pulse width measurement, carrier frequency measurement and bandwidth measurement, and generates pulse descriptor information for each detection pulse.

[0052] The system includes a sorting and identification module that receives pulse descriptor information, sorts the pulse descriptor information, performs pulse deinterleaving and radiation source sorting, and identifies the radiation source type and threat level. It also includes an interference decision module for generating interference strategies.

[0053] The channel selection and interference timing control module selects effective interference channels from all sub-band channels and generates working timing signals for the digital channelized transceiver multiplexing module, storage and playback module, and transmission signal generation module according to the interference strategy.

[0054] The signal storage and playback module stores and plays signals within the effective interference channel according to the working timing control signal and interference strategy.

[0055] The signal generation module generates interference signals for each sub-band based on the working timing control signal and the interference strategy.

[0056] The transmission signal generation module uses digital radio frequency storage technology. During the effective period of the interference transmission gate, it performs delay superposition, frequency modulation and other processing on the stored data of each sub-band channel according to the interference pattern and parameters to generate interference signals for each sub-band.

[0057] The high-speed DAC converts the reconstructed broadband digital intermediate frequency signal into an analog intermediate frequency signal, which is then up-converted and amplified by the broadband RF front end before being transmitted by the antenna.

[0058] To achieve digital channelized transceiver multiplexing design, the mathematical models of the receiver and transmitter must match. That is, the sampling rate fs, the number of channels K, the channel center frequency position fk, the decimation / interpolation factor M, the filter order N, etc., must be the same, and the parameters must all satisfy K=FM, N+1=PK, where K, M, N, and P are positive integers. Only when the basic module parameters of the receiver and transmitter are the same can a conformal design be achieved.

[0059] Based on the above, the design and implementation steps of the digital channelized transceiver multiplexing module are as follows: Figure 2 As shown, from the analysis of digital up-conversion and down-conversion requirements to the design process of the digital channelized transceiver multiplexing module, the core lies in the conformal design of the reconfiguration of the receive channelization and the transmit channelization.

[0060] S1. Determine the operating parameters of the receiver and transmitter according to design requirements.

[0061] The sampling rate fs, number of channels K, channel center frequency position fk, decimation / interpolation factor M, and filter order N are determined according to design requirements, where K=FM, N+1=PK, and F, M, N, and P are positive integers. Generally, the calculation parameters F=2 and P=6 are chosen. Figure 3 As shown, the operating parameters of the receiver and transmitter are made the same.

[0062] S2. Determine the structure of the digital channelized receiver and transmitter based on the determined operating parameters.

[0063] Derive the structure of the channelized receiver and transmitter. The channelized receiver includes an input adjustment module, a DFT / IDFT module, a polyphase filter module, and a coefficient adjustment module, with the connections as follows: Figure 3 As shown; the channelized transmitter includes a coefficient adjustment module, a DFT / IDFT module, a polyphase filtering module, a data combining module, and an output adjustment module, with the connections as follows: Figure 4 As shown.

[0064] The input adjustment module adjusts the received signal of the digital channelized receiver to the format adapted to the polyphase filter module, i.e., the K-channel parallel format.

[0065] The DFT / IDFT module implements DFT or IDFT functions based on the interface control, and selects the DFT or IDFT function based on the specific form derived from the digital channelized receiver and transmitter.

[0066] In the derivation of the digital channelized receiver and transmitter, the filter is converted into a polyphase filter form, and the polyphase filter module implements this function.

[0067] In the derivation of the digital channelized receiver and transmitter, there is a part where the K parallel signals are multiplied by a coefficient of ±1 according to the channel number and the operating cycle. The coefficient adjustment module implements the function of multiplying the K parallel signals by 1 or -1 according to the channel number and the operating cycle.

[0068] The data merging module is a function in digital channelized transmitters. This module merges the first half and the second half of the output data from the DFT / IDFT module before outputting the result.

[0069] The output adjustment module is a function in the digital channelized transmitter. This module adjusts the K-channel parallel format signal output by the data combining module into a serial transmission signal format.

[0070] S3. Extract the common modules of the digital channelized receiver and transmitter, and implement each module in the channelized receiver and transmitter in a modular manner.

[0071] The shared modules include a DFT / IDFT module, a multiphase filtering module, and a coefficient adjustment module.

[0072] S4. Add a digital channelized receiver and transmitter data selection module to add input data selection control function to the shared module.

[0073] The multiphase filter module adds an input data selection control function. During receive timing, the output of the input adjustment module is selected as the input of the multiphase filter module. During transmit timing, the output of the DFT / IDFT module is selected as the input of the multiphase filter module.

[0074] The DFT / IDFT module adds an input data selection control function. During receive timing, the output of the multiphase filter module is selected as the input of the DFT / IDFT module, and during transmit timing, the output of the coefficient adjustment module is selected as the input of the DFT / IDFT module.

[0075] The coefficient adjustment module adds an input data selection control function. During the receive timing, the output of the DFT / IDFT module is selected as the input of the coefficient adjustment module, and during the transmit timing, the output of the channelized transmit signal is selected as the input of the coefficient adjustment module.

[0076] The input adjustment module is used only within the receiver, therefore no additional data selection control function is needed. The data combining module is used only within the transmitter, therefore no additional data selection control function is needed. The output adjustment module is used only within the transmitter, therefore no additional data selection control function is needed.

[0077] Based on the indication marks of the digital channelized receiver and transmitter, the connection order of each module is adjusted, the data flow direction of each module is adjusted, and the input data selection of the DFT / IDFT module, polyphase filter module, and coefficient adjustment module is controlled to achieve the purpose of adjusting the connection order of each module. Different connection orders of each module can realize the functions of polyphase filter channelized receiver and transmitter, that is, the receiving and transmitting functions can be realized on the same set of hardware.

[0078] The digital signal processing system with a transceiver multiplexing architecture disclosed in the above embodiments is implemented based on the RFSoC platform. It integrates a high-speed ADC, a high-speed DAC, a digital channelized transceiver multiplexing module, a parameter measurement module, a guided channel selection and interference timing control module, a signal storage and playback module, and a transmit signal generation module into the programmable logic resources of the RFSoC chip. The sorting and identification module and the interference decision module are deployed in the ARM processor or multi-core DSP of the RFSoC chip. By leveraging the high integration of the RFSoC chip, functions such as direct RF sampling, digital channelized transceiver multiplexing, parameter measurement, and transmit signal generation are integrated into a single chip, significantly reducing system size, weight, and power consumption.

[0079] The digital signal processing system with a transmit / receive multiplexing architecture disclosed in the above embodiments is deployed in an unmanned aerial vehicle (UAV)-borne reconnaissance and jamming payload. In an UAV-borne scenario, the system receives radar signals through a shared antenna array, and after down-conversion by a broadband radio frequency front-end and processing by an RFSoC chip, it achieves reconnaissance, sorting, identification, and jamming of enemy radar signals.

[0080] Given a sampling rate fs = 4800 GHz, number of channels K = 64, an odd-numbered channel structure, a decimation / interpolation factor M = 32, a filter order N = 383, an input signal pulse width of 10 μs, a pulse repetition frequency of 50 μs, and the simultaneous presence of three single-tone signals with frequencies [2912, 3800, 4225] MHz, and a linear frequency modulated signal with a starting frequency of 3700 MHz and a bandwidth of 50 MHz (upward sweep), the time-frequency diagrams of the input and output signals are as follows: Figure 6 , Figure 7 As shown, it can be seen that frequency reconstruction without offset can be achieved in multi-signal scenarios.

[0081] The digital signal processing system with a transmit / receive multiplexing architecture disclosed in the above embodiments:

[0082] Core hardware resource reuse (conformal design): The same set of polyphase filtering and DFT / IDFT hardware modules is used for both receive digital channelization and transmit channelization reconstruction. Compared with existing solutions that require separate channelization modules for receive and transmit, hardware resource consumption is reduced by about half. With the same hardware resources, more channels can be supported, enabling more accurate parameter measurements and freeing up resources for other modules such as signal modulation, making it particularly suitable for miniaturized and compact systems. Furthermore, since the coefficient design of the branch filter bank remains the same in receive and transmit modes, no reloading is required, resulting in fast switching speeds.

[0083] High platform adaptability: It can be implemented based on the RFSoC platform, leveraging its high integration characteristics to integrate functions such as direct RF sampling, digital channelized transceiver multiplexing, parameter measurement, and transmit signal generation into a single chip, significantly reducing system size, weight, and power consumption, and meeting the stringent SWaP requirements of UAV-borne platforms. Furthermore, the channelized receiver and transmitter are located within the same device in the RFSoC platform, which is more conducive to achieving synchronous control of transmission and reception.

[0084] Furthermore, those skilled in the art should recognize that the various modules of the system disclosed in the embodiments of this application can be implemented in electronic hardware, computer software, or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, they are generally described in terms of function in this application. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can choose different methods to implement the described functions for each specific application and its actual constraints, but such implementation should not be considered to be beyond the scope of this application.

[0085] The technical solution of this application has been described in conjunction with the preferred embodiments shown in the accompanying drawings. Those skilled in the art should understand that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A digital signal processing system with a transmit / receive multiplexing architecture, characterized in that, include: High-speed ADC, high-speed DAC, digital channelized transceiver multiplexing module, parameter measurement module, guided channel selection and interference timing control module, signal storage and playback module, and transmitted signal generation module; The high-speed ADC samples the intermediate frequency signal after downconversion from the broadband RF front-end and outputs the broadband digital intermediate frequency signal to the digital channelized transceiver multiplexing module. The digital channelization transceiver multiplexing module realizes time-division multiplexing of receiving channelization and transmitting channelization reconstruction through data flow direction control signals: In the receiving state, the broadband digital intermediate frequency signal is decomposed by polyphase, branched filtering and DFT operation to obtain the output of each sub-band channel; in the transmitting state, the sub-band interference signals output by the transmitting signal generation module are reconstructed into broadband digital intermediate frequency signals after IDFT operation and polyphase synthesis. The parameter measurement module performs pulse time-domain parameter measurement and frequency measurement on the output of each sub-band channel, and generates pulse descriptor information for each detected pulse; The channel selection and interference timing control module selects effective interference channels from all sub-band channels and generates working timing signals for the digital channelized transceiver multiplexing module, storage and playback module, and transmission signal generation module according to the interference strategy. The signal storage and playback module stores and plays signals within the effective interference channel according to the working timing control signal and interference strategy; The transmission signal generation module generates interference signals for each sub-band based on the working timing control signal and the interference strategy; The high-speed DAC converts the reconstructed broadband digital intermediate frequency signal into an analog intermediate frequency signal, which is then up-converted and amplified by the broadband RF front end before being transmitted by the antenna.

2. The digital signal processing system with a transmit / receive multiplexing architecture according to claim 1, characterized in that, The configuration includes a sorting and identification module that receives pulse descriptor information, sorts the pulse descriptor information, performs pulse deinterleaving and radiation source sorting, identifies radiation source type and threat level, and configures an interference decision module to generate interference strategies.

3. The digital signal processing system with a transmit / receive multiplexing architecture according to claim 2, characterized in that, The digital channelized transceiver multiplexing module is implemented using polyphase filtering and DFT / IDFT structures, including a polyphase decomposition unit, a branch filter bank, a DFT / IDFT operation unit, and a polyphase synthesis unit.

4. The digital signal processing system with a transmit / receive multiplexing architecture according to claim 3, characterized in that, The time-division multiplexing cycle of the digital channelized transceiver multiplexing module is determined by the working timing control signal. The receiving processing and transmitting processing are executed alternately, and the receiving path and the transmitting path share the same set of polyphase filtering and DFT / IDFT hardware resources.

5. The digital signal processing system with a transmit / receive multiplexing architecture according to claim 4, characterized in that, The parameter measurement module performs parallel processing on the output of each sub-band channel, including detection, time of arrival measurement, pulse width measurement, carrier frequency measurement, and bandwidth measurement.

6. The digital signal processing system with a transmit / receive multiplexing architecture according to claim 5, characterized in that, The transmission signal generation module uses digital radio frequency storage technology. During the effective period of the interference transmission gate, it performs delay superposition and frequency modulation processing on the stored data of each sub-band channel according to the interference pattern and parameters.

7. A design method for a digital signal processing system with a transceiver multiplexing architecture, used to design a digital channelized transceiver multiplexing module in the digital signal processing system with the transceiver multiplexing architecture of claim 1, characterized in that, include: S1. Determine the operating parameters of the receiver and transmitter; S2. Determine the structure of the digital channelized receiver and transmitter; S3. Extract the shared module between the digital channelization receiver and transmitter; S4. Add a digital channelized receiver and transmitter data selection module to add input data selection control function to the shared module.

8. The design method for a digital signal processing system with a transmit / receive multiplexing architecture according to claim 7, characterized in that, In S1, the sampling rate fs, the number of channels K, the channel center frequency position fk, the decimation / interpolation factor M, and the filter order N are determined according to the design requirements, and K=FM, N+1=PK, F, M, N, and P are positive integers. The calculation parameters F=2 and P=6 are selected to make the operating parameters of the receiver and transmitter the same.

9. The design method for a digital signal processing system with a transmit / receive multiplexing architecture according to claim 8, characterized in that, In S2, the structures of the channelized receiver and transmitter are derived. The channelized receiver includes an input adjustment module, a DFT / IDFT module, a polyphase filter module, and a coefficient adjustment module; the channelized transmitter includes a coefficient adjustment module, a DFT / IDFT module, a polyphase filter module, a data combining module, and an output adjustment module.

10. The design method for a digital signal processing system with a transmit / receive multiplexing architecture according to claim 9, characterized in that, In S3, the modules shared by the digital channelized receiver and transmitter are extracted, including the DFT / IDFT module, the polyphase filter module, and the coefficient adjustment module; In S4, a digital channelized receiver and transmitter data selection module is added, including an input adjustment module, a data combining module, and an output adjustment module; Based on the indication marks of the digital channelized receiver and transmitter, the connection order of each module is adjusted, and the input data selection of the DFT / IDFT module, polyphase filter module, and coefficient adjustment module is controlled to realize the receiving and transmitting functions on the same set of hardware.

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