A method for controlling communication fault tolerance between host computer and slave computer of electrochemical device

Abstract

The application relates to a general control method for communication fault tolerance between an upper computer and a lower computer, which can be applied to various electrochemical detection equipment. In the method, the upper computer pre-downloads all working steps to the lower computer, so that the lower computer has independent running capability; the upper computer caches states in real time during running, and the upper and lower computers monitor communication through heartbeat packets. When communication is interrupted, the upper computer records a first state, the lower computer synchronously records a communication interruption state and continues steady-state running. After reconnection, the two parties compare communication interruption time stamps for verification, the upper computer reads a current state of the lower computer as a second state, and missing data between the two states is supplemented to complete a log. The application ensures that detection data is complete and traceable during communication interruption, samples are not scrapped, and detection results are continuous and reliable.

Description

Technical Field

[0001] This invention relates to the field of electrochemical equipment control technology, specifically to a method for controlling the communication fault tolerance between the host computer and the slave computer of an electrochemical device, which is particularly suitable for long-cycle electrochemical detection scenarios such as battery charge and discharge detection, constant voltage charging, constant current charging, and leakage detection. Background Technology

[0002] In a series of long-term charge-discharge cycle tests for battery swelling, leakage, fatigue, etc., a complete test cycle typically takes anywhere from 15 days to 2 months. Such tests place extremely high demands on the continuity and integrity of data storage. The plastic changes and irreversible losses that occur in the battery during the test are important indicators for result evaluation. Interruption of the test will cause the battery performance data to lose continuity and cannot be accepted under current safety standards.

[0003] Traditional electrochemical detection systems consist of upper and lower computer units. The upper computer is responsible for process step editing, data display, and human-computer interaction, while the lower computer executes the specific detection steps. In actual industrial settings, strong electromagnetic interference, power fluctuations, and other factors can easily cause communication interruptions between the upper and lower computer units. Traditional solutions often directly stop the process or lose data after a communication interruption. At this point, the battery sample may have already undergone irreversible state changes, and restarting the detection process will not provide reliable experimental results. This results in the scrapping of the workpiece and a waste of waiting time.

[0004] While some communication fault-tolerant solutions exist in the existing technology, such as using a mid-level computer to cache data to solve the problem of data loss during upper-level computer failures, or using heartbeat monitoring to detect communication interruptions, none of them have solved the technical problem of the lower-level computer continuing to execute steps and achieving seamless continuity after a communication interruption. They also lack a special design for the long-cycle and irreversible characteristics of electrochemical detection. Summary of the Invention

[0005] To address the problems existing in the prior art, the purpose of this invention is to provide a method for controlling the communication fault tolerance between the host computer and the slave computer of an electrochemical device. When communication is interrupted, it can ensure the continuous operation of the detection steps, complete storage and automatic completion of detection data, and ensure that the test samples are not discarded and the test results are valid and reliable.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A method for fault-tolerant communication between a host computer and a slave computer in an electrochemical device, comprising the following steps: The host computer pre-downloads all process steps to the lower-level computer's memory for storage; During the detection process, the host computer caches the current process step, runtime, and parameter status in real time, and the host computer and the slave computer monitor the communication status through heartbeat packets. When communication is normal, the lower-level machine stores the detection data in real time during the execution of the detection steps, and cleans up the memory periodically after the data is successfully sent. When communication is interrupted and the system is abnormally offline, the communication fault tolerance process is executed: the host computer records the time point of the communication interruption and the current process step status, which is defined as the first state; the slave computer synchronously records the timestamp of the communication interruption, the current process step status, and the current process parameters, marking the communication interruption state; and the slave computer stops memory cleanup and maintains the current process parameters to continue steady-state operation and storage. After communication is restored, the host computer reads the current working state of the slave computer, defines it as the second state, automatically retrieves all missing detection data between the first state and the second state, and completes it to form a complete detection log.

[0007] The heartbeat detection specifically involves the host computer sending a heartbeat request frame to the slave computer at a preset period, and the slave computer replying with a heartbeat response frame; if no response is received from the other party for several consecutive periods, the communication link is determined to be interrupted.

[0008] The lower-level machine's memory is divided into several fixed-size data blocks, each data block being accompanied by a start timestamp and an end timestamp for that time period; When communication is normal, the lower-level machine releases the data block back to the idle pool after successfully sending the data block and receiving the confirmation signal from the upper-level machine. When communication is interrupted, the lower-level device marks all data blocks as pending upload and stops the cleanup operation.

[0009] When the communication interruption occurs, the host computer determines the type of communication interruption: If there is an abnormal offline situation, the communication fault tolerance process is executed. The host computer records the first state, and the slave computer continues to operate in a steady state. If the process is to actively go offline, the host computer sends a stop command to the slave computer before going offline, and the slave computer stops the current step.

[0010] Before the host computer reads the second state of the slave computer, the host computer and the slave computer perform a comparison and verification to determine the breakpoint location: If the difference between the first state timestamp recorded by the host computer and the communication interruption timestamp recorded by the slave computer is within the preset tolerance range, the breakpoint location is directly confirmed; if the difference exceeds the tolerance range, the breakpoint location is located by cross-locating the step number and sampling sequence number. After the breakpoint is determined, the time offset is calculated based on the first state timestamp to correct the time axis of the missing historical data.

[0011] The timeline correction of the missing historical data is specifically as follows: the host computer uses the first state timestamp recorded by itself as a reference, calculates the difference between the timestamp recorded by the host computer and the breakpoint timestamp recorded by the slave computer as a time offset, and adds the offset to the timestamps of all missing data uploaded by the slave computer.

[0012] After the timeline correction of the missing historical data is completed, the host computer sends the current reference time to the slave computer via a heartbeat packet. The slave computer then corrects its local clock to the host computer's time and restores the period calibration.

[0013] By adopting the above solution, this invention enables the continuous and uninterrupted execution of detection steps, complete and lossless storage of detection data, and automatic completion of detection data when an abnormal disconnection occurs between the host computer and the slave computer. This ensures that even if a communication failure occurs during long-cycle electrochemical detection, the test sample can still complete all detection procedures normally and generate a complete, continuous, and reliable detection data report.

[0014] Compared with existing technologies, this invention, through a pre-deployment mechanism, enables the lower-level machine to continue steady-state operation according to pre-stored steps even after communication interruption, without starting, stopping, or skipping steps. This fundamentally avoids detection interruptions and sample scrapping caused by communication interruptions. Simultaneously, a built-in judgment module enables differentiated handling of abnormal offline and active offline situations. Abnormal offline situations automatically resume operation, while active offline situations stop upon instruction, preventing misoperation. This invention effectively solves the technical problem of detection failure caused by communication interruptions under harsh environments such as strong electromagnetic interference and power fluctuations in electrochemical industrial settings, and has significant application value in long-cycle electrochemical detection fields such as battery charging and discharging.

[0015] Furthermore, this invention ensures that all detection data during communication interruptions is complete, traceable, and accurately spliced ​​through independent storage on both the upper and lower ends of the computer and breakpoint verification and time axis correction mechanisms after reconnection, thus achieving zero loss of detection data. Attached Figure Description

[0016] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0017] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are not intended to limit the present invention.

[0018] like Figure 1As shown, this invention discloses a general control method for fault-tolerant communication between a host computer and a slave computer, applicable to various electrochemical detection devices. In this method, the host computer pre-distributes all process steps to the slave computer, enabling it to operate independently. During operation, the host computer caches the status in real time, and the host and slave computers monitor communication via heartbeat packets. When communication is interrupted, the host computer records the first state, and the slave computer synchronously records the communication interruption state and continues steady-state operation. After reconnection, both sides compare the communication interruption timestamp for verification. The host computer reads the current state of the slave computer as the second state and retrieves the missing data between the two states to complete the log. This method ensures that the detection data is complete and traceable during communication interruption, samples are not discarded, and detection results are continuous and reliable.

[0019] The following section uses a battery charge-discharge cycle testing scenario as an example to provide a detailed explanation of the implementation of the above method.

[0020] In this embodiment, the test object is a certain type of lithium-ion battery, and the test parameters are set as follows: constant current charging stage, charging to 4.2V with a current of 0.5C; constant voltage charging stage, charging at 4.2V to a cutoff current of 0.05C; resting for 10 minutes; constant current discharging stage, discharging to 2.8V with a current of 1C; resting for 10 minutes; the above constitutes one cycle, and a total of 500 cycles are set; voltage, current, and temperature data are recorded throughout the process, with a sampling interval of 1 second. A complete test cycle takes approximately 36 days.

[0021] Step 1: Pre-issuance of work steps.

[0022] Both the host computer and the slave computer are powered on and started, and each clears its communication flag and communication failure record. The host computer establishes a communication connection with the slave computer through an industrial Ethernet network. After the connection is established, initial time synchronization is performed, and each records its initial timestamp.

[0023] After the testing personnel edit the complete work step file on the human-machine interface of the host computer and confirm the start, the host computer instantly sends all work step content in the form of data packets to the non-volatile memory of the slave computer via the communication interface. After receiving the complete work step file, the slave computer returns an acknowledgment signal to the host computer, indicating that the work step pre-delivery is complete. Thereafter, the slave computer independently executes the testing work according to the stored work step content, no longer relying on real-time instructions from the host computer.

[0024] Step 2: Real-time status caching and heartbeat detection.

[0025] After the pre-deployment of the work steps is completed, the host computer and the slave computer continuously monitor the communication link status via high-frequency heartbeat packets. The heartbeat detection is implemented as follows: the host computer sends a heartbeat request frame to the slave computer every 500 milliseconds, and the slave computer immediately replies with a heartbeat response frame upon receiving the request frame. If the host computer does not receive a heartbeat response frame from the slave computer within three consecutive cycles (i.e., 1.5 seconds), the communication link is considered interrupted. Similarly, the slave computer also sends a heartbeat signal to the host computer at the same interval; if it does not receive a response from the host computer within three consecutive cycles, the communication is also considered interrupted.

[0026] During the detection process, the host computer caches the current step number, runtime, voltage, current, and temperature values ​​of each channel in real time. Specifically, the host computer allocates a buffer in memory and writes the current running status to the buffer once per second, and simultaneously stores it in a log file on the local hard drive.

[0027] Step 3: Independent storage and memory management for the lower-level machine.

[0028] During the execution of the detection steps, the lower-level machine stores the detection data in its local memory in real time. The detection data includes: step execution record, voltage data, current data, temperature data, runtime data, and timestamps. The lower-level machine's memory is divided into several fixed-size data blocks, each storing one hour of detection data, along with the start and end timestamps for that time period.

[0029] When communication is normal, after the lower-level machine completes the writing of each data block, successfully sends it to the upper-level machine, and receives an acknowledgment signal from the upper-level machine, it marks the data block as "acknowledged" and releases it back to the free pool after a 30-second delay for subsequent data writing. Simultaneously, the lower-level machine checks the overall memory occupancy rate every 24 hours. If the occupancy rate exceeds 80%, it prioritizes clearing the oldest acknowledged data block to ensure that memory does not overflow and guarantees ample memory capacity throughout long-term monitoring.

[0030] When communication is interrupted, the lower-level machine marks all data blocks as "pending upload" and ceases any cleanup operations, continuously writing new detection data into idle data blocks. When the memory occupancy rate reaches a preset warning value (e.g., 95%), the lower-level machine activates an overwrite strategy: in chronological order from earliest to latest, the earliest successfully uploaded data blocks are overwritten with new data. Since the lower-level machine's memory capacity is configured to store all data for at least one complete detection cycle, data loss due to memory fullness will not occur during a normal detection cycle.

[0031] Step 4: Record and differentiate communication interruption status.

[0032] During the 127th cycle of testing (approximately day 18), strong electromagnetic interference caused by the startup of high-power equipment on-site led to an interruption in Ethernet communication between the host computer and the slave computer. After three consecutive cycles of no response to the heartbeat packet, both the host computer and the slave computer determined that communication had been interrupted, and the system entered the communication interruption handling process.

[0033] The host computer first determines the type of communication interruption. The host computer has a built-in offline type determination module that monitors the triggering method of the communication interruption event in real time. If the communication interruption is caused by any situation other than a voluntary pause or exit (i.e., abnormal offline, including but not limited to: communication interruption caused by electromagnetic interference, equipment restart caused by power fluctuations, host computer offline due to network failure, host computer software crash due to unknown errors, etc.), the judgment module marks it as "abnormal offline". At this time, the communication fault tolerance process is executed: the host computer automatically records the timestamp of the moment of communication interruption (e.g., 10:23:17 AM on the same day) and the current process step status (cycle 127, constant current discharge stage, current voltage 3.15V, discharge time 23 minutes), defines it as the first state, and persists the first state to the local hard disk. At the same time, after the lower computer has not received a heartbeat request frame for a period of time, it also synchronously determines that the communication is interrupted, immediately records the timestamp of the moment of communication interruption (recorded by the lower computer's local clock), the current process step status, and the current process parameters, stores the above information in an independent state area in the local memory, and marks itself as a communication interruption state. Subsequently, the lower-level machine continues to operate in a steady state: it does not stop the current step, does not jump to the next step, and does not change the current process parameters (maintaining the constant current discharge parameter 1C), and continues to execute the remaining detection tasks according to the step content stored in the memory.

[0034] If the communication interruption is caused by the inspector actively closing the software via the "Exit" button on the host computer's human-machine interface, or manually pausing the inspection via the "Pause" button, the judgment module marks it as actively offline. In this case, the host computer sends a stop command with an active offline flag to the slave computer via the communication interface before going offline. Upon receiving the stop command, the slave computer parses the active offline flag, then stops the current step according to the preset safety stop procedure, saves the current status data, and returns a stop confirmation signal to the host computer.

[0035] In this embodiment, the communication interruption was caused by abnormal offline due to strong electromagnetic interference, so the system executed the abnormal offline handling procedure. The communication interruption lasted for about 4 hours. During this period, the lower-level machine maintained the current constant current discharge parameters (1C) and continued to run, independently completing the constant current discharge stage of the 127th cycle (from the voltage continuously changing from 3.15V to the discharge cutoff voltage of 2.8V) and the subsequent resting stage, and continued to execute the 128th cycle and subsequent steps. All detection data was stored in the lower-level machine memory in real time without any loss.

[0036] The aforementioned differentiated design ensures that the system can respond correctly in any communication interruption scenario: it automatically resumes operation and does not lose data when abnormally offline; it stops according to instructions when actively offline to avoid accidental operation.

[0037] Step 5: Reconnect and verify against time points.

[0038] After communication was restored (at 14:30:00 that afternoon), the lower-level computer and the upper-level computer re-established their communication connection. Once the connection was established, the upper and lower-level computers first compared the time of the communication interruption: The host computer sends its recorded first state timestamp (10:23:17 AM on the same day) to the slave computer, and the slave computer sends its recorded communication interruption timestamp when the communication interruption occurs to the host computer. Both computers compare these two timestamps. If the difference is within a preset tolerance range (e.g., ±5 seconds), it confirms that both computers recorded the same communication interruption event, and the breakpoint location is consistent. If, due to extreme circumstances (such as slave computer clock drift or restart), the difference exceeds the tolerance range, the breakpoint location is further located by cross-referencing the step sequence number and sampling sequence number. After the breakpoint location is determined, the host computer uses its own recorded first state timestamp as a reference, calculates the difference between this timestamp and the breakpoint timestamp recorded by the slave computer as a time offset, and adds this offset to the timestamps of all missing data uploaded by the slave computer to complete the timeline calibration of the historical data, ensuring that the spliced ​​detection log timeline is continuous, accurate, and without jumps or regressions.

[0039] After historical data calibration is completed, the host computer sends the current reference time to the slave computer via a heartbeat packet. The slave computer then corrects its local clock to the host computer's time, restoring the periodic calibration mechanism to ensure that both computers maintain time consistency in subsequent operations. This concludes the reconnection and time point comparison verification phase.

[0040] After the time point comparison and verification is completed, the host computer automatically reads the current process status of the slave computer and defines it as the second state. In this embodiment, the host computer reads the current state of the slave computer as: 128th cycle, constant current discharge stage, current voltage 3.12V, discharge time 8 minutes.

[0041] Step 6: Retrieve missing data and complete logs.

[0042] Based on the difference between the first state (cycle 127, constant current discharge stage, voltage 3.15V, time 10:23:17) and the second state (cycle 128, constant current discharge stage, voltage 3.12V, time 14:30:00), the host computer automatically calculates the missing data range from the time of communication interruption to the time of reconnection: that is, all detection data between 10:23:17 and 14:30:00, including voltage curves, current curves, and temperature curves, totaling approximately 15,000 data points.

[0043] Subsequently, the host computer sends a data retrieval request to the slave computer, and the slave computer uploads all data blocks marked "pending upload" to the host computer in chronological order. A breakpoint resumption method is used during the upload process: after each data block is uploaded, the slave computer marks the data block as "uploaded" and releases it; if communication is interrupted again during the upload process, it reconnects and resumes transmission from the point where the current unfinished data block was interrupted, ensuring transmission stability in scenarios with large data volumes.

[0044] After receiving all the missing data, the host computer inserts the data into the original detection log in timestamp order, forming a complete and time-continuous detection data chain. In this embodiment, after the host computer inserts the 15,000 supplementary data points, the discharge curve of the 127th cycle exhibits a complete exponential decay pattern, continuously changing from 3.15V to the discharge cutoff voltage of 2.8V without any breaks or abnormal jumps.

[0045] The completed data is displayed on the host computer, including: The real-time data curve displays the real-time changes of parameters such as voltage, current, and temperature, with time on the horizontal axis and measured values ​​on the vertical axis. After data completion, the completed data is automatically plotted with the same color and line style as the normal data to maintain the visual continuity of the curve. At the same time, the words "Data Completed" and the number of completed data points are marked below the corresponding time period of the curve with a light-colored background.

[0046] The step status indicator displays information such as the current step number, step type, elapsed runtime, and remaining runtime. After data completion, the runtime for this area is automatically updated to include the total runtime during the communication interruption period.

[0047] The data integrity indicator displays the current data integrity level as a progress bar. After reconnection and data completion, the indicator value returns to 100%, and statistical information such as the number of communication interruptions (1 in this case), the total duration of the communication interruption (4 hours), and the amount of data completed (approximately 15,000 data points) is displayed.

[0048] The lower-level machine continues to perform the test until all 500 cycles are completed. After the test is completed, the lower-level machine uploads all remaining data to the upper-level machine, which generates a complete test report, including voltage-time curves, current-time curves, temperature-time curves, and capacity decay data for all cycles.

[0049] In summary, this invention, through a pre-processing mechanism, sends all process steps to the lower-level machine's memory in advance when the host computer starts the detection process. This enables the lower-level machine to still independently complete all detection tasks even after the communication between the host computer and the upper-level machine is interrupted. This fundamentally eliminates the constraint of the communication link between the host and lower-level machines on the continuity of detection and avoids the defect in traditional solutions where the lower-level machine cannot continue to run due to the interruption of instructions from the host computer.

[0050] When a communication interruption occurs, both the host computer and the slave computer independently record the timestamp of the interruption and the status of the process step. The host computer records the first state, while the slave computer synchronously records the communication interruption status and marks the disconnection, achieving dual-end redundant storage of communication interruption information. The slave computer maintains steady-state operation without stopping, skipping steps, or changing parameters, ensuring that the detection process is not interrupted or disturbed by the host computer's offline status. This eliminates the problem of sample scrapping due to communication interruptions in long-cycle electrochemical detection, and avoids the waste of time and sample preparation costs caused by restarting the detection.

[0051] After reconnection, the system prioritizes the breakpoint verification process: It confirms the consistency of the breakpoint location by exchanging and comparing the communication interruption timestamps recorded by the upper and lower computers. If the timestamp deviation exceeds the tolerance range, it further uses the step sequence number and sampling sequence number for cross-location to ensure accurate breakpoint location determination under any extreme circumstances. After the breakpoint is determined, the time offset is calculated based on the first state timestamp to correct the historical timeline of the missing data, ensuring that the spliced ​​detection log timeline is continuous, accurate, and without jumps or regressions. After historical data correction is completed, heartbeat cycle synchronization is restored to ensure that the upper and lower computers maintain consistent time in subsequent operations. Subsequently, the upper computer reads the current step state of the lower computer, defines it as the second state, automatically retrieves all missing data between the first and second states, and completes it to form a complete detection log.

[0052] This invention effectively solves the technical problem of frequent communication interruptions of host computers leading to detection interruptions, data loss, and workpiece scrapping under harsh environments such as strong electromagnetic interference and power fluctuations in electrochemical industrial sites. It has significant application value and broad market prospects in long-cycle electrochemical detection fields such as battery charge and discharge detection, constant voltage charging, constant current charging, and leakage detection.

[0053] The above description is merely an embodiment of the present invention and does not constitute any limitation on the technical scope of the present invention. Therefore, any minor modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A method for fault-tolerant communication between a host computer and a slave computer in an electrochemical device, characterized in that, Includes the following steps: The host computer pre-downloads all process steps to the lower-level computer's memory for storage; During the detection process, the host computer caches the current process step, runtime, and parameter status in real time, and the host computer and the slave computer monitor the communication status through heartbeat packets. When communication is normal, the lower-level machine stores the detection data in real time during the execution of the detection steps, and cleans up the memory periodically after the data is successfully sent. When communication is interrupted and the system is abnormally offline, the communication fault tolerance process is executed: the host computer records the time point of the communication interruption and the current process step status, which is defined as the first state; the slave computer synchronously records the timestamp of the communication interruption, the current process step status, and the current process parameters, marking the communication interruption state; and the slave computer stops memory cleanup and maintains the current process parameters to continue steady-state operation and storage. After communication is restored, the host computer reads the current working state of the slave computer, defines it as the second state, automatically retrieves all missing detection data between the first state and the second state, and completes it to form a complete detection log.

2. The method for fault-tolerant communication between a host computer and a slave computer of an electrochemical device according to claim 1, characterized in that, The heartbeat detection specifically involves the host computer sending a heartbeat request frame to the slave computer at a preset period, and the slave computer replying with a heartbeat response frame; if no response is received from the other party for several consecutive periods, the communication link is determined to be interrupted.

3. The method for fault-tolerant communication between a host computer and a slave computer of an electrochemical device according to claim 1, characterized in that, The lower-level machine's memory is divided into several fixed-size data blocks, each data block being accompanied by a start timestamp and an end timestamp for that time period; When communication is normal, the lower-level machine releases the data block back to the idle pool after successfully sending the data block and receiving the confirmation signal from the upper-level machine. When communication is interrupted, the lower-level device marks all data blocks as pending upload and stops the cleanup operation.

4. The method for fault-tolerant communication between a host computer and a slave computer of an electrochemical device according to claim 1, characterized in that, When the communication interruption occurs, the host computer determines the type of communication interruption: If there is an abnormal offline situation, the communication fault tolerance process is executed. The host computer records the first state, and the slave computer continues to operate in a steady state. If the process is to actively go offline, the host computer sends a stop command to the slave computer before going offline, and the slave computer stops the current step.

5. A method for fault-tolerant communication between a host computer and a slave computer of an electrochemical device according to claim 1, characterized in that, Before the host computer reads the second state of the slave computer, the host computer and the slave computer perform a comparison and verification to determine the breakpoint location: If the difference between the first state timestamp recorded by the host computer and the communication interruption timestamp recorded by the slave computer is within the preset tolerance range, the breakpoint location is directly confirmed; if the difference exceeds the tolerance range, the breakpoint location is located by cross-locating the step number and sampling sequence number. After the breakpoint is determined, the time offset is calculated based on the first state timestamp to correct the time axis of the missing historical data.

6. The method for fault-tolerant communication between a host computer and a slave computer of an electrochemical device according to claim 1, characterized in that, The timeline correction of the missing historical data is specifically as follows: the host computer uses the first state timestamp recorded by itself as a reference, calculates the difference between the timestamp recorded by the host computer and the breakpoint timestamp recorded by the slave computer as a time offset, and adds the offset to the timestamps of all missing data uploaded by the slave computer.

7. A method for fault-tolerant communication between a host computer and a slave computer of an electrochemical device according to claim 6, characterized in that, After the timeline correction of the missing historical data is completed, the host computer sends the current reference time to the slave computer via a heartbeat packet. The slave computer then corrects its local clock to the host computer's time and restores the period calibration.

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