Communication method and device based on SPI protocol and embedded device

Abstract

The application discloses a communication method and device based on a SPI protocol and an embedded device. In the method, an address space used for configuring parameter mapping is compressed by bits to form a compact address space, and multi-byte communication data is transmitted after being segmented based on the compact address space. Since the address space is compressed by bits to form the compact address space, the utilization of the address space is improved, the address transmission overhead is reduced, and the transmission efficiency in the case of limited resources is improved. In addition, the multi-byte communication data is transmitted after being segmented, so that the incomplete data caused by interference or timing problems in the cross-SPI transmission is avoided.

Description

Technical Field

[0001] This application relates to the technical field of computer systems, and more particularly to communication methods, apparatus and embedded devices based on the SPI protocol. Background Technology

[0002] In common engineering practices, communication between the CPU and FPGA typically uses standard SPI communication or parallel bus communication. SPI (Serial Peripheral Interface) is a high-speed, full-duplex communication bus primarily used in electrically erasable programmable read-only memories (EEPROMs). Between Programmable Read-Only Memory (EEPROM), FLASH, real-time clock, AD converter, and digital signal processor and digital signal decoder.

[0003] However, in many practical applications, such as oscilloscopes needing to read large amounts of waveform data in real time, portable devices having limited GPIO resources, and the need to quickly configure multiple parameter registers, the transmission efficiency of related technologies based on the SPI protocol needs to be improved under resource constraints. Summary of the Invention

[0004] In view of this, this application provides a communication method, apparatus and embedded device based on the SPI protocol, which can improve transmission efficiency under resource constraints.

[0005] In a first aspect, this application provides a communication method based on the SPI protocol, comprising: The address space used for configuration parameter mapping is bit-compressed to form a compact address space; where the compact address space carries multiple configuration parameters in a single byte address, and the bit compression is compression using bitwise operations; Based on a compact address space, multi-byte communication data is transmitted after being segmented.

[0006] Optionally, bit compression specifically includes: The configuration parameters are coded according to the function type; Bit field allocation is performed on configuration parameters based on encoding; Based on bit field allocation, configuration parameters are compressed using bitwise operations, compressing multiple configuration parameters into a single byte.

[0007] Optionally, the encoding strategy is as follows: the high 4 bits are the main function code used to distinguish different functions, and the low 4 bits are the sub-function code or parameter index used to distinguish different types of functions under the same function.

[0008] Optionally, the segmentation strategy is as follows: the first byte of multi-byte communication data contains the address and data length, and the portion exceeding one byte is the data content.

[0009] Optionally, the method further includes: The address space is divided into multiple address regions; Communication data is transmitted independently based on the address region.

[0010] Optionally, the process of transmitting multi-byte communication data after segmentation includes: Lock the target register when writing multi-byte communication data.

[0011] Optionally, the process of transmitting multi-byte communication data after segmentation includes: After receiving multi-byte communication data, perform a checksum update after verification.

[0012] Secondly, this application provides a communication device based on the SPI protocol, comprising: The compression module is used to perform bit compression on the address space used for configuration parameter mapping to form a compact address space; wherein, the compact address space carries multiple configuration parameters in a single byte address, and the bit compression is compression using bit operations; The transmission module is used to transmit multi-byte communication data after it has been segmented, based on a compact address space.

[0013] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described above.

[0014] Fourthly, this application provides an embedded device including a processor and a memory, wherein the processor is coupled to the memory; Memory, used to store computer programs; A processor is used to execute computer programs stored in memory, causing the embedded device to perform the methods described above.

[0015] The method disclosed in this application performs bit compression on the address space used for configuration parameter mapping to form a compact address space, and then transmits multi-byte communication data after segmentation based on this compact address space. Because the address space is compressed into a compact address space, the utilization rate of the address space is improved, address transmission overhead is reduced, and thus transmission efficiency is improved under resource constraints. Furthermore, transmitting multi-byte communication data after segmentation avoids potential incompleteness of data transmitted across SPI due to interference or timing issues. Attached Figure Description

[0016] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0017] Figure 1 An architecture diagram of an embedded system provided by an exemplary embodiment is shown.

[0018] Figure 2 An operational flowchart of an exemplary embodiment of a communication method based on the SPI protocol is shown.

[0019] Figure 3 A block diagram of a communication device based on the SPI protocol provided in an exemplary embodiment is shown.

[0020] Figure 4 A block diagram illustrating the configuration of an embedded device provided in an exemplary embodiment is shown. Detailed Implementation

[0021] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0022] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices. The naming or numbering of steps appearing in this application does not imply that the steps in the method flow must be performed in the chronological / logical order indicated by the naming or numbering. The execution order of named or numbered process steps can be changed according to the desired technical purpose, as long as the same or similar technical effect is achieved. The division of units in this application is a logical division. In practical applications, there may be other division methods. For example, multiple units may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the shown or discussed mutual coupling, direct coupling, or communication connection may be through some interface, and the indirect coupling or communication connection between units may be electrical or other similar forms, none of which are limited in this application. Furthermore, the units or sub-units described as separate components may or may not be physically separated, may or may not be physical units, or may be distributed among multiple circuit units. Some or all of the units can be selected to achieve the purpose of the solution in this application according to actual needs.

[0023] First, it is necessary to explain the creation process of the technical solution of this application.

[0024] In common engineering practices, communication between the CPU and FPGA typically uses standard SPI communication or parallel bus communication. SPI (Serial Peripheral Interface) is a high-speed, full-duplex communication bus primarily used in electrically erasable programmable read-only memories (EEPROMs). Between Programmable Read-Only Memory (EEPROM), FLASH, real-time clock, AD converter, and digital signal processor and digital signal decoder.

[0025] Given the above context, if efficient CPU-FPGA communication needs to be achieved with limited hardware resources, the following "engineering trigger scenarios" will force the team to evaluate whether a more optimized communication protocol is required: 1. High-speed data acquisition scenario: Oscilloscopes need to read a large amount of waveform data in real time, and the traditional SPI protocol is not efficient enough.

[0026] 2. Resource-constrained scenarios: Portable devices have limited GPIO resources and cannot use complex parallel buses.

[0027] 3. Multi-parameter configuration scenario: requires rapid configuration of multiple parameter registers and high address space utilization.

[0028] 4. Low power consumption scenarios: It is necessary to reduce the number of communication times and reduce power consumption.

[0029] To address the above scenarios, engineers typically first try increasing the SPI clock frequency. However, this approach exposes a combination of problems, including low address mapping efficiency, difficulty in guaranteeing the integrity of multi-byte data, and complex state synchronization. Directly using standard SPI communication usually faces the following drawbacks: (1) Low address space utilization In the traditional SPI protocol, the address and data are transmitted separately, and a single-byte address can only map a limited register space.

[0030] (2) Data transmission efficiency is limited Each parameter configuration requires multiple SPI transmissions, resulting in significant protocol overhead.

[0031] (3) The integrity of multi-byte data is difficult to guarantee. Data transmitted across SPI may be incomplete due to interference or timing issues.

[0032] (4) Complex state synchronization State synchronization between the CPU and FPGA requires additional communication overhead.

[0033] Therefore, this application provides a communication method based on the SPI protocol. This method is applicable to embedded systems. Those skilled in the art have mastered the relevant principles of embedded systems. An embedded system is a dedicated computer system centered on applications, based on computer technology, with customizable hardware and software, and strictly meeting specific functional, reliability, cost, size, and power consumption requirements. Its core essence is a "stealth computer" deeply optimized for a single task. The fundamental difference between it and a general-purpose computer is that it does not pursue multifunctionality, but rather achieves extreme reliability and real-time performance of specific functions under resource-constrained conditions through highly customized hardware and software co-design. To distinguish it from the term "embedded device" used below, the embedded system mentioned herein refers to software (excluding hardware).

[0034] Please refer to Figure 1 ,in Figure 1An exemplary embodiment of an embedded system architecture diagram is shown. Taking an oscilloscope system as an example, the following logical layers are formed: application layer 120, communication protocol layer 140, and physical layer 160.

[0035] Application layer 120 is used for parameter configuration, data reading, and status query. Since parameter configuration, data reading, and status query are well-known to those skilled in the art, they will be briefly described here.

[0036] The communication protocol layer 140 is used for address mapping, bit compression, data transmission, and state synchronization. Address mapping, bit compression, data transmission, and state synchronization are the tasks involved in this communication method and will be discussed in detail later.

[0037] Physical layer 160 is used for the SPI interface, data buffer, and timing control. Since the SPI interface, data buffer, and timing control are well-known to those skilled in the art, they will be briefly described here.

[0038] It should be noted that the aforementioned communication protocol layer 140 ≠ the entire hardware system; communication protocol layer 140 can be used for communication methods based on the SPI protocol. Next, in conjunction with... Figure 2 ,in Figure 2 An operational flowchart of an exemplary embodiment of a communication method based on the SPI protocol is shown. This method is implemented via steps S220-S260.

[0039] In S220, the address space used for configuration parameter mapping is bit-compressed to form a compact address space; wherein, the compact address space carries multiple configuration parameters in a single byte address, and the bit compression is compression using bit operations.

[0040] Here, the technical effects of a "compact address space" are as follows: (1) Improve address utilization, reduce address transmission overhead, and increase the proportion of effective data transmission; (2) Improve access efficiency, that is, parameter configuration can be completed within a single cycle without the need for multi-cycle addressing; (3) Enhance scalability, that is, to accommodate more functional modules in a limited address space and support future functional expansion; (4) Reduce power consumption, that is, reduce unnecessary address transmission and reduce communication power consumption.

[0041] Here, "bit compression using bitwise operations" refers to compression performed through bitwise operations. Bitwise operations are operations that directly manipulate the binary bits (bits) of integers in memory. Bitwise operation types include bitwise AND, bitwise OR, bitwise XOR, bitwise NOT, left shift, and right shift. The bitwise AND operation returns 1 only if both bits are 1; otherwise, it returns 0. The bitwise OR operation returns 1 if at least one bit is 1. The bitwise XOR operation returns 0 if the two bits are the same, and 1 if they are different. The bitwise NOT operation reverses the order of bits, changing 0 to 1 and 1 to 0. The left shift operation shifts all binary bits to the left by a specified number of positions, discarding the most significant bits and filling the least significant bits with 0s. The right shift operation shifts all binary bits to the right by a specified number of positions, discarding the least significant bits and filling the most significant bits with 0s or the sign bit. In one alternative embodiment, bit compression specifically includes the following steps: A1. Encode the configuration parameters according to the function type.

[0042] Understandably, the purpose of encoding is to decode a single-byte address carrying multiple configuration parameters, which has been compressed in place.

[0043] As an optional example of the coding strategy, the high 4 bits are the main function code used to distinguish different functions, and the low 4 bits are the sub-function code or parameter index used to distinguish different types of functions under the same function.

[0044] Here, the main function code can be used to distinguish different functions, including channel configuration, trigger configuration, and sampling configuration.

[0045] A2. Assign bit fields to configuration parameters based on encoding.

[0046] In this application, bit field allocation may take the form well known in the art. As is well known, bit fields are defined in a structure (struct) and the number of bits they occupy is specified by appending the number of bits after the member variable.

[0047] For example, the basic syntax format: struct structure_name { data_type_member_name: number of bits used;}; For example (using TCP header flag compression as an example): Suppose we need to store 8 boolean states (such as the SYN, ACK, FIN flags in the TCP header), using a regular int or bool array might take 8 to 32 bytes. Using bit fields, we can perfectly compress them into 1 byte (8 bits): struct TCP_Flags { unsigned char FIN : 1; / / Occupies bit 0 unsigned char SYN : 1; / / Occupies the first bit unsigned char RST : 1; / / Occupies the 2nd bit unsigned char PSH : 1; / / Occupies the 3rd bit unsigned char ACK : 1; / / Occupies the 4th bit unsigned char URG : 1; / / Occupies the 5th bit unsigned char ECE : 1; / / Occupies the 6th bit unsigned char CWR : 1; / / Occupies the 7th bit / / Theoretically, these 8 flag bits are compressed into 1 byte of space. In this example, by using the ":1" allocation method, eight independent switch values ​​are "crammed" into a single unsignedchar memory unit, greatly saving address space.

[0048] The bit field allocation in this application may adopt the following rules: (1) Same type packing principle: If the total number of bits of adjacent bit fields of the same data type is less than the size of the data type (e.g., unsigned int is usually 32 bits), the compiler will pack them tightly in the same storage unit without leaving any gaps.

[0049] (2) Cross-cell allocation: If the total number of bits in adjacent bit fields exceeds the size of the basic data type, the excess part will be allocated starting from the next storage cell.

[0050] (3) Prohibit cross-byte / cell storage: A bit field member must be stored completely in the same storage unit and cannot cross two bytes or two int boundaries. If there are not enough bits left in the current unit to fit the next bit field, the compiler will skip the remaining empty bits and put the next bit field into a new storage unit.

[0051] (4) Anonymous bit fields (filling and alignment): You can define bit fields without names (such as "int: 4;"), which are purely placeholders (filling). If you use "int : 0;", it forces the next bit field member to be allocated starting from the beginning of the next memory unit.

[0052] A3. Based on bit field allocation, the configuration parameters are compressed through bit operations, compressing multiple configuration parameters into a single byte.

[0053] Those skilled in the art can determine the specific compression method based on well-known bitwise operations and the principle of compression into a single byte; this application does not rely on a specific compression method. As an exemplary operation, this step "compressing configuration parameters through bitwise operations" includes the following process: A31. Define a bitmask, which means assigning a fixed "position" (i.e., which position) to each configuration parameter. The left shift operator << is typically used to generate the corresponding hexadecimal or binary mask. The C code for this process is as follows: / / Define bitmasks for 8 configuration parameters, corresponding to bits 0 through 7 of the byte respectively. #define CONFIG_ENABLE_CACHE(1<<0) / / Binary 00000001, bit 0: Enable caching #define CONFIG_DEBUG_MODE(1<<1) / / Binary 00000010, bit 1: debug mode #define CONFIG_LOG_ARCHIVE(1<<2) / / Binary 00000100, second bit: log archiving #define CONFIG_AUTO_UPDATE(1<<3) / / Binary 00001000, 3rd bit: Automatic update / / ... can be further defined up to (1<<7).

[0054] A32. Packaging and setting parameters: When a configuration parameter needs to be enabled, a bitwise OR (|) operation is used. Its function is that "if any bit is 1, the result is 1," thus enabling the specified bit without affecting other bits. The C language code for this process is as follows: unsigned char configByte = 0; / / Initialize to 0 (all configurations disabled) Enable "Enable caching" and "Debug mode" configByte = configByte | CONFIG_ENABLE_CACHE; configByte = configByte | CONFIG_DEBUG_MODE; / / Abbreviated form: configByte |= CONFIG_LOG_ARCHIVE; / / Enable "Log Archiving" again / / At this point, the binary value of configByte is 00000111 (decimal 7). A33. Modifying and clearing parameters: To disable a specific configuration, you need to combine bitwise AND (&) and bitwise NOT (~). ~ will change 0s to 1s and 1s to 0s in the mask, and then the & operation will "clear" the specified bit while leaving other bits unchanged. The C code for this process is as follows: / / Turn off "Debug Mode" configByte = configByte&(~CONFIG_DEBUG_MODE); / / Abbreviated form: configByte&= ~CONFIG_DEBUG_MODE; / / At this point, the binary representation of configByte changes from 00000111 to 00000101.

[0055] A34. Reading and checking parameters: To determine whether a configuration is enabled, perform a bitwise AND (&) operation between the compressed byte and the corresponding mask. If the result is not 0, it means that the bit is 1 (enabled). The C code for this process is as follows: / / Turn off "Debug Mode" configByte = configByte&(~CONFIG_DEBUG_MODE); / / Abbreviated form: configByte&= ~CONFIG_DEBUG_MODE; / / At this point, the binary representation of configByte changes from 00000111 to 00000101.

[0056] In the specific implementation of "compressing configuration parameters through bitwise operations" discussed above, the principle is to understand the configuration parameters as "on / off". As another illustrative method for this step of "compressing configuration parameters through bitwise operations", the technical idea is to store the configuration parameter as a small range of values ​​(e.g., a range of 0-3), and to allocate multiple consecutive bits to the same parameter. Specifically, this includes the following process: A31' allocation: For example, use the lowest 2 bits (bits 0 and 1) to store the "volume level" (0-3), and use the 2nd bit to store the "mute switch".

[0057] A32´ Write (Packing): First clear the area, then shift and write.

[0058] configByte = (configByte&~0x03) | (volumeLevel&0x03); (Note: 0x03 is binary 00000011, used to operate on the lower 2 bits) A33' Read (Unpack): Shift and AND with the mask.

[0059] int currentVolume = configByte&0x03.

[0060] The configuration parameter mapping involved in this operation S220 is a well-known technique in computer communication systems. As a preferred method, the configuration parameter mapping can employ a multi-level mapping mechanism of "main address → sub-address → bit field three-level mapping". Here, "main address → sub-address → bit field three-level mapping" is a classic hierarchical addressing and bit packing technique in embedded and system programming. Its core idea is to mimic the multi-level page table mechanism in computer memory management, ultimately locating a specific bit in a specific hardware register through layer-by-layer indexing. It can include the following processes.

[0061] B1. Determine the primary address (equivalent to locating a "memory block" or "device").

[0062] The main address acts as a large container or base address. It is typically used to locate a specific physical device, a functional module, or a contiguous memory region. In practice, the CPU or controller first retrieves this main address. In a computer system, this is equivalent to an index in the Page Global Directory (PGD); in embedded peripherals, it is equivalent to the base address of a specific GPIO port (e.g., 0x40020000 represents the entire GPIOA port).

[0063] B2. Determine the second-level sub-address (equivalent to locating the "specific register" or "parameter group") A sub-address is a further subdivision within the range defined by the main address. It is typically represented as an offset used to locate a specific register or parameter group within the device or module.

[0064] The specific operation involves adding the "main address" and the "sub-address (offset)" to calculate the absolute physical address of the target register. In practice, this is equivalent to an index in the page table entry (PTE). For example, adding the sub-address offset 0x14 to the main address 0x40020000 (GPIOA) yields the absolute address 0x40020014, which may correspond exactly to the "Port Output Data Register (ODR)".

[0065] B3. Determine the third-level bit field (equivalent to locating the specific bit within the register) The bit field is the most microscopic level. After locating a specific register (usually a 16-bit or 32-bit integer), we don't need to modify the entire register; instead, we only need to manipulate a single bit or several consecutive bits. Specifically, this involves precisely extracting or modifying the target bit using a bitmask and bitwise operations. A practical example is that this is equivalent to further refining the page offset to a specific bit within a byte. For instance, in register 0x40020014, bit 5 precisely controls the high and low levels of pin 5.

[0066] In the mapping of configuration parameters in this application, a dynamic mapping table is preferred, as this allows for modification of the mapping relationship at runtime. The principle of the dynamic mapping table is to decouple the binding relationship between "physical address / parameter ID" and "logical variable / business meaning" from static hard coding and place it in a data structure that can be dynamically added, deleted, modified, and queried at runtime.

[0067] To construct a dynamic mapping table, the following steps can be followed in practice: C1. Define the data structure of the mapping table.

[0068] First, a data structure capable of holding the mapping relationship needs to be established in memory. The most common methods are hash tables (Hash Maps / Dictionaries) or arrays / linked lists.

[0069] Key: This is usually a physical address, register offset, or parameter ID (e.g., 0x1004 or "MOTOR_1_CTRL").

[0070] Value: A value is a struct or object containing rich metadata, typically including: Logical variable name (e.g., "target_speed") Data types (such as INT16, FLOAT32) Read and write permissions (e.g., READ_ONLY, READ_WRITE) Data scaling ratio (e.g., original value 100 represents 10.0 degrees Celsius) The actual memory pointer or callback function (pointing to the actual location of the parameter in memory or the processing logic). C2. Implement the dynamic management interface for the mapping table. To make the mapping table "dynamic," a standard CRUD interface needs to be provided, allowing the host computer, configuration files, or internal logic to operate on the mapping table during system runtime. Register / Bind: Inserts a new mapping record into the mapping table during system startup or hot update. For example, dynamically binds the newly connected sensor parameter 0x2001 to the logical name "temp_sensor_new".

[0071] Unregister / Unbind: When a device goes offline or a function is disabled, the corresponding record is removed from the mapping table to release resources.

[0072] Dynamic Update: Modifies the mapping attributes of an address without restarting the system. For example, temporarily downgrades the permissions of a parameter from "read and write" to "read only".

[0073] Lookup and Resolve: This is the core runtime function of the mapping table. When an access request is received (such as reading address 0x1004), the system no longer looks up rigid macro definitions, but instead searches the mapping table in real time for the logical variable and data type corresponding to that address, and then performs the specific read and write operations.

[0074] C3. Externalization and persistence of mapping tables.

[0075] Dynamic mapping tables are often combined with external storage to achieve truly flexible configuration: Configuration file loading: The mapping relationships are written in JSON, XML, or Excel spreadsheets. At system startup, these files are parsed and automatically populated into an in-memory mapping table. This way, modifying parameter mappings only requires changing the configuration file, without recompiling the code.

[0076] Dynamic distribution via network / bus: In complex distributed systems, the master station can distribute new mapping rules to the slave stations in real time via the network (such as TCP / IP, Redis, etc.), and the slave stations can dynamically update their local mapping tables after receiving the rules.

[0077] Furthermore, the mapping of configuration parameters in this application can also employ bit field multiplexing, allowing different bit fields of the same physical address to map different functions. "Bit field multiplexing" refers to the same set of physical bits representing completely different parameter meanings in different contexts, modes, or time stages. Bit field multiplexing can adopt the following modes: (1) Mode switching reuse The way the target bit field is interpreted can be changed by using a separate "mode control bit" or "mode register".

[0078] In practice, a mode register (e.g., MODE_REG) is first set, and a certain bit (e.g., Bit0) is used to determine whether the current mode is "Mode A" or "Mode B".

[0079] Then set a multiplexed parameter register (e.g., CONFIG_REG), with its lower 4 bits (Bit[3:0]) as the multiplexed bit field.

[0080] When MODE_REG.Bit 0 = 0: Bit[3:0] of CONFIG_REG is interpreted as "motor speed level (0-15)".

[0081] When MODE_REG.Bit 0 = 1: Bit[3:0] of CONFIG_REG is interpreted as "the preset angle of the robotic arm (0-15)".

[0082] (2) Dynamic remapping reuse This practice is very common in complex System-on-Chip (SoC) or high-performance MCU, where a dedicated "remap" mechanism is usually provided by hardware.

[0083] In practice, the hardware provides a dedicated remapping control register (such as the AFIO_MAPR register in STM32, or the Remap control bit in some bus matrices).

[0084] By modifying specific addresses in the remapping register, the logic signal of a peripheral device (such as serial port TX / RX, timer channel) can be dynamically switched from the default pin / address to a completely different set of physical pins or internal register addresses.

[0085] For example, by default, Bit[7:4] controls the baud rate of peripheral A; when remapping is enabled, the physical connection of Bit[7:4] is cut off and instead mapped to the interrupt trigger threshold of peripheral B.

[0086] Application scenarios: PCB routing optimization (avoiding flying wires), switching peripheral channels between the bootloader and the application, or dynamically changing the layout of hardware functional modules at runtime.

[0087] (3) Time / Phase Reuse The most typical phases are the system startup phase and the normal operation phase.

[0088] In actual operation, at the moment of power-on reset, the hardware logic will latch the level state of a certain physical pin (PAD) or read the specific startup pin configuration.

[0089] During the startup phase: the bit field configuration of a memory address (such as 0x0000) is mapped to "boot device selection" (for example, 0 represents booting from Flash, and 1 represents booting from SRAM).

[0090] After startup: The system enters the normal operation phase, and the bit field configuration of this address or this group of pins is reinterpreted as "general purpose GPIO input" or "debug interface enable bit".

[0091] In addition, address aliases can be used in the mapping of configuration parameters in this application, which can support multiple address accesses for the same function.

[0092] This operation S220 involves address space. Preferably, the address space location can be logically mapped to the FPGA internal registers. The physical implementation can be flexibly selected: on-chip RAM for high-speed access scenarios, dedicated register groups for low-latency scenarios, or a hybrid implementation to balance performance and flexibility.

[0093] The address space can be 256 bytes in size, but can be expanded to a larger space as needed.

[0094] In S240, multi-byte communication data is transmitted after being segmented, based on a compact address space.

[0095] In one optional specific embodiment, the segmentation strategy is as follows: the first byte of the multi-byte communication data contains the address and data length, and the portion exceeding one byte is the data content.

[0096] Therefore, this segmentation strategy avoids the possibility of incomplete data transmission across SPI due to interference or timing issues.

[0097] It is understandable that during the transmission of multi-byte communication data after segmentation, the data writing operation involves splitting large data into multiple small data packets.

[0098] In one optional specific embodiment, the process of transmitting multi-byte communication data after segmentation includes: Lock the target register when writing multi-byte communication data.

[0099] In one optional specific embodiment, the process of transmitting multi-byte communication data after segmentation includes: After receiving multi-byte communication data, perform a checksum update after verification.

[0100] In one optional specific embodiment, the process of transmitting multi-byte communication data after segmentation further includes: Confirmation mechanism: The FPGA returns a confirmation signal after receiving the data.

[0101] It should be noted that if an error occurs during the writing process after segmenting multi-byte communication data, the following actions can be taken: (1) Automatically roll back to the state before writing; (2) Return error code and prompt for retry; (3) Record error log for easy debugging.

[0102] In this operation S240, after segmenting the multi-byte communication data, the following may also be included: S241, Abnormality Detection and Recovery Actions.

[0103] Specifically, it can be done in the following ways: (1) Address out of bounds If the access address is outside the valid range, an error code will be returned, and the operation will be rejected. (2) Data length exceeded the limit If the data length exceeds the maximum allowed value, the data will be truncated or an error will be returned.

[0104] (3) Checksum error If the received data does not match the checksum, the data is discarded and a retransmission is requested.

[0105] In one optional specific embodiment, the method further includes: S260. Divide the address space into multiple address regions.

[0106] The technical benefits of address space partitioning are reflected in the following aspects: (1) Improve access efficiency: Optimize transmission strategies according to access modes; (2) Enhanced reliability: Read-write separation prevents accidental operations; (3) Easy to expand: Reserved address space supports functional expansion; (4) Reduce complexity: Structured address space simplifies software implementation.

[0107] Here, different address areas can be designated as parameter configuration areas, waveform data reading areas, status query areas, etc. For example, if the address range is 0x00-0x3F, it can be defined as a parameter configuration area with read-write data; if the address range is 0x40-0x7F, it can be defined as a status query area with read-only data; if the address range is 0x80-0xFF, it can be defined as a waveform data area with read-only data.

[0108] Here, the address space partitioning strategy can be demonstrated as follows: (1) Access frequency: The status query area (0x40-0x7F) for high-frequency access is separated from the waveform data area (0x80-0xFF) for low-frequency access; (2) Data characteristics: Configuration parameters (read and write) are separated from status data (read only). (3) Security level: Critical configuration area is isolated from ordinary configuration area (4) Transmission efficiency: Large blocks of continuous data are transmitted in burst mode. S280. Transmit communication data independently according to the address area.

[0109] For data transmission based on the parameter configuration area, a compact address mapping is adopted to support the rapid configuration of multiple parameters, including but not limited to: a) each parameter occupies 1-2 bytes of address; b) support batch configuration of multiple parameters; c) automatic synchronization of FPGA status after configuration.

[0110] For data transmission based on waveform data areas, continuous address block transmission is adopted to improve data reading efficiency, including but not limited to: supporting burst read mode, automatic address increment, and reducing the number of SPI transmissions.

[0111] For data transmission based on the status query area, real-time status feedback is provided, including but not limited to obtaining multiple status bits in a single query, supporting masked queries, and triggering interrupts when status changes occur.

[0112] Please refer to Figure 3 This diagram illustrates the configuration of a communication device based on the SPI protocol provided in this application. The device 300 includes: Compression module 320 is used to perform bit compression on the address space used for configuration parameter mapping to form a compact address space; wherein, the compact address space carries multiple configuration parameters in a single byte address, and the bit compression is compression using bit operations; The transmission module 340 is used to transmit multi-byte communication data after it has been segmented, based on a compact address space.

[0113] Since the methods mentioned above have already been discussed in detail, the specific execution of the above modules will not be repeated here.

[0114] The following describes an embedded device provided in an embodiment of this application. Please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is a schematic diagram of an embedded device provided in an embodiment of this application. The embedded device 400 can specifically be an autonomous vehicle, a mobile phone, a tablet, a laptop, a desktop computer, a monitoring data processing device, etc., and is not limited thereto. The embedded device 400 is used to implement... Figure 2 The embedded device in the corresponding embodiment has the following functions. Specifically, the embedded device 400 includes: a receiver 401, a transmitter 402, a processor 403, and a memory 404 (wherein the number of processors 403 in the execution device 400 can be one or more). Figure 4 (Taking a processor as an example), processor 403 may include application processor 4031 and communication processor 4032. In some embodiments of this application, receiver 401, transmitter 402, processor 403 and memory 404 may be connected via a bus or other means.

[0115] Memory 404 may include read-only memory and random access memory, and provides instructions and data to processor 403. A portion of memory 404 may also include non-volatile random access memory (NVRAM). Memory 404 stores processor and operation instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.

[0116] Processor 403 controls the operation of the execution device. In specific applications, the various components of the execution device are coupled together through a bus system, which may include not only the data bus, but also power buses, control buses, and status signal buses. However, for clarity, all buses are referred to as the bus system in the diagram.

[0117] The methods disclosed in the embodiments of this application can be applied to processor 403, or implemented by processor 403. Processor 403 can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of processor 403 or by instructions in the form of software. The processor 403 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, and may further include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor 403 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 404, and processor 403 reads the information from memory 404 and, in conjunction with its hardware, completes the steps of the above method.

[0118] Receiver 401 can be used to receive input digital or character information, and to generate signal inputs related to the settings and function control of the execution device. Transmitter 402 can be used to output digital or character information through the first interface; transmitter 402 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; transmitter 402 may also include a display device such as a display screen.

[0119] In this embodiment of the application, processor 403 is used to execute... Figure 4 The method for obtaining system capacity executed by the execution device in the corresponding embodiment. The specific manner in which the application processor 4031 in processor 403 executes the above steps is the same as that in this application. Figure 2 The various method embodiments are based on the same concept, and the technical effects they bring are the same as those in this application. Figure 2 The corresponding method embodiments are the same, and for details, please refer to the description in the method embodiments shown above in this application, which will not be repeated here.

[0120] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A communication method based on the SPI protocol, characterized in that, include: The address space used for configuration parameter mapping is bit-compressed to form a compact address space; wherein the compact address space carries multiple configuration parameters in a single byte address, and the bit compression is compression using bit operations; Based on a compact address space, multi-byte communication data is transmitted after being segmented.

2. The method according to claim 1, characterized in that, Bit compression, specifically including: The configuration parameters are coded according to the function type; Bit field allocation is performed on configuration parameters based on encoding; Based on bit field allocation, configuration parameters are compressed using bitwise operations, compressing multiple configuration parameters into a single byte.

3. The method according to claim 2, characterized in that, The coding strategy is as follows: the high 4 bits are the main function code used to distinguish different functions, and the low 4 bits are the sub-function code or parameter index used to distinguish different types of functions under the same function.

4. The method according to claim 1, characterized in that, The specific strategy for segmentation is that the first byte of multi-byte communication data contains the address and data length, while the portion exceeding one byte is the data content.

5. The method according to claim 1, characterized in that, The method also includes: The address space is divided into multiple address regions; Communication data is transmitted independently based on the address region.

6. The method according to claim 1, characterized in that, The process of transmitting multi-byte communication data after segmentation includes: Lock the target register when writing multi-byte communication data.

7. The method according to claim 1, characterized in that, The process of transmitting multi-byte communication data after segmentation includes: After receiving multi-byte communication data, perform a checksum update after verification.

8. A communication device based on the SPI protocol, characterized in that, include: The compression module is used to perform bit compression on the address space used for configuration parameter mapping to form a compact address space; wherein, the compact address space carries multiple configuration parameters in a single byte address, and the bit compression is compression using bit operations; The transmission module is used to transmit multi-byte communication data after it has been segmented, based on a compact address space.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When a computer program is executed by a processor, it implements the method as claimed in any one of claims 1 to 7.

10. An embedded device, characterized in that, Includes a processor and memory, with the processor coupled to the memory; Memory, used to store computer programs; A processor for executing a computer program in memory, causing an embedded device to perform the method as claimed in any one of claims 1 to 7.

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