Adaptive management and control device and method of FPGA-based HDMI receiving end

Abstract

The application discloses a kind of based on FPGA's HDMI receiving end's adaptive management and control device and method, belong to video receiving technical field.The application is effective in HPD and after source end reads EDID is completed, not directly pass video data, but comprehensive locking signal continuous validity, pixel clock frequency range, line field synchronization state and the consistency of multiple frame video parameters are carried out joint stability determination, and pixel output gate is opened after determining link stability;Simultaneously, HDMI receives whole process is divided into unconnected, waits locking, waits timing stability, stable reception, abnormal recovery working state, and different fault scene design mild, moderate, severe three-grade grading abnormal recovery strategy.The application can realize link automatic convergence and recovery under the scene such as hot plug, resolution switching, signal transient, effectively protect rear stage image processing and algorithm module, greatly improve the robustness and unattended operation ability of FPGA video receiving system.

Description

Technical Field

[0001] This invention relates to video receiving technology, and more particularly to an adaptive control device and method for an HDMI receiver based on FPGA. Background Technology

[0002] With the development of video acquisition, image processing, display control, and industrial inspection systems, HDMI interfaces are widely used for high-definition image input. HDMI receivers typically need to perform functions such as hot-plug detection, EDID information response, TMDS high-speed serial data reception, clock recovery, video timing analysis, pixel data output, and abnormal state handling. In devices that use FPGAs as the core of video acquisition and processing, the HDMI receiving link usually also needs to work in conjunction with subsequent image processing, buffering, display, or algorithm modules; therefore, the stability of the receiving process directly affects the overall operating status of the device.

[0003] Existing solutions can generally achieve HDMI signal reception and pixel data output, but in engineering applications, situations such as input source plugging / unplugging, resolution switching, signal interruption, brief clock loss, or source renegotiation may still occur. If the system only focuses on the reception function itself and lacks a unified state judgment and anomaly recovery process, the receiving link may output data to subsequent stages before it is fully stable, or manual reconfiguration, resetting of local modules, or even system restart may be required after an anomaly.

[0004] Furthermore, some systems use external receiver chips or fixed receiving procedures for HDMI input. While this meets basic reception requirements, it increases board-level components and debugging steps, and makes it difficult to achieve close integration with the video processing logic within the FPGA. For devices requiring rapid iteration, low-cost implementation, or long-term unattended operation, a technical solution is still needed that can perform reception status monitoring, controlled negotiation, hierarchical recovery, and output protection on the FPGA side, enabling the HDMI receiving link to automatically recover and maintain stable output under signal changes or abnormal conditions. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an adaptive control device and method for an HDMI receiver based on FPGA, which addresses the deficiencies in the prior art.

[0006] The technical solution adopted by this invention to solve its technical problem is: an adaptive control device for an HDMI receiver based on FPGA. The FPGA is equipped with an HDMI receiving module. The control device is used to access the lock status signal, pixel clock, video timing signal and pixel data stream output by the HDMI receiving module, and output a reset control signal to the HDMI receiving module, while driving the HPD signal of the HDMI interface. The adaptive control device includes: an external interface layer, a receiving and parsing layer, a state determination layer, and a recovery and output layer; The external interface layer is configured with an HPD / EDID control module and a register configuration interface; The HPD / EDID control module is used to provide hot-plug status and display capability information to the external HDMI source. It first detects the HDMI interface cable connection status, completes EDID content loading and reception parameter configuration while keeping HPD in an invalid state, and then pulls the HPD level high after the internal resources of the FPGA are ready to trigger the external video source to read EDID through the DDC channel. The receiving and parsing layer is configured with a data receiving module, a clock and lock monitoring module, and a video timing recognition module; The data receiving module is used to receive the lock status signal, pixel clock, video timing signal and pixel data stream output by the HDMI receiving module; If the current pixel clock cycle transmits a real RGB pixel image data stream, which is considered a valid display of the image, then the data is in a valid state. The clock and lock monitoring module is used to determine whether the lock status signal is continuously valid within a preset time window and whether the pixel clock frequency is within a preset legal range based on the lock status signal and the pixel clock, and outputs a clock stability flag to the receiving status determination module. The video timing recognition module is used to continuously count line synchronization, field synchronization, effective frame size, and frame period after the clock stability flag is valid. When the timing parameters of multiple consecutive frames are consistent and are within the preset supported timing set list, the timing stability flag is output to the receiving status determination module. The status determination layer includes a status determination receiving module; The receive status determination module is used to generate the link working status based on the clock stability flag, timing stability flag, and data validity status. The link working status includes: "not connected, waiting to lock, waiting for timing to stabilize, stable reception, and abnormal recovery". The recovery and output layer is equipped with an anomaly recovery control module and an output protection module; Set up an output protection module to prevent the real pixel data stream from being released when the link does not reach stable reception conditions; The output protection module is used to block the effective pixel data stream in an unstable reception state; and to allow the real pixel data to pass after receiving a stable reception indication. The anomaly recovery control module is used to identify the link anomaly level and execute a graded recovery strategy.

[0007] According to the above scheme, the link's working status is generated based on the clock stability flag, timing stability flag, and data validity status. Specifically as follows: Not connected state: When no HDMI interface 5V signal or cable connection signal is detected, HPD remains at an invalid level, the clock stability flag, timing stability flag and data validity flag are cleared, and the output protection module remains in a state of blocking real pixel data; Waiting for lockout state: After the cable is detected and the EDID content and receiving parameters are prepared, HPD is pulled high to trigger the external video source to establish a link; in this state, the lockout state signal and pixel clock output by the HDMI receiving module are continuously monitored. Only when the lockout state signal is continuously valid within the preset lockout determination time and the pixel clock frequency is within the preset legal range, a clock stability flag is generated and the system enters the waiting timing stability state. Waiting for timing stability: After the clock stability flag is valid, the line synchronization, field synchronization, effective frame width, effective frame height, and frame period are counted frame by frame. When the effective frame size is consistent for N consecutive frames, the deviation of the synchronization period and frame period does not exceed the preset tolerance, and the corresponding timing is within the supported timing sequence list, a timing stability flag is generated. If the clock stability flag fails, the system returns to the waiting locked state; if the cable is unplugged, the system returns to the disconnected state. Stable reception status: When the clock stability flag, timing stability flag, and data validity flag are all valid, the pixel output gating is opened and real pixel data is allowed to pass through, while the lock status, pixel clock, video timing, and data validity status are continuously monitored. Abnormal recovery state: When any stable condition fails during stable reception, the pixel output gating is immediately turned off and output protection is entered. Then, mild, moderate or severe recovery is performed according to the duration, type and number of recovery attempts. After mild recovery, the system returns to the joint state determination. After moderate recovery, the system returns to the waiting timing stability state. After severe recovery, the system returns to the waiting lock state. After multiple severe recovery failures, the HPD is pulled down and the system returns to the renegotiation process.

[0008] According to the above scheme, the register configuration interface is used to provide software-configurable parameters, including EDID selection, supported resolution list, lock determination time, number of exception recovery attempts, and output protection mode.

[0009] According to the above scheme, the output protection module is used to block the effective pixel data stream in an unstable reception state and output a black field, fixed background color or invalid data flag to the subsequent stage.

[0010] According to the above scheme, the anomaly recovery control module identifies the link anomaly level and executes a graded recovery strategy as follows: Mild anomalies only clear the video output buffer; moderate anomalies reset the video timing recognition module and output protection module; severe anomalies reset the HDMI receiver module via the reset control signal; in the event of multiple severe recovery failures, HPD is pulled low and then pulled back after a delay, triggering the external video source to re-execute EDID negotiation.

[0011] This invention also provides an FPGA-based adaptive control method for HDMI reception, comprising the following steps: S1. The FPGA powers on and completes clock, reset and register initialization. Then, it detects the HDMI cable connection status. In the HPD invalid state, it completes EDID loading and receive parameter configuration. After the internal resources of the FPGA are ready, the HPD level is pulled high to trigger the external video source to read the EDID through the DDC channel and output the TMDS video signal. S2. Receive the lock status signal, pixel clock, video timing signal and pixel data stream output by the existing HDMI receiver module, without modifying the TMDS receiving and decoding logic inside the HDMI receiver module. S3. Based on the lock status signal and the pixel clock, determine whether the lock status signal is continuously valid within the preset time window and whether the pixel clock frequency is within the preset legal range, and output a clock stability flag to the receiving status determination module. During the RX lock detection phase, the lock status signal is filtered by a time window. The clock link is determined to be stable only when the lock signal is continuously valid within a preset duration and the pixel clock frequency is within the legal range. Then, a clock stability flag is output to the receiving status determination module. S4. Continuously count timing parameters including line synchronization, field synchronization, effective frame size, and frame period. When the timing parameters of multiple consecutive frames are consistent and within the preset supported timing set list, output a timing stability flag to the receiving status determination module. If the timing parameters change or are not within the supported range, it is considered that the video source is switching or the current input is not supported. The preset supported timing set includes video timing conforming to the CTA-861 standard, and VESA DMT / CVT display timing configured according to application needs; S5. Combine clock stability conditions, timing stability conditions, and data validity conditions to make a joint state decision. After entering a stable reception state, the real pixel data is released; during the unstable period, the output protection state is maintained. S6. During operation, monitor link anomalies in real time. If an anomaly is detected, enter the anomaly recovery state and perform recovery processing.

[0012] According to the above scheme, in step S5, the output protection state includes being configured to output black screen, gray screen, fixed color screen or invalid data flag.

[0013] According to the above scheme, in step S6, during the operation, link anomalies are monitored in real time, and graded recovery processing is performed as follows: If an invalid single frame of data or a brief synchronization jitter is detected, it is determined to be a minor anomaly, the output buffer is cleared and the receiving link is kept working; If a resolution switch or consecutive multi-frame timing changes are detected, it is determined to be a moderate anomaly. The video timing recognition and output protection logic is reset, and the system waits for a stable timing sequence. If a pixel clock is detected to be lost for an extended period or the receiving link is detected to be out of lock for an extended period, it is determined to be a severe anomaly, and a reset signal is output to reset the HDMI receiving link. If the recovery process fails after more than the set number of attempts, it returns to the EDID preparation state, pulls down HPD and pulls it up again after a delay, triggering the external video source to re-complete EDID negotiation and link establishment.

[0014] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described scheme.

[0015] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method in the above-described scheme.

[0016] The beneficial effects of this invention are: This invention, after HPD is valid and the EDID is read from the source end, does not immediately release video data. Instead, it performs a joint stability determination by comprehensively locking the validity of continuous frames, pixel clock intervals, horizontal and vertical sync signal states, and the consistency of continuous frame parameters. Output gating is only activated after these conditions are met. This effectively filters out invalid transition frames generated during the initial link establishment, resolution switching, and transient signal disturbances, preventing abnormal video data from being input to subsequent modules. It effectively avoids problems such as screen tearing and image processing anomalies, enhancing the system's operational stability in scenarios involving hot-swapping and dynamic signal changes. Furthermore, this invention fully reuses existing HDMI receiver modules, offering strong compatibility and high portability. Attached Figure Description

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings: Figure 1 This is a device diagram according to an embodiment of the present invention; Figure 2 This is a flowchart of a method according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the link working state transition according to an embodiment of the present invention; Figure 4 This is a timing diagram illustrating HPD, EDID, locking, timing convergence, and data release in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] like Figure 1 As shown, an adaptive control device for an HDMI receiver based on FPGA is described. The FPGA is equipped with an HDMI receiving module. The control device is used to access the lock status signal, pixel clock, video timing signal and pixel data stream output by the HDMI receiving module, and output a reset control signal to the HDMI receiving module, while driving the HPD signal of the HDMI interface. The adaptive control device includes: an external interface layer, a receiving and parsing layer, a state determination layer, and a recovery and output layer; The external interface layer is configured with an HPD / EDID control module and a register configuration interface; The HPD / EDID control module provides hot-plug status and display capability information to external HDMI sources. After the system powers on, the module first detects the 5V of the HDMI interface or the cable connection status. While keeping HPD inactive, it completes the loading of EDID content and configuration of reception parameters. Once the internal resources of the FPGA are ready, it pulls the HPD level high to trigger the external video source to read the EDID through the DDC channel. Once the external video source detects that the HPD is valid, it reads the EDID through the DDC channel and outputs a video signal with the corresponding resolution according to the capabilities declared in the EDID. This prevents the video source from outputting a signal prematurely before the FPGA is ready, and also prevents the source from reading EDID information that is not yet fully prepared.

[0020] The register configuration interface provides software-configurable parameters, including EDID selection, supported resolution list, lock determination time, number of exception recovery attempts, and output protection mode. The receiving and parsing layer is configured with a data receiving module, a clock and lock monitoring module, and a video timing recognition module; The data receiving module is used to receive the lock status signal, pixel clock, video timing signal and pixel data stream output by the HDMI receiving module; The HDMI receiver module can be formed by combining a high-speed transceiver, receive control logic, and necessary protocol parsing logic within an FPGA, or it can be implemented using an equivalent receive subsystem. This invention does not limit the specific manufacturer or version, but only requires that it provide information such as lock status, pixel clock, valid video signal, and pixel data for subsequent determination.

[0021] The clock and lock monitoring module is used to determine whether the lock status signal is continuously valid within a preset time window and whether the pixel clock frequency is within a preset legal range based on the lock status signal and the pixel clock, and outputs a clock stability flag to the receiving status determination module. The clock and lock monitoring module is used to detect TMDS-related clocks, pixel clocks, and the lock status of the HDMI receive link. This module does not immediately determine successful reception upon the appearance of a lock signal. Instead, it requires the lock signal to be continuously valid within a preset time window and the pixel clock frequency to be within a preset range before outputting a stability flag to the receive status determination module.

[0022] The video timing recognition module is used to continuously count line synchronization, field synchronization, effective frame size, and frame period after the clock stabilization flag is valid. When the timing parameters of multiple consecutive frames are consistent and are within the preset supported resolution list, the timing stabilization flag is output to the receiving status determination module. The status determination layer includes a status determination receiving module; The receive status determination module is used to generate the link operating status based on the integrated clock stability flag, timing stability flag, and data validity status. The link working status includes states such as "not connected, waiting to lock, waiting for timing to stabilize, stable reception, and abnormal recovery". The explanation is as follows: (1) No connection state: When no HDMI interface 5V signal or cable access signal is detected, HPD is kept at an invalid level, the clock stability flag, timing stability flag and data validity flag are cleared, and the output protection module is kept in the state of blocking real pixel data.

[0023] (2) Waiting for lock state: After the cable is detected and the EDID content and receiving parameters are prepared, HPD is pulled high to trigger the external video source to establish a link; in this state, the lock state signal and pixel clock output by the HDMI receiving module are continuously detected. Only when the lock state signal is continuously valid within the preset lock determination time and the pixel clock frequency is within the preset legal range, a clock stability flag is generated and the system enters the waiting timing stability state.

[0024] (3) Waiting for timing stability: After the clock stability flag is valid, the line synchronization, field synchronization, effective frame width, effective frame height and frame period are counted frame by frame; when the effective frame size of N consecutive frames is consistent, the deviation of the synchronization period and frame period does not exceed the preset tolerance, and the corresponding timing is within the supported timing sequence list, a timing stability flag is generated. If the clock stability flag fails, the system returns to the waiting lock state; if the cable is unplugged, the system returns to the disconnected state.

[0025] (4) Stable reception status: When the clock stability flag, timing stability flag and data validity flag are all valid, the pixel output gate is opened and the real pixel data is allowed to pass through. At the same time, the lock status, pixel clock, video timing and data validity status are monitored.

[0026] (5) Abnormal recovery state: When any stable condition fails during stable reception, the pixel output gate is immediately turned off and output protection is entered. Then, mild, moderate or severe recovery is performed according to the duration of the abnormality, the type of abnormality and the number of recovery attempts. After mild recovery, the joint state determination is returned. After moderate recovery, the waiting timing stable state is returned. After severe recovery, the waiting lock state is returned. After multiple severe recovery failures, HPD is pulled down and the renegotiation process is returned.

[0027] The recovery and output layer is equipped with an anomaly recovery control module and an output protection module; An output protection module is configured to prevent the real pixel data stream from being transmitted when the link does not reach stable reception conditions. The output protection module is used to block the valid pixel data stream in unstable reception conditions and output a black field, fixed background color, or invalid data flag to the subsequent stage. Real pixel data is transmitted after a stable reception indication is received. The anomaly recovery control module is used to identify the link anomaly level and execute a graded recovery strategy.

[0028] The tiered recovery strategy is implemented as follows: Anomalies are categorized into mild, moderate, and severe anomalies. The following descriptions of brief synchronization jitter, prolonged data loss, prolonged lockout, and multiple moderate recovery failures are all determined by comparison with predefined threshold parameters.

[0029] Minor anomalies include invalid single-frame data or brief synchronization jitter. In these cases, only the output buffer is cleared while the receive link remains operational. Moderate anomalies include resolution switching and inconsistent timing across multiple consecutive frames. In these cases, the timing identification module and output protection module are reset, and the system waits for stable timing. Severe anomalies include prolonged pixel clock loss, prolonged receive link lockout, or multiple moderate recovery failures. In these cases, the HDMI receive link is reset.

[0030] If the severe recovery still fails, the HPD pull-down, delay, EDID loading, and HPD pull-up process is re-executed to re-establish the connection with the external source. This strategy eliminates the need to reset the entire FPGA every time an anomaly occurs, and also eliminates the need for manual intervention. For common scenarios such as plugging / unplugging, resolution switching, and brief signal instability, the system can automatically recover within a short time.

[0031] like Figure 2 The present invention also provides an FPGA-based adaptive control method for HDMI reception, comprising the following steps: S1. The FPGA powers on and completes clock, reset and register initialization. Then, it detects the HDMI cable connection status. In the HPD invalid state, it completes EDID loading and receive parameter configuration. After the internal resources of the FPGA are ready, the HPD level is pulled high to trigger the external video source to read the EDID through the DDC channel and output the TMDS video signal. S2. Receive the lock status signal, pixel clock, video timing signal and pixel data stream output by the existing HDMI receiver module, without modifying the TMDS receiving and decoding logic inside the HDMI receiver module. S3. Based on the lock status signal and the pixel clock, determine whether the lock signal is continuously effective within the preset time window and whether the pixel clock frequency is within the preset legal range, and output a clock stability flag to the receiving status determination module. During the RX lock detection phase, the lock status signal is filtered by a time window. The clock link is determined to be stable only when the lock signal is continuously valid within a preset duration and the pixel clock frequency is within the legal range. Then, a clock stability flag is output to the receiving status determination module. S4. Continuously count timing parameters including line synchronization, field synchronization, effective frame size, and frame period. When the timing parameters of multiple consecutive frames are consistent and within the preset supported timing set list, output a timing stability flag to the receiving status determination module. If the timing parameters change or are not within the supported range, it is considered that the video source is switching or the current input is not supported. The preset supported timing set includes video timing conforming to the CTA-861 standard, and VESA DMT / CVT display timing configured according to application needs; S5. Combine clock stability conditions, timing stability conditions, and data validity conditions to make a joint state decision. After entering a stable reception state, the real pixel data is released. During the unstable period, the output protection state is maintained, including configuration to output black field, gray field, fixed color image, or data invalid flag. S6. During operation, monitor link anomalies in real time. If an anomaly is detected, enter the anomaly recovery state and perform recovery processing.

[0032] If an invalid single frame of data or a brief synchronization jitter is detected, it is determined to be a minor anomaly, the output buffer is cleared and the receiving link is kept working; If a resolution switch or consecutive multi-frame timing changes are detected, it is determined to be a moderate anomaly. The video timing recognition and output protection logic is reset, and the system waits for a stable timing sequence. If a pixel clock is detected to be lost for an extended period or the receiving link is detected to be out of lock for an extended period, it is determined to be a severe anomaly, and a reset signal is output to reset the HDMI receiving link. If the recovery process fails after more than the set number of attempts, it returns to the EDID preparation state, pulls down HPD and pulls it up again after a delay, triggering the external video source to re-complete EDID negotiation and link establishment.

[0033] During a light recovery, the pixel output gating is first disabled and the video output buffer is cleared. Then, the process returns to step S5 to re-execute the joint state determination. During a medium recovery, the video timing recognition module and output protection logic are reset, the timing stability flag is cleared, and the process returns to step S4 to re-count the timing of consecutive frames. During a heavy recovery, the HDMI receive link is reset, the clock stability flag and timing stability flag are cleared, and the process returns to step S3 to re-determine the locked state and pixel clock stability. If the heavy recovery attempts reach the preset limit and recovery is still not achieved, the process returns to step S1, pulls down the HPD, and pulls it back up after a preset delay to trigger the external video source to reread the EDID and establish a link. If a cable is detected to be disconnected during any recovery stage, the process returns to the disconnected state.

[0034] State process Figure 3 As shown, this invention divides the HDMI RX reception process into states such as disconnection, EDID preparation, HPD activation, RX lock detection, timing stability determination, stable reception, anomaly recovery, and output protection. Under normal circumstances, the system enters the EDID preparation state from the disconnection state and waits for source output after HPD activation; when both RX lock and timing stability conditions are met, it enters the stable reception state. In abnormal situations, the system enters the anomaly recovery and output protection states. Minor anomalies can return to timing stability determination, while severe anomalies or multiple recovery failures return to EDID preparation and HPD renegotiation. This state process allows the recovery actions of the receive link to have clear boundaries, avoiding simply treating all anomalies as a global reset.

[0035] Such as time sequence Figure 4 As shown, this invention organizes the handshake process from the perspective of the HDMI receiver. The receiver first detects the HDMI 5V connection or cable access, and completes EDID and receive parameter preparation during the HPD invalidation period. Then, HPD is activated. After the source detects HPD validity, it reads the EDID through the DDC and starts outputting the TMDS signal and pixel clock based on the EDID. After the RX lock signal becomes valid, the system still needs to wait for the pixel clock and video timing to stabilize continuously before finally opening the output gating to allow real pixel data to be passed to the subsequent image processing module. During stages T0 to T7, the output protection module can continuously output a black screen, a fixed color, or an invalid flag, thereby preventing subsequent modules from misprocessing abnormal frames.

[0036] The lock-to-stabilization time can be set from several milliseconds to hundreds of milliseconds to filter out momentary lock-to-stabilization jitter. The number of timing-stabilized frames can be set from 2 to 8 frames to confirm that the input format has stabilized. The number of abnormal recovery attempts can be set from 1 to 5; after exceeding this number, HPD renegotiation is triggered.

[0037] This invention employs a graded anomaly recovery and output protection mechanism. In the event of a mild / moderate anomaly, local modules are recovered first. In the event of a severe anomaly, the receiving link is reset or HPD negotiation is retried, thereby shortening the recovery time, reducing the impact on other video processing modules inside the FPGA, and improving the stability of continuous system operation.

[0038] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. An adaptive control device for an HDMI receiver based on FPGA, characterized in that, include: The FPGA is equipped with an HDMI receiving module. The control device is used to access the lock status signal, pixel clock, video timing signal and pixel data stream output by the HDMI receiving module, and output a reset control signal to the HDMI receiving module, while driving the HPD signal of the HDMI interface. The adaptive control device is characterized by comprising: an external interface layer, a receiving and parsing layer, a state determination layer, and a recovery and output layer; The external interface layer is configured with an HPD / EDID control module and a register configuration interface; The HPD / EDID control module is used to provide hot-plug status and display capability information to external HDMI sources; The receiving and parsing layer is configured with a data receiving module, a clock and lock monitoring module, and a video timing recognition module; The data receiving module is used to receive the lock status signal, pixel clock, video timing signal and pixel data stream output by the HDMI receiving module; The clock and lock monitoring module is used to output a clock stability flag to the receiving status determination module when it is determined that the lock status signal is continuously valid within a preset time window and the pixel clock frequency is within a preset legal range, based on the lock status signal and the pixel clock. The video timing recognition module is used to output a timing stability flag to the receiving state determination module after the clock stability flag is valid, when the timing parameters of multiple consecutive frames are consistent and are within the preset supported timing set list; The status determination layer includes a status determination receiving module; The receive status determination module is used to generate the link working status based on the clock stability flag, timing stability flag, and data validity status. The link operating states include: not connected, waiting to lock, waiting for timing to stabilize, stable reception, and abnormal recovery. The recovery and output layer is equipped with an anomaly recovery control module and an output protection module; The output protection module is used to prevent the real pixel data stream from being transmitted when the link does not reach stable reception conditions; The anomaly recovery control module is used to identify the link anomaly level and execute recovery strategies.

2. The adaptive control device for an HDMI receiver based on FPGA according to claim 1, characterized in that, The link's operating status is generated based on the clock stability flag, timing stability flag, and data validity status. Specifically as follows: Not connected state: When no HDMI interface 5V signal or cable connection signal is detected, HPD remains at an invalid level, the clock stability flag, timing stability flag and data validity flag are cleared, and the output protection module remains in a state of blocking real pixel data; Waiting for lockout state: After detecting cable access and completing the preparation of EDID content and receive parameters, pull HPD high to trigger the external video source to establish a link; In this state, the lock status signal and pixel clock output by the HDMI receiving module are continuously monitored. Only when the lock status signal is continuously valid within the preset lock determination time and the pixel clock frequency is within the preset legal range, a clock stability flag is generated and the system enters the waiting timing stability state. Waiting for timing stability: After the clock stability flag is valid, count the line synchronization, field synchronization, effective frame width, effective frame height and frame period frame by frame; A timing stability flag is generated when the effective frame size of N consecutive frames is consistent, the deviation of the synchronization period and frame period does not exceed the preset tolerance, and the corresponding timing is within the supported timing sequence list. If the clock stability flag fails, it returns to the wait-lock state; if the cable is unplugged, it returns to the disconnected state. Stable reception status: When the clock stability flag, timing stability flag, and data validity flag are all valid, the pixel output gating is opened and real pixel data is allowed to pass through, while the lock status, pixel clock, video timing, and data validity status are continuously monitored. Abnormal recovery state: When any stable condition fails during stable reception, the pixel output gating is immediately turned off and output protection is entered. Then, mild, moderate or severe recovery is performed according to the duration, type and number of recovery attempts. After mild recovery, the system returns to the joint state determination. After moderate recovery, the system returns to the waiting timing stability state. After severe recovery, the system returns to the waiting lock state. After multiple severe recovery failures, the HPD is pulled down and the system returns to the renegotiation process.

3. The adaptive control device for an HDMI receiver based on FPGA according to claim 1, characterized in that, The register configuration interface is used to provide software-configurable parameters, including EDID selection, supported resolution list, lock determination time, number of exception recovery attempts, and output protection mode.

4. The adaptive control device for an HDMI receiver based on FPGA according to claim 1, characterized in that, The output protection module is used to block the effective pixel data stream in an unstable reception state and output a black field, fixed background color, or invalid data flag to the subsequent stage.

5. The adaptive control device for an HDMI receiver based on FPGA according to claim 1, characterized in that, In the anomaly recovery control module, the link anomaly level is identified and a graded recovery strategy is executed as follows: Mild anomalies only clear the video output buffer; moderate anomalies reset the video timing recognition module and output protection module; severe anomalies reset the HDMI receiver module via the reset control signal; in the event of multiple severe recovery failures, HPD is pulled low and then pulled back after a delay, triggering the external video source to re-execute EDID negotiation.

6. An adaptive control method for HDMI reception based on an FPGA adaptive control device according to any one of claims 1 to 5, characterized in that, Includes the following steps: S1. The FPGA powers on and completes clock, reset and register initialization. Then, it detects the HDMI cable connection status. In the HPD invalid state, it completes EDID loading and receive parameter configuration. After the internal resources of the FPGA are ready, the HPD level is pulled high to trigger the external video source to read the EDID through the DDC channel and output the TMDS video signal. S2. Receive the lock status signal, pixel clock, video timing signal and pixel data stream output by the existing HDMI receiver module, without modifying the TMDS receiving and decoding logic inside the HDMI receiver module. S3. Based on the lock status signal and the pixel clock, determine whether the lock status signal is continuously valid within the preset time window and whether the pixel clock frequency is within the preset legal range, and output a clock stability flag to the receiving status determination module. During the lock detection phase of the HDMI receiver module inside the FPGA, the lock status signal is filtered by a time window. Only when the lock signal is continuously valid within a preset duration and the pixel clock frequency is within the legal range is the clock link determined to be stable, and then a clock stability flag is output to the receiver status determination module. S4. Continuously count timing parameters including line synchronization, field synchronization, effective frame size, and frame period. When the timing parameters of multiple consecutive frames are consistent and are within the preset supported timing set list, output a timing stability flag to the receiving status determination module. If the timing parameters change or are not within the supported range, it is assumed that the video source is switching or the current input is not supported. S5. Combine clock stability conditions, timing stability conditions, and data validity conditions to make a joint state decision, and release the real pixel data after entering a stable reception state. Maintain output protection during periods of instability; S6. During operation, monitor link anomalies in real time. If an anomaly is detected, enter the anomaly recovery state and perform recovery processing.

7. The adaptive control method for HDMI reception of the FPGA adaptive control device according to claim 6, characterized in that, In step S5, the output protection status includes being configured to output black screen, gray screen, fixed color screen, or invalid data flag.

8. The adaptive control method for HDMI reception of the FPGA adaptive control device according to claim 6, characterized in that, In step S6, during the operation, link anomalies are monitored in real time, and tiered recovery processing is performed as follows: If an invalid single frame of data or a brief synchronization jitter is detected, it is determined to be a minor anomaly, the output buffer is cleared and the receiving link is kept working; If a resolution switch or consecutive multi-frame timing changes are detected, it is determined to be a moderate anomaly. The video timing recognition and output protection logic is reset, and the system waits for a stable timing sequence. If a pixel clock is detected to be lost for an extended period or the receiving link is detected to be out of lock for an extended period, it is determined to be a severe anomaly, and a reset signal is output to reset the HDMI receiving link. If the recovery process fails after more than the set number of attempts, it returns to the EDID preparation state, pulls down HPD and pulls it up again after a delay, triggering the external video source to re-complete EDID negotiation and link establishment.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 6 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 6 to 8.

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