Image sensor and vehicle

Abstract

The application discloses an image sensor and a vehicle, and belongs to the technical field of sensors. In the application, the vehicle can be configured with an intelligent driving mode. In the intelligent driving mode, relevant image data can be collected through the image sensor. The image sensor comprises a pixel circuit and a gain amplification circuit. In a signal reading stage, the pixel circuit sequentially outputs a high-gain signal and a low-gain signal under the control of a pixel control signal. Meanwhile, the gain amplification circuit is switched between a first gain mode and a second gain mode under the control of a gain switching signal, and the high-gain signal and the low-gain signal are amplified in the first gain mode, and the high-gain signal is amplified in the second gain mode. In this way, a three-gain signal output is equivalently realized, so that the dynamic range of the image sensor can be expanded without the need to additionally increase transistors to ensure a small area of the pixel circuit.

Description

Technical Field

[0001] This application relates to the field of sensor technology, and more particularly to an image sensor and a vehicle. Background Technology

[0002] In image sensors, the gain conversion transistor inside the pixel circuit is controlled by the DCG (Dual Conversion Gain) signal to achieve high-to-low gain switching, allowing readout of both high-gain and low-gain pixel signals. However, this confines the pixel signal gain conversion function to within the pixel circuit itself. Since the potential well capacity of the pixel circuit is limited by its area, this restricts the dynamic range of the image sensor. Summary of the Invention

[0003] This application provides an image sensor and a vehicle that extends the dynamic range of the image sensor, thereby at least partially solving the aforementioned technical problems.

[0004] To achieve the above objectives, according to a first aspect of this application, an image sensor is provided, comprising: The pixel circuit is used to sequentially output high-gain signals and low-gain signals according to the pixel control signals during the signal readout stage. The high-gain signals include high-gain reset signals and high-gain pixel signals, the low-gain signals include low-gain pixel signals and low-gain reset signals, and the pixel control signals include transmission control signals, gain control signals, and row selection signals. A gain amplifier circuit, connected to a pixel circuit, is used to switch between a first gain mode and a second gain mode under the control of a gain switching signal. In the first gain mode, it amplifies the high-gain signal and the low-gain signal respectively, and in the second gain mode, it amplifies the high-gain signal. The first gain of the first gain mode is less than the second gain of the second gain mode.

[0005] Secondly, a vehicle is also proposed, including the image sensor described above.

[0006] In summary, in this application, the image sensor includes a pixel circuit and a gain amplifier circuit. During the signal readout stage, the pixel circuit sequentially outputs a high-gain signal and a low-gain signal under the control of a pixel control signal. Simultaneously, the gain amplifier circuit switches between a first gain mode and a second gain mode under the control of a gain switching signal. In the first gain mode, it amplifies both the high-gain signal and the low-gain signal respectively, and in the second gain mode, it amplifies the high-gain signal. Thus, when the pixel circuit outputs signals with two gain levels, the gain amplifier circuit, located outside the pixel circuit, amplifies the low-gain signal in the first gain mode to obtain a signal with one gain level. It then amplifies the high-gain signal in both the first and second gain modes, achieving gain subdivision of the high-gain signal to obtain signals with two gain levels, effectively achieving a three-gain signal output. Therefore, the dynamic range of the image sensor can be expanded without adding additional transistors to maintain a small pixel circuit area.

[0007] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of the structure of an image sensor according to an exemplary embodiment of this application; Figure 2 This is a schematic diagram of the pixel circuit arrangement according to an exemplary embodiment of this application; Figure 3 This is another schematic diagram of the structure of an image sensor according to an exemplary embodiment of this application; Figure 4 The circuit schematics are of the pixel circuit and gain amplifier circuit of the exemplary embodiments of this application; Figure 5 This is a control timing diagram of the pixel circuit and gain amplifier circuit according to an exemplary embodiment of this application.

[0010] Explanation of icon numbers: 100. Pixel circuit; 101. Photoelectric conversion module; 102. Overflow module; 103. Signal output module; 200. Gain amplifier circuit; PPD, photoelectric conversion element; M1, transmission transistor; M2, gain control transistor; M3, first reset transistor; M4, second reset transistor; M5, follower transistor; M6, select transistor; C1, first capacitor; FD1, first floating diffusion node; FD2, second floating diffusion node; U1, operational amplifier; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; SW1, first switching device; SW2, second switching device; SW3, the third switching device; SW4, the fourth switching device.

[0011] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0013] Firstly, referring to Figure 1 This application provides an image sensor, which may include a pixel circuit 100 and a gain amplifier circuit 200. The pixel circuit 100 is used to sequentially output a high-gain signal and a low-gain signal according to a pixel control signal during the signal readout stage. The high-gain signal may include a high-gain reset signal and a high-gain pixel signal, and the low-gain signal may include a low-gain pixel signal and a low-gain reset signal. The pixel control signal may include a transmission control signal, a gain control signal, and a row selection signal. The gain amplifier circuit 200, connected to the pixel circuit 100, is used to switch between a first gain mode and a second gain mode under the control of a gain switching signal. In the first gain mode, it amplifies both the high-gain signal and the low-gain signal respectively, and in the second gain mode, it amplifies the high-gain signal. The first gain of the first gain mode is less than the second gain of the second gain mode.

[0014] It should be noted that, as Figure 2As shown, the image sensor may include multiple pixel circuits 100 arranged in a two-dimensional matrix array. Pixel circuits 100 in the same column are connected to a column line, and pixel circuits 100 in the same row are connected to a row line. Correspondingly, there are multiple gain amplifier circuits 200, with each gain amplifier circuit 200 connected to a column line. Therefore, the signal processing circuit of the image sensor can read the output signals of the pixel circuits 100 row by row and process them to obtain the corresponding image. The operating states of the pixel circuits 100 may include a high conversion gain state and a low conversion gain state. When the pixel circuit 100 operates in the high conversion gain state, it outputs a high-gain signal; when the pixel circuit 100 operates in the low conversion gain state, it outputs a low-gain signal. Thus, dual conversion gain can be achieved internally within the pixel circuit 100.

[0015] In this embodiment, the gain amplifier circuit 200 can perform gain conversion on the high-gain signal and low-gain signal output by the pixel circuit 100 in the analog domain. Specifically, when the gain amplifier circuit 200 operates in the first gain mode, it provides a relatively small analog gain to amplify the high-gain signal and the low-gain signal respectively, resulting in a high-gain signal with the first gain and a low-gain signal with the first gain. When the gain amplifier circuit 200 operates in the second gain mode, it provides a relatively large analog gain to amplify the high-gain signal, resulting in a high-gain signal with the second gain. Since the second gain is greater than the first gain, the gain of the low-gain signal is less than the gain of the high-gain signal. Thus, a high-gain signal with the second gain, a high-gain signal with the first gain, and a low-gain signal with the first gain are obtained, with the gains decreasing sequentially. Compared to performing high and low gain conversion only within the pixel circuit 100, the gain amplifier circuit 200 can split the high-gain signal into two, effectively achieving a signal output with three gain levels, which can extend the dynamic range of the single-frame image signal of the image sensor.

[0016] In some embodiments, when the pixel circuit 100 operates in a high conversion gain state, it sequentially outputs a high-gain reset signal and a high-gain pixel signal; when the pixel circuit 100 operates in a low conversion gain state, it sequentially outputs a low-gain pixel signal and a low-gain reset signal. The reset signal is the signal corresponding to the node potential of the first floating diffusion node FD1 when the pixel circuit 100 is in the reset state, and the pixel signal is the signal corresponding to the node potential after photogenerated charge is transferred to the first floating diffusion node FD1. The signal processing circuit can perform correlated double sampling (CDS) on the pixel signal read under the same conversion gain state and the same gain mode with the reset signal to eliminate reset noise and fixed pattern noise, thereby obtaining an effective image signal.

[0017] In specific implementation, for high-gain reset signals with small amplitudes, the gain amplifier circuit 200 first amplifies them in the first gain mode to obtain a high-gain reset signal with the first gain, and then switches to the second gain mode for amplification to obtain a high-gain reset signal with the second gain. For high-gain pixel signals with small amplitudes, the gain amplifier circuit 200 first amplifies them in the second gain mode to obtain a high-gain pixel signal with the second gain, and then switches to the first gain mode for amplification to obtain a high-gain pixel signal with the first gain. This ensures that the high-gain reset signal and the high-gain pixel signal ultimately obtain the same total analog gain, thereby ensuring that the high and low gain amplification factors can be completely canceled during subsequent correlation double sampling to effectively eliminate reset noise. For low-gain pixel signals and low-gain reset signals with large amplitudes, the gain amplifier circuit 200 amplifies them only in the first gain mode with smaller gain to obtain low-gain pixel signals with the first gain and low-gain reset signals with the first gain, which can avoid saturation of low-gain signals. Thus, after the above analog domain gain conversion, the six signals obtained can be sent to the analog-to-digital converter (ADC) of the signal processing circuit for quantization.

[0018] Understandably, the signal processing circuit can also select signals corresponding to three gain levels for image synthesis. For example, for pixels with low exposure, a high-gain signal amplified by the second gain mode can be used for image synthesis to ensure a good signal-to-noise ratio in dark areas; for pixels with moderate exposure, a high-gain signal amplified by the first gain mode can be used; and for pixels with high exposure, a low-gain signal amplified by the first gain mode can be used to avoid saturation in bright areas. In this way, the image sensor can obtain a high dynamic range image within a single frame without multi-frame exposure synthesis, avoiding motion artifacts and reducing reliance on high-bit-depth analog-to-digital converters, thereby reducing hardware costs.

[0019] In some of these embodiments, reference is made to Figure 3The pixel circuit 100 may include a photoelectric conversion module 101, an overflow module 102, and a signal output module 103. The photoelectric conversion module 101, connected to the first floating diffusion node FD1, is used to transfer internally stored photogenerated charge to the first floating diffusion node FD1 according to the transmission control signal TX during the signal readout phase. The overflow module 102, connected to the first floating diffusion node FD1, is used to store overflow photogenerated charge exceeding the full-well capacity of the photoelectric conversion module 101, and transfers the overflow photogenerated charge to the first floating diffusion node FD1 according to the gain control signal LFG during the signal readout phase. The signal output module 103, connected to the first floating diffusion node FD1, is used to sequentially output a high-gain reset signal, a high-gain pixel signal, a low-gain pixel signal, and a low-gain reset signal during the signal readout phase, according to the node potential of the first floating diffusion node FD1, under the timing coordination of the row selection signal RS, the transmission control signal TX, and the gain control signal LFG.

[0020] Reference Figure 5 It should be noted that in actual use, the pixel circuit 100 typically undergoes an exposure reset phase (t1-t2), an integration phase (t2-t3), and a signal readout phase (t3-t4) sequentially within each frame period. The exposure reset phase resets the photoelectric conversion module 101, the overflow module 102, and the first floating diffusion node FD1 to a known potential, clearing residual charge from the previous frame in the pixel circuit 100. The integration phase allows the photoelectric conversion module 101 to continuously collect and store photogenerated charge under illumination, while overflow charge exceeding the full-well capacity of the photoelectric conversion module 101 is stored by the overflow module 102. The signal readout phase, through the timing coordination of the row selection signal RS, the transmission control signal TX, and the gain control signal LFG, sequentially outputs the reset level and image level of the first floating diffusion node FD1 under different conversion gain states. This collectively ensures that the pixel circuit 100 can completely output a high-gain reset signal, a high-gain pixel signal, a low-gain pixel signal, and a low-gain reset signal within a single exposure.

[0021] In this embodiment, when the gain control signal LFG controls the overflow module 102 to disconnect from the first floating diffusion node FD1, and the transmission control signal TX controls the photoelectric conversion module 101 to disconnect from the first floating diffusion node FD1, the total capacitance of the first floating diffusion node FD1 is its own capacitance, the pixel circuit 100 operates in a high conversion gain state, the first floating diffusion node FD1 only has a reset level, and outputs a high-gain reset signal; when the gain control signal LFG controls the overflow module 102 to disconnect from the first floating diffusion node FD1, and the transmission control signal TX controls the photoelectric conversion module 101 to conduct from the first floating diffusion node FD1, the total capacitance of the first floating diffusion node FD1 is its own capacitance, the pixel circuit 100 operates in a high conversion gain state, the photoelectric conversion module 101 transfers its internal photogenerated charge to the first floating diffusion node FD1, and the pixel circuit 100 outputs a high-gain pixel signal; when the gain control signal LFG controls the overflow module 102 to disconnect from the first floating diffusion node FD1 ... pixel circuit 100 outputs a high-gain pixel signal; when the gain control signal LFG controls the overflow module 102 to disconnect from the first floating diffusion node FD1, the pixel circuit 100 operates in a high conversion gain state, the pixel circuit 100 outputs a high-gain pixel signal; when the gain control signal LFG controls the overflow module 102 to disconnect from the first floating diffusion node FD1, the pixel circuit 100 operates in a high conversion gain state, the pixel circuit 100 output When the dynamic diffusion nodes FD1 are connected, and the transmission control signal TX controls the photoelectric conversion module 101 to conduct with the first floating diffusion node FD1, the overflow module 102 is connected with the first floating diffusion node FD1, effectively increasing the total capacitance of the first floating diffusion node FD1. The pixel circuit 100 operates in a low conversion gain state, and the photoelectric conversion module 101 transfers the photogenerated charge stored internally to the first floating diffusion node FD1, causing the pixel circuit 100 to output a low-gain pixel signal. When the gain control signal LFG controls the overflow module 102 to conduct with the first floating diffusion node FD1, and the transmission control signal TX controls the photoelectric conversion module 101 to disconnect with the first floating diffusion node FD1, the overflow module 102 is connected with the first floating diffusion node FD1, effectively increasing the total capacitance of the first floating diffusion node FD1. The pixel circuit 100 operates in a low conversion gain state, the first floating diffusion node FD1 only has a reset level, and the pixel circuit 100 outputs a low-gain reset signal. The signal output module 103 is connected to the first floating diffusion node FD1. Under the gating control of the line selection signal RS, and in coordination with the timing of the transmission control signal TX and the gain control signal LFG, the node potential of the first floating diffusion node FD1 is read out in the order of high-gain reset signal, high-gain image signal, low-gain image signal, and low-gain reset signal to the subsequent gain amplifier circuit 200. This completes the output of high and low gain signals within a single exposure, laying the signal foundation for the gain conversion and dynamic range expansion of the subsequent gain amplifier circuit 200 in the analog domain.

[0022] In some specific embodiments, reference is made to Figure 5The signal readout phase includes a first sub-phase (Phase 1) and a second sub-phase (Phase 2) for reading out the high-gain reset signal, a third sub-phase (Phase 3) and a fourth sub-phase (Phase 4) for reading out the high-gain pixel signal, a fifth sub-phase (Phase 5) for reading out the low-gain pixel signal, and a sixth sub-phase (Phase 6) for reading out the low-gain reset signal. (Refer to...) Figure 4 The photoelectric conversion module 101 includes a photoelectric conversion element PPD and a transmission transistor M1. The photoelectric conversion element PPD includes a first electrode grounded and a second electrode connected to the transmission transistor M1. The transmission transistor M1 includes a first electrode connected to the photoelectric conversion element PPD, a second electrode connected to a first floating diffusion node FD1, and a control electrode for receiving the transmission control signal TX. (Refer to...) Figure 5 In the first sub-stage (Phase 1), the second sub-stage (Phase 2), and the sixth sub-stage (Phase 6), the transmission transistor M1 is turned off under the control of the transmission control signal TX, disconnecting the photoelectric conversion element PPD from the first floating diffusion node FD1. In the third sub-stage (Phase 3), the fourth sub-stage (Phase 4), and the fifth sub-stage (Phase 5), the transmission transistor M1 is turned on under the control of the transmission control signal TX, transferring the photogenerated charge stored in the photoelectric conversion element PPD to the first floating diffusion node FD1.

[0023] In this embodiment, the photoelectric conversion element PPD can be a photodiode, used to convert incident light into photogenerated charge and store it in its potential well. (Refer to...) Figure 5 During the exposure reset phase, the transfer transistor M1 is turned on under the control of the transfer control signal TX, which can clear the residual charge of the photoelectric conversion element PPD from the previous frame. During the integration phase, the transfer transistor M1 is turned off under the control of the transfer control signal TX, so that the photoelectric conversion element PPD continues to collect and store photogenerated charge. During the signal readout stage: In the first sub-stage (Phase 1), the second sub-stage (Phase 2), and the sixth sub-stage (Phase 6), the transmission transistor M1 is turned off under the control of the transmission control signal TX, disconnecting the photoelectric conversion element PPD from the first floating diffusion node FD1, so that the first floating diffusion node FD1 is only at a reset level, causing the subsequent signal output circuit to output the corresponding reset signal according to the reset level of the first floating diffusion node FD1; In the third sub-stage (Phase 3), the fourth sub-stage (Phase 4), and the fifth sub-stage (Phase 5), the transmission transistor M1 is turned on under the control of the transmission control signal TX, transferring the photogenerated charge stored in the photoelectric conversion element PPD to the first floating diffusion node FD1, so that the node potential of the first floating diffusion node FD1 changes with the amount of photogenerated charge, causing the subsequent signal output circuit to output the corresponding pixel signal.

[0024] In some specific embodiments, the overflow module 102 may include a gain control transistor M2 and a first capacitor C1. (Refer to...) Figure 4 The gain control transistor M2 includes a first electrode connected to the first floating diffusion node FD1, a second electrode connected to the second floating diffusion node FD2, and a control electrode to which the gain control signal LFG is applied. The first capacitor C1 includes a first electrode connected to the second floating diffusion node FD2 and a second electrode to which a bias voltage is applied. (Refer to...) Figure 5 In the first sub-stage (Phase 1), second sub-stage (Phase 2), third sub-stage (Phase 3), and fourth sub-stage (Phase 4), the gain control transistor M2 is turned off under the control of the gain control signal LFG, causing the signal output module 103 to output a high-gain reset signal according to the node potential in the first and second sub-stages (Phase 1 and Phase 2), and a high-gain pixel signal according to the node potential in the third and fourth sub-stages (Phase 3 and Phase 4). In the fifth and sixth sub-stages (Phase 5 and Phase 6), the gain control transistor M2 is turned on under the control of the gain control signal LFG, transferring the overflowed photogenerated charge to the first floating diffusion node FD1, causing the signal output module 103 to output a low-gain pixel signal according to the node potential in the fifth sub-stage (Phase 5) and a low-gain reset signal in the sixth sub-stage (Phase 6).

[0025] In this embodiment, the first capacitor C1 is a LOFIC (Lateral Overflow Integration Capacitor), with its right plate connected to the gain control transistor M2 via the second floating diffusion node FD2, and its left plate connected to a bias voltage. Specifically, during the exposure reset phase, the gain control transistor M2 is turned on under the control of the gain control signal LFG, clearing the residual charge on the first capacitor C1 from the previous frame. During the integration phase, the gain control transistor M2 is turned off under the control of the gain control signal LFG, allowing the first capacitor C1 to collect and store the overflow photogenerated charge. During the signal readout phase: In the first sub-phase (Phase 1) and the second sub-phase (Phase 2), the gain control transistor M2 is turned off under the control of the gain control signal LFG. The first capacitor C1 is disconnected from the first floating diffusion node FD1, which maintains a small equivalent capacitance and a high conversion gain, causing the pixel circuit 100 to operate in a high conversion gain state. If the transmission transistor M1 is turned off at this time, the first floating diffusion node FD1 only has a reset level, and the signal output module 103 outputs a high-gain reset signal accordingly. Similarly, in the third sub-phase (Phase 3) and the fourth sub-phase (Phase 4), the gain control transistor M2 is turned off under the control of the gain control signal LFG, causing the pixel circuit 100 to operate in a high conversion gain state. If the transmission transistor M1 is turned on at this time, the first floating diffusion node FD1 has photogenerated charge. The signal output module 103 outputs a high-gain pixel signal accordingly. In the fifth sub-stage (Phase 5) and the sixth sub-stage (Phase 6), the gain control transistor M2 is turned on under the control of the gain control signal LFG, and the first capacitor C1 (and the overflow photogenerated charge) is connected to the first floating diffusion node FD1, which increases the equivalent capacitance of the first floating diffusion node FD1 and reduces the conversion gain, so that the pixel circuit 100 operates in a low conversion gain state. In the fifth sub-stage (Phase 5), the transmission transistor M1 is turned on, and the charge on the first floating diffusion node FD1 is the superposition of photogenerated charge and overflow photogenerated charge, so that the signal output module 103 outputs a low-gain pixel signal accordingly. In the sixth sub-stage (Phase 6), the transmission transistor M1 is turned off, and the first floating diffusion node FD1 is at a reset level, so that the signal output module 103 outputs a low-gain reset signal accordingly. Thus, by turning the gain control transistor M2 on and off, it is possible to control whether the first floating diffusion node FD1 is connected to the LOFIC capacitor, thereby enabling the switchable readout of the high conversion gain state and the low conversion gain state of the pixel circuit 100. In conjunction with turning the transmission transistor M1 on and off, a high-gain reset signal, a high-gain pixel signal, a low-gain pixel signal, and a low-gain reset signal can be output sequentially.

[0026] In addition, such as Figure 5As shown, before the first sub-stage Phase 1 of the signal readout stage, the gain control transistor M2 can also be briefly turned on under the control of the gain control signal LFG to pull the potentials of the first floating diffusion node FD1 and the second floating diffusion node FD2 to the same initial level, creating a stable and linear starting condition for subsequent signal readout, and realizing soft switching protection during the dual conversion gain switching process inside the pixel circuit 100.

[0027] In some specific embodiments, the overflow module 102 may further include a first reset transistor M3 and a second reset transistor M4. (Refer to...) Figure 4 The first reset transistor M3 includes a first electrode connected to the second floating diffusion node FD2, a second electrode connected to the power supply voltage VDDA, and a control electrode connected to the first reset control signal RSTA. The second reset transistor M4 includes a first electrode connected to the second terminal of the first capacitor C1, a second electrode connected to the power supply voltage VDDA, and a control electrode connected to the second reset control signal RSTB. (Refer to...) Figure 5 In the exposure reset stage before the sixth sub-stage (Phase 6) and the signal readout stage, the first reset transistor M3 is turned on under the control of the first reset control signal RSTA, and the second reset transistor M4 is turned on under the control of the second reset control signal RSTB to reset the charge in the first capacitor C1. In the other sub-stages of the signal readout stage besides the sixth sub-stage (Phase 6), the first reset transistor M3 is turned off under the control of the first reset control signal RSTA, and the second reset transistor M4 is turned off under the control of the second reset control signal RSTB to avoid the reset operation interfering with normal readout.

[0028] In this embodiment, a first reset transistor M3 and a second reset transistor M4 can also be set in the overflow module 102 to reset the two ends of the first capacitor C1, so that the charge on the left and right plates of the LOFIC capacitor and the second floating diffusion stage is cleared, preparing for the storage of overflow charge in the integration stage; at the same time, at the beginning of the sixth sub-stage Phase 6, the two reset transistors are turned on again under the control of the reset signal, and the first floating diffusion node FD1 is reset together through the turned-on gain control transistor M2, so that the first floating diffusion node FD1 is only at the reset level, so that the sixth sub-stage Phase 6 can read out the low gain reset signal.

[0029] In some specific embodiments, the overflow module 102 may further include a first switching device SW1. (Refer to...) Figure 4 The first switching device SW1 includes a first electrode connected to the second terminal of the first capacitor C1, a second electrode connected to a bias voltage, and a control electrode connected to an isolation control signal VCAP. (Refer to...) Figure 4During the exposure reset stage and the sixth sub-stage (Phase 6), the first switching device SW1 is turned off under the control of the isolation control signal VCAP, isolating the bias voltage from the power supply voltage VDDA. During the signal readout stage, in other sub-stages besides the sixth sub-stage (Phase 6), the first switching device SW1 is turned on under the control of the isolation control signal VCAP, causing the gain control transistor M2 to transfer the reset charge stored in the first capacitor and the overflow photogenerated charge to the first floating diffusion node FD1, respectively.

[0030] In this embodiment, the bias voltage is supplied to the second terminal of the first capacitor C1 via the first switching device SW1. During the exposure reset stage and the sixth sub-stage (Phase 6), the bias voltage is isolated from the power supply voltage VDDA by the first switching device SW1, which can prevent the bias voltage from short-circuiting with the power supply voltage VDDA when the reset transistor is turned on, thus affecting the safety of the pixel circuit 100. In the signal readout stage, in other sub-stages besides the sixth sub-stage (Phase 6), the bias voltage is supplied to the first capacitor C1 via the first switching device SW1, which can ensure that the pixel circuit 100 outputs signals normally. This can improve the safety and stability of the pixel circuit 100.

[0031] In some specific embodiments, the signal output module 103 includes a follower transistor M5 and a select transistor M6. (Refer to...) Figure 4 The follower transistor M5 includes a first electrode connected to the power supply voltage VDDA, a second electrode connected to the select transistor M6, and a control electrode connected to the first floating diffusion node FD1. The select transistor M6 includes a first electrode connected to the follower transistor M5, a second electrode connected to the gain amplifier circuit 200, and a control electrode connected to the row selection signal RS. (Refer to...) Figure 4 During the signal readout stage, the follower transistor M5 outputs an analog voltage signal corresponding to the node potential to the select transistor M6. The select transistor M6 is turned on under the control of the row selection signal RS, and sequentially outputs a high-gain reset signal, a high-gain pixel signal, a low-gain pixel signal, and a low-gain reset signal according to the analog voltage signal. Thus, the pixel circuit 100 transmits the node potentials under different conversion gain states losslessly to the subsequent gain amplifier circuit 200 in a source-follower manner.

[0032] In this embodiment, the follower transistor M5 operates in a source-follower mode. Its control electrode senses the node potential of the first floating diffusion node FD1 and outputs an analog voltage signal corresponding to the node potential. In the multiple pixel circuits 100 in the same column, the second electrode of each selection transistor M6 is connected to the same column line. The row selection signal RS of each row pixel circuit 100 is time-divisionally effective, so that only the selection transistor M6 of one row pixel circuit 100 is turned on at any given time. Thus, multiple rows of pixel circuits 100 can time-division multiplex the same column line for signal readout, saving hardware resources of the column line and gain amplifier circuit 200, which helps to reduce the cost of the image sensor.

[0033] As an example, refer to Figure 4 The gain amplifier circuit 200 may include an operational amplifier U1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a second switching device SW2, and a third switching device SW3. (Refer to...) Figure 3 Operational amplifier U1 includes an inverting input terminal connected to the first electrode of a second capacitor C2, a non-inverting input terminal connected to a reference voltage, and an output terminal. The second capacitor C2 also includes a second electrode connected to pixel circuit 100. A third capacitor C3 is connected between the inverting input terminal and the output terminal. A fourth capacitor C4 includes a first electrode connected to the first electrode of a second switching device SW2 and a second electrode connected to the first electrode of a third switching device SW3. The second switching device SW2 also includes a second electrode connected to the inverting input terminal and a control electrode connected to the gain switching signal. The third switching device SW3 also includes a second electrode connected to the output terminal and a control electrode for the gain switching signal. (Refer to...) Figure 5 The second switching device SW2 and the third switching device SW3 are turned on under the control of the gain switching signal SW_PGA_GAIN, so that the gain amplifier circuit 200 operates in the first gain mode. The second switching device SW2 and the third switching device SW3 are turned off under the control of the gain switching signal SW_PGA_GAIN, so that the gain amplifier circuit 200 operates in the second gain mode.

[0034] In this embodiment, the second capacitor C2 is a sampling capacitor, and its second terminal receives the output signal of the pixel circuit 100 via the column line; the third capacitor C3 is a bridging capacitor connected between the inverting input and output terminals of the operational amplifier U1, determining the basic amplification gain of the second gain mode; the fourth capacitor C4, together with the second switching device SW2 and the third switching device SW3, constitutes the gain switching branch. When the second switching device SW2 and the third switching device SW3 are off, the equivalent bridging capacitor is the third capacitor C3, and the second gain of the second gain mode is G2 = c1 / c3; when the second switching device SW2 and the third switching device SW3 are on, the equivalent bridging capacitor is the parallel connection of the third capacitor C3 and the fourth capacitor C4 (c3∥c4), and the first gain of the first gain mode is G1 = c1 / (c3∥c4). Since c3∥c4 is greater than c3, the first gain G1 is less than the second gain G2, which can realize the hierarchical (secondary) analog amplification of high-gain signals. Wherein, c1 is the capacitance value of the first capacitor C1, c2 is the capacitance value of the second capacitor C2, c3 is the capacitance value of the third capacitor C3, and c4 is the capacitance value of the fourth capacitor C4. The values ​​of each capacitor can be calibrated through circuit simulation based on the target gain and linearity, and this application does not impose any limitations on this.

[0035] Reference Figure 4 and Figure 5In the specific implementation, in the first sub-stage (Phase 1), the pixel circuit 100 outputs a high-gain reset signal, and the second switching device SW2 and the third switching device SW3 are turned on under the control of the gain switching signal SW_PGA_GAIN, causing the gain amplifier circuit 200 to operate in the first gain mode, amplifying the high-gain reset signal to obtain a high-gain reset signal with the first gain. In the second sub-stage (Phase 2), the pixel circuit 100 outputs a high-gain reset signal, and the second switching device SW2 and the third switching device SW3 are turned off under the control of the gain switching signal SW_PGA_GAIN, causing the gain amplifier circuit 200 to operate in the second gain mode, amplifying the high-gain reset signal to obtain a high-gain reset signal with the second gain. In the third sub-stage (Phase 3), the pixel circuit 100 outputs a high-gain pixel signal, and the second switching device SW2 and the third switching device SW3 are turned off under the control of the gain switching signal SW_PGA_GAIN, causing the gain amplifier circuit 200 to operate in the second gain mode, amplifying the high-gain pixel signal to obtain a high-gain pixel signal with the second gain. In the fourth sub-stage (Phase 4), the pixel circuit 100 outputs a high-gain pixel signal. The second switch SW2 and the third switch SW3 are turned on under the control of the gain switching signal SW_PGA_GAIN, causing the gain amplifier circuit 200 to operate in the first gain mode, amplifying the high-gain pixel signal to obtain a high-gain pixel signal with the first gain. In the fifth sub-stage (Phase 5), the pixel circuit 100 outputs a low-gain pixel signal. The second switch SW2 and the third switch SW3 are turned on under the control of the gain switching signal SW_PGA_GAIN, causing the gain amplifier circuit 200 to operate in the first gain mode, amplifying the low-gain pixel signal to obtain a low-gain pixel signal with the first gain. In the sixth sub-stage (Phase 6), the pixel circuit 100 outputs a low-gain reset signal. The second switch SW2 and the third switch SW3 are turned on under the control of the gain switching signal SW_PGA_GAIN, causing the gain amplifier circuit 200 to operate in the first gain mode, amplifying the low-gain reset signal to obtain a low-gain reset signal with the first gain.

[0036] In some specific embodiments, the gain amplifier circuit 200 further includes a fourth switching device SW4. The fourth switching device SW4 includes a first electrode connected to the inverting input terminal, a second electrode connected to the output terminal, and a control electrode connected to a third reset control signal RST_PGA, so that it is turned on under the control of the third reset control signal RST_PGA to reset the operational amplifier U1.

[0037] In this embodiment, as Figure 4As shown, the reset signal interval can be read out in the first sub-stage Phase 1, the second sub-stage Phase 2, and the sixth sub-stage Phase 6, and the fourth switching device SW4 can be turned on to make the inverting input terminal and the output terminal of the operational amplifier U1 at the same potential, thereby discharging the residual charge on the bridging capacitor and completing the reset of the gain amplifier circuit 200.

[0038] In some specific embodiments, the reference voltage includes a first reference voltage and a second reference voltage, and the image sensor may further include a reference voltage circuit. This reference voltage circuit, connected to the non-inverting input, is used to: provide a first reference voltage to the non-inverting input in Phase 5 and Phase 6, and provide a second reference voltage to the non-inverting input in other sub-phases besides Phase 5 and Phase 6. The first reference voltage is greater than the second reference voltage.

[0039] In this embodiment, the reference voltage VCM connected to the non-inverting input can be configured to different levels in different sub-stages. Specifically, in the fifth sub-stage (Phase 5) and the sixth sub-stage (Phase 6) where the low-gain signal is read out, a larger first reference voltage is configured to ensure that the operational amplifier U1 operates normally under a larger input common-mode, which can adapt to the larger node potential swing under the low conversion gain state. In the remaining sub-stages, a smaller second reference voltage is configured to adapt to the smaller node potential swing under the high conversion gain state. In this way, by providing two reference voltages in a time-division manner through the reference voltage circuit, it can be ensured that the gain amplifier circuit 200 is in the linear amplification region in all sub-stages of the full range, thereby avoiding low-gain signal drift.

[0040] Reference Figure 4 The complete signal readout process of an image sensor is described exemplarily. Specifically, during the exposure reset stage, the first reset transistor M3 is turned on under the control of the first reset control signal RSTA, and the second reset transistor M4 is turned on under the control of the second reset control signal RSTB, clearing the charge on the left and right plates of the first capacitor C1, the second floating diffusion node FD2, and the first floating diffusion node FD1, thereby resetting the pixel circuit 100. Simultaneously, the first switching device SW1 is turned off under the control of the isolation control signal VCAP, isolating the bias voltage from the power supply voltage VDDA and preventing a short circuit between the bias voltage and the power supply voltage VDDA. During the integration stage after the exposure reset is completed, the photoelectric conversion element PPD accumulates photogenerated charge in the pixel, and after the charge integration is completed, the signal readout stage begins.

[0041] The signal readout phase includes the first sub-phase Phase 1 and the second sub-phase Phase 2 for reading out the high-gain reset signal, the third sub-phase Phase 3 and the fourth sub-phase Phase 4 for reading out the high-gain pixel signal, the fifth sub-phase Phase 5 for reading out the low-gain pixel signal, and the sixth sub-phase Phase 6 for reading out the low-gain reset signal.

[0042] During the signal readout stage, the row selection signal RS changes from low level to high level, turning on the selection transistor M6 and starting the readout process.

[0043] Before the first sub-stage Phase 1, the gain control signal LFG first outputs a high-level pulse to control the gain control transistor M2 to turn on. In conjunction with the bias voltage, the reset charge on the first capacitor C1 in the reset state is transferred to the second floating diffusion node FD2 and the first floating diffusion node FD1 in sequence.

[0044] In the first sub-stage (Phase 1) and the second sub-stage (Phase 2), the first switching device SW1 is turned on under the control of the isolation control signal VCAP, the transmission transistor M1 is turned off under the control of the transmission control signal TX, and the gain control transistor M2 is turned off under the control of the gain control signal LFG, setting the first floating diffusion node FD1 to a reset level. The selection transistor M6 is turned on under the control of the row selection signal RS, outputting a high-gain reset signal. Simultaneously, in the first sub-stage (Phase 1), the fourth switching device SW4 is turned on under the control of the third reset control signal RST_PGA, affecting the operational amplifier... When U1 is reset, the second switching device SW2 and the third switching device SW3 are turned on under the control of the gain switching signal SW_PGA_GAIN, so that the gain amplifier circuit 200 operates in the first gain mode, amplifying the high-gain reset signal to obtain the first-gain high-gain reset signal; in the second sub-stage Phase 2, the second switching device SW2 and the third switching device SW3 are turned off under the control of the gain switching signal SW_PGA_GAIN, so that the gain amplifier circuit 200 operates in the second gain mode, amplifying the high-gain reset signal to obtain the second-gain high-gain reset signal.

[0045] In the third sub-stage (Phase 3) and the fourth sub-stage (Phase 4), the first switching device SW1 is turned on under the control of the isolation control signal VCAP, the transmission transistor M1 is turned on under the control of the transmission control signal TX, and the gain control transistor M2 is turned off under the control of the gain control signal LFG, making the first floating diffusion node FD1 reach the image level. The selection transistor M6 is turned on under the control of the row selection signal RS, outputting a high-gain pixel signal. Simultaneously, in the third sub-stage (Phase 3), the fourth switching device SW4 is turned off under the control of the third reset control signal RST_PGA, and the second switching devices SW2 and SW3 are turned off under the control of the gain switching signal SW_PGA_GAIN, causing the gain amplifier circuit 200 to operate in the second gain mode, amplifying the high-gain pixel signal to obtain a high-gain pixel signal with the second gain. In the fourth sub-stage (Phase 4), the second switching devices SW2 and SW3 are turned on under the control of the gain switching signal SW_PGA_GAIN, causing the gain amplifier circuit 200 to operate in the first gain mode, amplifying the high-gain pixel signal to obtain a high-gain pixel signal with the first gain.

[0046] In the fifth sub-stage (Phase 5), the first switching device SW1 is turned on under the control of the isolation control signal VCAP, the transmission transistor M1 is turned on under the control of the transmission control signal TX, and the gain control transistor M2 is turned on under the control of the gain control signal LFG, making the first floating diffusion node FD1 the image level with a LOFIC capacitor. The selection transistor M6 is turned on under the control of the row selection signal RS, outputting a low-gain pixel signal. The fourth switching device SW4 is turned off under the control of the third reset control signal RST_PGA, and the second switching device SW2 and the third switching device SW3 are turned on under the control of the gain switching signal SW_PGA_GAIN, making the gain amplifier circuit 200 work in the first gain mode, amplifying the low-gain pixel signal to obtain the first gain low-gain pixel signal.

[0047] In Phase 6, firstly, the first reset transistor M3 is turned on under the control of the first reset control signal RSTA, the second reset transistor M4 is turned on under the control of the second reset control signal RSTB, the gain control transistor M2 is turned on under the control of the gain control signal LFG, and the first switching device SW1 is turned off under the control of the isolation control signal VCAP, resetting the first capacitor C1 and the first floating diffusion node FD1; then, the first switching device SW1 is turned on under the control of the isolation control signal VCAP, the transmission transistor M1 is turned off under the control of the transmission control signal TX, and the gain control transistor M2 is turned off under the control of the transmission control signal TX. The gain control transistor M2 is turned on under the control of the gain control signal LFG, making the first floating diffusion node FD1 a reset level with a LOFIC capacitor. The selection transistor M6 is turned on under the control of the row selection signal RS, outputting a low-gain reset signal. The fourth switching device SW4 is turned on under the control of the third reset control signal RST_PGA. The second switching device SW2 and the third switching device SW3 are turned on under the control of the gain switching signal SW_PGA_GAIN, making the gain amplifier circuit 200 work in the first gain mode, amplifying the low-gain reset signal to obtain the first gain low-gain reset signal.

[0048] Secondly, this application also proposes a vehicle that includes an image sensor as described in any of the above embodiments. The specific structure of the image sensor is as described in the above embodiments. Since this vehicle adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0049] In this embodiment, the vehicle can be a plug-in hybrid electric vehicle or a new energy vehicle, etc., and this disclosure does not specifically limit it. The vehicle can be configured with an intelligent driving mode, in which relevant image data can be collected through an image sensor.

[0050] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an apparatus or system comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an apparatus or system. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the apparatus or system that includes that element.

[0051] In the description of this application, unless otherwise expressly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0052] In the description of this application, the use of terms such as "first," "second," etc., is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Furthermore, "multiple" means two or more, unless otherwise explicitly defined.

[0053] In the description of this application, the suffixes such as "module," "part," or "unit" used to denote elements are merely for the purpose of illustration and have no specific meaning in themselves. Therefore, "module," "part," or "unit" can be used interchangeably. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0054] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0055] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0056] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An image sensor, characterized in that, include: A pixel circuit is used to sequentially output a high-gain signal and a low-gain signal according to a pixel control signal during the signal readout stage; the high-gain signal includes a high-gain reset signal and a high-gain pixel signal, the low-gain signal includes a low-gain pixel signal and a low-gain reset signal, and the pixel control signal includes a transmission control signal, a gain control signal, and a row selection signal; A gain amplifier circuit, connected to the pixel circuit, is used to switch between a first gain mode and a second gain mode under the control of a gain switching signal, and to amplify the high-gain signal and the low-gain signal respectively in the first gain mode, and to amplify the high-gain signal in the second gain mode; wherein, the first gain of the first gain mode is less than the second gain of the second gain mode.

2. The image sensor according to claim 1, characterized in that, The pixel circuit includes: A photoelectric conversion module, connected to a first floating diffusion node, is used to transfer the internally stored photogenerated charge to the first floating diffusion node according to the transmission control signal during the signal readout stage. An overflow module, connected to the first floating diffusion node, is used to store overflow photogenerated charge exceeding the full-well capacity of the photoelectric conversion module, and to transfer the overflow photogenerated charge to the first floating diffusion node according to the gain control signal during the signal readout stage. The signal output module, connected to the first floating diffusion node, is used to sequentially output the high-gain reset signal, the high-gain pixel signal, the low-gain pixel signal, and the low-gain reset signal during the signal readout phase according to the node potential of the first floating diffusion node, under the timing coordination of the row selection signal, the transmission control signal, and the gain control signal.

3. The image sensor according to claim 2, characterized in that, The signal readout stage includes a first sub-stage and a second sub-stage for reading out the high-gain reset signal, a third sub-stage and a fourth sub-stage for reading out the high-gain pixel signal, a fifth sub-stage for reading out the low-gain pixel signal, and a sixth sub-stage for reading out the low-gain reset signal. The photoelectric conversion module includes a photoelectric conversion element and a transmission transistor; The photoelectric conversion element includes a grounded first electrode and a second electrode connected to the transmission transistor; The transmission transistor includes a first electrode connected to the photoelectric conversion element, a second electrode connected to the first floating diffusion node, and a control electrode that receives the transmission control signal; In the first sub-stage, the second sub-stage, and the sixth sub-stage, the transmission transistor is turned off under the control of the transmission control signal, disconnecting the photoelectric conversion element from the first floating diffusion node. In the third, fourth, and fifth sub-stages, the transmission transistor is turned on under the control of the transmission control signal, transferring the photogenerated charge stored in the photoelectric conversion element to the first floating diffusion node.

4. The image sensor according to claim 3, characterized in that, The overflow module includes a gain control transistor and a first capacitor; The gain control transistor includes a first electrode connected to the first floating diffusion node, a second electrode connected to the second floating diffusion node, and a control electrode that receives the gain control signal. The first capacitor includes a first terminal connected to the second floating diffusion node and a second terminal connected to a bias voltage; In the first sub-stage, the second sub-stage, the third sub-stage, and the fourth sub-stage, the gain control transistor is turned off under the control of the gain control signal, so that the signal output module outputs the high-gain reset signal according to the node potential in the first sub-stage and the second sub-stage, and outputs the high-gain pixel signal according to the node potential in the third sub-stage and the fourth sub-stage. In the fifth and sixth sub-stages, the gain control transistor is turned on under the control of the gain control signal, transferring the overflow photogenerated charge to the first floating diffusion node, so that the signal output module outputs the low-gain pixel signal in the fifth sub-stage and the low-gain reset signal in the sixth sub-stage according to the node potential.

5. The image sensor according to claim 4, characterized in that, The overflow module further includes a first reset transistor and a second reset transistor; The first reset transistor includes a first electrode connected to the second floating diffusion node, a second electrode connected to a power supply voltage, and a control electrode connected to a first reset control signal; The second reset transistor includes a first electrode connected to the second terminal of the first capacitor, a second electrode connected to the power supply voltage, and a control electrode connected to the second reset control signal; In the exposure reset stage prior to the sixth sub-stage and the signal readout stage, the first reset transistor is turned on under the control of the first reset control signal, and the second reset transistor is turned on under the control of the second reset control signal to reset the charge in the first capacitor. In other sub-stages of the signal readout stage besides the sixth sub-stage, the first reset transistor is turned off under the control of the first reset control signal, and the second reset transistor is turned off under the control of the second reset control signal.

6. The image sensor according to claim 5, characterized in that, The overflow module also includes a first switching device; The first switching device includes a first electrode connected to the second terminal of the first capacitor, a second electrode connected to the bias voltage, and a control electrode connected to the isolation control signal; In the exposure reset stage and the sixth sub-stage, the first switching device is turned off under the control of the isolation control signal to isolate the bias voltage from the power supply voltage. In the signal readout stage, in other sub-stages besides the sixth sub-stage, the first switching device is turned on under the control of the isolation control signal to transfer the reset charge stored in the first capacitor and the overflow photogenerated charge to the first floating diffusion node, respectively.

7. The image sensor according to claim 2, characterized in that, The signal output module includes a follower transistor and a selection transistor; The follower transistor includes a first electrode connected to a power supply voltage, a second electrode connected to the select transistor, and a control electrode connected to the first floating diffusion node; The selection transistor includes a first electrode connected to the follower transistor, a second electrode connected to the gain amplifier circuit, and a control electrode connected to the row selection signal; During the signal readout phase, the follower transistor outputs an analog voltage signal corresponding to the node potential to the selection transistor. The selection transistor is turned on under the control of the row selection signal and sequentially outputs the high-gain reset signal, the high-gain pixel signal, the low-gain pixel signal, and the low-gain reset signal according to the analog voltage signal.

8. The image sensor according to claim 1, characterized in that, The gain amplifier circuit includes an operational amplifier, a second capacitor, a third capacitor, a fourth capacitor, a second switching device, and a third switching device. The operational amplifier includes an inverting input terminal connected to the first pole of the second capacitor, a non-inverting input terminal connected to a reference voltage, and an output terminal; The second capacitor also includes a second electrode connected to the pixel circuit; The third capacitor is connected between the inverting input terminal and the output terminal; The fourth capacitor includes a first electrode connected to the first electrode of the second switching device and a second electrode connected to the first electrode of the third switching device; The second switching device further includes a second electrode connected to the inverting input terminal and a control electrode connected to the gain switching signal; The third switching device further includes a second electrode connected to the output terminal, and a control electrode connected to the gain switching signal; Wherein, the second switching device and the third switching device are turned on under the control of the gain switching signal, so that the gain amplifier circuit operates in the first gain mode; the second switching device and the third switching device are turned off under the control of the gain switching signal, so that the gain amplifier circuit operates in the second gain mode. The gain amplifier circuit also includes a fourth switching device; The fourth switching device includes a first electrode connected to the inverting input terminal, a second electrode connected to the output terminal, and a control electrode connected to a third reset control signal, so as to conduct under the control of the third reset control signal to reset the operational amplifier.

9. The image sensor according to claim 8, characterized in that, The reference voltage includes a first reference voltage and a second reference voltage. The signal readout stage includes a first sub-stage and a second sub-stage for reading out the high-gain reset signal, a third sub-stage and a fourth sub-stage for reading out the high-gain pixel signal, a fifth sub-stage for reading out the low-gain pixel signal, and a sixth sub-stage for reading out the low-gain reset signal. The image sensor also includes: A reference voltage circuit, connected to the non-inverting input terminal, is used for: In the fifth and sixth sub-stages, the first reference voltage is provided to the non-inverting input terminal; in other sub-stages besides the fifth and sixth sub-stages, the second reference voltage is provided to the non-inverting input terminal; wherein the first reference voltage is greater than the second reference voltage.

10. A vehicle, characterized in that, Including the image sensor as described in any one of claims 1 to 9.

Images