Multilinear signal output circuit and image sensor

Abstract

The application provides a multi-line state signal output circuit and an image sensor, wherein the multi-line state signal output circuit is composed of a signal conversion circuit and a multi-voltage generation circuit, the multi-voltage generation circuit comprises a voltage output circuit, an upper pull resistance switch array and a lower pull resistance switch array, the upper pull resistance switch array comprises six upper pull resistance switches, the lower pull resistance switch array comprises six lower pull resistance switches, the six upper pull resistance switches and the six lower pull resistance switches respectively receive two groups of corresponding switch signals and trigger on-off, so as to output preset impedances with different sizes, the voltage output circuit outputs voltage signals with different sizes through voltage division, and through the on-off combination of the six parallel upper pull resistance switches and the six parallel lower pull resistance switches, seven selectable levels are generated at a single output end, and the transmission requirement of seven levels of line signal levels of the C-PHY 3.1 protocol is adapted.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, and particularly relates to a multi-line signal output circuit and an image sensor. Background Technology

[0002] With the rapid iteration of terminal applications such as high-definition imaging in smartphones, ultra-high-resolution displays, and high-speed image sensing, devices are placing higher demands on the transmission bandwidth, transmission efficiency, and link compatibility of the MIPI C-PHY interface. Traditional C-PHY 2.1 and earlier versions employ a six-wire, three-level transmission mechanism, relying on a three-wire differential architecture to achieve high-speed data transmission. Compared to the D-PHY interface, it offers advantages such as simplified wiring, no independent clock line, and strong anti-crosstalk capabilities, making it suitable for medium- and low-speed high-definition transmission scenarios for a long time. However, this mode only supports three single-ended levels and six line state combinations, limiting the amount of information carried by the symbol. The potential for increasing the symbol rate under high-speed transmission is limited, making it difficult to meet the transmission requirements of high-bandwidth services such as ultra-high-definition displays and high-frame-rate industrial cameras, becoming a major bottleneck for the performance iteration of high-speed interfaces.

[0003] To overcome the bandwidth limitations of the traditional six-line three-level architecture and optimize high-speed signal integrity and power consumption adaptability, the MIPI Alliance introduced an eighteen-line and seven-level transmission mechanism for the first time in C-PHY version 3.0. In C-PHY version 3.1, it further improved electrical parameter standardization, level accuracy optimization, and mode compatibility, becoming key technologies for next-generation C-PHY high-speed transmission. Compared to the traditional three-level six-line mode, the C-PHY 3.1 architecture, while maintaining the original three-line transmission topology and full hardware pin compatibility, adds multiple sets of intermediate normalized level levels, expanding the single-ended signal level to a seven-order line signal level. These seven levels, from low to high, are called LSL0 to LSL6, significantly enriching the line state combinations, significantly increasing the amount of data that a single symbol can carry, greatly improving the data transmission rate, and balancing high-speed transmission with hardware multiplexing.

[0004] The iterative upgrade of the seven-level generation mechanism of the C-PHY 3.1 protocol essentially utilizes refined multi-level encoding technology to overcome the bandwidth and scenario limitations of traditional three-level transmission while maintaining compatibility with the hardware architecture of previous generations. It balances transmission rate, signal integrity, power consumption, and electromagnetic compatibility performance, becoming a key transmission support technology for high-end scenarios such as ultra-high-resolution imaging and high-speed automotive displays. It also lays the foundation for the level architecture of subsequent ultra-high-speed transmission iterations of the C-PHY interface. Currently, mainstream traditional C-PHY hardware circuits can only achieve three-level signal output, which cannot meet the seven-level generation requirements of the C-PHY 3.1 protocol. Therefore, there is an urgent need to design a highly adaptable and accurate seven-level line signal generation circuit to support the engineering implementation and performance optimization of the next-generation C-PHY high-speed interface. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-line signal output circuit, which aims to solve the problem that traditional C-PHY hardware circuits can only realize three-level signal output and cannot generate the seven-level line signal level required by the C-PHY 3.1 protocol.

[0006] A first aspect of this invention provides a multi-line signal output circuit, comprising: The signal conversion circuit includes three signal conversion units. Each signal conversion unit is used to receive a three-bit binary digital code and convert it into two corresponding sets of switch signals. Each set of switch signals includes six switch signals. A multi-voltage generation circuit includes three level generation units, each connected to a signal conversion unit. The output of each level generation unit is connected to a common-mode voltage terminal via a matching resistor. The three level generation units are used to output multiple sets of voltage signals with different linear states. Each level generation unit includes: Voltage output circuit, used to output working voltage; A pull-up resistor switch array is connected between the voltage output circuit and the output terminal of the level generating unit. The pull-up resistor switch array includes six pull-up resistor switches connected in parallel. The six pull-up resistor switches are used to receive the six switch signals of one group and trigger the on / off state accordingly. When each pull-up resistor switch is turned on, it switches the output preset impedance. A pull-down resistor switch array is connected between the output terminal and the ground terminal of the level generating unit. The pull-down resistor switch array includes six parallel pull-down resistor switches. The six pull-down resistor switches are used to receive the switching signals of another set of six switches and trigger the on / off state accordingly. When each pull-down resistor switch is turned on, it switches the output preset impedance. The switching state of each pull-up resistor switch is opposite to the switching state of the corresponding pull-down resistor switch.

[0007] Optionally, the pull-up resistor switch includes a first transistor and a first resistor connected in series between the voltage output circuit and the output terminal of the level generating unit; The pull-down resistor switch includes a second resistor and a second transistor connected in series between the output terminal of the level generating unit and the ground terminal.

[0008] Optionally, the resistance value of the first resistor is equal to the resistance value of the second resistor, and the resistance value of the first transistor is equal to the resistance value of the second transistor.

[0009] Optionally, the level states of the six switching signals in one group are opposite to the level states of the six switching signals in another group, and the switching type of the first transistor is the same as the switching type of the second transistor. Alternatively, the level states of the six switching signals in one group are identical to the level states of the six switching signals in another group, and the switching type of the first transistor is opposite to the switching type of the second transistor.

[0010] Optionally, the level states of the six switching signals in one group are opposite to the level states of the six switching signals in another group. The signal conversion unit includes: The first logic circuit is used to receive the level signals corresponding to each bit in the three-bit binary code, and to logically convert and output a first switch signal and a first inverted switch signal that is inverse of the first switch signal. The second logic circuit is used to receive the level signals corresponding to the first and second bits of the three-bit binary code, and to logically convert and output a second switch signal and a second inverted switch signal that is inverse of the second switch signal. The third logic circuit is used to receive the level signals corresponding to each bit in the three-bit binary code, and to logically convert and output a third switch signal and a third inverted switch signal that is inverted by the third switch signal. The fourth logic circuit is used to receive the level signal corresponding to the first bit of the three-bit binary code, and to logically convert and output a fourth switch signal and a fourth inverted switch signal that is inverted by the fourth switch signal. The fifth logic circuit is used to receive the level signals corresponding to each bit in the three-bit binary code, and to logically convert and output a fifth switch signal and a fifth inverted switch signal that is inverted by the fifth switch signal; The sixth logic circuit is used to receive the level signals corresponding to the first and second bits of the three-bit binary code, and to logically convert and output a sixth switch signal and a sixth inverted switch signal that is inverse of the sixth switch signal.

[0011] Optionally, the first logic circuit includes a first OR gate, a first transmission gate, and a first inverter; The input terminals of the first OR gate respectively receive the level signals corresponding to each bit in the three-bit binary code. The output terminal of the first OR gate, the input terminal of the first transmission gate, and the input terminal of the first inverter are connected. The output terminal of the first transmission gate is used to output the first switch signal, and the output terminal of the first inverter is used to output the first inverting switch signal. The second logic circuit includes a second OR gate, a second transmission gate, and a second inverter; The input terminals of the second OR gate are respectively the level signals corresponding to the first and second bits of the three-bit binary code. The output terminal of the second OR gate, the input terminal of the second transmission gate, and the input terminal of the second inverter are connected. The output terminal of the second transmission gate is used to output the second switch signal, and the output terminal of the second inverter is used to output the second inverting switch signal. The third logic circuit includes a first AND gate, a third OR gate, a third transmission gate, and a third inverter; The input terminal of the first AND gate is used to receive the level signals corresponding to the second and third bits of the three-bit binary code. The output terminal of the first AND gate is connected to the first input terminal of the third OR gate. The second input terminal of the third OR gate is used to receive the level signal corresponding to the first bit of the three-bit binary code. The output terminal of the third OR gate, the input terminal of the third transmission gate, and the input terminal of the third inverter are connected. The output terminal of the third transmission gate is used to output the third switch signal. The output terminal of the third inverter is used to output the third inverting switch signal. The fourth logic circuit includes a fourth inverter, a fifth inverter, a sixth inverter, and a fourth transmission gate; The input terminal of the fourth inverter is used to receive the level signal corresponding to the first bit of the three-bit binary code. The input terminal of the fourth inverter is connected to the input terminal of the fifth inverter. The output terminal of the fifth inverter, the input terminal of the fourth transmission gate, and the input terminal of the sixth inverter are connected. The output terminal of the fourth transmission gate is used to output the fourth switch signal. The output terminal of the sixth inverter is used to output the fourth inverting switch signal. The fifth logic circuit includes a fourth OR gate, a second AND gate, a fifth transmission gate, and a seventh inverter; The input terminal of the fourth OR gate is used to receive the level signals corresponding to the second and third bits of the three-bit binary code. The output terminal of the fourth OR gate is connected to the first input terminal of the second AND gate. The second input terminal of the second AND gate is used to receive the level signal corresponding to the first bit of the three-bit binary code. The output terminal of the second AND gate, the input terminal of the fifth transmission gate, and the input terminal of the seventh inverter are connected. The output terminal of the fifth transmission gate is used to output the fifth switch signal. The output terminal of the seventh inverter is used to output the fifth inverting switch signal. The sixth logic circuit includes a third AND gate, a sixth transmission gate, and an eighth inverter; The input terminal of the third AND gate is used to receive the level signals corresponding to the first and second bits of the three-bit binary code. The output terminal of the third AND gate, the input terminal of the sixth transmission gate, and the input terminal of the eighth inverter are connected. The output terminal of the sixth transmission gate is used to output the sixth switch signal, and the output terminal of the eighth inverter is used to output the sixth inverting switch signal.

[0012] Optionally, the level states of the six switching signals in one group are identical to the level states of the six switching signals in another group. The signal conversion unit includes: The seventh logic circuit is used to receive the level signals corresponding to each bit in the three-bit binary code and to logically convert and output the first switch signal. The eighth logic circuit is used to receive the level signals corresponding to the first and second bits of the three-bit binary code, and to logically convert and output the second switching signal. The ninth logic circuit is used to receive the level signals corresponding to each bit in the three-bit binary code and to logically convert and output the third switch signal; The tenth logic circuit is used to receive the level signal corresponding to the first bit of the three-bit binary code and to logically convert and output the fourth switch signal. The eleventh logic circuit is used to receive the level signals corresponding to each bit in the three-bit binary code and to logically convert and output the fifth switch signal. The twelfth logic circuit is used to receive the level signals corresponding to the first and second bits of the three-bit binary code, and to logically convert and output the sixth switch signal.

[0013] Optionally, the seventh logic circuit includes a fifth OR gate and a seventh transmission gate; The input terminals of the fifth OR gate receive the level signals corresponding to each bit in the three-bit binary code, and the output terminal of the fifth OR gate is connected to the input terminal of the seventh transmission gate. The output terminal of the seventh transmission gate is used to output the first switch signal. The eighth logic circuit includes a sixth OR gate and an eighth transmission gate; The input terminals of the sixth OR gate are respectively the level signals corresponding to the first and second bits of the three-bit binary code. The output terminal of the sixth OR gate is connected to the input terminal of the eighth transmission gate. The output terminal of the eighth transmission gate is used to output the second switching signal. The ninth logic circuit includes a fourth AND gate, a seventh OR gate, and a ninth transmission gate; The input terminal of the fourth AND gate is used to receive the level signals corresponding to the second and third bits of the three-bit binary code. The output terminal of the fourth AND gate is connected to the first input terminal of the seventh OR gate. The second input terminal of the seventh OR gate is used to receive the level signal corresponding to the first bit of the three-bit binary code. The output terminal of the seventh OR gate is connected to the input terminal of the ninth transmission gate. The output terminal of the ninth transmission gate is used to output the third switch signal. The tenth logic circuit includes a ninth inverter, a tenth inverter, and a tenth transmission gate; The input terminal of the ninth inverter is used to receive the level signal corresponding to the first bit of the three-bit binary code. The input terminal of the ninth inverter is connected to the input terminal of the tenth inverter. The output terminal of the tenth inverter is connected to the input terminal of the tenth transmission gate. The output terminal of the tenth transmission gate is used to output the fourth switch signal. The eleventh logic circuit includes an eighth OR gate, a fifth AND gate, and an eleventh transmission gate; The input terminal of the eighth OR gate is used to receive the level signals corresponding to the second and third bits of the three-bit binary code. The output terminal of the eighth OR gate is connected to the first input terminal of the fifth AND gate. The second input terminal of the fifth AND gate is used to receive the level signal corresponding to the first bit of the three-bit binary code. The output terminal of the fifth AND gate is connected to the input terminal of the eleventh transmission gate. The output terminal of the eleventh transmission gate is used to output the fifth switch signal. The twelfth logic circuit includes a sixth AND gate and a twelfth transmission gate; The input terminal of the sixth AND gate is used to receive the level signal corresponding to the first and second bits of the three-bit binary code. The output terminal of the sixth AND gate is connected to the input terminal of the twelfth transmission gate, and the output terminal of the twelfth transmission gate is used to output the sixth switch signal.

[0014] Optionally, the voltage output circuit includes a third transistor; The first terminal of the third transistor is connected to the positive voltage terminal, the second terminal of the third transistor constitutes the output terminal of the voltage output circuit, and the control terminal of the third transistor is used to receive the bias voltage.

[0015] Optionally, the multi-line signal output circuit further includes: A bias voltage circuit is connected to the voltage output circuit, and the bias voltage circuit is used to output the bias voltage.

[0016] Optionally, the bias voltage circuit includes a third resistor, a fourth resistor, a fourth transistor, and an operational amplifier; The non-inverting input terminal of the operational amplifier is used to input a reference voltage. The output terminal of the operational amplifier is connected to the control terminal of the fourth transistor. The first terminal of the fourth transistor is connected to the positive voltage terminal. The second terminal of the fourth transistor is connected to the first terminal of the third resistor. The second terminal of the third resistor, the first terminal of the fourth resistor, and the inverting input terminal of the operational amplifier are connected. The second terminal of the fourth resistor is grounded.

[0017] Optionally, each of the level generating units outputs seven voltage signals of different magnitudes according to two different sets of switching signals, and the three level generating units are combined to generate eighteen sets of voltage signals with different linear states.

[0018] A second aspect of the present invention provides an image sensor including the multi-line signal output circuit described above.

[0019] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above-mentioned multi-line signal output circuit is composed of a signal conversion circuit and a multi-voltage generation circuit. The multi-voltage generation circuit includes a voltage output circuit, a pull-up resistor switch array, and a pull-down resistor switch array. The pull-up resistor switch array includes six pull-up resistor switches, and the pull-down resistor switch array includes six pull-down resistor switches. The six pull-up resistor switches and the six pull-down resistor switches respectively receive two sets of corresponding switch signals and trigger on / off states, thereby outputting preset impedances of different magnitudes. The voltage output circuit outputs voltage signals of different magnitudes after voltage division. Through the on / off combination of the six parallel pull-up resistor switches and the six parallel pull-down resistor switches, a seven-level selectable level is generated at a single output terminal, which is compatible with the seven-level line signal level transmission requirements of the C-PHY 3.1 protocol. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a first structure of a multi-line signal output circuit provided in an embodiment of the present invention; Figure 2 This is a first circuit diagram of a multi-line signal output circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a first structure of a signal conversion unit provided in an embodiment of the present invention; Figure 4 A circuit diagram of the first logic circuit provided in an embodiment of the present invention; Figure 5 A circuit diagram of the second logic circuit provided in an embodiment of the present invention; Figure 6 A circuit diagram of the third logic circuit provided in an embodiment of the present invention; Figure 7 A circuit diagram of the fourth logic circuit provided in an embodiment of the present invention; Figure 8 A circuit diagram of the fifth logic circuit provided in an embodiment of the present invention; Figure 9 A circuit diagram of the sixth logic circuit provided in an embodiment of the present invention; Figure 10 This is a second circuit diagram of a multi-line signal output circuit provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of a second structure of the signal conversion unit provided in an embodiment of the present invention; Figure 12 A circuit diagram of the seventh logic circuit provided in an embodiment of the present invention; Figure 13 A circuit diagram of the eighth logic circuit provided in an embodiment of the present invention; Figure 14 A circuit diagram of the ninth logic circuit provided in an embodiment of the present invention; Figure 15 A circuit diagram of the tenth logic circuit provided in an embodiment of the present invention; Figure 16 A circuit diagram of the eleventh logic circuit provided in an embodiment of the present invention; Figure 17 A circuit diagram of the twelfth logic circuit provided in an embodiment of the present invention; Figure 18 This is a schematic diagram of a second structure of the multi-line signal output circuit provided in an embodiment of the present invention; Figure 19 This is a circuit diagram of the bias voltage circuit provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0022] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0023] A first aspect of the present invention provides a multi-line signal output circuit.

[0024] like Figure 1 As shown, in this embodiment, the multi-line signal output circuit includes: The signal conversion circuit 1 includes three signal conversion units 100. Each signal conversion unit 100 is used to receive one three-bit binary digital code and convert it into two corresponding sets of switch signals. Each set of switch signals includes six switch signals. The multi-voltage generation circuit 2 includes three level generation units 200, each connected to a signal conversion unit 100. The output of each level generation unit 200 is connected to a common-mode voltage terminal via a matching resistor Rz. The three level generation units 200 are used to output multiple sets of voltage signals with different linear states. Each level generation unit 200 includes: Voltage output circuit 210 is used to output the working voltage; Pull-up resistor switch array 220 is connected between the voltage output circuit 210 and the output terminal of the level generating unit 200. Pull-up resistor switch array 220 includes six parallel pull-up resistor switches 221. The six pull-up resistor switches 221 are used to receive one of the six switching signals of one group and trigger the on and off accordingly. When each pull-up resistor switch 221 is turned on, the output preset impedance is switched. A pull-down resistor switch array 230 is connected between the output terminal and the ground terminal of the level generating unit 200. The pull-down resistor switch array 230 includes six parallel pull-down resistor switches 231. The six pull-down resistor switches 231 are used to receive six switching signals from another set and trigger the on / off state accordingly. When each pull-down resistor switch 231 is turned on, it switches the output preset impedance. The switching state of each pull-up resistor switch 221 is opposite to the switching state of the corresponding pull-down resistor switch 231.

[0025] In this embodiment, the multi-line signal output circuit includes a signal conversion circuit 1 and a multi-voltage generation circuit 2. The signal conversion circuit 1 includes three signal conversion units 100, each corresponding to one of the three output channels. Each signal conversion unit 100 receives one three-bit binary code, the value range of which is from binary 000 to binary 110, a total of seven values, corresponding to the seventh-order line signal levels LSL0 to LSL6. The signal conversion unit 100 logically converts the three-bit binary code into two sets of switching signals, each set of switching signals including six switching signals. One set of switching signals is used to control the six switches of the pull-up resistor switch 221, and the other set is used to control the six switches of the pull-down resistor switch 231. There is a definite correspondence between the two sets of switching signals, where the pull-up resistor switch 221 corresponds to the pull-up resistor switch 221, and the pull-down resistor switch 231 corresponds to the pull-down resistor switch 231.

[0026] The multi-voltage generation circuit 2 includes three level generation units 200, each connected to one of the three signal conversion units 100. Each level generation unit 200 receives two sets of switching signals output from the corresponding signal conversion unit 100 and generates a voltage signal of the corresponding order at its output terminal based on the on / off combination of the switching signals. The output terminals of the three level generation units 200 are labeled A, B, and C, respectively. The three circuits work together to complete the combined output of multi-line signals. Terminals A, B, and C are each connected to the common-mode voltage terminal through a matching resistor Rz. The resistance value of the matching resistor Rz can be designed to be 50Ω to match the characteristic impedance of the transmission line and reduce signal reflection. The voltage at the common-mode voltage terminal is denoted as Vcptx, and the three output signals are differentially transmitted using Vcptx as the common-mode reference point.

[0027] The three-channel level generating unit 200 can output multiple sets of voltage signals with different amplitudes by combining different switching signals. The non-repeating arrangement of the three voltage signals can form a variety of line states, adapting to the high-speed transmission encoding rules specified in the protocol.

[0028] Each level generating unit 200 includes a voltage output circuit 210, a pull-up resistor switch array 220, and a pull-down resistor switch array 230. The voltage output circuit 210 provides the operating voltage for the pull-up resistor switches 221, and its output voltage is denoted as Vs. The pull-up resistor switch array 220 is connected between the output terminal of the voltage output circuit 210 and the output terminal of the level generating unit 200, and includes six pull-up resistor switches 221 connected in parallel. The control terminals of the six pull-up resistor switches 221 respectively receive one set of six switching signals output by the signal conversion unit 100. Each pull-up resistor switch 221 is turned on or off under the trigger of the corresponding switching signal. When turned on, the branch presents a preset impedance, and when turned off, the branch presents a high impedance state.

[0029] The pull-down resistor switch array 230 is connected between the output terminal of the level generating unit 200 and the ground terminal, and includes six pull-down resistor switches 231 connected in parallel. The control terminals of the six pull-down resistor switches 231 respectively receive another set of six switching signals output by the signal conversion unit 100. Each pull-down resistor switch 231 is turned on or off when triggered by the corresponding switching signal. When it is turned on, the branch presents a preset impedance, and when it is turned off, the branch presents a high impedance state.

[0030] There is a one-to-one pairing relationship between the pull-up resistor switch array 220 and the pull-down resistor switch array 230. That is, the first pull-up resistor switch 221 is paired with the first pull-down resistor switch 231, the second pull-up resistor switch 221 is paired with the second pull-down resistor switch 231, and so on up to the sixth channel. In each pairing, the switching state of the pull-up resistor switch 221 is opposite to the switching state of the corresponding pull-down resistor switch 231. That is, when the pull-up resistor switch 221 is on, the corresponding pull-down resistor switch 231 is off, and when the pull-up resistor switch 221 is off, the corresponding pull-down resistor switch 231 is on. This complementary switch configuration ensures that, under any switch combination, the sum of the equivalent pull-up impedance between the output terminal of the level generating unit 200 and the voltage output circuit 210 and the equivalent pull-down impedance between the output terminal and the ground terminal remains constant. Specifically, in the six parallel branches, each branch is either pulled up and turned off, or pulled up and turned off and pulled down and turned on. Therefore, the total number of conducting branches is always six, and the sum of the number of pulled up and pulled down branches is always 6. When the impedance of a single conducting branch is a fixed value, the parallel combination relationship between the equivalent impedance of the pull-up and the equivalent impedance of the pull-down changes monotonically with the number of conducting branches, realizing the gradient adjustment of the output voltage amplitude and generating multi-level differentiated line signal levels.

[0031] Pull-up resistor switch 221 and pull-down resistor switch 231 can be composed of corresponding resistors and switches. In an optional embodiment, such as... Figure 2 and Figure 10 As shown, the pull-up resistor switch 221 includes a first transistor M1 and a first resistor R1 connected in series between the voltage output circuit 210 and the output terminal of the level generating unit 200; The pull-down resistor switch 231 includes a second resistor R2 and a second transistor M2 connected in series between the output terminal of the level generating unit 200 and the ground terminal.

[0032] In this embodiment, each pull-up resistor switch 221 is composed of a first transistor M1 and a first resistor R1 connected in series. The series structure is stably arranged on the signal transmission branch between the voltage output circuit 210 and the output terminal of the level generation unit 200. The first transistor M1 is used as a switching device, which receives an external switching signal through its gate to switch between conduction and cutoff. The first resistor R1 is used as a current-limiting voltage divider device, which works with the transistor to form a fixed impedance branch to ensure the stability of the impedance parameters after the branch is turned on.

[0033] Each pull-down resistor switch 231 consists of a second resistor R2 and a second transistor M2 connected in series. This series connection is arranged on the signal feedback branch between the output of the level generating unit 200 and the circuit ground. The second transistor M2 performs the switch control function, switching its operating state according to the received switch signal. The second resistor R2, together with the transistor, forms a ground impedance branch, which, together with the impedance structure of the pull-up resistor switch 221, forms a voltage divider matching relationship, providing a voltage divider basis for multi-level output.

[0034] The six pull-up resistor switches 221 form a parallel array structure. Any number of pull-up resistor switches 221 can be independently connected to their corresponding impedance without interfering with the operation of other branches. The six pull-down resistor switches 231 also adopt a parallel array design, with each branch operating independently and without affecting others. By adjusting the conduction ratio of different numbers of pull-up and pull-down branches, the equivalent impedance between the output terminal and the operating voltage terminal and ground terminal can be changed. Based on the principle of resistor voltage division, voltage signals of different amplitudes can be output, achieving a gradient output of the signal level.

[0035] In an optional embodiment, the resistance of the first resistor R1 is equal to the resistance of the second resistor R2, and the on-resistance of the first transistor M1 is equal to the on-resistance of the second transistor M2. Therefore, the preset impedance when each pull-up resistor switch 221 is turned on is equal to the preset impedance when each pull-down resistor switch 231 is turned on, which is the sum of the on-resistance of a single switch and a single series resistance. The design value of the preset impedance is 300Ω, which is the design target and needs to be verified. When k pull-up switches are turned on and 6-k pull-down switches are turned on in the six parallel branches, the equivalent pull-up impedance between the output terminal and the voltage output terminal is 300Ω divided by k, and the equivalent pull-down impedance between the output terminal and the ground terminal is 300Ω divided by 6-k. The value of k ranges from 0 to 6, corresponding to seven different impedance combinations, thereby generating seven different voltage levels at the output terminal.

[0036] It should be noted that the switching types of the first transistor M1 and the second transistor M2 can be the same or opposite, depending on the selection of the switching control scheme. When both the first transistor M1 and the second transistor M2 are NMOS transistors, the two sets of switching signals need to be inverted one by one, that is, the signal level of the pull-up resistor switch 221 is opposite to the corresponding signal level of the pull-down resistor switch 231, to ensure that the pull-up is turned on and the pull-down is turned off. When the first transistor M1 is a PMOS transistor and the second transistor M2 is an NMOS transistor, the two sets of switching signals can be the same one by one, that is, the signal level of the pull-up resistor switch 221 is the same as the corresponding signal level of the pull-down resistor switch 231, because PMOS transistors and NMOS transistors exhibit opposite switching states at the same gate level. The above two schemes will be described in detail in subsequent embodiments.

[0037] In an alternative embodiment, such as Figure 2As shown, the level states of one group of six-way switch signals are opposite to those of another group of six-way switch signals, and the switching type of the first transistor M1 is the same as that of the second transistor M2.

[0038] In this embodiment, the first transistor M1 and the second transistor M2 can both be NMOS transistors or both be PMOS transistors. Taking the example of both being NMOS transistors, when the pull-up resistor switch 221 signal is high, the first transistor M1 is turned on, and at this time the corresponding pull-down resistor switch 231 signal is low, and the second transistor M2 is turned off; when the pull-up resistor switch 221 signal is low, the first transistor M1 is turned off, and at this time the corresponding pull-down resistor switch 231 signal is high, and the second transistor M2 is turned on, thereby realizing complementary switching of pull-up and pull-down.

[0039] To achieve two sets of inverting switch signals, the signal conversion unit 100 needs to simultaneously output six switch signals and six inverting switch signals. In an optional embodiment, such as... Figure 3 As shown, the signal conversion unit 100 includes: The first logic circuit 110 is used to receive the level signals corresponding to each bit in the three-bit binary digital code, and to logically convert and output the first switch signal inp1 and the first inverted switch signal inn1 that is inverse of the first switch signal inp1. The second logic circuit 120 is used to receive the level signals corresponding to the first and second bits of the three-bit binary code, and to logically convert and output the second switch signal inp2 and the second inverted switch signal inn2 that is inverse of the second switch signal inp2. The third logic circuit 130 is used to receive the level signals corresponding to each bit in the three-bit binary digital code, and to logically convert and output the third switch signal inp3 and the third inverted switch signal inn3 that is inverted by the third switch signal inp3. The fourth logic circuit 140 is used to receive the level signal corresponding to the first bit of the three-bit binary digital code, and to logically convert and output the fourth switch signal inp4 and the fourth inverted switch signal inn4 which is the inverse of the fourth switch signal inp4. The fifth logic circuit 150 is used to receive the level signal corresponding to each bit in the three-bit binary digital code, and to logically convert and output the fifth switch signal inp5 and the fifth inverted switch signal inn5 that is inverted by the fifth switch signal inp5. The sixth logic circuit 160 is used to receive the level signals corresponding to the first and second bits of the three-bit binary code, and to logically convert and output the sixth switch signal inp6 and the sixth inverted switch signal inn6 which is the inverse of the sixth switch signal inp6.

[0040] In this embodiment, each logic circuit receives a specific combination of three bits of binary code and performs logic conversion to output a switch signal and an inverted switch signal that is the opposite of the switch signal. The six logic circuits output a total of six switch signals inp1 to inp6 and six inverted switch signals inn1 to inn6, where the first switch signal inp1 is the inverted version of the first inverted switch signal inn1, the second switch signal inp2 is the inverted version of the second inverted switch signal inn2, and so on. The six switch signals inp1 to inp6 are used to control the six pull-up resistor switches 221 of the pull-up resistor switch array 220, and the six inverted switch signals inn1 to inn6 are used to control the six pull-down resistor switches 231 of the pull-down resistor switch array 230.

[0041] A three-bit binary code is denoted as V2V1V0, where V2 is the most significant bit (first bit), V1 is the middle bit (second bit), and V0 is the least significant bit (third bit). The seven possible values ​​of the three-bit binary code (000, 001, 010, 011, 100, 101, 110) correspond to LSL0 to LSL6, respectively. The logical expression between the six-channel switch signals inp1 to inp6 and the three-bit binary code is as follows: inp1 = V2 or V1 or V0; inp2 = V2 or V1; inp3 = V2 or (V1 and V0); inp4 = V2; inp5 = V2 and (V1 or V0); inp6 = V1 and V2; The first switch signal inp1 is high when V2, V1, and V0 are 001, 010, 011, 100, 101, and 110, and low when V2, V1, and V0 are 000. That is, the first switch signal inp1 is obtained by performing a logical OR operation on V1, V2, and V0 sequentially. The second switch signal inp2 is high when V2, V1, and V0 are 010, 011, 100, 101, and 110, and low when V2, V1, and V0 are 000 and 001. That is, the second switch signal inp2 is obtained by performing a logical OR operation on V2 and V1. The third switch signal inp3 is high when V2, V1, and V0 are 011, 100, 101, and 110, and low when V2, V1, and V0 are 000, 001, and 010. That is, the third switch signal inp3 is obtained by first performing a logical AND operation on V1 and V0, and then performing a logical OR operation on the result with V2. The fourth switch signal, inp4, is high when V2, V1, and V0 are 100, 101, and 110, and low when they are 000, 001, 010, and 011. That is, the fourth switch signal inp4 is V2 itself. The fifth switch signal, inp5, is high when V2, V1, and V0 are 101 and 110, and low when they are 000, 001, 010, 011, and 100. That is, the fifth switch signal inp5 is obtained by first performing a logical OR operation on V1 and V0, and then performing a logical AND operation on the result with V2. The sixth switch signal, inp6, is high when V2, V1, and V0 are 110, and low for all other values. That is, the sixth switch signal inp6 is obtained by performing a logical AND operation on V1 and V2.

[0042] The above logic converts a three-bit binary code into a six-channel thermometer code. As the binary value increases, the first switch signal (inp1) through the sixth switch signal (inp6) sequentially becomes high, exhibiting a thermometer-like increasing pattern. When the binary code is 000, all six switch signals (inp1 through inp6) are low, pull-up resistor 221 is completely off, pull-down resistor 231 is completely on, and the output is the lowest level, LSL0. When the binary code is 001, the first switch signal (inp1) is high, and the second through sixth switch signals (inp2 through inp6) are low, one pull-up resistor is on, and five pull-down resistors are on, resulting in the output LSL1. Similarly, when the binary code is 110, all six switch signals (inp1 through inp6) are high, pull-up resistor 221 is on, pull-down resistor 231 is completely off, and the output is the highest level, LSL6.

[0043] Each logic circuit can be composed of corresponding logic gates. In an optional embodiment, such as... Figure 4 As shown, the first logic circuit 110 includes a first OR gate U1, a first transmission gate TG1, and a first inverter INV1; The input terminals of the first OR gate U1 receive the level signals corresponding to each bit in the three-bit binary digital code. The output terminal of the first OR gate U1, the input terminal of the first transmission gate TG1, and the input terminal of the first inverter INV1 are connected. The output terminal of the first transmission gate TG1 is used to output the first switch signal inp1, and the output terminal of the first inverter INV1 is used to output the first inverting switch signal inn1. like Figure 5 As shown, the second logic circuit 120 includes a second OR gate U2, a second transmission gate TG2, and a second inverter INV2; The input terminals of the second OR gate U2 are respectively the level signals corresponding to the first and second bits of the three-bit binary digital code. The output terminal of the second OR gate U2 is connected to the input terminal of the second transmission gate TG2 and the input terminal of the second inverter INV2. The output terminal of the second transmission gate TG2 is used to output the second switch signal inp2, and the output terminal of the second inverter INV2 is used to output the second inverting switch signal inn2. like Figure 6 As shown, the third logic circuit 130 includes a first AND gate U3, a third OR gate U4, a third transmission gate TG3, and a third inverter INV3; The input of the first AND gate U3 is used to receive the level signals corresponding to the second and third bits of the three-bit binary code. The output of the first AND gate U3 is connected to the first input of the third OR gate U4. The second input of the third OR gate U4 is used to receive the level signal corresponding to the first bit of the three-bit binary code. The output of the third OR gate U4, the input of the third transmission gate TG3, and the input of the third inverter INV3 are connected. The output of the third transmission gate TG3 is used to output the third switch signal inp3. The output of the third inverter INV3 is used to output the third inverting switch signal inn3. like Figure 7 As shown, the fourth logic circuit 140 includes a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, and a fourth transmission gate TG4; The input of the fourth inverter INV4 is used to receive the level signal corresponding to the first bit of the three-bit binary code. The input of the fourth inverter INV4 is connected to the input of the fifth inverter INV5. The output of the fifth inverter INV5, the input of the fourth transmission gate TG4, and the input of the sixth inverter INV6 are connected. The output of the fourth transmission gate TG4 is used to output the fourth switch signal inp4, and the output of the sixth inverter INV6 is used to output the fourth inverting switch signal inn4. like Figure 8 As shown, the fifth logic circuit 150 includes a fourth OR gate U5, a second AND gate U6, a fifth transmission gate TG5, and a seventh inverter INV7; The input of the fourth OR gate U5 is used to receive the level signals corresponding to the second and third bits of the three-bit binary code. The output of the fourth OR gate U5 is connected to the first input of the second AND gate U6. The second input of the second AND gate U6 is used to receive the level signal corresponding to the first bit of the three-bit binary code. The output of the second AND gate U6, the input of the fifth transmission gate TG5, and the input of the seventh inverter INV7 are connected. The output of the fifth transmission gate TG5 is used to output the fifth switch signal inp5, and the output of the seventh inverter INV7 is used to output the fifth inverting switch signal inn5. like Figure 9 As shown, the sixth logic circuit 160 includes a third AND gate U7, a sixth transmission gate TG6, and an eighth inverter INV8; The input of the third AND gate U7 is used to receive the level signals corresponding to the first and second bits of the three-bit binary code. The output of the third AND gate U7, the input of the sixth transmission gate TG6, and the input of the eighth inverter INV8 are connected. The output of the sixth transmission gate TG6 is used to output the sixth switch signal inp6, and the output of the eighth inverter INV8 is used to output the sixth inverting switch signal inn6.

[0044] In this embodiment, the first logic circuit 110 includes a first OR gate U1, a first transmission gate TG1, and a first inverter INV1. The first OR gate U1 has three input terminals, which respectively receive the level signals corresponding to the three-bit binary digital codes V2, V1, and V0. The first OR gate U1 performs a logical OR operation on the three input signals, and the output result is connected to the input terminals of the first transmission gate TG1 and the first inverter INV1. The output terminal of the first transmission gate TG1 outputs a first switch signal inp1, and the output terminal of the first inverter INV1 outputs a first inverted switch signal inn1. The first transmission gate TG1 is used to buffer and delay the first switch signal inp1 to ensure that the propagation delays of the two signals, the first switch signal inp1 and the first inverted switch signal inn1, are consistent, avoiding transient errors caused by the simultaneous conduction or deactivation of the pull-up and pull-down resistor switches 231 due to delay mismatch. The first inverter INV1 inverts the output of the first OR gate U1 to generate a first inverted switch signal inn1 with the opposite level to the first switch signal inp1.

[0045] The second logic circuit 120 includes a second OR gate U2, a second transmission gate TG2, and a second inverter INV2. The second OR gate U2 has two inputs, receiving the level signals corresponding to the first bit V2 and the second bit V1 of a three-bit binary code, respectively. The second OR gate U2 performs a logical OR operation on V2 and V1, and the output is simultaneously connected to the inputs of the second transmission gate TG2 and the second inverter INV2. The output of the second transmission gate TG2 outputs a second switching signal inp2, and the output of the second inverter INV2 outputs a second inverting switching signal inn2. The functions of the second transmission gate TG2 and the second inverter INV2 are the same as their counterparts in the first logic circuit 110, used for delay matching and signal inversion.

[0046] The third logic circuit 130 includes a first AND gate U3, a third OR gate U4, a third transmission gate TG3, and a third inverter INV3. The first AND gate U3 has two inputs, receiving the level signals corresponding to the second bit V1 and the third bit V0 of the three-bit binary code, respectively, and performing a logical AND operation on V1 and V0. The output of the first AND gate U3 is connected to the first input of the third OR gate U4, and the second input of the third OR gate U4 receives the level signal corresponding to the first bit V2 of the three-bit binary code. The third OR gate U4 performs a logical OR operation on the output of the first AND gate U3 and V2, and the output is simultaneously connected to the inputs of the third transmission gate TG3 and the third inverter INV3. The output of the third transmission gate TG3 outputs a third switch signal inp3, and the output of the third inverter INV3 outputs a third inverting switch signal inn3. This logic structure implements the third switch signal inp3 by first performing a logical AND operation on V1 and V0, and then performing a logical OR operation on the result with V2. That is, when V2 is high, the third switch signal inp3 is high, and when V2 is low, V1 and V0 need to be high at the same time for the third switch signal inp3 to be high.

[0047] The fourth logic circuit 140 includes a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, and a fourth transmission gate TG4. The input of the fourth inverter INV4 receives the level signal corresponding to the first bit V2 of the three-bit binary code. The input of the fourth inverter INV4 is also connected to the input of the fifth inverter INV5. The fourth inverter INV4 and the fifth inverter INV5 are connected in parallel, both receiving the V2 signal at their inputs, and their outputs are also connected together. This parallel inverter structure enhances the driving capability and provides a more balanced driving strength between the rising and falling edges. The output of the parallel inverter is connected to both the input of the fourth transmission gate TG4 and the input of the sixth inverter INV6. The output of the fourth transmission gate TG4 outputs a fourth switching signal inp4, and the output of the sixth inverter INV6 outputs a fourth inverted switching signal inn4. This logic structure ensures that the fourth switch signal inp4 is equal to the signal of V2 after two stages of inversion, that is, the fourth switch signal inp4 is in phase with V2, and the fourth inverted switch signal inn4 is inverted with V2.

[0048] The fifth logic circuit 150 includes a fourth OR gate U5, a second AND gate U6, a fifth transmission gate TG5, and a seventh inverter INV7. The fourth OR gate U5 has two inputs, receiving the level signals corresponding to the second bit V1 and the third bit V0 of the three-bit binary code, respectively, and performing a logical OR operation on V1 and V0. The output of the fourth OR gate U5 is connected to the first input of the second AND gate U6, and the second input of the second AND gate U6 receives the level signal corresponding to the first bit V2 of the three-bit binary code. The second AND gate U6 performs a logical AND operation on the output of the fourth OR gate U5 and V2, and the output is simultaneously connected to the inputs of the fifth transmission gate TG5 and the seventh inverter INV7. The output of the fifth transmission gate TG5 outputs the fifth switch signal inp5, and the output of the seventh inverter INV7 outputs the fifth inverting switch signal inn5. This logic structure implements the fifth switch signal inp5 by first performing a logical OR operation on V1 and V0, and then performing a logical AND operation on the result with V2. That is, the fifth switch signal is only high when V2 is high and at least one of V1 and V0 is high.

[0049] The sixth logic circuit 160 includes a third AND gate U7, a sixth transmission gate TG6, and an eighth inverter INV8. The third AND gate U7 has two inputs, receiving the level signals corresponding to the first bit V2 and the second bit V1 of the three-bit binary code, respectively, and performing a logical AND operation on V2 and V1. The output of the third AND gate U7 is connected to both the input of the sixth transmission gate TG6 and the input of the eighth inverter INV8. The output of the sixth transmission gate TG6 outputs the sixth switch signal inp6, and the output of the eighth inverter INV8 outputs the sixth inverted switch signal inn6. This logic structure ensures that the sixth switch signal inp6 is obtained by performing a logical AND operation on V1 and V2; that is, inp6 is only high when both V2 and V1 are high.

[0050] In the six logic circuits described above, transmission gates are used to buffer and delay the switching signals, ensuring consistent propagation delays between the first switching signal inp1 and the sixth switching signal inp6, as well as between each switching signal and its inverted signal. Inverters are used to generate inverted switching signals and also serve as buffer drivers. The three signal conversion units 100 have identical circuit structures, processing the three-bit binary codes of channels A, B, and C respectively, and outputting their respective six-channel switching signals and six-channel inverted switching signals.

[0051] In another alternative embodiment, such as Figure 10 As shown, the level states of one group of six-way switch signals are exactly the same as those of another group of six-way switch signals, and the switching type of the first transistor M1 is opposite to that of the second transistor M2.

[0052] In this embodiment, the first transistor M1 of the pull-up resistor switch 221 is a PMOS transistor, and the second transistor M2 of the pull-down resistor switch 231 is an NMOS transistor. The PMOS transistor is turned on when its gate is low and turned off when its gate is high, while the NMOS transistor is turned on when its gate is high and turned off when its gate is low. Therefore, when the same switch signal is simultaneously connected to the gates of the first transistor M1 and the second transistor M2, a high switch signal turns off the first transistor M1 and turns on the second transistor M2, while a low switch signal turns on the first transistor M1 and turns off the second transistor M2. This naturally achieves complementary pull-up and pull-down switching without the need to generate an additional inverting switch signal.

[0053] The signal conversion unit 100 only needs to output six first switch signals inp1 to the sixth switch signal inp6, without needing to output inverting switch signals. The six switch signals are simultaneously connected to the gate of the first transistor M1 in the corresponding pull-up resistor switch 221 and the gate of the second transistor M2 in the pull-down resistor switch 231.

[0054] Corresponding to the above structure and signal type, signal conversion circuit 1 can adopt corresponding logic circuits. In an optional embodiment, such as... Figure 11 As shown, the signal conversion unit 100 includes: The seventh logic circuit 170 is used to receive the level signals corresponding to each bit in the three-bit binary code and to logically convert and output the first switch signal inp1; The eighth logic circuit 180 is used to receive the level signals corresponding to the first and second bits of the three-bit binary code, and to logically convert and output the second switch signal inp2. The ninth logic circuit 190 is used to receive the level signals corresponding to each bit in the three-bit binary code and to logically convert and output the third switch signal inp3; The tenth logic circuit 1100 is used to receive the level signal corresponding to the first bit of the three-bit binary code and to logically convert and output the fourth switch signal inp4. The eleventh logic circuit 1110 is used to receive the level signals corresponding to each bit in the three-bit binary code and to logically convert and output the fifth switch signal inp5; The twelfth logic circuit 1120 is used to receive the level signals corresponding to the first and second bits of the three-bit binary code, and to logically convert and output the sixth switch signal inp6.

[0055] In this embodiment, the signal conversion unit 100 includes six logic circuits, from the seventh logic circuit 170 to the twelfth logic circuit 1120. Each logic circuit receives a specific combination of three bits of binary code and performs logic conversion to output one switching signal. The six logic circuits output six switching signals inp1 to inp6.

[0056] The three-digit binary code is still denoted as V2V1V0, and the seven possible values ​​from 000 to 110 correspond to LSL0 to LSL6 respectively. The first switch signal inp1 is obtained by performing a logical OR operation on V1, V2, and V0 in sequence. The second switch signal inp2 is obtained by performing a logical OR operation on V2 and V1. The third switch signal inp3 is obtained by performing a logical AND operation on V1 and V0 first, and then performing a logical OR operation on the result with V2. The fourth switch signal inp4 is V2 itself. The fifth switch signal inp5 is obtained by performing a logical OR operation on V1 and V0 first, and then performing a logical AND operation on the result with V2. The sixth switch signal inp6 is obtained by performing a logical AND operation on V1 and V2.

[0057] It should be noted that in this embodiment, since the first transistor M1 of the pull-up resistor switch 221 is a PMOS transistor, the effective level of the switch signal is opposite to that in the previous embodiment. In the previous embodiment, the first transistor M1 is turned on when the switch signal is high; in this embodiment, the first transistor M1 is turned on when the switch signal is low. Therefore, when the binary code is 000, the first switch signal inp1 to the sixth switch signal inp6 are all low, the first transistor M1 is fully turned on, and the second transistor M2 is fully turned off. This is the opposite of the case in the previous embodiment where the binary code 000 corresponds to the full conduction of the pull-down resistor switch 231. To maintain the correspondence between the binary code and the level order, the value of the binary code can be mapped inversely to the level order, or an inverting stage can be added to the logic circuit. The specific mapping method can be determined according to the system design requirements, and this embodiment does not limit it.

[0058] The seventh logic circuit 170 and the twelfth logic circuit 1120 can be composed of corresponding logic gates, such as Figure 12 As shown, in an optional embodiment, the seventh logic circuit 170 includes a fifth OR gate U8 and a seventh transmission gate TG7; The inputs of the fifth OR gate U8 receive the level signals corresponding to each bit of the three-bit binary code. The output of the fifth OR gate U8 is connected to the input of the seventh transmission gate TG7. The output of the seventh transmission gate TG7 is used to output the first switch signal inp1. like Figure 13 As shown, the eighth logic circuit 180 includes a sixth OR gate U9 and an eighth transmission gate TG8; The input terminals of the sixth OR gate U9 are respectively the level signals corresponding to the first and second bits of the three-bit binary digital code. The output terminal of the sixth OR gate U9 is connected to the input terminal of the eighth transmission gate TG8. The output terminal of the eighth transmission gate TG8 is used to output the second switch signal inp2. like Figure 14 As shown, the ninth logic circuit 190 includes a fourth AND gate U10, a seventh OR gate U11, and a ninth transmission gate TG9; The input of the fourth AND gate U10 is used to receive the level signals corresponding to the second and third bits of the three-bit binary code. The output of the fourth AND gate U10 is connected to the first input of the seventh OR gate U11. The second input of the seventh OR gate U11 is used to receive the level signal corresponding to the first bit of the three-bit binary code. The output of the seventh OR gate U11 is connected to the input of the ninth transmission gate TG9. The output of the ninth transmission gate TG9 is used to output the third switch signal inp3. like Figure 15 As shown, the tenth logic circuit 1100 includes a ninth inverter INV9, a tenth inverter INV10, and a tenth transmission gate TG10. The input of the ninth inverter INV9 is used to receive the level signal corresponding to the first bit of the three-bit binary code. The input of the ninth inverter INV9 is connected to the input of the tenth inverter INV10. The output of the tenth inverter INV10 is connected to the input of the tenth transmission gate TG10. The output of the tenth transmission gate TG10 is used to output the fourth switch signal inp4. like Figure 16 As shown, the eleventh logic circuit 1110 includes an eighth OR gate U12, a fifth AND gate U13, and an eleventh transmission gate TG11; The input of the eighth OR gate U12 is used to receive the level signals corresponding to the second and third bits of the three-bit binary code. The output of the eighth OR gate U12 is connected to the first input of the fifth AND gate U13. The second input of the fifth AND gate U13 is used to receive the level signal corresponding to the first bit of the three-bit binary code. The output of the fifth AND gate U13 is connected to the input of the eleventh transmission gate TG11. The output of the eleventh transmission gate TG11 is used to output the fifth switch signal inp5. like Figure 17 As shown, the twelfth logic circuit 1120 includes a sixth AND gate U14 and a twelfth transmission gate TG12; The input of the sixth AND gate U14 is used to receive the level signals corresponding to the first and second bits of the three-bit binary code. The output of the sixth AND gate U14 is connected to the input of the twelfth transmission gate TG12. The output of the twelfth transmission gate TG12 is used to output the sixth switch signal inp6.

[0059] In this embodiment, the seventh logic circuit 170 includes a fifth OR gate U8 and a seventh transmission gate TG7. The fifth OR gate U8 has three input terminals, which respectively receive the level signals corresponding to the three-bit binary codes V2, V1, and V0. The fifth OR gate U8 performs a logical OR operation on the three input signals, and the output result is connected to the input terminal of the seventh transmission gate TG7. The output terminal of the seventh transmission gate TG7 outputs the first switch signal inp1. The seventh transmission gate TG7 is used to buffer and delay the first switch signal inp1 to ensure that the propagation delay is consistent among the six switch signals.

[0060] The eighth logic circuit 180 includes a sixth OR gate U9 and an eighth transmission gate TG8. The sixth OR gate U9 has two inputs, receiving the level signals corresponding to the first bit V2 and the second bit V1 of the three-bit binary code, respectively. The sixth OR gate U9 performs a logical OR operation on V2 and V1, and the output is connected to the input of the eighth transmission gate TG8. The output of the eighth transmission gate TG8 outputs the second switching signal inp2.

[0061] The ninth logic circuit 190 includes a fourth AND gate U10, a seventh OR gate U11, and a ninth transmission gate TG9. The fourth AND gate U10 has two inputs, receiving the level signals corresponding to the second bit V1 and the third bit V0 of the three-bit binary code, respectively, and performing a logical AND operation on V1 and V0. The output of the fourth AND gate U10 is connected to the first input of the seventh OR gate U11, and the second input of the seventh OR gate U11 receives the level signal corresponding to the first bit V2 of the three-bit binary code. The seventh OR gate U11 performs a logical OR operation on the output of the fourth AND gate U10 and V2, and the output result is connected to the input of the ninth transmission gate TG9. The output of the ninth transmission gate TG9 outputs the third switch signal inp3.

[0062] The tenth logic circuit 1100 includes a ninth inverter INV9, a tenth inverter INV10, and a tenth transmission gate TG10. The input of the ninth inverter INV9 receives the level signal corresponding to the first bit V2 of the three-bit binary code. The input of the ninth inverter INV9 is also connected to the input of the tenth inverter INV10. The ninth inverter INV9 and the tenth inverter INV10 are connected in parallel, both receiving the V2 signal at their inputs, and their outputs are also connected together. The output of the parallel inverters is connected to the input of the tenth transmission gate TG10. The output of the tenth transmission gate TG10 outputs the fourth switching signal inp4. This logic structure ensures that the fourth switching signal inp4 is equal to the signal after V2 has been inverted twice, meaning that the fourth switching signal inp4 is in phase with V2.

[0063] The eleventh logic circuit 1110 includes an eighth OR gate U12, a fifth AND gate U13, and an eleventh transmission gate TG11. The eighth OR gate U12 has two inputs, receiving the level signals corresponding to the second bit V1 and the third bit V0 of the three-bit binary code, respectively, and performing a logical OR operation on V1 and V0. The output of the eighth OR gate U12 is connected to the first input of the fifth AND gate U13, and the second input of the fifth AND gate U13 receives the level signal corresponding to the first bit V2 of the three-bit binary code. The fifth AND gate U13 performs a logical AND operation on the output of the eighth OR gate U12 and V2, and the output is connected to the input of the eleventh transmission gate TG11. The output of the eleventh transmission gate TG11 outputs the fifth switch signal inp5.

[0064] The twelfth logic circuit 1120 includes a sixth AND gate U14 and a twelfth transmission gate TG12. The sixth AND gate U14 has two inputs, receiving the level signals corresponding to the first bit V2 and the second bit V1 of the three-bit binary code, respectively, and performing a logical AND operation on V2 and V1. The output of the sixth AND gate U14 is connected to the input of the twelfth transmission gate TG12. The output of the twelfth transmission gate TG12 outputs the sixth switching signal inp6.

[0065] The voltage output circuit 210 is used to provide the operating voltage for the pull-up resistor switch array 220, and can employ corresponding bias circuits, voltage regulator circuits, etc. In an optional embodiment, such as... Figure 18 As shown, the voltage output circuit 210 includes a third transistor M3; The first terminal of the third transistor M3 is connected to the positive voltage terminal VDD, and the second terminal of the third transistor M3 forms the output terminal of the voltage output circuit 210. The control terminal of the third transistor M3 is used to receive the bias voltage Vreps. The third transistor M3 operates in the subthreshold region, and its drain current varies exponentially with the gate-source voltage. When the device current fluctuation is small and at least one switch in the pull-up resistor switch array 220 is turned on, the gate-source voltage difference of the third transistor M3 can be considered to remain basically constant, and therefore the source voltage is approximately constant.

[0066] The third transistor M3 can be either an NMOS or a PMOS transistor. When an NMOS transistor is used, the drain of the third transistor M3 is connected to the positive voltage terminal VDD, the source forms the output terminal, and the gate receives the bias voltage Vreps. In this case, the third transistor M3 is a common-drain structure, i.e., a source follower, and the output voltage Vs is equal to the bias voltage Vreps minus the gate-source voltage. When a PMOS transistor is used, the source of the third transistor M3 is connected to the positive voltage terminal VDD, the drain forms the output terminal, and the gate receives the bias voltage Vreps. In this case, the third transistor M3 is a common-source current source load. The specific type of transistor used depends on the system power supply architecture and the design of the bias voltage circuit 3, and this embodiment does not limit it.

[0067] Each of the three level generating units 200 includes a voltage output circuit 210, meaning that the three third transistors M3 provide pull-up operating voltages for channels A, B, and C, respectively. The control terminals of all three third transistors M3 are connected to the same bias voltage Vreps, therefore the pull-up operating voltages of the three channels have the same bias condition. Ideally, the source voltages of the three channels are approximately equal, denoted as Vs. The voltage matching degree between the three channels depends on the device matching of the three third transistors M3. In integrated circuit manufacturing, device matching accuracy can be improved through common-center placement or cross-coupling placement.

[0068] Furthermore, in order to provide the bias voltage Vreps, in an optional embodiment, the multi-line signal output circuit further includes: The bias voltage circuit 3 is connected to the voltage output circuit 210. The bias voltage circuit 3 is used to output the bias voltage Vreps, thereby providing a stable bias voltage Vreps for the third transistor M3 in the voltage output circuit 210.

[0069] In an alternative embodiment, such as Figure 19As shown, the bias voltage circuit 3 includes a third resistor R3, a fourth resistor R4, a fourth transistor M4, and an operational amplifier OPA; The non-inverting input of the operational amplifier OPA is used to input the reference voltage Vcm. The output of the operational amplifier OPA is connected to the control terminal of the fourth transistor M4. The first terminal of the fourth transistor M4 is connected to the positive voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3, the first terminal of the fourth resistor R4, and the inverting input of the operational amplifier OPA are connected. The second terminal of the fourth resistor R4 is grounded.

[0070] In this embodiment, the operational amplifier (OPA) operates in negative feedback mode. According to the virtual short principle, the voltage at the non-inverting input terminal is equal to the voltage at the inverting input terminal, i.e., Vfb equals Vcm. The voltage at the feedback node Vfb is determined by the voltage division of the output current of the fourth transistor M4 by the third resistor R3 and the fourth resistor R4. Let the drain current of the fourth transistor M4 be Id, the resistance of the third resistor R3 be R3, and the resistance of the fourth resistor R4 be R4, then Vfb equals Id. R4. Since Vfb equals Vcm, Id equals Vcm / R4. The voltage across the third resistor R3 is Id. R3 is Vcm multiplied by R3 / R4. The source voltage of the fourth transistor M4, which is the voltage at the first terminal of the third resistor R3, is Vfb plus the voltage across the third resistor R3.

[0071] The fourth transistor M4 and the third transistor M3 in the voltage output circuit 210 form a current mirror relationship, both having the same gate bias voltage Vreps. When the fourth transistor M4 and the third transistor M3 have the same aspect ratio and operate in the same region, the drain current of the third transistor M3 is equal to the drain current of the fourth transistor M4, i.e., equal to Vcm / R4. By adjusting the resistance ratio of the third resistor R3 and the fourth resistor R4, the operating point of the fourth transistor M4 can be set, thereby setting the bias current of the third transistor M3.

[0072] The fourth transistor M4 operates in the subthreshold region, and its drain current Id This formula shows that there is an exponential relationship between the drain current and the gate-source voltage, where I0 is a parameter proportional to the transistor width-to-length ratio, and V... GS V is the voltage difference between the gate and the source. T Let VT be the thermal voltage, and n be the non-ideality factor. The thermal voltage VT is proportional to the absolute temperature and is approximately 26 millivolts at room temperature. The non-ideality factor n reflects the degree to which the subthreshold current deviates from the ideal exponential relationship, and is typically between 1 and 2.

[0073] The bias voltage Vreps generated by bias voltage circuit 3 is connected to the gate of the third transistor M3 in the three level generating units 200, providing a uniform bias for the three channels. Through the negative feedback of operational amplifier OPA, the bias voltage Vreps can track changes in the reference voltage Vcm and maintain a relatively stable bias current under fluctuations in power supply voltage and temperature. The reference voltage Vcm can be generated by a bandgap reference circuit, which can provide a temperature-independent reference voltage Vcm, thereby further improving the stability of the bias.

[0074] The three-channel level generating unit 200 can output different voltage signals, thereby forming a variety of voltage signals with different linear states. In an optional embodiment, each level generating unit 200 outputs seven voltage signals of different magnitudes according to two different sets of switching signals, and the three-channel level generating units 200 combine to generate eighteen sets of voltage signals with different linear states.

[0075] In this embodiment, the generation principle of the seventh-order line signal level and the process of the three-channel level generating unit 200 generating eighteen sets of line states are described in detail, in conjunction with the above embodiments.

[0076] The output voltage of each level generating unit 200 is determined by the voltage division between the output voltage Vs and the ground terminal by the pull-up equivalent impedance and the pull-down equivalent impedance. Assume that k pull-up resistor switches 221 in the pull-up resistor switch array 220 are conducting, and 6-k pull-down resistor switches 231 in the pull-down resistor switch array 230 are conducting. The preset impedance of a single conducting branch is Rsw. Then, the pull-up equivalent impedance is Rsw divided by k, and the pull-down equivalent impedance is Rsw divided by 6-k. The output voltage equals Vs multiplied by the pull-down equivalent impedance divided by the sum of the pull-up and pull-down equivalent impedances. Substituting into the impedance expression, the output voltage equals Vs multiplied by k divided by 6. Therefore, when k takes the values ​​0, 1, 2, 3, 4, 5, and 6, the output voltages are 0, 1 / 6Vs, 2 / 6Vs, 1 / 6Vs, 4 / 6Vs, 5 / 6Vs, and Vs, respectively.

[0077] In the actual circuit, the output terminal is also connected to the common-mode voltage terminal through a matching resistor Rz, and the voltage at the common-mode voltage terminal is Vcptx. Considering the matching resistor Rz, the calculation of the output voltage requires the application of Kirchhoff's voltage law and Kirchhoff's current law.

[0078] Taking a preset impedance of 300Ω and a matching resistor Rz of 50Ω as an example, the calculation results of three typical linear combinations are described separately.

[0079] The first linear combination: the voltage at point A is LSL0, the voltage at point B is LSL3, and the voltage at point C is LSL6. In this case, all pull-down resistors 231 in channel A are on, and all pull-up resistors 221 are off. The equivalent impedance between point A and ground is 50Ω, i.e., six 300Ω parallel circuits. In channel B, three pull-up resistors 221 and three pull-down resistors 231 are on. The equivalent impedance between point B and Vs is 100Ω, i.e., three 300Ω parallel circuits. The equivalent impedance between point B and ground is also 100Ω. In channel C, all pull-up resistors 221 are on, and all pull-down resistors 231 are off. The equivalent impedance between point C and Vs is 50Ω. According to Kirchhoff's laws, the voltage at point A is 0.250Vs, the voltage at point B is 0.500Vs, the voltage at point C is 0.750Vs, and the common-mode voltage Vcptx is 0.500Vs. The voltages at points A, B, and C can be arranged in six non-repeating combinations using LSL0, LSL3, and LSL6, resulting in six linear states.

[0080] The second linear combination: Voltage at point A is LSL1, voltage at point B is LSL2, and voltage at point C is LSL6. In this case, one of the pull-up resistors 221 in channel A is conducting, and five of the pull-down resistors 231 are conducting. The equivalent impedance between point A and Vs is 300Ω, and the equivalent impedance between point A and ground is 60Ω, i.e., five 300Ω parallel circuits. In channel B, two of the pull-up resistors 221 are conducting, and four of the pull-down resistors 231 are conducting. The equivalent impedance between point B and Vs is 150Ω, and the equivalent impedance between point B and ground is 75Ω. In channel C, all pull-up resistors 221 are conducting, and all pull-down resistors 231 are off. The equivalent impedance between point C and Vs_C is 50Ω. According to Kirchhoff's laws, the voltage at point A is 0.333Vs, the voltage at point B is 0.417Vs, and the voltage at point C is 0.750Vs. The voltages at points A, B, and C can be arranged in LSL1, LSL2, and LSL6 without repetition to generate six more linear states.

[0081] The third linear combination: the voltage at point A is LSL0, the voltage at point B is LSL4, and the voltage at point C is LSL5. In this case, all pull-up resistors 221 in channel A are off, and all pull-down resistors 231 are on. The equivalent impedance between point A and ground is 50Ω. In channel B, four pull-up resistors 221 are on, and two pull-down resistors 231 are on. The equivalent impedance between point B and Vs is 75Ω, and the equivalent impedance between point B and ground is 150Ω. In channel C, five pull-up resistors 221 are on, and one pull-down resistor 231 is on. The equivalent impedance between point C and Vs is 60Ω, and the equivalent impedance between point C and ground is 300Ω. According to Kirchhoff's laws, the voltage at point A is 0.250Vs, the voltage at point B is 0.583Vs, and the voltage at point C is 0.667Vs. The voltages at points A, B, and C can be arranged in LSL0, LSL4, and LSL5 without repetition, which can also generate six more linear states.

[0082] Each of the three line state combinations described above generates six line states, for a total of eighteen line states. The seventh-order line signal levels LSL0 to LSL6 are spaced at 1 / 12Vs intervals, corresponding to voltages of 0.250Vs, 0.333Vs, 0.417Vs, 0.500Vs, 0.583Vs, 0.667Vs, and 0.750Vs, respectively. By flexibly combining the seventh-order line signal levels, eighteen line states can be formed, which can adapt to the transmission requirements of the C-PHY 3.1 protocol.

[0083] A second aspect of the present invention provides an image sensor, which includes a multi-line signal output circuit. The specific structure of the multi-line signal output circuit is as described in the above embodiments. Since this image sensor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0084] In this embodiment, the image sensor typically includes a pixel array, row decoders, column decoders, an analog front-end, an analog-to-digital converter, an image signal processor, and an output interface. The output interface can adopt the MIPI C-PHY protocol to transmit high-speed image data via three-wire differential pairs. The multi-line signal output circuit provided in this application is integrated into the transmitting end of the output interface and is used to encode digital image data into a seventh-order line signal level and drive the transmission line.

[0085] In the image sensor, the outputs of the three level generation units 200 correspond to the three transmission lines of the C-PHY interface, and these three transmission lines are connected to the common-mode voltage terminal through a matching resistor Rz. The signal conversion circuit 1 receives the three-bit binary code encoded from the image data and converts it into six switching signals, controlling the level generation units 200 to output voltage signals of the corresponding order. The three output signals are combined to form the eighteen line states defined by the C-PHY 3.1 protocol, enabling high-speed data transmission.

[0086] This image sensor can be applied to devices requiring high-speed image transmission, such as smartphones, tablets, laptops, automotive cameras, industrial cameras, and security monitoring systems. Because the C-PHY 3.1 protocol can transmit more data at the same symbol rate, this image sensor can support higher resolution and higher frame rate image output while maintaining compatibility with the hardware pins of previous C-PHY protocols.

[0087] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A multi-line signal output circuit, characterized in that, include: The signal conversion circuit includes three signal conversion units. Each signal conversion unit is used to receive a three-bit binary digital code and convert it into two corresponding sets of switch signals. Each set of switch signals includes six switch signals. A multi-voltage generation circuit includes three level generation units, each connected to a signal conversion unit. The output of each level generation unit is connected to a common-mode voltage terminal via a matching resistor. The three level generation units are used to output multiple sets of voltage signals with different linear states. Each level generation unit includes: Voltage output circuit, used to output working voltage; A pull-up resistor switch array is connected between the voltage output circuit and the output terminal of the level generating unit. The pull-up resistor switch array includes six pull-up resistor switches connected in parallel. The six pull-up resistor switches are used to receive the six switch signals of one group and trigger the on / off state accordingly. When each pull-up resistor switch is turned on, it switches the output preset impedance. A pull-down resistor switch array is connected between the output terminal and the ground terminal of the level generating unit. The pull-down resistor switch array includes six parallel pull-down resistor switches. The six pull-down resistor switches are used to receive the switching signals of another set of six switches and trigger the on / off state accordingly. When each pull-down resistor switch is turned on, it switches the output preset impedance. The switching state of each pull-up resistor switch is opposite to the switching state of the corresponding pull-down resistor switch.

2. The multi-line signal output circuit as described in claim 1, characterized in that, The pull-up resistor switch includes a first transistor and a first resistor connected in series between the voltage output circuit and the output terminal of the level generating unit; The pull-down resistor switch includes a second resistor and a second transistor connected in series between the output terminal of the level generating unit and the ground terminal.

3. The multi-line signal output circuit as described in claim 2, characterized in that, The resistance of the first resistor is equal to the resistance of the second resistor, and the resistance of the first transistor is equal to the resistance of the second transistor.

4. The multi-line signal output circuit as described in claim 2, characterized in that, The level states of the six switching signals in one group are opposite to those of the six switching signals in another group, and the switching type of the first transistor is the same as that of the second transistor. Alternatively, the level states of the six switching signals in one group are identical to the level states of the six switching signals in another group, and the switching type of the first transistor is opposite to the switching type of the second transistor.

5. The multi-line signal output circuit as described in claim 4, characterized in that, The level states of the six switching signals in one group are opposite to those of the six switching signals in the other group. The signal conversion unit includes: The first logic circuit is used to receive the level signals corresponding to each bit in the three-bit binary code, and to logically convert and output a first switch signal and a first inverted switch signal that is inverse of the first switch signal. The second logic circuit is used to receive the level signals corresponding to the first and second bits of the three-bit binary code, and to logically convert and output a second switch signal and a second inverted switch signal that is inverse of the second switch signal. The third logic circuit is used to receive the level signals corresponding to each bit in the three-bit binary code, and to logically convert and output a third switch signal and a third inverted switch signal that is inverted by the third switch signal. The fourth logic circuit is used to receive the level signal corresponding to the first bit of the three-bit binary code, and to logically convert and output a fourth switch signal and a fourth inverted switch signal that is inverted by the fourth switch signal. The fifth logic circuit is used to receive the level signals corresponding to each bit in the three-bit binary code, and to logically convert and output a fifth switch signal and a fifth inverted switch signal that is inverted by the fifth switch signal; The sixth logic circuit is used to receive the level signals corresponding to the first and second bits of the three-bit binary code, and to logically convert and output a sixth switch signal and a sixth inverted switch signal that is inverse of the sixth switch signal.

6. The multi-line signal output circuit as described in claim 5, characterized in that, The first logic circuit includes a first OR gate, a first transmission gate, and a first inverter; The input terminals of the first OR gate respectively receive the level signals corresponding to each bit in the three-bit binary code. The output terminal of the first OR gate, the input terminal of the first transmission gate, and the input terminal of the first inverter are connected. The output terminal of the first transmission gate is used to output the first switch signal, and the output terminal of the first inverter is used to output the first inverting switch signal. The second logic circuit includes a second OR gate, a second transmission gate, and a second inverter; The input terminals of the second OR gate are respectively the level signals corresponding to the first and second bits of the three-bit binary code. The output terminal of the second OR gate, the input terminal of the second transmission gate, and the input terminal of the second inverter are connected. The output terminal of the second transmission gate is used to output the second switch signal, and the output terminal of the second inverter is used to output the second inverting switch signal. The third logic circuit includes a first AND gate, a third OR gate, a third transmission gate, and a third inverter; The input terminal of the first AND gate is used to receive the level signals corresponding to the second and third bits of the three-bit binary code. The output terminal of the first AND gate is connected to the first input terminal of the third OR gate. The second input terminal of the third OR gate is used to receive the level signal corresponding to the first bit of the three-bit binary code. The output terminal of the third OR gate, the input terminal of the third transmission gate, and the input terminal of the third inverter are connected. The output terminal of the third transmission gate is used to output the third switch signal. The output terminal of the third inverter is used to output the third inverting switch signal. The fourth logic circuit includes a fourth inverter, a fifth inverter, a sixth inverter, and a fourth transmission gate; The input terminal of the fourth inverter is used to receive the level signal corresponding to the first bit of the three-bit binary code. The input terminal of the fourth inverter is connected to the input terminal of the fifth inverter. The output terminal of the fifth inverter, the input terminal of the fourth transmission gate, and the input terminal of the sixth inverter are connected. The output terminal of the fourth transmission gate is used to output the fourth switch signal. The output terminal of the sixth inverter is used to output the fourth inverting switch signal. The fifth logic circuit includes a fourth OR gate, a second AND gate, a fifth transmission gate, and a seventh inverter; The input terminal of the fourth OR gate is used to receive the level signals corresponding to the second and third bits of the three-bit binary code. The output terminal of the fourth OR gate is connected to the first input terminal of the second AND gate. The second input terminal of the second AND gate is used to receive the level signal corresponding to the first bit of the three-bit binary code. The output terminal of the second AND gate, the input terminal of the fifth transmission gate, and the input terminal of the seventh inverter are connected. The output terminal of the fifth transmission gate is used to output the fifth switch signal. The output terminal of the seventh inverter is used to output the fifth inverting switch signal. The sixth logic circuit includes a third AND gate, a sixth transmission gate, and an eighth inverter; The input terminal of the third AND gate is used to receive the level signals corresponding to the first and second bits of the three-bit binary code. The output terminal of the third AND gate, the input terminal of the sixth transmission gate, and the input terminal of the eighth inverter are connected. The output terminal of the sixth transmission gate is used to output the sixth switch signal, and the output terminal of the eighth inverter is used to output the sixth inverting switch signal.

7. The multi-line signal output circuit as described in claim 4, characterized in that, The level state of the six switching signals in one group is the same as the level state of the six switching signals in another group. The signal conversion unit includes: The seventh logic circuit is used to receive the level signals corresponding to each bit in the three-bit binary code and to logically convert and output the first switch signal. The eighth logic circuit is used to receive the level signals corresponding to the first and second bits of the three-bit binary code, and to logically convert and output the second switching signal. The ninth logic circuit is used to receive the level signals corresponding to each bit in the three-bit binary code and to logically convert and output the third switch signal; The tenth logic circuit is used to receive the level signal corresponding to the first bit of the three-bit binary code and to logically convert and output the fourth switch signal. The eleventh logic circuit is used to receive the level signals corresponding to each bit in the three-bit binary code and to logically convert and output the fifth switch signal. The twelfth logic circuit is used to receive the level signals corresponding to the first and second bits of the three-bit binary code, and to logically convert and output the sixth switch signal.

8. The multi-line signal output circuit as described in claim 7, characterized in that, The seventh logic circuit includes a fifth OR gate and a seventh transmission gate; The input terminals of the fifth OR gate receive the level signals corresponding to each bit in the three-bit binary code, and the output terminal of the fifth OR gate is connected to the input terminal of the seventh transmission gate. The output terminal of the seventh transmission gate is used to output the first switch signal. The eighth logic circuit includes a sixth OR gate and an eighth transmission gate; The input terminals of the sixth OR gate are respectively the level signals corresponding to the first and second bits of the three-bit binary code. The output terminal of the sixth OR gate is connected to the input terminal of the eighth transmission gate. The output terminal of the eighth transmission gate is used to output the second switching signal. The ninth logic circuit includes a fourth AND gate, a seventh OR gate, and a ninth transmission gate; The input terminal of the fourth AND gate is used to receive the level signals corresponding to the second and third bits of the three-bit binary code. The output terminal of the fourth AND gate is connected to the first input terminal of the seventh OR gate. The second input terminal of the seventh OR gate is used to receive the level signal corresponding to the first bit of the three-bit binary code. The output terminal of the seventh OR gate is connected to the input terminal of the ninth transmission gate. The output terminal of the ninth transmission gate is used to output the third switch signal. The tenth logic circuit includes a ninth inverter, a tenth inverter, and a tenth transmission gate; The input terminal of the ninth inverter is used to receive the level signal corresponding to the first bit of the three-bit binary code. The input terminal of the ninth inverter is connected to the input terminal of the tenth inverter. The output terminal of the tenth inverter is connected to the input terminal of the tenth transmission gate. The output terminal of the tenth transmission gate is used to output the fourth switch signal. The eleventh logic circuit includes an eighth OR gate, a fifth AND gate, and an eleventh transmission gate; The input terminal of the eighth OR gate is used to receive the level signals corresponding to the second and third bits of the three-bit binary code. The output terminal of the eighth OR gate is connected to the first input terminal of the fifth AND gate. The second input terminal of the fifth AND gate is used to receive the level signal corresponding to the first bit of the three-bit binary code. The output terminal of the fifth AND gate is connected to the input terminal of the eleventh transmission gate. The output terminal of the eleventh transmission gate is used to output the fifth switch signal. The twelfth logic circuit includes a sixth AND gate and a twelfth transmission gate; The input terminal of the sixth AND gate is used to receive the level signal corresponding to the first and second bits of the three-bit binary code. The output terminal of the sixth AND gate is connected to the input terminal of the twelfth transmission gate, and the output terminal of the twelfth transmission gate is used to output the sixth switch signal.

9. The multi-line signal output circuit as described in claim 1, characterized in that, The voltage output circuit includes a third transistor; The first terminal of the third transistor is connected to the positive voltage terminal, the second terminal of the third transistor constitutes the output terminal of the voltage output circuit, and the control terminal of the third transistor is used to receive the bias voltage.

10. The multi-line signal output circuit as described in claim 9, characterized in that, The multi-line signal output circuit also includes: A bias voltage circuit is connected to the voltage output circuit, and the bias voltage circuit is used to output the bias voltage.

11. The multi-line signal output circuit as described in claim 10, characterized in that, The bias voltage circuit includes a third resistor, a fourth resistor, a fourth transistor, and an operational amplifier; The non-inverting input terminal of the operational amplifier is used to input a reference voltage. The output terminal of the operational amplifier is connected to the control terminal of the fourth transistor. The first terminal of the fourth transistor is connected to the positive voltage terminal. The second terminal of the fourth transistor is connected to the first terminal of the third resistor. The second terminal of the third resistor, the first terminal of the fourth resistor, and the inverting input terminal of the operational amplifier are connected. The second terminal of the fourth resistor is grounded.

12. The multi-line signal output circuit according to any one of claims 1 to 11, characterized in that, Each of the level generating units outputs seven voltage signals of different magnitudes based on two different sets of switching signals. The three level generating units combine to generate eighteen sets of voltage signals with different linear states.

13. An image sensor, characterized in that, It includes the multi-line signal output circuit as described in any one of claims 1 to 12.

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