A low noise sense circuit and method based on clock-flip counting

Abstract

The application discloses a low-noise readout circuit and method based on clock flip counting, wherein a clock generator generates first and second clock signals with opposite phases; a slope generator generates coarse and fine quantization slope signals; a reset level quantization stage compares a pixel signal to be quantized with the fine quantization slope signal; a signal level coarse quantization stage compares the pixel signal to be quantized with the coarse quantization slope signal; a signal level fine quantization stage compares the pixel signal to be quantized with the sum of the fine quantization slope signal and the coarse quantization step voltage value; a counter alternately receives the first and second clock signals for counting, and quantizes the pixel signal to be quantized multiple times based on the comparison result; the reset level quantization stage and the signal level fine quantization stage alternately use the first and second clock signals for counting, and the odd-time quantization uses the first clock signal for counting, and the even-time quantization uses the second clock signal for counting; and the signal level coarse quantization stage uses the first clock signal for counting. The application can reduce quantization error and improve readout precision.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and particularly to a low-noise readout circuit structure under imaging conditions of high-speed, high-precision CMOS image sensors, specifically to a low-noise readout circuit and method based on clock flip counting. Background Technology

[0002] Column-parallel single-slope analog-to-digital converters (SSADCs) have been widely used in CMOS image sensors (CIS) due to their simple structure and high linearity. However, with the rapid development of emerging fields such as artificial intelligence, signal strength is constantly decreasing under weak light and low-light conditions, leading to an increasing demand for low-noise readout circuits. Noise in traditional column-parallel SSADCs has become a significant factor affecting image quality.

[0003] Noise in CMOS image sensors primarily originates from two sources: pattern noise and random noise. Pattern noise is mainly composed of Fixed Pattern Noise (FPN), which arises primarily from differences in pixel doping concentration and process characteristics. Random noise mainly includes thermal noise, 1 / f noise, RTS noise, and shot noise; it is temporally random and varies between frames. Digital Correlated Multiple Sampling (D-CMS) technology can eliminate FPN and effectively suppress random noise, but it introduces quantization noise, which can cause bit errors and degrade image quality. This problem becomes particularly severe as the operating frequency and quantization accuracy of CMOS image sensors increase; therefore, achieving low-noise signal readout remains a key challenge in the development of low-noise readout circuits. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, this invention proposes a low-noise readout circuit and method based on clock-to-flip counting. This method can sequentially quantize multiple samples in D-CMS using a flip clock without increasing the extra power consumption of the counter, thereby reducing quantization error and improving the readout accuracy of the circuit.

[0005] The objective of this invention can be achieved through the following technical solutions.

[0006] A low-noise readout circuit based on clock-to-flip counting includes a clock generator, a ramp generator, a comparator, and a counter; the clock generator is used to generate a first clock signal and a second clock signal with opposite phases; the ramp generator is used to generate a coarse-quantized ramp signal and a fine-quantized ramp signal. The comparator's first positive input, first negative input, second positive input, and second negative input are respectively connected to a fine quantization ramp signal, the pixel signal to be quantized, a coarse quantization ramp signal, and a reference voltage signal. The comparator's output is connected to a counting switch. During the reset-level quantization phase, the reference voltage signal and the coarse quantization ramp signal remain equal, and the pixel signal to be quantized is compared with the fine quantization ramp signal. During the signal-level coarse quantization phase, the reference voltage signal and the fine quantization ramp signal remain equal, and the pixel signal to be quantized is compared with the coarse quantization ramp signal. During the signal-level fine quantization phase, the pixel signal to be quantized is compared with the sum of the fine quantization ramp signal and the coarse quantization step voltage value. The counter is constructed using a chain of D flip-flops and is divided into a fine quantization section and a coarse quantization section. The counter sequentially receives a first clock signal and a second clock signal with opposite phases to count, and completes multiple sampling quantizations of the pixel signal to be quantized based on the comparison results of the comparator. Specifically, in the reset level quantization stage and the signal level fine quantization stage, the first clock signal and the second clock signal are used alternately for counting. Odd-numbered sampling quantizations use the first clock signal for counting, and even-numbered sampling quantizations use the second clock signal for counting. In the signal level coarse quantization stage, the first clock signal is used for counting.

[0007] Furthermore, in the D flip-flop chain of the fine quantization section, the clock input pin of the first-stage D flip-flop is connected to the fine quantization switch via a bit-inverting module, and the clock input pins of the remaining stages of the D flip-flop are all connected to the inverted output pin of the previous stage of the D flip-flop via a bit-inverting module. The inverted output pin of the last stage of the D flip-flop is connected to the first input of the multiplexer, and the second input of the multiplexer is connected to the coarse quantization switch. In the D flip-flop chain of the coarse quantization section, the clock input pin of the first-stage D flip-flop is connected to the output of the multiplexer via a bit-inverting module, and the clock input pins of the remaining stages of the D flip-flop are all connected to the inverted output pin of the previous stage of the D flip-flop via a bit-inverting module. The inverted output pin and input pin of each stage of the D flip-flop are connected, and the inverted output pin of each stage of the D flip-flop in both the fine and coarse quantization sections is connected to the subsequent processing circuit via a register and a buffer. One end of the counting switch is connected to the clock generator, one end is connected to the comparator output, and the other end is connected to the fine quantization switch and the coarse quantization switch, respectively.

[0008] The objective of this invention can also be achieved through the following technical solutions.

[0009] A low-noise readout method based on clock toggle counting, applicable to the above circuit, includes the following steps: Reset phase: The comparator uses an auto-zero transistor to eliminate offset, pulls all input levels to the same potential, presets the highest bit of the fine quantization part of the counter to 1, and resets all other bits to 0; Reset level quantization stage: A comparator is used to compare the pixel signal to be quantized with the fine quantization ramp signal. Its output signal controls the counter to count multiple times, thereby realizing multiple sampling quantization of the pixel signal to be quantized. Among them, the first clock signal is used for counting the odd number of sampling quantizations, and the second clock signal is used for counting the even number of sampling quantizations. Bit-inverting stage: The counting results of the pre-counted redundant bit values ​​and reset level quantization values ​​stored in the counter are inverted bit by bit through the bit-inverting module; Signal level coarse quantization stage: A comparator is used to compare the pixel signal to be quantized with the coarse quantization ramp signal. Its output signal controls the counter to count, thereby realizing the sampling quantization of the pixel signal to be quantized. Among them, the first clock signal is used to drive the counter to perform a single count and store the coarse quantization step voltage value at the time of flip. Signal level fine quantization stage: A comparator is used to compare the pixel signal to be quantized with the sum of the fine quantization ramp signal and the coarse quantization step voltage value. Its output signal controls the counter to count multiple times, thereby realizing multiple sampling quantization of the pixel signal to be quantized. Among them, the first clock signal is used for counting the odd number of sampling quantizations, and the second clock signal is used for counting the even number of sampling quantizations. Finally, the value in the counter is discarded after removing the lower log2(m) bits, and the final quantization result is obtained; where m is the number of multiple samples.

[0010] Furthermore, during the reset level quantization phase, the reference voltage signal remains equal to the coarse quantization ramp signal; during the signal level coarse quantization phase, the reference voltage signal remains equal to the fine quantization ramp signal.

[0011] Compared with the prior art, the beneficial effects of the technical solution of the present invention are: (1) Significantly reduced quantization error rate: This invention introduces a first clock signal (CLK) and a second clock signal (NCLK) with opposite phases to alternately drive the counter during multi-sample quantization. Compared with traditional single-clock counting, this invention ensures that at any given time, the comparator flip position for at least half of the sampling counts deviates from the edge of the code value. Taking 4 samples as an example, the maximum quantization error of the traditional method can reach 4 code values, while this invention limits the maximum quantization error to within 2 code values, fundamentally suppressing the accumulation of errors caused by random noise.

[0012] (2) High efficiency in suppressing random noise: By using a clock-flipping counting mechanism, the synchronization between random noise and the counting edge is disrupted. When the comparator jitters at the code value edge due to noise in a certain sampling, the decision point of the next sampling is exactly in the level stable region due to the clock phase reversal. This complementary sampling strategy effectively filters out the random noise component in time and significantly improves the signal-to-noise ratio (SNR).

[0013] (3) Extremely low hardware overhead, which is conducive to high-density integration: Compared with the scheme of using time-to-digital converters (TDC) or other complex digital filtering algorithms to suppress quantization noise, the present invention only requires adding an inverting clock and a multiplexer (MUX) before the existing counter architecture. This design adds almost no additional transistors and power consumption, making it very suitable for CMOS image sensors with large pixel arrays and limited column area.

[0014] (4) Perfect compatibility with D-CMS technology, eliminating the hidden danger of quantization noise: The clock flip counting method proposed in this invention has a natural compatibility with digital correlation multiple sampling (D-CMS) technology. While retaining the advantages of D-CMS in eliminating fixed pattern noise (FPN), it effectively overcomes the large amount of quantization noise amplified by multiple sampling accumulation in D-CMS technology itself, and solves the problem of quantization noise degrading the imaging quality in high frame rate and high precision CIS applications.

[0015] (5) Adapting to the requirements of high-speed and high-precision imaging: With the increase of clock frequency and the decrease of operating voltage, comparators are more sensitive to noise, and the error risk of traditional counting methods increases exponentially. The flip counting method provided by this invention is not sensitive to changes in clock frequency, and can still maintain stable error suppression capability even under high-speed clock drive, which is particularly suitable for the new generation of CIS chips with high bandwidth and low voltage operation.

[0016] (6) The implementation mechanism is simple and reliable, and easy to port to the process: The present invention is based on the underlying principle of counter edge triggering, and does not involve complex analog circuit adjustment or complex digital signal processing algorithms. The scheme is implemented with pure digital logic, is not sensitive to process fluctuations, has good process robustness, and is easy to port and mass-produce between different foundries and process nodes. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the low-noise readout circuit based on clock flip counting of the present invention.

[0018] Figure 2 The basic operating timing circuit diagram of the low-noise readout circuit of this invention is shown (taking m=4 as an example).

[0019] Figure 3(a) shows the count values ​​of the traditional counting method D-CMS (taking m = 4 as an example).

[0020] Figure 3(b) shows the D-CMS count value of the clock flip counting method of the present invention (taking m = 4 as an example). Detailed Implementation

[0021] The present invention will now be further described with reference to the accompanying drawings.

[0022] like Figure 1 As shown, the low-noise readout circuit based on clock-to-flip counting of this invention mainly includes a clock generator, a ramp generator, a comparator CMP, and a counter. The clock generator is used to generate a first clock signal CLK and a second clock signal NCLK with opposite phases. The ramp generator is used to generate a coarse-quantized ramp signal V. ramp_c And fine-grained ramp signal V ramp_f .

[0023] The first positive input, first negative input, second positive input, and second negative input of the comparator CMP are respectively connected to the fine-quantization ramp signal V. ramp_f The pixel signal V to be quantized pixel Coarse quantization ramp signal V ramp_c Reference voltage signal V ref The output of the comparator CMP is connected to the counting switch S0. During the reset level quantization phase, the reference voltage signal V... ref With coarse quantization ramp signal V ramp_c To maintain equality, the pixel signal V to be quantized pixel With fine-grained ramp signal V ramp_f Comparison; during the signal level coarse quantization stage, the reference voltage signal V ref With fine-grained ramp signal V ramp_f To maintain equality, the pixel signal V to be quantized pixel With coarse quantization ramp signal V ramp_c Comparison; in the signal level fine quantization stage, the pixel signal V to be quantized is... pixel With fine-grained ramp signal V ramp_f and coarse-quantized step voltage value V c Compare the sums.

[0024] The counter is constructed using a D flip-flop chain, divided into a fine quantization section and a coarse quantization section. The counter sequentially receives a first clock signal CLK and a second clock signal NCLK with opposite phases to perform counting, and completes the quantization of the pixel signal V based on the multiple comparison results of the comparator CMP (i.e., the comparator output signal). pixelThe system performs multiple sampling quantization. The counter includes several D flip-flops, a bit-inverting module, a register, a buffer, and a multiplexer. The D flip-flops count in response to a clock signal. The bit-inverting module inverts the quantization code value of the pixel signal to be quantized during the reset phase, subtracting the quantization code value from the pixel signal during the reset phase from the final result. The register stores the quantization result, which is then driven by the buffer to output the final code value. The multiplexer switches between counting during the coarse quantization phase and the fine quantization phase. During the reset quantization phase and the fine quantization phase, the counter alternately uses the first clock signal CLK and the second clock signal NCLK for counting. Odd-numbered sampling quantizations use the first clock signal CLK, and even-numbered sampling quantizations use the second clock signal NCLK. During the coarse quantization phase, the first clock signal CLK is used for counting.

[0025] In this system, the number of D flip-flops in the coarse quantization section of the counter is equal to the number of coarse quantization bits, and the number of D flip-flops in the fine quantization section is the number of fine quantization bits plus log2(m), where m is the number of multi-sampling operations. In the fine quantization D flip-flop chain, the clock input pin "CLK" of the first-stage D flip-flop is connected to the fine quantization switch via the bit-inverting module BWI. The clock input pin "CLK" of each of the remaining D flip-flops is connected to the inverted output pin "CLK" of the previous D flip-flop via the bit-inverting module BWI. "The inverting output pin of the last stage D flip-flop" "Connect to the first input of the multiplexer MUX, and connect the second input of the multiplexer MUX to the coarse quantization switch." In the coarse-quantization section of the D flip-flop chain, the clock input pin "CLK" of the first-stage D flip-flop is connected to the output of the multiplexer MUX via the bit-inverting module BWI. The clock input pin "CLK" of all other D flip-flops is connected to the inverted output pin "CLK" of the preceding stage D flip-flop via the bit-inverting module BWI. "; The inverted output pin of each stage of the D flip-flop" "Connected to its own input pin D, it is the inverting output pin of each D flip-flop in the fine and coarse quantization sections." All connections are routed through register REG and buffer BUFFER to subsequent processing circuits; one end of the counting switch S0 is connected to the clock generator, the other end is connected to the comparator output, and the other end is connected to the fine-tuning switch. and coarse quantization switch .

[0026] Current methods primarily reduce quantization errors using Time-to-Digital Converters (TDCs), but this increases circuit complexity, further prolongs the D-CMS operating time, and results in additional area and power consumption waste. This invention proposes a low-noise readout method based on clock-to-flip counting. This method is applicable to the aforementioned low-noise readout circuits. During multi-sampling quantization, a counter sequentially receives a first clock signal and a second clock signal with opposite phases for counting. Quantization is then completed based on multiple comparisons of the pixel signal and the ramp signal by a comparator, achieving low-noise readout of the D-CMS. The specific methods of this invention include the following: Reset phase: The comparator uses an auto-zero transistor to eliminate offset, suppressing the influence of comparator offset voltage on the flip point. At the same time, all input levels are pulled to the same potential for subsequent comparisons. The highest bit of the fine quantization part in the counter is preset to 1, and all other bits are reset to 0.

[0027] For example, Figure 2 The basic timing circuit diagram of the low-noise readout circuit based on D-CMS of this invention is given, with sampling number m=4 and coarse quantization bit depth n. c =6, number of refinements n f Taking 7 (including 1 bit redundancy) as an example, fine-tuning the switch. With coarse quantization switch The timing is reversed. At this time, during the reset phase, only the 7th bit (BIT7, the bit before MUX) in the counter is preset to 1, and all other bits are reset to 0.

[0028] Reset level quantization phase: At this time, the reference voltage signal V ref With coarse quantization ramp signal V ramp_c To maintain equality and avoid affecting the comparison result, a comparator is used to quantize the pixel signal V. pixel And fine-grained ramp signal V ramp_f Comparison based on the comparator's output signal V comp_out The counter is controlled to count multiple times, thereby realizing the pixel signal V to be quantized. pixel Multiple sampling quantizations are performed; the clock signal is input to the fine quantization count bit (bit 0) of the counter to start counting. The first clock signal CLK (traditional clock signal) and the second clock signal NCLK (flip clock signal) are selected in turn by the first clock selection signal C1 and the second clock selection signal C2 to drive the counter to count. When C1 is valid, CLK is selected and when C2 is valid, NCLK is selected. Odd-numbered sampling quantizations (e.g., the 1st and 3rd times) are counted using the first clock signal CLK, and even-numbered sampling quantizations (e.g., the 2nd and 4th times) are counted using the second clock signal NCLK.

[0029] Bit-inverting stage: The count results of the pre-counted redundant bit values ​​and reset level quantization values ​​stored in the counter are inverted bit by bit through the bit-inverting module BWI, so as to directly eliminate the D-CMS and redundant bit count values ​​through the circuit.

[0030] Signal level coarse quantization stage: At this time, the reference voltage signal V ref With fine-grained ramp signal V ramp_f To maintain equality and avoid affecting the comparison result, a comparator is used to quantize the pixel signal V. pixel and coarse quantization ramp signal V ramp_c Comparison based on the comparator's output signal V comp_out The counter is controlled to count, thereby realizing the pixel signal V to be quantized. pixel Sampling quantization. Due to the large step voltage difference ΔV of the coarse slope, only one sampling is performed in D-CMS. In order to directly participate in D-CMS calculation, the clock signal is directly connected to the coarse quantization counter bit (e.g., bit 8 in the figure) to start coarse quantization counting. The first clock signal CLK (traditional clock signal) is used to drive the counter for single counting and store the coarse quantization step voltage value V at the time of the down-flip. c .

[0031] Signal level fine quantization stage: A comparator is used to quantize the pixel signal V. pixel With fine-grained ramp signal V ramp_f and the coarse step voltage value V during the flip. c Compare the sums (i.e., V) pixel With V ramp_f +V c (Comparison), the purpose is to refine the quantized ramp signal V ramp_f Shift to the pixel signal V to be quantized pixel The interval in which it is located. Based on the comparator's output signal V comp_out The counter is controlled to count multiple times, thereby realizing the pixel signal V to be quantized. pixel Multiple sampling quantizations are performed. The clock signal is connected to the fine quantization counter bit (bit 0 in the figure) to start counting. The first clock signal CLK (traditional clock signal) and the second clock signal NCLK (flip clock signal) are selected in turn by the first clock selection signal C1 and the second clock selection signal C2 to drive the counter to count. When C1 is valid, CLK is selected and when C2 is valid, NCLK is selected. Odd-numbered sampling quantizations use the first clock signal CLK for counting, and even-numbered sampling quantizations use the second clock signal NCLK for counting.

[0032] Because random noise interference can cause a quantization dead zone when concatenating coarse and fine quantization code values ​​between two SS ADC steps, an extra 1 bit is added as a redundancy bit in the fine quantization part. That is, the fine quantization range is increased by an extra 0.5ΔV above and below. The addition of the redundancy bit can avoid the generation of quantization dead zone, but this extra count value needs to be eliminated by calculation, that is, 1 needs to be subtracted from the bit before the multiplexer MUX (e.g., the 7th bit in the figure, Bit7). Finally, the value in the counter is discarded after removing the lower log2(m) bits (e.g., log2(4)=2) to obtain the final quantization result read after D-CMS.

[0033] Compared to the counters in traditional readout circuits, the core idea of ​​this invention is to use two clock signals with opposite phases to count sequentially, thereby suppressing the influence of random noise on the quantization results of the counter. When the comparator flips at the code value edge of a traditional counter, due to the influence of random noise, each sample in D-CMS may yield different results. The more samples taken, the greater the possibility of accumulated bit errors. Taking the number of samples m=4 as an example, the counting result of the traditional counting method is shown in Figure 3(a), where the sum of the 4 counts may produce a code value with a maximum error of 4. The clock-flipping counting method proposed in this invention, as shown in Figure 3(b), ensures that at least half of the flip positions are not at the code value edge position at any given time, and the sum of the 4 counts may only produce a code value with a maximum error of 2. As the clock frequency increases, the reduction in bit errors by the clock-flipping counting method becomes more significant compared to the traditional counting method, reducing the bit error problem that may be caused by random noise.

[0034] This invention proposes a toggle counting method based on the edge-triggered principle of a counter. By using two completely opposite clocks to quantize the multi-sampled signal in turn, the comparator flip position for at least half of the quantization cycles is not at the edge of the code value. This greatly reduces the bit error problem caused by random noise, realizing a low-noise readout circuit for CMOS image sensors, especially under high-speed and high-precision imaging conditions.

[0035] Although the functions and working processes of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the specific functions and working processes described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these are within the protection scope of the present invention.

Claims

1. A low-noise readout circuit based on clock-to-flip counting, characterized in that, It includes a clock generator, a ramp generator, a comparator, and a counter; the clock generator is used to generate a first clock signal and a second clock signal with opposite phases; the ramp generator is used to generate a coarse ramp signal and a fine ramp signal; The comparator's first positive input, first negative input, second positive input, and second negative input are respectively connected to a fine quantization ramp signal, the pixel signal to be quantized, a coarse quantization ramp signal, and a reference voltage signal. The comparator's output is connected to a counting switch. During the reset-level quantization phase, the reference voltage signal and the coarse quantization ramp signal remain equal, and the pixel signal to be quantized is compared with the fine quantization ramp signal. During the signal-level coarse quantization phase, the reference voltage signal and the fine quantization ramp signal remain equal, and the pixel signal to be quantized is compared with the coarse quantization ramp signal. During the signal-level fine quantization phase, the pixel signal to be quantized is compared with the sum of the fine quantization ramp signal and the coarse quantization step voltage value. The counter is constructed using a chain of D flip-flops and is divided into a fine quantization section and a coarse quantization section. The counter sequentially receives a first clock signal and a second clock signal with opposite phases to count, and completes multiple sampling quantizations of the pixel signal to be quantized based on the comparison results of the comparator. Specifically, in the reset level quantization stage and the signal level fine quantization stage, the first clock signal and the second clock signal are used alternately for counting. Odd-numbered sampling quantizations use the first clock signal for counting, and even-numbered sampling quantizations use the second clock signal for counting. In the signal level coarse quantization stage, the first clock signal is used for counting.

2. The low-noise readout circuit based on clock-to-flip counting according to claim 1, characterized in that, In the fine quantization section's D flip-flop chain, the clock input pin of the first-stage D flip-flop is connected to the fine quantization switch via a bit-inverting module. The clock input pins of all other D flip-flops are connected to the inverted output pin of the preceding stage D flip-flop via bit-inverting modules. The inverted output pin of the last stage D flip-flop is connected to the first input of a multiplexer, and the second input of the multiplexer is connected to the coarse quantization switch. In the coarse quantization section's D flip-flop chain, the clock input pin of the first-stage D flip-flop is connected to the output of a multiplexer via a bit-inverting module. The clock input pins of all other D flip-flops are connected to the inverted output pin of the preceding stage D flip-flop via bit-inverting modules. The inverted output pin and input pin of each stage D flip-flop are connected. The inverted output pin of each stage D flip-flop in both the fine and coarse quantization sections is connected to subsequent processing circuits via registers and buffers. One end of the counting switch is connected to the clock generator, one end is connected to the comparator output, and the other end is connected to the fine quantization switch and the coarse quantization switch, respectively.

3. A low-noise readout method based on clock-to-flip counting, applicable to the circuit described in any one of claims 1 or 2, characterized in that, Includes the following processes: Reset phase: The comparator uses an auto-zero transistor to eliminate offset, pulls all input levels to the same potential, presets the highest bit of the fine quantization part of the counter to 1, and resets all other bits to 0; Reset level quantization stage: A comparator is used to compare the pixel signal to be quantized with the fine quantization ramp signal. Its output signal controls the counter to count multiple times, thereby realizing multiple sampling quantization of the pixel signal to be quantized. Among them, the first clock signal is used for counting the odd number of sampling quantizations, and the second clock signal is used for counting the even number of sampling quantizations. Bit-inverting stage: The counting results of the pre-counted redundant bit values ​​and reset level quantization values ​​stored in the counter are inverted bit by bit through the bit-inverting module; Signal level coarse quantization stage: A comparator is used to compare the pixel signal to be quantized with the coarse quantization ramp signal. Its output signal controls the counter to count, thereby realizing the sampling quantization of the pixel signal to be quantized. Among them, the first clock signal is used to drive the counter to perform a single count and store the coarse quantization step voltage value at the time of flip. Signal level fine quantization stage: A comparator is used to compare the pixel signal to be quantized with the sum of the fine quantization ramp signal and the coarse quantization step voltage value. Its output signal controls the counter to count multiple times, thereby realizing multiple sampling quantization of the pixel signal to be quantized. Among them, the first clock signal is used for counting the odd number of sampling quantizations, and the second clock signal is used for counting the even number of sampling quantizations. Finally, the value in the counter is discarded after removing the lower log2(m) bits, and the final quantization result is obtained; where m is the number of multiple samples.

4. The low-noise readout method based on clock flip counting according to claim 1, characterized in that, During the reset level quantization phase, the reference voltage signal remains equal to the coarse quantization ramp signal; during the signal level coarse quantization phase, the reference voltage signal remains equal to the fine quantization ramp signal.

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