A lightweight neural network internet of things intrusion detection method for low-power devices

Abstract

The application provides a lightweight neural network Internet of Things intrusion detection method for low-power equipment, and belongs to the fields of Internet of Things network security and edge lightweight deep learning. First, the five-tuple traffic of the Internet of Things is normalized, sparse noise is preprocessed, and redundant empty packets are removed. A lightweight backbone network is constructed by combining a segmented deep separable convolution with one-dimensional channel attention, and a joint compression strategy is adopted in combination with quantization and pruning. The edge local offline reasoning is adopted, and the cloud computing power support is not required. The model parameter quantity is compressed to be less than or equal to 128 KB, the single traffic reasoning power consumption is less than 2.1 mW, the intrusion detection accuracy is more than 96.7%, the method is suitable for low-power Internet of Things terminals without an operating system, and the pain points of the three resources of traditional model computing power, memory and power consumption are solved.

Description

Technical Field

[0001] This invention relates to the fields of IoT network security and edge lightweight deep learning technology, and in particular to a lightweight neural network IoT intrusion detection method for low-power devices. Background Technology

[0002] Currently, IoT terminals are widely used in smart water management, indoor sensing, and outdoor energy consumption data collection. These devices generally use low-power main control chips such as STM32 and CC2530, with memory ≤256KB, main frequency ≤72MHz, no floating-point arithmetic unit, and battery life ≥2 years. Existing IoT intrusion detection is divided into two categories: cloud detection and traditional lightweight model edge detection. Cloud detection requires continuous uploading of traffic data packets, and uplink communication power consumption accounts for 62% of the device's total power consumption, which cannot be supported by passive devices in the field. Traditional intrusion detection models based on MobileNet and one-dimensional CNN have problems such as redundant convolutional channels and excessive parameters in fully connected layers. Even after quantization, the memory still exceeds 512KB, exceeding the memory limit of low-power devices. Moreover, floating-point operations during inference will trigger chip overclocking, increasing instantaneous power consumption by more than 3 times, which can easily cause the device to power off and restart.

[0003] Meanwhile, existing lightweight networks only perform structural pruning and do not consider the characteristics of IoT traffic: IoT traffic is mainly composed of short messages and periodic heartbeats, with over 90% consisting of redundant data with fixed fields. General lightweight models cannot specifically remove redundant traffic features, leading to the problem of normal heartbeats being misidentified as scanning attacks. Furthermore, existing detection methods rely on online gradient updates, but low-power devices cannot store optimizer parameters and cannot complete local iterative updates. In summary, existing technologies suffer from four major drawbacks: excessive power consumption, memory overload, high false alarm rate, and inability to be deployed offline. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing lightweight intrusion detection models, such as high resource consumption, high communication power consumption, high false alarm rate, and inability to adapt to minimalist low-power terminals. It provides a lightweight IoT intrusion detection method that is fully local and offline, with software and hardware collaboration, achieving zero cloud interaction, extremely low memory usage, and milliwatt-level inference power consumption.

[0005] To achieve the above-mentioned objectives, the technical solution adopted by this invention is as follows:

[0006] A lightweight neural network IoT intrusion detection method for low-power devices, applied to bare-metal IoT terminals with SRAM ≤ 256KB, no hardware floating-point unit, and no operating system, includes the following steps:

[0007] S1 bypass captures the original packets of the IoT radio frequency link, extracts the five-tuple time-series traffic features, removes fixed redundant fields of the packets through static masking, and obtains fixed-point traffic features by integer shift extreme value truncation and normalization, without performing floating-point division operations throughout the process.

[0008] S2 inputs the fixed-point traffic features into a lightweight segmented attention neural network. The network includes segmented depth separable convolutional layers, a micro local channel attention module, and a two-layer sparse fully connected layer. The segmented convolutions perform independent operations on the traffic features in groups, and the local channel attention only assigns weights to intrusion-sensitive features.

[0009] S3 performs triple offline compression of the model through structured pruning, 8-bit symmetric zero-offset quantization, and weight sparsification, and then saves the model to the local Flash memory on the terminal.

[0010] The S4 terminal completes intrusion classification inference locally, performs hierarchical radio frequency blocking, minimal log storage, and scheduled batch reporting responses; all inference operations are completed locally on the terminal, without real-time cloud traffic interaction.

[0011] As an improvement, the static mask in S1 is a read-only, fixed mask with a dynamic update cycle of no less than 30 days. The static mask is generated by statistically analyzing 200 consecutive normal periodic IoT heartbeat messages with the same channel and device ID, and filtering out 16 bits or more of unchanged frame header, frame tail CRC check, and link address padding fields. Only fixed redundancy at the link layer is removed, without modifying the application layer payload fields. The overall redundant field removal rate of the message is consistently no less than 41%.

[0012] The extreme value truncation normalization uses a right shift of 3 bits integer shift operation, which only maps the flow characteristics within the range of [0.03, 11.2]. Characteristics outside the range are directly truncated to the extreme values ​​of the range. Finally, the floating-point characteristics are uniformly mapped to 4-bit unsigned fixed-point integers of 0-15. The entire process does not call the MCU floating-point arithmetic library and does not generate floating-point arithmetic power consumption.

[0013] As an improvement, the segmented depth separable convolution in S2 adopts an architecture of independent convolution within groups and zero feature interaction between groups. The 128-dimensional time-series traffic features are equally divided into 4 groups of 32-dimensional sub-features. Each group is independently configured with a 1×3 one-dimensional channel-wise convolution kernel, a fixed convolution stride of 1, and a padding number of 0. Cross-group splicing and cross-group convolution fusion are eliminated.

[0014] The miniature local channel attention module eliminates the two fully connected layers of dimensionality reduction and upgrading in traditional SE attention, retaining only a single set of sub-features with mean pooling. It selects eight strongly correlated intrusion features: packet transmission interval, payload fluctuation amplitude, application layer illegal command code, source node address jump, destination port illegal access, packet replay interval, payload length mutation, and channel occupancy duration. Channel weights are calculated only for these eight features, while the remaining 120 low-sensitivity features are forcibly fixed with a weight of 1 and do not participate in the weight iteration calculation.

[0015] As an improvement, the 8-bit symmetric zero-offset quantization in S3 is zero-point-free quantization. Quantization ranges are set separately for two types of parameters: convolution weights and fully connected weights. The quantization range for convolution weights is [-7.92, 8.15], and the quantization range for fully connected weights is [-5.14, 6.27]. The quantization zero-point offset is uniformly set to zero, eliminating the need to store the two auxiliary parameters, zero-point offset and scaling factor, in the terminal Flash, thus reducing auxiliary storage overhead by 12.3KB.

[0016] The weight sparsity threshold is 0.001 for the absolute value of the weight. During offline pruning, the zero-weight position is marked synchronously. The terminal firmware has a built-in hardware-level jump instruction, which is different from software-based jump. During the MCU instruction prefetching stage, the multiply-accumulate instruction corresponding to the zero weight is skipped directly, without needing to read the weight register data.

[0017] As an improvement, the two-level intrusion response in S4 is based on the model output classification confidence level: Level 1 anomalies are port slow scanning and accidental address probing, with a model confidence level of 0.5-0.7. Only 4 bytes of binary minimal logs are stored locally, with byte allocation consisting of 1 byte timestamp offset, 1 byte anomaly type encoding, and 2 bytes message hash digest. ASCII string storage is abandoned, and the storage overhead of a single log is compressed by 92%. Level 2 intrusions are replay attacks, DDoS flooding, and illegal application layer tampering, with a model confidence level ≥0.7. No RTOS task scheduling is required; the MCU peripheral clock register is directly modified to disable the RF transceiver clock, and the blocking latency is ≤2ms.

[0018] The logs are reported in batches at a fixed time of 3:00 AM daily, with the device waking up at its lowest power consumption. The duration of each wake-up call does not exceed 100ms.

[0019] As an improvement, the lookup table-based Hard-Swish fixed-point activation in S2 is replaced by piecewise linear fitting lookup table, abandoning the sigmoid exponential floating-point operation in the original Hard-Swish. Based on the fixed-point input interval of [-8,8], 32 equally spaced lookup table nodes are divided, and the corresponding output values ​​are fitted in advance on the PC. The static lookup table array is generated and solidified into the MCU read-only Flash, occupying 1.18KB of Flash space.

[0020] The table lookup read uses offset direct addressing, eliminating the need for binary search. The activation latency of a single feature is controlled within 0.2ms, and the power consumption is reduced by 67% compared to floating-point activation. It is compatible with chips without FPU computational limitations.

[0021] As an improvement, the MCU main frequency is permanently statically locked. During the device power-on initialization phase, the system clock control register is directly configured to fix the core main frequency at 48MHz and the peripheral bus clock at 24MHz, and the dynamic voltage frequency adjustment, clock multiplication, and sleep wake-up automatic frequency increase functions are permanently disabled.

[0022] At the same time, the cache prefetch function is disabled during inference to avoid clock jitter caused by sudden memory access, eliminate instantaneous power consumption spikes of 2-5 times during inference, ensure that the power consumption fluctuation does not exceed ±0.1mW throughout the inference process, and match the low power discharge curve of the battery.

[0023] As an improvement, the hardware-level skip logic of the MCU multiply-accumulate unit includes three levels of skipping: the first level skips data SRAM reading and does not read the input feature data corresponding to zero weight;

[0024] The second stage skips ALU multiplication and accumulation operations and disables the ALU clock; the third stage skips result DDR write-back and does not occupy bus write-back bandwidth. With the combined effect of these three skips, the number of memory read / write operations for network inference with 65% sparsity is reduced by 63%, and the peak SRAM usage for inference drops from 224KB to 189KB, meeting the memory redundancy requirements for SRAM devices with 256KB and below.

[0025] As an improvement, in the SRAM≤64KB ultra-low power terminal adaptation scheme, the dynamic feature selection adopts the Pearson correlation coefficient selection mechanism, retaining only 4 core features with a correlation coefficient ≥0.75 with the intrusion tag: message packet interval, payload length, source address jump, and illegal instruction code; the feature grouping is adjusted to 6 groups of 21-dimensional sub-features, and low-correlation redundant dimensions are randomly discarded if there are insufficient dimensions; the structured pruning weight threshold is reduced from 0.002 to 0.0008, and shallow convolutional small weight kernels are additionally removed. The final model occupies 59KB of Flash, 57KB of peak SRAM, and reserves 7KB of memory stack redundancy.

[0026] The beneficial effects of this invention are as follows:

[0027] 1. Power consumption optimization: The entire process is local offline inference, eliminating cloud uplink communication power consumption. Fixed-point operation avoids chip FPU overclocking. The average power consumption of a single traffic inference is 2.07mW, which is 78.3% lower than the power consumption of the MobileNet one-dimensional intrusion detection model.

[0028] 2. Memory adaptation: The peak memory usage of the compressed model is 189KB, which is compatible with all 256KB-level low-power MCUs on the market and does not require external storage chips.

[0029] 3. Improved accuracy: A segmented convolutional algorithm tailored for IoT short message traffic, combined with local attention, reduced the false alarm rate of heartbeat packets from 12.4% to 1.1%;

[0030] 4. Low deployment threshold: No operating system dependency, can be directly embedded into the bare metal MCU underlying firmware, suitable for passive low-power IoT scenarios in the wild. Attached Figure Description

[0031] Figure 1 This is a flowchart illustrating the overall process of a lightweight neural network IoT intrusion detection method for low-power devices according to the present invention.

[0032] Figure 2 This is a schematic diagram of the internal hierarchical structure of a lightweight segmented attention neural network, which is a lightweight neural network IoT intrusion detection method for low-power devices according to the present invention.

[0033] Figure 3 This is a schematic diagram of the low-power MCU terminal model inference hardware resource interaction of a lightweight neural network IoT intrusion detection method for low-power devices according to the present invention.

[0034] Figure 4 This is a bar chart comparing the memory, power consumption, and accuracy metrics of a lightweight neural network IoT intrusion detection method for low-power devices proposed in this invention with existing lightweight detection models. Detailed Implementation

[0035] To facilitate a clearer understanding of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Identical components are denoted by the same reference numerals. It should be noted that the terms "front," "rear," "left," "right," "up," and "down" used in the following description refer to directions in the accompanying drawings, while the terms "inner" and "outer" refer to directions toward or away from the geometric center of a specific component, respectively.

[0036] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0037] It should be noted that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0038] like Figure 1-4 As shown, a lightweight neural network IoT intrusion detection method for low-power devices includes four steps executed sequentially: traffic acquisition and redundancy denoising preprocessing, lightweight segmented attention neural network inference, model joint compression and solidification, and intrusion alarm and traffic blocking. All computations are deployed locally on the low-power IoT terminal without cloud data interaction. The low-power device is defined as an IoT sensing terminal with on-chip SRAM ≤ 256KB, Flash ≤ 1MB, no hardware FPU, and an operating voltage of 2.2-3.3V.

[0039] 1. Traffic Acquisition and Redundancy Reduction Preprocessing: The terminal network card bypasses and captures the original packets of three mainstream IoT link layers: LoRa, ZigBee, and MQTT. It extracts the timing features of the source address, destination address, packet length, packet interval, and application layer instruction quintuple. For IoT periodic heartbeat packets, a fixed field mask template is designed to remove fixed redundant fields such as packet headers and check bits, with a redundancy removal rate of no less than 41%. Extreme value truncation normalization is used to replace the traditional min-max normalization, avoiding division floating-point operations and compressing the feature value range to the integer range of 0-15, which is compatible with the chip's fixed-point arithmetic unit.

[0040] 2. Lightweight Segmented Attention Neural Network Inference: A one-dimensional segmented depthwise separable convolutional-channel attention hybrid network is constructed, eliminating pooling layers and deep fully connected layers. The backbone network is divided into three segments: a shallow segmented convolutional layer splits a single 128-dimensional traffic feature into four groups of 32-dimensional sub-features, performing channel-wise convolutions in each group without feature interaction between groups, reducing convolutional computation by 75%; a mid-layer micro-channel attention module assigns weights only to the eight abnormally sensitive traffic features, abandoning global attention, reducing the number of parameters by 92%; and two sparse fully connected layers at the back end, with the number of neurons set to 32 and 5 respectively, outputting five types of detection results: normal, port scan, DDoS, malicious tampering, and replay attack.

[0041] 3. Joint Model Compression and Terminal Fixation: A triple joint compression approach is employed, combining structured pruning, 8-bit symmetric quantization, and weight sparsification. The first step, structured pruning, removes redundant convolutional kernels with output weights below a threshold of 0.002 without disrupting the network topology. The second step, 8-bit symmetric quantization, directly maps 32-bit floating-point weights to fixed-point integers, setting the offset to zero, thus eliminating the storage overhead of quantization offsets. The third step, weight sparsification, forces weights with absolute values ​​less than 0.001 to be zeroed, skipping zero-weight calculations via terminal zero-value skip instructions. After compression, the overall Flash memory usage is 124KB, and the peak SRAM inference usage is 189KB.

[0042] 4. Local Alarms and Traffic Blocking: The terminal has a built-in link bypass blocking pin. After an intrusion is detected, the RF transceiver pins are directly shut down through the underlying registers without the need for operating system scheduling, thus blocking malicious traffic. At the same time, alarm logs are stored locally, and a simplified alarm summary is uploaded only during the device's timed wake-up window, further reducing communication power consumption.

[0043] Example 1: Deployment of Outdoor Temperature Sensing Terminal Intrusion Detection Based on STM32L476 Low-Power MCU

[0044] The hardware in this embodiment is an STM32L476RG main controller with 128KB SRAM, 1MB Flash, no hardware FPU, and an SX1278 LoRa RF module for communication. Its sleep power consumption is 0.72mW, and its operating frequency is fixed at 48MHz (dynamic overclocking is prohibited). The detection targets three common intrusion behaviors of outdoor temperature sensing terminals: port scanning, replay attacks, and unauthorized MQTT writes.

[0045] Step S1: Real-time acquisition of link layer traffic and bare-metal noise reduction preprocessing

[0046] A traffic capture hook is attached within the MCU bare-metal low-level interrupt service function, and LoRa physical layer messages are directly parsed within the RF receive interrupt, bypassing the TCP / IP protocol stack and reducing protocol stack memory overhead. Each message has a fixed length of 92 bytes, and the following five-tuple timing features are extracted: source node short address (2 bytes), destination node short address (2 bytes), application layer instruction code (1 byte), time interval between consecutive messages (4 bytes), and payload length (2 bytes). These are concatenated into a 128-dimensional standardized feature vector, padding with zeros if necessary.

[0047] Redundancy and noise reduction refinement: The structure of 200 consecutive normal heartbeat packets is statistically analyzed, and the fixed 47-byte frame header and CRC checksum tail are extracted. A static mask table is generated and stored in the MCU's read-only Flash memory. After message reception, the fixed redundant bytes are directly overwritten using the mask table, eliminating the need for dynamic calculation. Extreme value truncation and normalization parameters: The extreme values ​​of local normal traffic characteristics over the past 7 days are statistically analyzed, with a maximum value of 11.2 and a minimum value of 0.03. Features exceeding the specified range are directly truncated. Integer shift operations replace floating-point division, with a fixed shift of 3 bits, converting the features into 4-bit fixed-point integers (0-15) without any floating-point operations.

[0048] Step S2: Lightweight segmented attention neural network layer-by-layer inference execution

[0049] (1) Segmented depth separable convolutional layer: Input 128-dimensional fixed-point features, equally divided into 4 groups of 32-dimensional sub-features, with a fixed kernel size of 1×3, a per-channel convolution stride of 1, and no cross-group convolution. Traditional one-dimensional convolution requires 128 groups of convolution kernels, but this embodiment only uses 32 groups of grouped convolution kernels, reducing the number of convolution operations from 49152 to 12288. The convolution activation function is replaced with a Hard-Swish fixed-point approximation version, eliminating exponential floating-point operations and completing activation through a lookup table method. The lookup table has only 32 entries and occupies 1.2KB of Flash.

[0050] (2) Miniature Local Channel Attention Module: This module filters strongly correlated features of IoT intrusion, namely, message interval, payload length, command code, and source address fluctuation (8 features in total). Channel weights are calculated only for these 8 features, while the weights of the remaining 120 features are fixed at 1. The weight calculation adopts simplified global average pooling, calculating only the mean of a single set of sub-features to avoid global mean traversal. The number of parameters in the attention module is only 41, which is much lower than the 2048 parameters of traditional SE attention.

[0051] (3) Sparse fully connected classification layer: The first fully connected layer takes 128-dimensional attention-weighted features as input and outputs 32-dimensional latent features. The sparsity is set to 65%, that is, 65% of the neuron weights are permanently fixed to 0. The second fully connected layer outputs 5-dimensional classification probabilities. The fixed-point softmax simplified algorithm is adopted, which only retains the maximum value comparison logic and omits the exponential and logarithmic operations. The classification delay is controlled within 13ms.

[0052] Step S3: Offline joint compression of the model and firmware solidification

[0053] Offline compression is performed offline on the PC using PyTorch, without consuming terminal computing power: 1) Structured pruning: With a validation set false positive rate increase of ≤0.5% as a constraint, iterative pruning is performed for 3 rounds, removing 21 redundant convolutional kernels; 2) 8-bit symmetric quantization: quantization range [-7.92, 8.15], symmetric zeros are set to 0, eliminating the need to store zero offset parameters, and the weights are compressed from 496KB (32-bit floating-point) to 124KB; 3) Zero-weight instruction adaptation: the MCU's underlying inference firmware is modified to skip multiplication and addition operations when a weight of 0 is detected. Actual inference SRAM usage is reduced from 224KB to 189KB, meeting the 128KB SRAM hardware limit. After compression, the model is converted to a binary bin file and directly merged into the MCU's underlying bare-metal firmware, without running an RTOS operating system.

[0054] Step S4: Local Intrusion Response and Low-Power Log Storage

[0055] Tiered response after intrusion detection: Level 1 anomaly (minor port probe): Record a 4-byte minimal log locally (timestamp + anomaly type code) and store it in the Flash free partition without triggering RF reporting; Level 2 intrusion (replay, illegal write): Directly manipulate the GPIO underlying registers, disable the SX1278 RF transceiver clock, block subsequent traffic, and block delay ≤2ms; The device is woken up at 3 AM daily for 100ms to upload the daily anomaly codes in batches, with a single reporting power consumption of 0.31mW, which is 94% lower than real-time reporting power consumption.

[0056] Example 2: Comparison of control experimental parameters

[0057] Using the publicly available IoT-23 intrusion dataset, we compared our method with three metrics: 1) Model Flash usage: 124KB / 482KB / 927KB; 2) Power consumption per inference line: 2.07mW / 9.52mW / 14.36mW; 3) Intrusion detection accuracy: 96.72% / 95.14% / 94.81%; 4) Heartbeat false alarm rate: 1.1% / 12.4% / 15.7%. The data demonstrates that our method comprehensively outperforms existing solutions in terms of resource consumption and detection accuracy.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A lightweight neural network IoT intrusion detection method for low-power devices, characterized in that, For applications in bare-metal IoT terminals with SRAM ≤ 256KB, no hardware floating-point unit, and no operating system, the following steps are included: S1 bypass captures the original packets of the IoT radio frequency link, extracts the five-tuple time-series traffic features, removes fixed redundant fields of the packets through static masking, and obtains fixed-point traffic features by integer shift extreme value truncation and normalization, without performing floating-point division operations throughout the process. S2 inputs the fixed-point traffic features into a lightweight segmented attention neural network. The network includes segmented depth separable convolutional layers, a micro local channel attention module, and a two-layer sparse fully connected layer. The segmented convolutions perform independent operations on the traffic features in groups, and the local channel attention only assigns weights to intrusion-sensitive features. S3 performs triple offline compression of the model through structured pruning, 8-bit symmetric zero-offset quantization, and weight sparsification, and then saves the model to the local Flash memory on the terminal. The S4 terminal completes intrusion classification inference locally, performs hierarchical radio frequency blocking, minimal log storage, and scheduled batch reporting responses; all inference operations are completed locally on the terminal, without real-time cloud traffic interaction.

2. The lightweight neural network IoT intrusion detection method for low-power devices according to claim 1, characterized in that: In S1, the static mask is a read-only, fixed mask with a dynamic update cycle of no less than 30 days. The static mask is generated by statistically analyzing 200 consecutive normal periodic IoT heartbeat messages with the same channel and device ID, filtering out 16 bits or more of unchanged frame header, frame tail CRC check, and link address padding fields. Only fixed redundancy at the link layer is removed, without modifying the application layer payload fields. The overall redundancy field removal rate of the message is consistently no less than 41%. The extreme value truncation normalization uses a right shift of 3 bits integer shift operation, which only maps the flow characteristics within the range of [0.03, 11.2]. Characteristics outside the range are directly truncated to the extreme values ​​of the range. Finally, the floating-point characteristics are uniformly mapped to 4-bit unsigned fixed-point integers of 0-15. The entire process does not call the MCU floating-point arithmetic library and does not generate floating-point arithmetic power consumption.

3. The lightweight neural network IoT intrusion detection method for low-power devices according to claim 1, characterized in that: S2 employs a segmented depth-separable convolution architecture with independent convolution within groups and zero-feature interaction between groups. It equally divides the 128-dimensional temporal traffic features into 4 groups of 32-dimensional sub-features. Each group is independently configured with a 1×3 one-dimensional channel-wise convolution kernel, a fixed convolution stride of 1, and 0 padding. Cross-group splicing and cross-group convolution fusion are eliminated. The miniature local channel attention module eliminates the two fully connected layers of dimensionality reduction and upgrading in traditional SE attention, retaining only a single set of sub-features with mean pooling. It selects eight strongly correlated intrusion features: packet transmission interval, payload fluctuation amplitude, application layer illegal command code, source node address jump, destination port illegal access, packet replay interval, payload length mutation, and channel occupancy duration. Channel weights are calculated only for these eight features, while the remaining 120 low-sensitivity features are forcibly fixed with a weight of 1 and do not participate in the weight iteration calculation.

4. The lightweight neural network IoT intrusion detection method for low-power devices according to claim 1, characterized in that: In S3, 8-bit symmetric zero-offset quantization is zero-point-free quantization. Quantization ranges are set separately for two types of parameters: convolution weights and fully connected weights. The quantization range for convolution weights is [-7.92, 8.15], and the quantization range for fully connected weights is [-5.14, 6.27]. The quantization zero-point offset is uniformly set to zero, eliminating the need to store two types of auxiliary parameters, zero-point offset and scaling factor, in the terminal Flash, reducing auxiliary storage overhead by 12.3KB. The weight sparsity threshold is 0.001 for the absolute value of the weight. During offline pruning, the zero-weight position is marked synchronously. The terminal firmware has a built-in hardware-level jump instruction, which is different from software-based jump. During the MCU instruction prefetching stage, the multiply-accumulate instruction corresponding to the zero weight is skipped directly, without needing to read the weight register data.

5. The lightweight neural network IoT intrusion detection method for low-power devices according to claim 1, characterized in that: The two-level intrusion response classification in S4 is based on the model output classification confidence level: Level 1 anomalies are port slow scanning and accidental address probing, with a model confidence level of 0.5-0.

7. Only 4 bytes of binary minimal logs are stored locally, with byte allocation consisting of 1 byte timestamp offset, 1 byte anomaly type encoding, and 2 bytes message hash digest. ASCII string storage is abandoned, and the storage overhead of a single log is compressed by 92%. Level 2 intrusions are replay attacks, DDoS flooding, and illegal application layer tampering, with a model confidence level ≥0.

7. No RTOS task scheduling is required; the MCU peripheral clock register is directly modified to disable the RF transceiver clock, and the blocking latency is ≤2ms. The logs are reported in batches at a fixed time of 3:00 AM daily, with the device waking up at its lowest power consumption. The duration of each wake-up call does not exceed 100ms.

6. The lightweight neural network IoT intrusion detection method for low-power devices according to claim 1, characterized in that: In S2, the lookup table-based Hard-Swish fixed-point activation is replaced by piecewise linear fitting lookup table. The sigmoid exponential floating-point operation in the original Hard-Swish is abandoned. Based on the fixed-point input interval of [-8,8], 32 equally spaced lookup table nodes are divided. The corresponding output values ​​are fitted in advance on the PC and a static lookup table array is generated and fixed to the MCU read-only Flash, occupying 1.18KB of Flash space. The table lookup read uses offset direct addressing, eliminating the need for binary search. The activation latency of a single feature is controlled within 0.2ms, and the power consumption is reduced by 67% compared to floating-point activation. It is compatible with chips without FPU computational limitations.

7. The lightweight neural network IoT intrusion detection method for low-power devices according to claim 1, characterized in that: The MCU main frequency is permanently statically locked. During the device power-on initialization phase, the system clock control register is directly configured to fix the core main frequency at 48MHz and the peripheral bus clock at 24MHz, and the dynamic voltage frequency adjustment, clock multiplication, and sleep-wake automatic frequency increase functions are permanently disabled. At the same time, the cache prefetch function is disabled during inference to avoid clock jitter caused by sudden memory access, eliminate instantaneous power consumption spikes of 2-5 times during inference, ensure that the power consumption fluctuation does not exceed ±0.1mW throughout the inference process, and match the low power discharge curve of the battery.

8. A lightweight neural network IoT intrusion detection method for low-power devices according to claim 1, characterized in that: The hardware-level skip logic of the MCU multiply-accumulate unit includes three levels of skipping: the first level skips data SRAM reading and does not read the input feature data corresponding to zero weight; The second stage skips ALU multiplication and accumulation operations and turns off the arithmetic unit clock; the third stage skips result DDR write-back and does not occupy bus write-back bandwidth; with the synergistic effect of the three skips, the number of network inference memory read and write operations with a sparsity of 65% is reduced by 63%, and the peak SRAM usage for inference is reduced from 224KB to 189KB, meeting the memory redundancy requirements of SRAM devices with 256KB and below.

9. A lightweight neural network IoT intrusion detection method for low-power devices according to claim 1, characterized in that: In the SRAM≤64KB ultra-low power terminal adaptation solution, the dynamic feature selection adopts the Pearson correlation coefficient selection mechanism, retaining only those with a correlation coefficient ≥ 100% with the intrusion tag. The four core features of 0.75 are: message packet interval, payload length, source address jump, and illegal instruction code; the feature grouping is adjusted to 6 groups of 21-dimensional sub-features, and insufficient dimensions are randomly discarded with low relevance and redundancy; the structured pruning weight threshold is reduced from 0.002 to 0.0008, and shallow convolutional small weight kernels are additionally removed. The final model occupies 59KB of Flash, 57KB of peak SRAM, and reserves 7KB of memory stack redundancy.

Images