Wireless communication optimization method, system, and device

Abstract

The application relates to the technical field of wireless communication, and provides a wireless communication optimization method, system and device. The wireless communication optimization method comprises the following steps: performing real-time phase tracking on a receiving signal of a wireless communication chip by using a pilot signal, performing frequency offset compensation on the receiving signal according to the tracked phase, and performing channel state estimation to obtain channel state information; after decoding and noise reduction are performed on the receiving signal, the priority of each data processing path in a receiving link is determined according to the characteristics of a data stream after noise reduction; and the layout of each data processing path is optimized according to the priority of each data processing path. The method can optimize the power consumption of a wireless communication device through frequency offset compensation and layout optimization, thereby reducing the power consumption of the device and improving the endurance of the device.

Description

Technical Field

[0001] This application relates to the field of wireless communication technology, and in particular to a wireless communication optimization method, system and device. Background Technology

[0002] Currently, wireless communication technology is widely used in security, emergency response, and other scenarios. In security and emergency response scenarios, users utilize wireless communication devices to transmit business data via WiFi (wireless communication) chips.

[0003] However, most wireless communication devices are portable and battery-powered. In actual security and emergency scenarios, the WiFi chips in wireless communication devices consume a lot of power, which leads to rapid power consumption and insufficient battery life, making it difficult to achieve long-term data transmission. Summary of the Invention

[0004] In view of this, this application aims to propose a wireless communication optimization method to improve the quality of use of wireless communication devices.

[0005] To achieve the above objectives, the technical solution of this application is implemented as follows: A wireless communication optimization method, comprising: The received signal of the wireless communication chip is phase tracked in real time using pilot signals, and frequency offset compensation is performed on the received signal based on the tracked phase using a preset frequency offset compensation method. The channel state information is obtained by using the least squares algorithm to estimate the channel state of the received signal after frequency offset compensation. Based on the channel state information, a decoding method is determined, and the received signal is decoded using the decoding method. The decoded received signal is subjected to noise reduction and wavelet reconstruction to obtain the noise-reduced data stream. Based on the characteristics of the denoised data stream, a timing constraint model is determined, and based on the timing constraint model, the priority of each data processing path in the receiving link is determined; Based on the priority of each data processing path, the layout of each data processing path is optimized using a preset optimization algorithm.

[0006] Furthermore, the step of compensating for the frequency offset of the received signal based on the tracked phase using a preset frequency offset compensation method includes: The training sequence is obtained from the header of the received signal data packet, and the phase difference between the beginning and end of the training sequence is calculated. Estimate the channel impulse response in the received link; Based on the channel impulse response and the phase difference between the preceding and following training sequences, the residual frequency offset is estimated, and the received signal is compensated for the frequency offset based on the residual frequency offset.

[0007] Furthermore, estimating the residual frequency offset and compensating for the frequency offset of the received signal based on the residual frequency offset includes: The training sequence is cross-correlated with the locally stored historical training sequence to obtain the cross-correlation function and the maximum peak point of the cross-correlation function. Calculate the sample point offset of the maximum peak point relative to the theoretical peak position, where the theoretical peak position is the position of the maximum peak point when it is at a preset ideal zero frequency offset; The residual frequency offset is calculated based on the proportional relationship between the sample point offset and the symbol length of the training sequence; Based on the residual frequency offset, the received signal is reversed in the digital domain to achieve frequency offset compensation.

[0008] Furthermore, the decoding method includes hard-decision decoding and soft-decision decoding; The step of determining the decoding method based on the channel state information includes: Based on the channel state information, calculate the equivalent signal-to-noise ratio of the current receiving link; Based on the relative magnitude of the equivalent signal-to-noise ratio and the preset signal-to-noise ratio threshold, the decoding method corresponding to the receiving link is determined from the hard-decision decoding method and the soft-decision decoding method.

[0009] Furthermore, the step of performing noise reduction and wavelet reconstruction processing on the decoded received signal to obtain a noise-reduced data stream includes: The decoded received signal is subjected to multi-resolution wavelet decomposition to obtain each sub-band signal and the wavelet coefficients of each sub-band signal; Based on the statistical variance and energy distribution of the wavelet coefficients of each sub-band signal, a noise reduction threshold matching the sub-band signal is determined; Using the noise reduction threshold, noise components in each of the sub-band signals are filtered out. After wavelet reconstruction of each of the filtered sub-band signals, a noise-reduced data stream is obtained.

[0010] Furthermore, the step of optimizing the layout of each data processing path according to its priority using a preset optimization algorithm includes: The layout of the data processing path is iteratively perturbed and optimized; After each iteration, the cost function value corresponding to the layout of the data processing path after the iteration is calculated, and one iteration is completed; Based on the cost function value, the layout of the data processing path is iterated again using a preset optimization algorithm until the layout of the data processing path after the iteration satisfies the preset delay balance target, and the iteration ends.

[0011] Furthermore, the iterative perturbation optimization of the layout of the data processing path includes: The layout of the current data processing path is subject to a preset random perturbation operation, wherein the random perturbation operation includes swapping the processing order of adjacent data streams and adjusting the processing priority of non-critical data streams.

[0012] Furthermore, the wireless communication optimization method also includes: Statistically analyze the arrival intervals of historical signals and predict the arrival time of the signal in the next time period; Determine the predicted idle window based on the predicted arrival time of the signal in the next time period; Within the predicted idle window, the preset module in the wireless communication chip is controlled to enter a preset low-power sleep state; Real-time assessment of the current busy / idle status of the receiving link; Based on the busy / idle state of the receiving link and the arrival interval, a reserved time window is determined between the preset module waking up from a preset low-power sleep state and fully responding to the next signal.

[0013] Compared with related technologies, this application has at least the following advantages:

[0014] The wireless communication optimization method of this application integrates a real-time phase tracking and frequency offset compensation mechanism based on pilot signals in the receiving link, enabling the device to maintain stable synchronization even in dense multipath and high-speed mobile scenarios. Simultaneously, by using the least squares method to perform channel estimation after frequency offset compensation, the accuracy of channel state information estimation can be improved, thereby facilitating low bit error rate demodulation in complex environments and fundamentally reducing signal retransmission and power consumption waste caused by channel distortion. Furthermore, this embodiment also utilizes a preset optimization algorithm to optimize the layout of the data processing path to reduce the power consumption of the wireless communication chip, thereby improving the battery life of the wireless communication device.

[0015] Another objective of this application is to provide a wireless communication optimization system, comprising: The frequency offset compensation module is used to perform real-time phase tracking of the received signal of the wireless communication chip using pilot signals, and to perform frequency offset compensation on the received signal according to the tracked phase using a preset frequency offset compensation method. The channel state estimation module is used to perform channel state estimation on the frequency offset compensated received signal using the least squares algorithm to obtain channel state information. The decoding module is used to determine the decoding method based on the channel state information, and to decode the received signal using the decoding method. The noise reduction module is used to perform noise reduction and wavelet reconstruction processing on the decoded received signal to obtain a noise-reduced data stream. The layout optimization module is used to determine a timing constraint model based on the characteristics of the noise-reduced data stream, determine the priority of each data processing path in the receiving link based on the timing constraint model, and optimize the layout of each data processing path according to the priority of each data processing path using a preset optimization algorithm.

[0016] Another object of this application is to provide an electronic device comprising: Memory, used to store computer programs; A processor is configured to execute the computer program stored in the memory to implement the wireless communication optimization method described above.

[0017] The wireless communication optimization system and device described in this application can reduce the power consumption of the wireless communication chip and improve the battery life of the wireless communication device by implementing the above-described wireless communication optimization method. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a flowchart illustrating the wireless communication optimization method described in an embodiment of this application; Figure 2 This is a schematic diagram of the process for frequency offset compensation in the wireless communication optimization method described in the embodiments of this application; Figure 3 This is a flowchart illustrating the optimization of the data processing path layout in the wireless communication optimization method described in this application embodiment; Figure 4 This is a schematic diagram of the overall process of the wireless communication optimization method described in the embodiments of this application; Figure 5 This is a logical timing diagram of the wireless communication optimization method described in the embodiments of this application; Figure 6 This is a schematic diagram of the architecture of the wireless communication optimization system described in the embodiments of this application; Figure 7 This is a schematic diagram of the architecture of the electronic device described in the embodiments of this application.

[0019] Explanation of reference numerals in the attached figures: 610. Frequency offset compensation module; 620. Channel state estimation module; 630. Decoding module; 640. Noise reduction module; 650. Layout optimization module; 710. Processor; 720. Memory. Detailed Implementation

[0020] To make the technical solution and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0022] Furthermore, it should be noted that in the description of this application, if terms such as "upper," "lower," "inner," or "outer" appear, indicating orientation or positional relationship, these are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, if terms such as "first" or "second" appear, they are also used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] Furthermore, in the description of this application, unless otherwise expressly defined, the terms "installation," "connection," "joining," and "connector" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application in light of the specific circumstances.

[0024] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0025] The present application will now be described in detail through exemplary embodiments. However, it should be understood that, without further description, elements, structures, and features in one embodiment may be advantageously incorporated into other embodiments.

[0026] An embodiment of the first aspect of this application provides a wireless communication optimization method applied in WiFi (Wireless Fidelity) communication to reduce the power consumption of WiFi communication.

[0027] In related technologies, with the widespread use of smart devices and the advancement of wireless communication technology, industry users are increasingly relying on wireless communication when performing tasks, especially in situations such as urban security monitoring and emergency response, where WiFi communication technology provides important technical support.

[0028] For example, in urban security and emergency rescue operations, the network cannot be interrupted, and all communication equipment (AP, Wireless Access Point) is used to wirelessly transmit monitoring images, intercoms, and location data.

[0029] An industry communication device (AP) is a complete wireless communication device that includes a core WiFi chip, as well as a matching main control module, power management module, RF power amplifier module, antenna, network port, battery, storage module, heat dissipation components, etc.

[0030] Industrial communication equipment (APs) rely on internal WiFi chips to transmit WiFi signals and monitor images. For example, the WiFi chip performs tasks such as wireless signal calculation, demodulation, noise reduction, channel measurement, and data packet verification; therefore, the power consumption of the WiFi chip is the primary source of power consumption for industrial communication equipment APs.

[0031] When using access points (APs) for security and emergency response tasks, they typically need to maintain high efficiency for extended periods. For example, security and emergency response tasks may require industry communication equipment to operate continuously for hours or even all day. However, these APs often rely on battery power. When the WiFi chip operates under high load continuously, it consumes power quickly, causing the battery to run out rapidly and ultimately resulting in a complete interruption of wireless communication.

[0032] Currently, in related technologies, especially in scenarios with dense obstacles such as building assaults, WiFi signals exhibit multipath effects. This means that after a WiFi signal is emitted from the antenna of a device's access point (AP), it doesn't reach the soldier's camera / walkie-talkie in a straight line. Instead, the signal is repeatedly reflected and refracted through walls, metal doors, and glass, forming multiple signals of varying lengths that ultimately reach the WiFi chip's receiver. These multiple reflected signals superimpose and cancel each other out, resulting in severe waveform distortion. Simultaneously, radio frequency interference (i.e., dynamic interference) from walkie-talkies and other wireless devices in the field can lead to extremely chaotic signal reception.

[0033] Due to multipath effects and dynamic interference, excessive reflected signals and high interference noise occur, submerging the pilot signal and causing significant errors in the WiFi chip's channel environment calculation (i.e., inaccurate channel estimation). Furthermore, when channel estimation is inaccurate, the WiFi chip frequently misinterprets waveforms when demodulating high-definition, high-speed signals (high-order modulation), leading to a significant increase in the high-order modulation demodulation bit error rate and severely impacting the stable transmission of broadband data.

[0034] Furthermore, even after data demodulation, in scenarios such as high-speed movement, the channel changes rapidly as people run (high-speed movement Doppler effect), and sudden noise cannot be completely filtered out. A small amount of errors will remain hidden in the data stream, resulting in a small amount of residual noise in the data stream.

[0035] If the WiFi chip detects residual noise during data verification, the verification will fail, triggering a data packet retransmission. This frequent retransmission increases system power consumption and communication latency.

[0036] Meanwhile, when processing data streams, WiFi chips perform multiple tasks simultaneously, and the arrival times of signals from different modules are inconsistent, causing timing conflicts. To resolve these timing conflicts, the wiring tools for WiFi chips cram a large number of high-speed signal lines into a small chip area. In this area, transistors continuously and synchronously switch at high frequencies, causing a sudden surge in current and forming wiring hotspots (localized high-temperature areas).

[0037] This wiring hotspot problem caused by timing conflicts will form local power consumption peaks in long standby patrol mode, increasing the average power consumption of the whole machine, and the battery will be consumed faster, ultimately restricting the overall battery life and working stability of the device.

[0038] In view of this, in order to overcome the shortcomings of related technologies, the wireless communication optimization method in this embodiment combines... Figure 1 In terms of overall design, it includes the following steps S110-S150.

[0039] Step S110: Real-time phase tracking of the received signal of the wireless communication chip is performed using pilot signals, and frequency offset compensation is performed on the received signal using a preset frequency offset compensation method based on the phase offset obtained from the tracking.

[0040] Specifically, in practical applications, signals carrying business data are transmitted from the sending end to the receiving end. The sending end is a terminal device carrying video, voice, sensor data, etc., used to package the business data into WiFi radio electromagnetic waves for transmission. The sending end has an internal WiFi transmission link responsible for encoding, modulation, and transmission.

[0041] The receiving end is a device used to capture radio electromagnetic waves in the air and restore the original data. It receives the signal sent by the sending end, which is the received signal in this embodiment. The signal transmitted by the sending end is processed through the receiving link of the WiFi chip.

[0042] The wireless communication optimization method in this embodiment is applied at the receiving end, that is, it is executed by the receiving end.

[0043] In step S110, the pilot signal refers to a standard reference signal with a predefined waveform that is mixed into video, voice, and other data at the transmitting end. This pilot signal is specifically used by the WiFi chip to measure signal offset and distortion, and does not carry service data. Specifically, after the physical layer header preamble (the entire fixed reference area at the very beginning of the data packet) of the WiFi data packet, several pilot subcarriers are discretely inserted at fixed intervals within each service data symbol carrying video and voice service data, forming a distributed pilot signal.

[0044] The receiving link refers to the entire hardware circuit path in a WiFi chip (i.e., a wireless communication chip) from receiving signals through the antenna, filtering, amplifying, to demodulation and decoding.

[0045] Phase tracking refers to continuously and in real-time capturing the phase shift of the pilot signal waveform (where wall reflections and people running can cause continuous phase drift). Frequency offset refers to the frequency shift caused by a small frequency difference between the transmitting and receiving ends, or the moving Doppler effect. This type of frequency offset distorts the entire received signal.

[0046] Specifically, in step S110, the WiFi chip continuously captures pilot signals from the data stream in the receiving link, compares the standard pilot waveform symbol by symbol in real time, records the phase offset, and achieves phase tracking. Then, the real-time acquired phase offset is used for frequency offset compensation to counteract the frequency offset caused by Doppler and the hardware crystal oscillator, ultimately outputting the frequency offset-compensated received signal, thereby eliminating the fundamental signal distortion caused by the frequency offset and reducing the subsequent bit error rate.

[0047] In some of these exemplary implementations, refer to Figure 1 as well as Figure 2 In step S110 above, the received signal is frequency offset compensated according to the phase deviation value obtained by tracking using a preset frequency offset compensation method, which may specifically include the following steps S111-S113.

[0048] Step S111: Obtain the training sequence from the header of the received signal data packet and calculate the phase difference between the front and back of the training sequence.

[0049] Phase difference refers to the deviation between the phase of the waveform received by the receiver and the phase of the standard representation waveform in the same training sequence. Phase difference between preceding and following segments refers to the difference between the phase difference of the later segment of the waveform and the phase difference of the earlier segment in the training sequence, representing the magnitude of phase change during the transmission of the training sequence.

[0050] Specifically, a continuous standard waveform is set in the preamble of the physical layer header of the WiFi data packet. This continuous standard waveform is the pre-set long training field (also known as the training sequence).

[0051] Because the signal will travel a certain distance in the air before reaching the receiving antenna of the receiving end, and the waveform will be distorted due to the environment during the propagation process (for example, repeated reflections on walls, doors and windows, etc., causing multiple versions of training sequences to arrive at the receiving end at the same time, superimposing and canceling each other, thus causing waveform distortion), when the WiFi data packet carrying the training sequence is sent from the sending end to the receiving end, the training sequence received at the receiving end will be distorted.

[0052] After receiving the WiFi data packet, the receiving end extracts the built-in distorted training sequence from its packet header. Then, the received distorted training sequence is compared symbol-by-symbol with the standard original training sequence stored internally in the chip. The phase difference between the beginning and end of the training sequence is calculated, and then the difference is calculated to obtain the phase change of the entire sequence, i.e., the phase difference between the beginning and end of the training sequence. This phase change (phase difference between the beginning and end) directly reflects the frequency offset present in the current wireless receiving link, serving as the basis for subsequent frequency offset estimation.

[0053] Step S112: Estimate the channel impulse response in the receiving link.

[0054] Among them, the channel impulse response is a set of data that describes the characteristics of the wireless channel, such as the delay and attenuation of each reflection path after the signal is reflected by a wall, blocked, or interfered with.

[0055] In step S112, the least squares algorithm is used to estimate the channel impulse response. Specifically, the distorted training sequence extracted in step S111 is used as input, and the least squares algorithm is used to fit the received distorted training sequence and the standard original training sequence to the error. This allows the attenuation and delay of each reflection path to be calculated, thus obtaining the channel impulse response.

[0056] Step S113: Estimate the residual frequency offset based on the channel impulse response and the phase difference between the beginning and end of the training sequence, and compensate the received signal for the frequency offset based on the residual frequency offset.

[0057] In some exemplary embodiments, step S113 above, estimating the residual frequency offset and compensating for the frequency offset of the received signal based on the residual frequency offset, may specifically include:

[0058] The received values ​​of the training sequence in the time domain are cross-correlated with locally stored historical training sequences to obtain the cross-correlation function and its maximum peak point. The sample point offset of the maximum peak point relative to the theoretical peak position is calculated; the theoretical peak position is the location of the maximum peak point at a preset ideal zero frequency offset. Based on the proportional relationship between the sample point offset and the symbol length of the training sequence, the carrier frequency offset is estimated to obtain the residual frequency offset. Based on the residual frequency offset, the received signal is reverse-phase rotated in the digital domain to achieve frequency offset compensation.

[0059] In other words, the received values ​​of the training sequence in the time domain are first cross-correlated with locally stored known historical training sequences to calculate the sample point offset of the maximum peak point of the cross-correlation function relative to the theoretical peak position under ideal zero frequency offset. Then, based on the ratio of this sample point offset to the symbol length of the training sequence, the carrier frequency offset estimate is directly calculated to quickly obtain the initial residual frequency offset. Finally, based on the quantized residual frequency offset, the received signal is directly subjected to reverse phase rotation in the digital domain to perform frequency offset compensation.

[0060] This real-time correction of frequency offset via digital phase rotation effectively suppresses inter-carrier interference and improves the stability of the orthogonal frequency division multiplexing system.

[0061] Specifically, the received value of the training sequence in the time domain refers to the distorted training sequence sample data obtained by the receiving antenna after being processed by analog-to-digital conversion and other methods, arranged in chronological order. That is, the training sequence consists of multiple time-domain sampling points, and the received value in the time domain is the time-domain sampling point.

[0062] The local historical training sequence refers to a standard training sequence waveform that is embedded in the wireless communication chip (i.e., WiFi chip) and is uniformly agreed upon by both the transmitting and receiving parties, without distortion. In other words, the local historical training sequence is an ideal training sequence with zero noise and zero frequency deviation.

[0063] Cross-correlation is a signal alignment algorithm. Specifically, based on the time-domain sampling points of the received distorted training sequence, it calculates the matching degree point-by-point with the local historical training sequence within a sliding window. The matching degree is the cross-correlation result. Each time-domain sampling point is a position, and a matching degree is obtained at each position, resulting in a set of matching degree values ​​at different positions. The matching degree data at each position are then curve-fitted to generate a complete cross-correlation curve, and the corresponding functional relationship is obtained. This functional relationship is the cross-correlation function. Next, the highest point of the cross-correlation curve is retrieved; the position corresponding to this highest point is the maximum peak point of the cross-correlation function. Subtracting the theoretical peak position from the actual maximum peak point position yields the sample point offset, with the unit being the number of sampling points.

[0064] Specifically, when performing a sliding cross-correlation operation between the distorted training sequence and the local historical training sequence, this cross-correlation operation can be implemented using a fixed-point complex multiplication algorithm. Furthermore, when the cross-correlation energy exceeds a preset threshold, the peak position can be directly locked; the arrival time of the training sequence corresponding to this peak position is the maximum peak point. For example, under ideal zero-frequency offset conditions, the cross-correlation peak appears at the 64th sample point (with the sequence center as a reference).

[0065] In actual processing, the sample offset can be obtained by comparing the offset of the actual maximum peak point with the theoretical maximum peak point (64th sample point) using a sampling rate of 160MHz as a benchmark.

[0066] Then, based on the sample offset, a carrier frequency offset estimate is calculated to obtain the residual frequency offset. The formula for calculating this carrier frequency offset estimate is as follows: .

[0067] in, This is the estimated carrier frequency offset, representing the amount of the received signal offset relative to the local carrier frequency. This represents the sample point offset (integer) between the measured peak of the cross-correlation function and the theoretical peak at ideal zero frequency offset. It's worth noting that when the actual peak occurs after the theoretical position, .

[0068] This refers to the subcarrier spacing, which is 312.5 kHz for the IEEE 802.11ac / ax standard. The symbol length (in the number of sample points) of the training sequence used for cross-correlation.

[0069] In a standard 128-point FFT system, the time-domain period length of a long training sequence (LTF) is... It supports a frequency offset detection range of ±40ppm, corresponding to ±232kHz in the 5.8GHz band.

[0070] After calculating the carrier frequency offset estimate After obtaining the residual frequency offset, the received signal is rotated in the opposite phase in the digital domain based on the residual frequency offset to achieve frequency offset compensation.

[0071] Specifically, based on the calculated frequency offset estimate The digital domain phase rotation compensation process is initiated. This process employs a direct digital frequency synthesis algorithm, configuring a phase accumulator and a sine / cosine lookup table, and analyzing the frequency control word. According to the formula Calculations show that This is the frequency control word, used to configure the DDS phase accumulator. In DDS, its negative value needs to be taken to achieve reverse compensation, so the actual value substituted into the formula is: , This refers to the bit width of the phase accumulator. Bit, This represents the magnitude of the phase accumulator. The system sampling rate is determined according to the design. , is a rounding function that quantizes the calculation result into the nearest integer value for hardware storage and use.

[0072] The compensation process is performed synchronously on the baseband I / Q path after digital down-conversion, applying a compensation to each sampling point. Phase rotation amount, In the first At each sampling time, the amount of phase compensation that needs to be applied to the received signal is... For discrete-time index (integer), counted from the start time of compensation as... , The sampling period is ,when hour, , Pi is a constant.

[0073] The phase rotation is achieved through complex multiplication: , In the first The baseband complex signal after frequency offset compensation at each sampling time. In the first The received baseband complex signal before frequency offset compensation at each sampling time. The imaginary unit, The complex rotation factor has a value equal to In hardware, this operation is implemented using lookup tables and complex multiplication algorithms.

[0074] The compensation mechanism in this embodiment has a resolution of 0.03Hz, and the compensation delay is completed within 8 sampling periods. In order to adapt to the dynamic frequency offset changes of industry equipment in high-speed moving scenarios, it can also be designed to support independent calculation and updating of frequency control words for each frame data packet, so as to ensure effective tracking even when the moving speed reaches 120km / h (corresponding to 350Hz Doppler frequency shift).

[0075] For example, in step S110, in the WIFI communication receiving link, a phase tracking procedure for the IEEE 802.11ac / ax standard is configured, which uses four pilot subcarriers embedded in the OFDM symbol as the basic working unit. In actual operation, the system operates on dual frequency bands of 2.4 GHz and 5.8 GHz, supporting channel bandwidth configurations of 20 MHz and 40 MHz. Pilot subcarriers are sampled in real time within a frame structure where each OFDM symbol duration is 3.2 μs (including a 0.8 μs cyclic prefix). A digital phase-locked loop (PLL) algorithm (with a loop bandwidth of 20 kHz) is employed. The phase detector takes the conjugate product of the received signal and the local pilot sequence as input, and drives a numerically controlled oscillation algorithm through quantization of the phase error signal. The compensation algorithm performs phase correction every 3.2 μs, achieving a correction accuracy of ±1.5°. The maximum trackable Doppler shift is 350 Hz (corresponding to a mobile scenario at 120 km / h). The phase-compensated signal enters the subsequent processing flow, ensuring that the phase noise of the 1024QAM constellation points is controlled within 3° when the multipath delay spread does not exceed 400 ns in dense urban environments.

[0076] After performing phase tracking to estimate the dynamic phase caused by multipath effects, joint frequency offset estimation and channel estimation are completed based on two identical long training fields (LTF, each 3.2 μs long) in the physical layer header preamble of the WiFi data packet.

[0077] The receiver performs frequency domain transformation on two consecutive LTFs to obtain the frequency domain sample value of each subcarrier. The frequency offset estimation algorithm is realized by calculating the phase difference between the same subcarriers of the two LTFs. That is, the average phase difference of 64 subcarriers (excluding guard subcarriers) is used as the frequency offset estimation benchmark. The phase difference detection accuracy reaches 0.01 radians, and the supported carrier frequency offset estimation range is ±40ppm (corresponding to ±232kHz@5.8GHz) to compensate for the combined effect of crystal oscillator frequency offset and Doppler frequency offset.

[0078] After frequency offset estimation is completed, a digital frequency synthesis algorithm is used to perform phase rotation compensation on the received signal. The frequency control word is dynamically configured according to the frequency offset estimation value, and the compensation resolution reaches 0.03Hz. The compensation process is carried out on the baseband signal after digital down-conversion. With a sampling rate of 160MHz as the reference, a corresponding phase rotation amount is applied to each sampling point to achieve frequency offset compensation.

[0079] After frequency offset compensation is completed in steps S111-S113, step S120 can be executed to perform channel state estimation on the frequency offset compensated received signal.

[0080] Step S120: Using the least squares algorithm, channel state estimation is performed on the frequency offset compensated received signal to obtain channel state information.

[0081] Specifically, the baseband signal that has completed frequency offset compensation enters the channel estimation stage. Frequency domain transformation processing is performed on the compensated long training sequence. The transformation processing adopts a radix-2 butterfly algorithm architecture, and the operation precision is maintained at 16-bit fixed point.

[0082] In the frequency domain, the received values ​​corresponding to the 52 valid data subcarriers are extracted. (r=1,...,52), with locally stored standard training sequences Perform least squares estimation: .

[0083] in, In the first The estimated channel frequency response (complex number) on each subcarrier represents the attenuation and phase rotation experienced by that subcarrier. To perform FFT transformation on the long training sequence after frequency offset compensation, at the th The received frequency domain values ​​(complex numbers) obtained on each data subcarrier. For locally stored, known standard training sequences in the first The transmit frequency domain value (complex number) on each data subcarrier is a value defined by the standard.

[0084] For subcarrier index (integer). This is the index set of valid data subcarriers. For a 20MHz bandwidth 802.11ac / axOFDM symbol, this set contains 52 subcarriers.

[0085] A 7-tap time-domain filter is performed on the original estimation result to achieve noise reduction optimization. The filter coefficient set for the time-domain filter is designed as [0.04, 0.12, 0.20, 0.28, 0.20, 0.12, 0.04]. This coefficient set is optimized for typical mobile speed scenarios of 2-60 km / h. The final output channel frequency response contains 52 complex coefficients, and the real and imaginary parts of each coefficient are quantized with 10-bit precision. At the same time, an 8-bit signal-to-noise ratio indicator value is generated (within the range of 0-40 dB, in 0.5 dB steps). The entire processing is completed within 3.2 μs after receiving the long training sequence. The output data is stored in a dedicated buffer and awaits reading by the physical layer controller through the AXI-Stream interface before the start of the next symbol period.

[0086] For example, after frequency offset compensation in step S110, the least squares algorithm is used to estimate the channel impulse response. The complex channel coefficients are calculated independently on each of the 52 data subcarriers. Matrix operations are performed using fixed-point arithmetic. The estimation results are smoothed by a 7-tap time-domain filter (the filter coefficients are optimized based on the typical moving speed of the equipment, 2-60 km / h). The output channel state information contains 52 complex coefficients, with the real and imaginary parts of each coefficient quantized with 10-bit precision, and an 8-bit signal-to-noise ratio indicator value is also provided for subsequent use.

[0087] Thus, in step S120, the frequency offset compensated received signal enters the frequency domain transformation processing pipeline, working in conjunction with the time domain equalizer to finally output calibrated channel state information, encapsulated in a dedicated data format, including: channel matrix H (52×1 complex vector), remaining frequency offset indication value (8-bit signed integer, unit 0.1ppm), channel quality indicator (CQI, 4-bit encoding, corresponding to MCS0-MCS11), and valid timestamp (32-bit system clock count). The obtained channel state information can be transmitted to the physical layer controller through a high-speed data interface, with the transmission delay controlled within 20 processing clock cycles, ensuring that the configuration of all calibration parameters is completed before the data fields arrive, meeting the industry communication specifications for timing synchronization.

[0088] Step S130: Determine the decoding method of the receiving link based on the channel state information, and use the decoding method to decode the received signal.

[0089] The decoding methods include hard-decision decoding and soft-decision decoding.

[0090] Hard-decision decoding refers to decoding using the LDPC algorithm, while soft-decision decoding refers to decoding using the Viterbi algorithm. The LDPC algorithm has stronger error correction capabilities than the Viterbi algorithm, but the Viterbi algorithm has lower complexity.

[0091] When the link quality is high, the less complex Viterbi algorithm can be chosen for decoding, which improves decoding speed while ensuring decoding quality. When the link quality is low, the more complex but error-correcting LDPC algorithm can be chosen for decoding, which avoids situations where the decoding effect is weak or even impossible. This adaptive selection of the decoding method based on channel state information significantly reduces the computational resource overhead at high modulation orders while maintaining error correction performance.

[0092] In some exemplary embodiments, step S130, determining the decoding method corresponding to the receiving link based on the channel state information, may specifically include: calculating the equivalent signal-to-noise ratio (SNR) of the current receiving link based on the channel state information; and determining the decoding method corresponding to the receiving link from hard-decision decoding methods and soft-decision decoding methods based on the relative magnitude of the equivalent SNR and a preset SNR threshold.

[0093] Specifically, a preliminary link quality assessment is performed based on channel state information, i.e., the equivalent signal-to-noise ratio (SNR) of the current channel is calculated. This provides an accurate and rapid quantification of channel quality for subsequent decoding path switching, ensuring real-time decision-making. Then, based on the link quality assessment results, either the LDPC hard-decision decoding path or the Viterbi soft-decision decoding path is dynamically selected. When the equivalent SNR is higher than a preset SNR threshold, the computationally less complex Viterbi algorithm is used as the decoding method to prioritize the decoding of the convolutionally coded portion of the received signal. When the equivalent SNR is lower than the preset SNR threshold, iterative decoding with stronger error correction capabilities is switched to the LDPC decoder for more accurate demodulation. In this way, decoding power consumption under high SNR conditions can be significantly reduced while ensuring communication reliability. Based on the adaptively selected decoding path, the calibrated channel state information is decoded to complete data stream recovery, achieving adaptive data stream recovery under channel conditions and improving overall energy efficiency.

[0094] Specifically, the calculation process for this equivalent signal-to-noise ratio includes:

[0095] Using the received long training sequence frequency domain response data as input, the channel coefficients and their corresponding signal-to-noise ratio (SNR) indicators on the effective data subcarriers are extracted. A sliding window averaging algorithm is then used to statistically process the channel quality indicators over multiple consecutive OFDM symbol periods to calculate the equivalent SNR. During the calculation, the equivalent signal-to-noise ratio (SNR) is obtained by comparing the squared modulus of the channel coefficient with the noise power estimate. The noise power estimate is obtained by statistically analyzing the received signal energy on the guard subcarrier. The equivalent SNR calculation result is quantized into a numerical range of 0-31.5 dB with a step accuracy of 0.5 dB. Simultaneously, it is updated in real time and stored in the system status buffer. The entire evaluation process is completed under the control of the communication link status monitoring unit, and the processing delay is controlled within 2 OFDM symbol periods (6.4 μs) to ensure that the evaluation results can reflect channel changes in a timely manner.

[0096] Specifically, the expression for this equivalent signal-to-noise ratio is as follows: .

[0097] In the formula: Equivalent signal-to-noise ratio (SNR) represents the average power ratio of signal to noise on the data subcarrier after channel estimation and smoothing. The expected (statistical average) operator is implemented in practice by averaging the measurements on all valid data subcarriers over multiple consecutive OFDM symbol periods using a sliding window method. This aims to smooth out the instantaneous fluctuations caused by fast fading and obtain a stable trend value. For the first The estimated complex channel coefficients on each subcarrier are obtained by performing channel estimation on a long training sequence after frequency offset compensation, followed by time-domain smoothing optimization. For the first The square of the channel coefficient amplitude on each subcarrier is proportional to the power of the received signal on that subcarrier (given the known transmit power). Calculation... This yields the average channel gain power. The noise power estimate is obtained by statistically analyzing the received signal energy on the guard subcarrier. In WiFi OFDM symbols, no valid signal is transmitted on the guard subcarrier, so the received energy on it can be considered a good estimate of the noise power.

[0098] Based on the calculated equivalent signal-to-noise ratio An adaptive decoding path selection mechanism is activated, which selects the path based on the relative magnitude of the equivalent signal-to-noise ratio (SNR) and a preset SNR threshold. More specifically, the preset SNR threshold may include a preset high SNR threshold and a preset low SNR threshold.

[0099] Among them, the preset high signal-to-noise ratio threshold It can be set to 24dB, with a preset low signal-to-noise ratio threshold. It can be set to 18dB. It is worth noting that the values ​​of the preset high signal-to-noise ratio threshold and the preset low signal-to-noise ratio threshold can be optimized and determined based on the packet error rate performance curve under typical conditions.

[0100] Specifically, when the equivalent signal-to-noise ratio When the equivalent signal-to-noise ratio (SNR) exceeds a preset high SNR threshold, the Viterbi soft-decision decoding method can be enabled for decoding. When the equivalent signal-to-noise ratio is less than the preset low signal-to-noise ratio threshold, the LDPC hard decision iterative decoding method can be switched to be used for decoding.

[0101] In addition, when the equivalent signal-to-noise ratio (SNR) is less than or equal to a preset high SNR threshold and greater than or equal to a preset low SNR threshold, for example, when the equivalent SNR is in the range of [18dB, 24dB], a hysteresis comparison strategy can be used to prevent frequent switching. For example, if the LDPC hard decision decoding method is set as the default decoding method in the initial state, and the LDPC hard decision decoding method was used before the equivalent SNR was in the range, then the LDPC hard decision decoding method will still be used when it is in the range to prevent frequent switching. Conversely, if the Viterbi soft decision decoding method was used before the equivalent SNR was in the range, then the Viterbi soft decision decoding method will still be used when it is in the range.

[0102] It is worth noting that the switching delay is controlled within one OFDM symbol period (3.2μs). The decoder selection signal is transmitted through the control interface, which also manages the iteration configuration of the LDPC decoder. When the error correction level is below 20dB, the maximum number of iterations is set to 10, and when it is above 20dB, it is reduced to 5. This optimizes the allocation of computing resources while ensuring error correction performance. All threshold parameters can be adjusted within a limited range through the configuration interface.

[0103] After selecting a decoding path, the corresponding decoding process can be initiated based on the selected path. When the Viterbi soft-decision decoding path is selected, the Viterbi decoding unit is activated to decode the convolutional coding portion. This decoding unit adopts a 4-state trellis structure, uses fixed-point arithmetic for path metric calculation, and sets the backtracking depth to 64 bits, achieving a balance between high throughput and low power consumption. When the LDPC hard-decision decoding path is selected, the LDPC iterative decoding engine is activated, supporting multiple code lengths and employing a minimum sum algorithm for message passing. Both decoding paths share the same input buffer interface. The input data is the soft-decision value after channel equalization, and the recovered bitstream is submitted to the Media Access Control (MAC) layer after CRC-32 verification. The entire decoding process is completed under the unified scheduling of the communication link controller, with a delay of no more than 5μs from decoding path selection to the first bit output, meeting the real-time requirements of communication.

[0104] The expression for the soft decision value after channel equalization is as follows: . .

[0105] In the formula: For the first The soft-decision output value after channel equalization on each subcarrier is a complex number. Its amplitude carries the reliability information of the transmitted symbol (the larger the amplitude, the more reliable), and its phase carries the phase information of the transmitted symbol. For the first The received frequency domain signal after frequency offset compensation on each subcarrier is the result of OFDM demodulation of the data portion of the entire WIFI data packet, and is the signal received on the [number]th subcarrier. Complex sampled values ​​obtained on each valid data subcarrier; For the first The equalizer coefficients on each subcarrier, based on the output of the channel estimation module. The calculated values ​​are used to compensate for the amplitude attenuation and phase rotation introduced by the channel. The equalizer coefficient generation function uses zero-forcing equalization, i.e. In the frequency domain, divide directly by the channel response to eliminate the influence of the channel.

[0106] After decoding the received signal in step S130, the following step S140 can be performed to perform noise reduction processing on the decoded received signal.

[0107] Step S140: Perform noise reduction processing on the decoded received signal to obtain a noise-reduced data stream.

[0108] Specifically, the decoded received signal is a data stream containing residual noise. The residual noise contained therein is, for example, stray interference noise that cannot be completely eliminated due to transient burst interference and remains in the decoded data stream.

[0109] In step S140, burst noise components in the original data stream of the decoded received signal are filtered out to achieve noise reduction processing, so as to obtain a clean data stream without burst noise, that is, to obtain the noise-reduced data stream.

[0110] In some exemplary embodiments, step S140 involves denoising the decoded received signal to obtain a denoised data stream. Specifically, this may include: performing multi-resolution wavelet decomposition on the decoded received signal to obtain sub-band signals and wavelet coefficients for each sub-band signal; dynamically calculating a denoising threshold matching the sub-band signal based on the statistical variance and energy distribution of the wavelet coefficients of each sub-band signal; filtering out noise components from each sub-band signal using the denoising threshold; and performing wavelet reconstruction on the filtered sub-band signals to obtain the denoised data stream.

[0111] Specifically, multi-resolution wavelet decomposition is an algorithm that splits signals into layers, capable of breaking down a mixed signal into multiple layers of components in different frequency ranges. For example, low frequencies represent valid video / voice service information, while high frequencies are mostly burst noise.

[0112] Subband signals are the individual signals obtained by dividing the decoded received signal into frequency ranges, with different subband signals corresponding to different frequency ranges. Wavelet coefficients refer to the set of values ​​used to describe the characteristics of each subband signal after multi-resolution wavelet decomposition of the decoded received signal. In other words, the subband signal is the carrier, and the wavelet coefficients are the values ​​at each specific location on the carrier.

[0113] Specifically, in this embodiment, the process of performing multi-resolution wavelet decomposition on the decoded received signal to obtain each sub-band signal includes: performing multi-resolution wavelet decomposition on the decoded output time-domain signal, wherein the multi-resolution wavelet decomposition uses the Daubechies-4 wavelet basis function, and the number of decomposition layers is set to 4 to match the time-frequency characteristics of typical burst interference in wireless local area networks. Wavelet decomposition processing is performed on the input decoded received signal, processing 256 sampling points per batch (corresponding to a 1.6μs time window), and sub-band decomposition is achieved through a four-stage decimation-2 filter bank. That is, the decoded time-domain signal is sent to a four-stage decimation-2 filter bank, and each decomposition stage processes two steps: the first step is low-pass filtering and downsampling to obtain the approximate components of that layer; the second step is high-pass filtering and downsampling to obtain the detail components of that layer.

[0114] After four layers of iterative decomposition, the final product is: one low-frequency approximate subband (cA4) and four high-frequency detail subbands (cD1, cD2, cD3, cD4). Each numerical point in the decomposition result is the wavelet coefficient corresponding to the subband. Each wavelet coefficient is stored in 16-bit fixed-point format. Subband cD1 covers the 40-80MHz frequency band, subband cD2 covers 20-40MHz, subband cD3 covers 10-20MHz, and subband cD4 covers 5-10MHz, in order to separate the signal characteristic components from multipath interference components. This decomposition process ensures that the OFDM symbol boundary timing is not disrupted.

[0115] After obtaining the sub-band signals, the noise reduction threshold matching the sub-band signals is dynamically calculated based on the statistical variance and energy distribution of the wavelet coefficients of each sub-band signal.

[0116] Statistical variance refers to the degree of fluctuation among all wavelet coefficients within the same subband. In noisy regions, the wavelet coefficients exhibit small fluctuations and their values ​​are concentrated around 0. For real business signals, the wavelet coefficients show large fluctuations and their values ​​are dispersed.

[0117] Energy distribution refers to the sum of the squares of all wavelet coefficients within a sub-band, representing the total signal strength within the corresponding frequency band. Specifically, sub-band signals with noise have low total energy, while effective sub-band signals carrying actual service data have high energy.

[0118] The noise reduction threshold is a threshold used to distinguish whether a wavelet signal is noise or valid based on its wavelet coefficients.

[0119] When filtering out noise components, all wavelet coefficients are traversed for each sub-band signal. The relative magnitude of the wavelet coefficient and the noise reduction threshold is compared. If the absolute value of the wavelet coefficient is less than the current noise reduction threshold, it is identified as a noise component, and the wavelet coefficient is directly set to 0, thus completing the noise filtering. If the absolute value of the wavelet coefficient is greater than or equal to the noise reduction threshold, it is identified as real business data, and the original wavelet coefficient value is retained unchanged. This accurately removes the wavelet coefficients corresponding to the noise, filtering out noise and retaining only the effective transmitted signal (such as the signal for transmitting monitoring images or intercom voice messages).

[0120] After filtering out the noise components, wavelet reconstruction is performed on each sub-band signal after filtering, and the denoised data stream can be obtained after reconstruction.

[0121] Wavelet reconstruction refers to the inverse operation of wavelet decomposition, which re-merges the multi-layered sub-band signals after noise removal and correction into a complete and continuous digital signal. That is, according to the reverse hierarchical order during decomposition, the high and low frequency sub-bands are superimposed and merged layer by layer. After the multi-layer signals are merged, a series of digital sequences without random noise, with regular bits and continuous flow is output. This data sequence is the noise-reduced data stream.

[0122] Furthermore, it is worth noting that in practical applications, the intensity of multipath reflections and burst RF noise changes in real time. If the noise reduction threshold is set to a fixed threshold, it is easy for weak effective signals to be mistakenly filtered out or for noise to remain after filtering. Therefore, in this embodiment, the noise reduction threshold that matches the interference intensity of the current subband signal is dynamically calculated using the statistical variance and energy distribution of the wavelet coefficients.

[0123] Specifically, based on the sub-band coefficients obtained from the decomposition, their statistical characteristics are analyzed in real time. For each detailed sub-band, the absolute median difference of the sub-band coefficients is calculated as an estimate of the noise level, and the L2 norm of the sub-band coefficients is calculated as a signal energy index.

[0124] Then, an adaptive thresholding algorithm is used to determine the noise reduction threshold. Specifically: for the first... For layer detail subbands, the noise reduction threshold can be set to: ,in, For the first The noise reduction threshold of layer detail subbands For the first The noise standard deviation estimate of a layer detail subband characterizes the noise intensity in that subband. For the first The number of coefficients in the layer detail subband. For the first The adaptive factor for layer detail subbands is adjusted in the range of 0.8-1.6.

[0125] It is worth noting that, to address the common pulse interference in real-world communication environments, an anomaly detection mechanism can be added. Specifically, when the peak value of a subband coefficient exceeds eight times its average, the threshold strategy is automatically switched. The threshold update cycle is synchronized with the OFDM symbol period, and anti-jitter filtering is implemented to prevent sudden threshold changes. Specifically, a soft thresholding function is used to shrink the detail subband coefficients: for detail subband coefficients... , processed value , These are the detail subband coefficients after soft-threshold shrinkage, which will replace the original detail subband coefficients. It participates in subsequent wavelet reconstruction to generate a denoised time-domain signal. For the sign function, when hour, ,when hour, ,when hour, Ensure the coefficients after processing symbols and Maintain consistency. For the original detail subband coefficients The absolute value, This is the core of soft threshold operation. If this coefficient is considered to be mainly noise, then... ,therefore ,final The noise is eliminated, if If so, then the coefficient is considered to contain a significant signal component. ,therefore ,final The signal is preserved, but its amplitude is "contracted". To protect the main signal components, a protection mechanism is implemented for sub-bands containing high-frequency components of the main signal. When the estimated signal-to-noise ratio of this sub-band is greater than 15dB, a protection mechanism is adopted. Conservative denoising is performed using a conservative threshold. The processed coefficients of each subband are sent to the reconstruction process. Wavelet inverse transform is performed through a four-level two-interpolation filter bank. Then, mirror symmetric boundary processing is adopted to output the denoised data stream. The total delay of the entire processing link is controlled within an acceptable range. The denoised data stream is then output to the subsequent processing flow.

[0126] Step S150: Based on the characteristics of the noise-reduced data stream, determine the timing constraint model, and based on the timing constraint model, determine the priority of each data processing path in the receiving link. According to the priority of each data processing path, use a preset optimization algorithm to optimize the layout of each data processing path.

[0127] Specifically, in step S150, based on the characteristics of the denoised data stream, the timing constraint model is first reconstructed, and based on the reconstructed timing constraint model, the priority of each data processing path in the receiving link is determined. The timing constraint model is a configurable dynamic parameter set that describes the upper limit of delay, the lower limit of throughput, and the processing resource quota that each data processing path must meet under the current service load and channel conditions.

[0128] The data processing paths consist of multiple parallel hardware paths within the wireless communication chip, each responsible for different operations such as filtering, noise reduction, verification, and caching. The layout of the data processing paths refers to the physical arrangement of the chip's internal circuitry, signal lines, and arithmetic units. In this embodiment, optimizing the layout of each data processing path refers to optimizing the physical arrangement of the chip's internal hardware circuitry, signal lines, and arithmetic units.

[0129] Specifically, in step S150, a timing constraint model is determined based on the characteristics of the denoised data stream, such as its rate, length, and transmission interval. The priority of each data processing path is then determined based on this model; for example, a high priority is set for the real-time video transmission path, while a low priority is set for the background cache verification path. According to the priority of each data processing path, a preset optimization algorithm is used to optimize the layout of each path. This includes adjusting the physical traces of the chips in each path and distributing high-concurrency computing modules, thereby reducing the chip's instantaneous power consumption, minimizing heat generation, and extending the overall battery life and stable operating time.

[0130] In some embodiments, a timing constraint model is determined based on the characteristics of the denoised data stream. Specifically, this may include analyzing and extracting statistical characteristics of the denoised data streams received within a preset continuous reception period. These statistical characteristics include data arrival intervals, payload length distribution, and hybrid decoding mode switching frequency, in order to capture dynamic operating modes and behavioral characteristics in complex scenarios.

[0131] Specifically, core characteristic parameters are calculated in real time within multiple consecutive data packet reception cycles, including data packet arrival interval, payload length distribution, and hybrid decoding mode switching frequency. The data packet arrival interval is obtained by recording the time difference between the end times of the preamble of two adjacent valid data packets, and the statistical window length is dynamically adapted to the current service traffic intensity. The payload length distribution is obtained by parsing the length field in the header of the physical layer protocol data unit, and the proportions of short packets (<256 bytes), medium packets (256-1024 bytes), and long packets (>1024 bytes) are classified and statistically analyzed. The hybrid decoding mode switching frequency is calculated by monitoring the number of times the LDPC and Viterbi decoding paths are switched per unit time. All characteristic parameters are maintained in a sliding window manner, and the statistical values ​​are updated once after each data packet is processed.

[0132] After obtaining the statistical features, the extracted statistical features are used as input to reconstruct the timing constraint model that characterizes the dynamic behavior of the communication link under actual working mode. The model focuses on constraining high-risk data processing paths caused by mode switching and burst data streams, so as to achieve precise timing control that matches the time-varying channel and service load and improve the timing convergence of the system.

[0133] Specifically, the process of reconstructing the timing constraint model can include: updating the latency constraints and priority weights within the model based on three types of features: data arrival interval, payload length distribution, and decoding mode switching frequency, using sliding window statistics and threshold-triggered adjustment methods. Specifically, firstly, core feature parameters, including data packet arrival interval, payload length distribution, and hybrid decoding mode switching frequency, are calculated in real time. Then, the parameters in the timing constraint model are adjusted according to the feature values ​​of the core feature parameters: if the arrival interval shortens and the payload increases, the latency constraints of high-throughput data channels are tightened (where high-throughput data channels refer to data streams carrying the main business content, specifically including aggregated data streams and real-time video / audio sampling data streams; the identification rule is: the data stream type belongs to continuous high-volume business data, and it needs to ensure that the physical layer negotiation rate is not less than 80% of the throughput). The identification timing can be during the protocol stack task preprocessing stage, based on the statistical features (arrival interval, payload length, switching frequency) output by the timing constraint model for judgment and marking. Tightening the latency constraints is reflected by adjusting the latency violation weight coefficient in the cost function; when a shortened arrival interval and increased payload are detected... In the simulated annealing cost function, the latency violation penalty weight for this data flow path is increased from the default value of 10, causing the optimization engine to prioritize finding lower latency layout schemes for the data flow path during iteration. That is, when the packet arrival interval is shortened by more than 30% compared to the historical average, and the payload length increases by more than 50% (i.e., the business traffic increases significantly), tightening is triggered. The tightening can be a proportional compression of the target latency upper limit by a compression factor. The tightened latency upper limit must not be lower than the hardware physical minimum processing latency. The compression factor is the ratio of the current average arrival interval to the historical average arrival interval. In the cost function, the latency violation weight coefficient of the path is multiplied by the reciprocal of the compression factor. That is, the larger the traffic and the shorter the interval, the heavier the penalty, guiding the optimization engine to converge towards a shorter latency layout.If the decoding switching frequency increases, the response priority of high-risk paths is enhanced (high-risk data processing paths refer to control data flows that directly affect the correctness of decoding, specifically including LDPC / Viterbi mode selection control flows and wavelet coefficient reconstruction trigger flows of the noise reduction module; the identification rule is: the data flow type belongs to mode switching control or reconstruction trigger signals, and once a delay violation occurs, it will directly lead to decoding failure or data retransmission); the enhanced priority is not achieved by directly increasing the priority level in the model, but by adjusting the scheduling order and reserving additional processing bandwidth in the protocol stack task scheduler, placing paths marked as P0 at the front of the scheduling queue and allocating 15% of additional processing time slots to ensure that they have priority in queuing; the priority increase rule is as follows: Specifically, this can include: triggering conditions such as increasing the decoding mode switching frequency by more than 100% compared to the historical average (rapid channel fluctuation), or increasing the equivalent signal-to-noise ratio by less than 12dB (channel quality degradation), and increasing the trigger priority by moving the target path's position in the scheduling queue up by N positions, but not exceeding 50% of the total queue length, where N = the total number of currently queued data streams × 30% (rounded up). A dynamic priority offset is added to the task descriptor, which changes linearly with the degree of channel fluctuation, and the greater the fluctuation, the greater the offset (and is recalculated before the start of each data packet processing cycle), and more processing time budget is reserved; and the update cycle is synchronized with the statistical window of the statistical characteristics.

[0134] Specifically, based on this timing constraint model, critical data flows, including high-risk data processing paths, high-throughput data channels, and global control signaling, can be pre-labeled in the communication protocol stack, setting their processing priorities and latency targets. Specifically, the priority determination method is pre-labeling and hierarchical constraints. That is, based on the output of the timing constraint model, data flows are divided into three levels (P0 / P1 / P2) during the protocol stack task preprocessing stage. (Specifically, the timing constraint model does not directly output priority labels; instead, it provides quantitative performance requirements for each data flow under the current operating conditions, including latency upper limits, throughput lower limits, and resource quotas, providing a basis for priority division. Priority division is the result of comparing and ranking the quantitative performance requirements with the system state. Priority division is based on the relative requirements of latency upper limits, throughput lower limits, and resource quotas, as well as the severity of the consequences of violations, ranking and classifying data flows. The stricter the constraints and the higher the cost of violation, the higher the priority of the data flow.) Each level is bound to different latency targets and resource allocation strategies. Among them, high-risk data processing paths can be marked with priority level P0, high-throughput data channels can be marked with priority level P1, and global control signaling can be marked with priority level P2, so as to ensure the performance of critical paths and reduce overall power consumption.

[0135] Specifically, the rules for determining priorities based on the parameters of the time-series constraint model can include: prioritizing rigid constraints, followed by resource requirements, and then business type. This is achieved by comparing the three parameters of each data stream with preset thresholds and then mapping them to the corresponding levels.

[0136] The P0 level (highest priority) determination rule is as follows: the latency constraint is the most stringent, and a violation will result in system malfunction. The trigger condition is that the upper limit of the latency of a certain data stream is ≤500μs, and the interruption of the data stream will cause decoding failure or loss of system control commands. The mapping basis is the most pressing upper limit of latency parameter in the timing constraint model corresponding to the data stream. The time requirement is close to the physical layer processing limit. Any timeout will directly cause communication interruption or serious bit errors. It must be classified into the highest priority P0 level to ensure that it receives the highest priority processing resources.

[0137] P1 Level (Medium Priority) Judgment Rules: Stricter latency constraints and carries the main business content. Triggering Conditions: When the upper limit of latency for a data stream is within the range of 500μs~1ms, and the lower limit of throughput is ≥80% of the physical layer negotiation rate. Mapping Basis: Determined by both the upper limit of latency and the lower limit of throughput. Although it has high requirements for real-time performance, the tolerable latency window is slightly wider than that of P0 level, and the requirements for data integrity are lower than those for control signaling. Based on throughput, it needs to be given priority in ensuring bandwidth resources, but short-term waiting is allowed in extreme congestion situations.

[0138] P2 Level (Lowest Priority) Judgment Rules: Lax latency constraints or no hard latency requirements. Triggering Condition: When the latency limit of a data stream is >1ms or no explicit latency limit is defined, and its interruption does not affect core communication functions. Mapping Basis: Based on the latency limit parameter in the timing constraint model, if this value is large or does not exist, it indicates that there is no rigid requirement for the real-time performance of this type of data stream, resource quotas are set to be allocated on demand, and no dedicated allocation is required. This type of data stream is of a management or auxiliary nature, has the lowest priority, and is only processed when the system has sufficient capacity.

[0139] Priority mapping is dynamically remapped as the sequence constraint model parameters are periodically updated, ensuring that priorities always reflect the actual needs under current channel and load conditions.

[0140] It is worth noting that the priority division needs to be updated synchronously. When the channel quality deteriorates: if the real-time equivalent signal-to-noise ratio decreases, the timing constraint model will automatically tighten the upper limit of the delay of high-priority data streams (e.g., from 500μs to 450μs). At this time, the data streams that were originally in the edge state will be upgraded to higher priority due to the new delay upper limit triggering the P0 level judgment condition.

[0141] When the workload decreases: If the data packet arrival interval is significantly extended, the timing constraint model relaxes the delay limit of non-critical data flows. At this time, data flows that were originally classified as P1 level due to strict delay requirements are downgraded to P2 level because their delay limit is relaxed to more than 1ms, in order to release system resources.

[0142] After reconstructing the time-series constraint model based on statistical characteristics, the priorities of each data processing path need to be adjusted according to the reconstructed model to determine the priority of the reconstructed data processing paths. The reconstructed time-series constraint model exists as a set of configurable parameters, which is distributed to the task scheduler of the communication protocol stack through the system management interface. The model's update cycle is synchronized with the statistical update cycle of the statistical characteristics to ensure rapid response to dynamic changes in channel conditions and service traffic.

[0143] For example, using the extracted statistical features as input, this time-constrained model dynamically adjusts the timing expectations for subsequent data processing based on the burstiness and load distribution of the current data packets: when it detects that the data packet arrival interval is shortening and the effective payload is increasing, the model automatically tightens the delay constraints on high-throughput data channels, requiring them to complete data stream forwarding in a shorter time; when it detects that the decoding mode switching frequency is increasing, the model determines that the channel is in a rapid fluctuation state, and accordingly enhances the response priority of high-risk data processing paths (such as decoder mode switching control paths) and reserves more processing time budget for them.

[0144] More specifically, based on the reconstructed timing constraint model, a critical data flow marking operation is performed during the task preprocessing stage of the communication protocol stack. Three types of critical data flows are identified and marked: high-risk data processing paths, including LDPC / Viterbi mode selection control flows and wavelet coefficient reconstruction trigger flows for the noise reduction module, are marked with a priority of P0, requiring end-to-end processing latency not exceeding the processing cycle of one data packet; high-throughput data channels, encompassing aggregated data bearer flows and real-time video / audio sampling data flows, are marked with a priority of P1, requiring data flow forwarding throughput not less than 80% of the physical layer negotiation rate; and global control signaling, including power management wake-up commands and channel status query commands, are marked with a priority of P2. All marking information is recorded in the task descriptor of the protocol stack for differentiated processing during subsequent task scheduling when allocating system resources such as processor cores, memory bandwidth, and DMA channels.

[0145] In some embodiments, the wireless communication optimization method further includes: statistically analyzing the arrival intervals of historical data packets and predicting the arrival time of data packets in the next time period. Based on the predicted arrival time of data packets in the next time period, a predicted idle window is determined. Within the predicted idle window, a preset module in the wireless communication chip is controlled to enter a preset low-power sleep state. The current busy / idle status of the receiving link is evaluated in real time. Based on the busy / idle status of the receiving link and the arrival intervals, a reserved time window is determined between the preset module waking up from the preset low-power sleep state and fully responding to the next data packet.

[0146] The preset module can be the radio frequency front-end, ADC (Analog-to-Digital Converter) sampling interface, and part of the baseband processing module in the receiving link.

[0147] Specifically, by statistically analyzing the arrival intervals of historical data packets, an exponentially weighted moving average algorithm is used to predict the arrival time of data packets in the next time period. Within the predicted idle window (the time period from the arrival of a data packet to the arrival of the next data packet), sleep commands can be actively sent to the RF front-end, ADC sampling interface, and some baseband processing modules in the receiving link to put them into a low-power sleep state.

[0148] Meanwhile, the Clear Channel Assessment (CCA) mechanism is used to assess the current channel's busy / idle status in real time. When CCA reports the channel as idle multiple times consecutively for a duration exceeding a preset static threshold, the timing margin allocation period is automatically extended. This increases the reserved time window between waking from sleep mode and fully responding to the next data packet, allowing the system to remain in deep sleep over a longer timescale and reducing power consumption waste caused by periodic wake-ups for invalid channel detection.

[0149] When a significant reduction in the data packet arrival interval is detected (more than 50% lower than the historical average) or the CCA state changes from frequent idle to busy, it is determined that a sudden change in the service mode has occurred. The timing margin allocation cycle is immediately shortened, and the reservation time between wake-up and response is shortened, so that the receiving link can quickly switch from low power mode to high responsiveness processing mode. In this way, while ensuring real-time communication, the power consumption caused by idle listening and invalid wake-up is minimized.

[0150] Furthermore, after determining the priority of each data processing path using the time-series constraint model, the layout of each data processing path needs to be optimized according to the priority of each data processing path using a preset optimization algorithm.

[0151] Reference Figure 3In some exemplary embodiments, in step S150, the layout of each data processing path is optimized according to the priority of each data processing path using a preset optimization algorithm, which may specifically include the following steps S151-S153.

[0152] Step S151: Iteratively optimize the layout of the data processing path using perturbation.

[0153] Step S152: After each iteration, calculate the cost function value corresponding to the layout of the data processing path after the iteration, and complete one iteration.

[0154] Step S153: Based on the cost function value, use a preset optimization algorithm to iterate the layout of the data processing path until the layout of the data processing path after iteration satisfies the preset delay balance target, and then end the iteration.

[0155] In some embodiments, step S151 involves iterative perturbation optimization of the data processing path layout, which may specifically include performing random perturbation operations on the current data processing path layout. These random perturbation operations include swapping the processing order of adjacent data streams and adjusting the processing priority of non-critical data streams. For data processing paths with priorities belonging to a preset target priority, local load balancing rescheduling is performed to achieve iterative perturbation optimization.

[0156] Specifically, in steps S151-S153, it is first necessary to establish a multi-objective cost function to drive simulated annealing optimization based on the reconstructed temporal constraint model.

[0157] The cost function includes three core variables: data processing path delay violations, data stream load distribution, and processing node congestion. Its calculation is based on the reliability requirements of wireless LAN communication and system resource scheduling specifications.

[0158] Among them, the number of data processing path delay violations is directly related to the system's timing convergence. Its calculation benchmark is the key data flow processing delay target defined in the model. For example, for high-risk data processing paths marked as P0, the end-to-end processing delay is required to be no less than +200μs and the queue waiting delay is required to be no less than +150μs. The number of violations is the difference between the actual processing delay analysis result and the above target.

[0159] Data flow load distribution is a key parameter affecting the dynamic power consumption and processing throughput of the system. Its estimation is based on the historical data flow statistical characteristics and the actual load of the current processing topology. The optimization goal is to control the load rate of the processing nodes of high-priority data flows to below 0.15 per millisecond in order to reduce the power consumption increase caused by node congestion.

[0160] The congestion level of a processing node characterizes the tension of local data processing resources. It is obtained by dividing the processing time axis into a scheduling window of 5ms×5ms and calculating the ratio of the number of task requests to the number of available processing time slots in each window. The maximum global congestion level is required to not exceed 85% in order to avoid increased processing delays and retransmissions due to over-congestion.

[0161] Specifically, the cost function can be: .

[0162] In the formula, Given the cost value (i.e., cost function value) of the current processing solution, the optimization goal is to find, through iteration, a solution that minimizes cost. The minimum processing solution comprehensively reflects the degree of poor performance of the solution in three dimensions: latency, load balancing, and schedulability. The smaller the value, the better the solution.

[0163] These are the weight coefficients for delay violations, data load, and congestion handling, respectively. Among them, the weight Wt for delay violations is 10, which is the maximum value of all weights. This represents that the core optimization objective is to meet the timing constraints. Any solution that causes the critical data flow to exceed the delay target will be significantly penalized by the cost function, driving the optimization algorithm to prioritize the elimination of violations.

[0164] The data load weight Wc is set to 0.5, which is the minimum value among all weights. This means that the tasks are distributed to avoid overloading individual nodes without significantly affecting latency, but without sacrificing latency performance for load balancing.

[0165] The congestion weight Wo is set to 1.5, which is a middle value, indicating that congestion control is an auxiliary but not negligible goal.

[0166] All three weights are fixed values ​​and are not dynamically adjusted based on channel status, service type, or number of iterations, ensuring the stability and reproducibility of the optimization process.

[0167] and For the first End-to-end latency violations and queue wait latency violations for each data stream; This is the sum of all data streams. The sum of all processing nodes; For the first Data arrival rate weighting factor for each processing node; For the first The current load rate of each processing node; Weighted sum of global load; To handle the global peak congestion level, the processing time axis is divided into scheduling windows. For each window, the following calculations are performed: , For the congestion level of each window, This represents the number of task requests within this window. The number of processing time slots available for this window. This is the maximum congestion level across all windows.

[0168] When using this cost function for optimization, the simulated annealing optimization engine is started to optimize the layout of the data processing path by using the simulated annealing optimization algorithm as the preset optimization algorithm.

[0169] Specifically, this simulated annealing optimization engine is calibrated based on system performance under typical business scenarios (standby mode and burst transmission mode). The initial temperature parameter is set to a relatively high value, corresponding to a high probability of the algorithm accepting suboptimal solutions. For example, the annealing temperature... The initial value (i.e., the initial temperature parameter) is set to 1.5 × 10. 5 And according to the geometric cooling schedule, it decays to 0.95 times every hundred iterations.

[0170] In each iteration, the simulated annealing optimization engine performs a random perturbation operation on the current data processing topology (i.e., the layout of data processing paths). The perturbation operation is limited to the system resource scheduling rules and includes: swapping the processing order of non-critical data streams; adjusting specific data streams from the current processing node to adjacent nodes under the premise of satisfying priority constraints; and locally splitting and rerouting data streams in high-congestion areas.

[0171] In addition, for critical data streams with a pre-labeled priority of P0, their processing topology is protected during the iteration process. That is, it is restricted to fine-tuning within its reserved 15% extra processing bandwidth to ensure that its latency target (less than 500 μs) is not compromised, and a new candidate processing scheme is generated after each perturbation.

[0172] Specifically, in each iteration of the simulated annealing optimization engine, a random perturbation operation is performed on the current global data processing topology. This operation includes two types: First, swapping the processing order of adjacent data streams. That is, while satisfying data dependencies, the processing order of two independent data streams in the waiting queue is interchanged to attempt to improve load balancing and data correlation conflicts within local processing units. Second, adjusting the processing priority of non-critical data streams. Within the limits of overall system latency constraints, the scheduling priority of non-critical services (such as background data synchronization) can be temporarily reduced, reserving corresponding computing resources for potential bursts of data streams. Specifically, a tiered downgrade approach can be used to adjust the processing priority of non-critical data streams. Specifically, the original scheduling priority (P2 level) is uniformly reduced by one priority level (to P3 level, i.e., the lowest background priority), triggered only within the limits of overall system latency constraints. Specific quantification conditions: The current global maximum latency violation count is 0, the queuing latency of all P0 / P1 level paths does not exceed 150μs, and the system's end-to-end processing latency has a margin of ≥200μs. After degradation, the adjusted non-critical data flows relinquish approximately 15% of their processing bandwidth or time slot resources, which are then reallocated to critical paths. When the system detects that the latency margin is below 100μs or a new latency violation occurs on a P0 / P1 level path, the degraded non-critical data flows immediately revert to their original P2 level. All disturbance operations are performed under the control of the system resource scheduler, ensuring that each modification affects no more than 0.5% of the data flow relationships in the global data processing scheme to maintain the stability of the iteration process.

[0173] After completing the basic random perturbation, the simulated annealing optimization engine performs targeted local rescheduling and load balancing on high-risk data processing paths with priority P0 and high-throughput data channels with priority P1, based on the pre-labeled files generated in the preprocessing stage.

[0174] This involves identifying data queues or processing nodes whose real-time processing congestion exceeds 75% and traversing critical data flows. Then, within the 15% additional processing time slots or bandwidth resources reserved for these nodes, a heuristic rescheduling algorithm based on a cost function is used for path reconstruction. This splits a single high-load data flow into multiple parallel processing sub-flows, and distributes the load by dynamically allocating intermediate buffers and processing threads. Specifically, in each iteration of the simulated annealing optimization engine, the cost function value is used as the evaluation criterion to prioritize local path adjustments for data flows on processing nodes with current congestion exceeding 75%. The core logic is that when the real-time congestion of a processing node or data queue exceeds a threshold, instead of randomly searching for the global optimum, the most congested node is selected based on feedback from the three variables in the cost function: latency violation rate, load distribution, and congestion. One or more data flows from this node are migrated to adjacent idle nodes with congestion below 60%, and the cost function value is recalculated after the migration. If the cost is reduced, the adjustment result is retained.

[0175] The splitting of high-load data streams is based on the effective payload length distribution characteristics of the data streams and the real-time load rate of the current processing nodes, determining the number of sub-streams and the data volume of each sub-stream. The specific splitting rules are as follows:

[0176] When the congestion level of a processing node containing a data stream exceeds 75%, the payload length of that data stream is extracted (obtained by parsing the PPDU header length field). If it is a long packet (>1024 bytes), it is split into multiple medium-sized sub-streams (256-1024 bytes). If it is a medium-sized packet, it is split into two sub-streams. If it is a short packet (<256 bytes), it is not split and is directly migrated to an adjacent idle node.

[0177] Furthermore, the maximum number of sub-streams is limited by the additional bandwidth quota of the priority level to which the data stream belongs. That is, a P0-level path is only allowed to be split within its reserved 15% additional processing bandwidth. For a P0-level data stream, it can be split into a maximum of 2 sub-streams.

[0178] For P1 level data streams, if the congestion of the processing channel to which it belongs exceeds 85%, it can be split into a maximum of 3 sub-streams. It is also necessary to ensure that the path delay of each sub-stream after splitting does not exceed 500 microseconds (P0 level) or meets the requirement that the throughput is not less than 80% of the physical layer negotiation rate (P1 level).

[0179] In addition, dynamic allocation of intermediate cache refers to allocating cache blocks of corresponding capacity as needed based on the number of sub-streams and the amount of data after splitting. Each sub-stream occupies a dedicated cache block, and the block size is configured to be 1.2 times the amount of data in the sub-stream. The allocation rule adopts the principle of proximity priority, giving priority to allocating cache blocks that are physically adjacent to the target processing node.

[0180] Load balancing in processing threads refers to dividing all processing tasks originally belonging to a single data stream into multiple parallel threads according to the proportion of data volume in the sub-streams. Each thread independently processes all link operations of a sub-stream, and the threads are synchronized by reading the completion pose of buffer blocks. After all sub-threads have completed processing, the processing results of each sub-stream are merged in the order of the original data stream.

[0181] Specifically, the rule for load balancing is to allocate processing tasks according to the proportion of data volume. For example, if a 1024-byte long packet is split into two sub-streams (512 bytes each), the two processing threads will each undertake 50% of the original processing workload; if it is split into three sub-streams (approximately 341 bytes each), the three threads will each undertake approximately 33.3% of the workload.

[0182] The allocation of threads is determined by the task scheduler based on the real-time load rate of each processing node. Substreams are preferentially allocated to the processing node with the lowest current congestion, and the total load of substreams allocated to any single node shall not exceed 85% of the node's processing capacity.

[0183] In addition, for high-throughput data channels, the data flow path is forced to prioritize passing through the computing node with the strongest processing capability or a dedicated acceleration unit, and the estimated queuing and processing delay of any processing and forwarding link is ensured not to exceed 25 microseconds, in order to meet the end-to-end path delay budget of 500 microseconds.

[0184] Specifically, the process of local surge scheduling and load balancing for high-risk data processing paths and high-throughput channels includes three adjustments to the physical layout and resource allocation of the data processing paths without changing the main processing architecture of the chip:

[0185] First, identify the data queues or processing nodes through which key data flows have a real-time processing congestion rate exceeding 75%. In the reserved 15% extra processing time slot, use a heuristic rescheduling algorithm based on a cost function to reconstruct the path, splitting a single high-load data flow into multiple parallel processing sub-flows. Then, by dynamically allocating intermediate buffers and processing threads, the load is distributed to adjacent idle processing nodes.

[0186] Second, for P1-level high-throughput data channels, the data flow path is forced to prioritize passing through the computing nodes with the strongest processing capabilities (on the existing physical interconnect topology of the chip, the mapping relationship between the data flow and the processing nodes is reconfigured to adjust the logical path; that is, at the task scheduling level, the processing tasks of the P1-level data flow are preferentially allocated to the physically adjacent and most powerful processing nodes, logically forming a data flow path through the strong nodes), ensuring that the estimated queuing and processing latency of any processing and forwarding link does not exceed 25 microseconds, meeting the 500 microsecond path latency budget. Specifically, this can be achieved through the following three executable scheduling actions, acting on the chip's resource allocation and task sequencing level: Action 1: Processing node binding, specifying a dedicated list of processing nodes for the P1-level data flow, sorted by node computing capabilities, with the strongest node at the top. When allocating tasks, the scheduler prioritizes selecting idle nodes from the head of the list, ensuring that the data flow tries to use the strongest node first. Action 2: Load-aware path selection. When the strongest node's congestion exceeds 85%, the scheduler allows P1-level data flows to be migrated to the second strongest node with a current congestion level below 60%. This migration rule is written into the perturbation operation set of the simulated annealing optimization engine as one of the constraints for cost function optimization. Action 3: Forced queuing and reservation. For P1-level data flows, a priority upgrade flag is set in the waiting queue of the bound strongest node, ensuring that its queuing position is always ahead of P2 / P3-level data flows on the same node. At the same time, 15% of the node's processing capacity is reserved as dedicated bandwidth for P1-level data flows to ensure that processing slots are available even under congestion.

[0187] Third, at the physical routing level, high-concurrency computing modules (high-concurrency computing modules refer to processing units that need to process multiple data streams per unit time and whose instantaneous flip-flop rate is significantly higher than the chip average level, specifically determined by three indicators: 1) Data stream throughput density: within any 5ms × 5ms scheduling window, if the number of data streams passing through the module exceeds twice the average number of data streams across all modules of the chip within that window, it is considered a high-concurrency module; 2) Transistor flip-flop frequency: if the flip-flop rate of the core computing unit inside the module consistently exceeds 70% within the clock cycle, that is, transistor state switching occurs in 70 out of every 100 clock cycles, it is considered high-concurrency. The high-concurrency computing module is defined by three criteria: First, instantaneous power density. The instantaneous power consumption of the module exceeds 1.5 times the chip's global average power density, and this value remains constant during burst transmission. Any processing unit that meets two or more of these criteria is considered a high-concurrency computing module. For example, a high-concurrency computing module may include: an LDPC decoder, a wavelet noise reduction unit, and an FFT / IFFT operation unit in the OFDM symbol processing process. These components are distributed to prevent multiple high-priority data streams from crowding the same chip area. Simultaneously, the physical spacing of corresponding signal lines is adjusted to reduce the instantaneous current peaks generated by the synchronous high-frequency switching of local transistors, eliminating wiring hotspots.

[0188] Specifically, the implementation process of distributing high-concurrency computing modules is as follows: The core principle of this distribution is to space the high-concurrency computing modules along the physical diagonal or four corners of the chip, and insert low-activity modules in between as buffer zones to disperse instantaneous current peaks and heat accumulation. The specific distribution strategy is as follows:

[0189] First, identify the core high-concurrency module cluster. From the global data processing topology, find all units marked as high-concurrency computing modules. By analyzing the data flow dependencies between modules, identify the module groups that have frequent data interactions with each other.

[0190] Then, a spatially distributed layout is implemented, physically separating the identified high-concurrency module clusters. The specific rules are as follows: high-concurrency computing modules that were originally clustered in a small area in the center of the chip (such as an area accounting for less than 15% of the total chip area) are redistributed to the four physical quadrants of the chip or different sections along the long side of the chip. For example, the LDPC decoder array is arranged in the upper left area of ​​the chip; the wavelet noise reduction filter bank is arranged in the lower right area of ​​the chip; the FFT / IFFT operation unit is arranged in the upper right area of ​​the chip; and the complex multiplier-adder array is arranged in the lower left area of ​​the chip. The physical spacing between each module should be at least 50 times the minimum linewidth of the area to ensure sufficient heat dissipation area and power supply regulation space.

[0191] Then, an isolation buffer is inserted. Between the dispersed high-concurrency computing modules, low-activity modules (such as slow control register groups, configuration parameter storage units, and idle buffer queues) are forcibly arranged as physical isolation zones. The transistor flip-flop rate of the low-activity modules is less than 10%, and they will not generate significant heat or instantaneous current. The width of the isolation zone is set to accommodate at least 3 standard signal wiring channels, which physically cuts off the mutual conduction paths of heat and current spikes.

[0192] Finally, adjust the physical spacing of the signal lines. For the global signal lines of the high-concurrency computing modules that are connected in a distributed manner, increase their physical spacing by 50% from the default value and add shielded ground wires to prevent crosstalk between multiple high-speed signal lines due to excessive distance, and at the same time avoid signal lines being squeezed into the same channel to form new wiring hotspots.

[0193] In addition, adjusting the physical spacing of corresponding signal lines can specifically identify the set of signal lines whose spacing needs to be adjusted, namely the critical high-speed signal lines in the data bus, control bus, and clock distribution network that connect to high-concurrency computing modules. In the routing constraint file of the EDA tool, additional spacing constraint rules are specified separately for critical high-speed signal lines, making them different from the default spacing rules for ordinary low-speed signal lines. When the routing engine is laying out and routing, it assigns a physical position to each signal line according to this constraint, ensuring that the spacing between it and adjacent signal lines is not less than the specified value.

[0194] When making adjustments, the principle of hierarchical and proportional approaches is followed. The minimum physical pitch allowed by the chip process (dmin, given by the design rule manual provided by the wafer foundry) is used as the benchmark, and different multiples are set according to the signal line flip rate and data flow priority.

[0195] The specific adjustment rules are as follows: Ordinary low-speed signal lines (control signaling, configuration parameters): maintain the default spacing, i.e., 1.0 × dmin. Medium-speed data signal lines (data buses related to P2-level data flows): adjust the spacing to 1.5 × dmin. High-speed critical signal lines (buses connecting high-concurrency modules, P1-level data channels): adjust the spacing to 2.0 × dmin; when the node congestion in the area where this signal line is located exceeds 75%, further increase the spacing to 2.5 × dmin. Clock distribution network signal lines: adjust the spacing to 3.0 × dmin, and grounded shielding wires must be installed on both sides.

[0196] It is worth noting that the following restrictions must be met during the adjustment process. Specifically: Restriction 1: Chip area constraint. Increasing the spacing between signal lines will result in occupying more wiring channel resources, increasing the total chip area, or squeezing the wiring space of other signal lines. The upper limit is set at 3.0 × dmin, that is, the spacing adjustment of any signal line shall not exceed this multiple.

[0197] Limitation 2: Timing delay constraint. Increasing the spacing reduces the parasitic capacitance between signal lines, but the signal line length needs to be increased, which introduces additional transmission delay. It is stipulated that the end-to-end signal propagation delay increase of all signal lines after spacing adjustment shall not exceed 5% of the original delay budget of the signal line. If the simulated annealing optimization engine finds that a spacing adjustment causes the delay to exceed the limit, it will automatically roll back the adjustment and try to replace the increased spacing solution by adjusting the detour path of adjacent signal lines.

[0198] Limitation 3: Boundary limitation of the adjustment range. Spacing adjustment is only performed within the high-speed signal line area where high-concurrency computing modules are interconnected, and does not involve all signal lines of the entire chip. Specifically, the boundary is within a radius of no more than 30% of the total wiring resources in the area centered on the high-concurrency computing module. Once this range is exceeded, the signal line spacing will revert to the default value.

[0199] The entire adjustment is completed through iterative perturbation by the simulated annealing optimization engine. Each perturbation modifies no more than 0.5% of the total global data flow relationship. P0-level paths are only allowed to be fine-tuned within their reserved 15% additional bandwidth.

[0200] After each perturbation operation, a new processing scheme is generated.

[0201] For example, the original processing scheme refers to the physical and logical layout state of the global data processing path at the start of the current iteration, specifically represented by a mapping table of data flow, processing node, and processing order. The mapping table contains three core types of information: data flow identifier (distinguishing between P0 / P1 / P2 levels and their specific service types, such as video stream V1, control signaling C1, and background synchronization B1), processing node number (the physical number of each computing unit within the chip, such as LDPC decoder #3, wavelet noise reduction unit #2, and buffer queue #5), and processing order number (the execution order of multiple data flows on the same node).

[0202] For example, the original processing scheme is specifically represented as: data stream V1 (P0 level) - node #3 (LDPC decoder) - sequence 1; data stream V2 (P1 level) - node #3 - sequence 2; data stream B1 (P2 level) - node #5 (buffer queue) - sequence 1.

[0203] The global latency violation count is 0, but the real-time congestion of node #3 has reached 78% (exceeding the 75% threshold). The overall system latency margin is 180μs (below the 200μs safety threshold). Therefore, it is stored in the protocol stack in the form of a task descriptor linked list. Each descriptor contains fields such as data stream ID, priority level, source node, target node, processing sequence number, and reserved time budget.

[0204] A perturbation operation refers to performing a constrained random fine-tuning on the original processing scheme. Each time, it only modifies no more than 0.5% of the entries in the global data flow relationship pair, and must not violate the hard latency constraints of data dependencies and P0-level paths.

[0205] The disturbance operation includes two types of actions: 1. Action one is to exchange the processing order of adjacent data streams, which means to exchange the processing order of two independent data streams with no data dependency in the waiting queue of the same processing node; 2. Action two is to adjust the processing node affiliation of non-critical data streams, and to migrate a certain P2 level data stream from the current node to an adjacent idle node with lower congestion.

[0206] Example of a disturbance operation: If the congestion level of node #3 is detected to be 78% and the congestion level of the adjacent node #7 (idle buffer unit) is 45%, then execute action two: migrate the background synchronization data stream B1 from node #5 to node #7, and at the same time swap the processing order of data stream V2 (P1 level) on node #3 with that of data stream V1 on node #3 (originally V1 order 1-V2 order 2, after swap V2 order 1-V1 order 2). This aims to reduce the instantaneous load peak of node #3 and improve the queuing delay of V2. The disturbance operation does not involve the change of node ownership of P0 level data stream V1, but only adjusts its execution order within the reserved 15% extra processing bandwidth.

[0207] The new processing scheme is an updated mapping table generated by recalculating the cost function value based on the perturbation operation and judging it according to the simulated annealing acceptance criterion. The difference from the original processing scheme lies in the change of the data flow belonging node or processing order, as well as the update delay and congestion prediction.

[0208] The example content of the new processing scheme is as follows: Data flow V1 (P0 level) - node #3 - sequence 2 (the execution order is shifted one position later compared with the original scheme); Data flow V2 (P1 level) - node #3 - sequence 1 (executed earlier compared with the original scheme); Data flow B1 (P2 level) - node #7 (buffer queue) - sequence 1 (the processing node has been changed compared with the original scheme).

[0209] The new processing scheme is then rapidly evaluated by calling a system performance evaluation model calibrated based on historical execution data. This model refers to a performance mapping function pre-fitted through offline simulation, used to quickly estimate the end-to-end latency, node congestion, and resource utilization of the current candidate processing scheme in each iteration of simulated annealing optimization. The core of this model is calibration based on historical execution data. Specifically, during the model development phase, a large number of processing schemes with different data flow combinations, load distributions, and processing orders are run on the simulation platform. The actual latency, throughput, and power consumption data of each processing node under each scheme are recorded. The data is then fitted into a multivariate regression function or lookup table set with data flow length, priority level, and node load rate as inputs and latency and congestion as outputs. The estimated latency and resource utilization of the affected data flow paths are recalculated, and rapid congestion and latency analysis is performed accordingly. Specifically, fast congestion and delay analysis refers to the process of rapidly calculating the task queuing status and data stream transmission time of each processing node in a new processing scheme. It involves summing the processing time required for all currently allocated data streams for each processing node and comparing it with the available processing time slots for that node to quantify the degree of congestion and the number of delay violations.

[0210] The congestion analysis is performed as follows: the processing time axis is divided into 5ms×5ms scheduling windows. For each window, the number of processing task requests for all data streams allocated to that node within the window (measured by the number of processing time slots required) is counted and divided by the total number of processing time slots available to that node within the window to obtain the congestion ratio of that window. The global maximum congestion is the maximum ratio of all nodes and all windows. If this ratio exceeds 85%, it is considered excessive congestion.

[0211] The latency analysis is performed as follows: For each data stream, the queuing time at each node along the path (i.e., the sum of the estimated processing times of all data streams preceding this data stream at that node) is added to the pure processing time to obtain the estimated latency of the data stream. The estimated latency is then subtracted from the latency target corresponding to the data stream priority level (e.g., P0 level requires an end-to-end latency of no less than +200μs and a queuing latency of no less than +150μs). If the difference is positive, a positive latency violation is generated; if it is negative or zero, there is no violation.

[0212] The number of path delay violations and the congestion handling rate are obtained. The cost function value is calculated in real time according to the formula, where the delay violation weighting coefficient is... Set to 10, data load weighting coefficient Set to 0.5 to handle congestion weighting coefficient Set it to 1.5.

[0213] Then, the cost function value of the new processing scheme is compared with the cost function value of the currently obtained optimal processing scheme.

[0214] That is, for each new processing scheme generated in each iteration, its load characteristics are re-extracted, and rapid incremental delay and congestion analysis is performed to calculate its corresponding cost function value.

[0215] For example, after the cost function is re-evaluated, the congestion of node #3 decreases from 78% to 72% (due to the shift of V1 and the advancement of V2, but the computational cost of V2 is lower than that of V1, resulting in a decrease in overall load). The number of global latency violations remains 0, and the overall latency margin increases from 180μs to 195μs. Furthermore, since the cost function value of the new processing scheme is lower than that of the original processing scheme, i.e., the congestion is reduced and the latency margin is increased, the simulated annealing engine accepts this scheme as the current optimal processing scheme. The new processing scheme is also stored in the form of a task descriptor linked list and participates in the perturbation optimization as the "original processing scheme" in the next iteration until the convergence conditions of zero latency violations at all P0 levels, a global maximum congestion of less than 80%, and a cost improvement of less than one-thousandth for five hundred consecutive iterations are met, and then the scheme is solidified.

[0216] The cost assessment specifically calculates the total number of path delay violations, the weighted sum of data flow load, and the peak congestion of the new solution, and compares it with the cost of the current optimal solution. According to the simulated annealing probability criterion, if the cost of the new solution is lower, it is unconditionally accepted as the current optimal solution. If the cost is higher, the deterioration is accepted with a state transition probability, allowing the algorithm to escape local optima in the early stages of optimization. As iterations proceed, the annealing temperature gradually decreases according to a predetermined cooling schedule, and the probability of accepting a deteriorated solution decreases accordingly, causing the search behavior to gradually converge to local improvements.

[0217] The formula for calculating the state transition probability is:

[0218] ; .

[0219] In the formula, The state transition probability for accepting a new, more costly processing scheme is a probability value between 0 and 1. A random number is generated in the interval [0, 1). If this random number is less than... If yes, then accept this worsening solution; otherwise, reject it. For cost increment, The cost value of the newly generated candidate processing scheme. The cost value of the currently accepted optimal processing solution, when This means that the new solution is worse than the current one; This is the current annealing temperature.

[0220] As iterations proceed, the annealing temperature gradually decreases according to a predetermined cooling schedule, reducing the probability of accepting worse solutions and causing the search behavior to gradually converge to local improvements. This optimization process continues until the following three convergence conditions are simultaneously met, at which point the optimization process ends, and the current optimal processing scheme is used as the final optimized data processing path layout.

[0221] The three convergence conditions are as follows: the number of processing delay violations for all P0-level critical data streams is zero; the global maximum processing node congestion drops below 80%; and the improvement of the cost function is less than one-thousandth in 500 consecutive iterations.

[0222] In addition, in this embodiment, channel state information and data packet arrival rate of the receiving link can be collected in real time with a period of 100ms. Short-term traffic trends are dynamically predicted using a triple exponential smoothing method. Based on the prediction results, high-priority data streams pre-marked as P0 are assigned a delay constraint weight that is 15% more lenient than the basic constraint. At the same time, a data stream priority factor with a value range of 1.0 to 2.0 is added to the simulated annealing optimization engine. When the equivalent signal-to-noise ratio is detected to be lower than 12dB or the instantaneous data packet arrival rate exceeds 200 packets / second, the cost coefficient of the corresponding data stream is automatically increased by 30%. This guides the simulated annealing optimization engine to prioritize the planning of processing paths with end-to-end latency of less than 5ms for high-priority data streams, thereby effectively avoiding data accumulation in the queue and reducing data packet timeout retransmissions caused by excessive processing latency.

[0223] Furthermore, in this embodiment, hotspot distribution and power consumption peaks can be monitored in real time through closed-loop feedback to dynamically adjust wiring weights and achieve stable power consumption of the WiFi communication chip.

[0224] Specifically, distributed power consumption monitoring points are deployed in the WIFI communication link to collect the power consumption status and data flow distribution characteristics of each data processing area in real time under long standby and burst transmission scenarios, forming a real-time power consumption perception capability at the communication link level.

[0225] Among them, the power consumption monitoring point takes the logic data stream processing unit as the basic monitoring object, and the monitoring granularity is refined to the power consumption change of each data packet processing cycle. The sampling period is dynamically synchronized with the data packet arrival interval.

[0226] Each monitoring point aggregates power consumption data to the central monitoring unit via an internal status reporting channel within the communication link. This central monitoring unit uses the data stream processing cycle as the time base to integrate and generate a global power consumption distribution map and a data stream hotspot topology map. Specifically, by aligning the real-time power consumption data reported by each distributed power consumption monitoring point according to the start and end times of the data stream processing cycle, and using the processing node coordinates as a spatial index, the power consumption values ​​and data stream identifiers of all monitoring points within the same cycle are superimposed onto a two-dimensional coordinate grid of the chip's physical layout, forming a node mapping map with power consumption and thermal values.

[0227] Specifically, the central monitoring unit uses the processing cycle of each data packet (the complete time period from when the data packet enters the receiving link to when the decoding output is completed) as a unified time reference, collects the instantaneous power consumption sampling values ​​of all processing nodes within the cycle, and then fills the power consumption value of each node into the preset chip layout coordinate table according to its physical location. At the same time, it marks the data flow ID and priority level of the node within the cycle, and finally generates two correlation maps, namely the global power consumption distribution map and the data flow hotspot topology map.

[0228] The global power consumption distribution map uses different color depths to indicate the power consumption levels at each coordinate point. The data flow hotspot topology map uses lines to indicate the flow path of data flow between nodes, and highlights nodes with congestion exceeding 75%.

[0229] The global power consumption distribution map identifies the instantaneous power consumption peaks during burst transmissions in processes such as LDPC decoding and wavelet denoising. The data flow hotspot topology map, based on the data processing channels, locates processing hotspot areas caused by data accumulation or frequent mode switching.

[0230] The central monitoring unit feeds the integrated monitoring data to the link optimization decision engine in real time, forming a closed-loop feedback system. It compares the real-time peak power consumption data with the preset standard power consumption models for each processing stage to identify processing nodes with abnormal power consumption. An abnormal power consumption node is defined as a processing node whose real-time monitored instantaneous peak power consumption exceeds the ±15% fluctuation range of the preset standard power consumption model for that stage. The judgment rule is as follows: the central monitoring unit compares the real-time peak power consumption of each processing node in the current monitoring period with the standard power consumption model value of the processing stage to which the node belongs under the same data packet length and priority level. If the measured value is more than 15% higher than the standard value, it is judged as excessively high power consumption. If the measured value is more than 15% lower than the standard value, and the node also has a congestion level below 40% or a latency violation record, it is judged as excessively low power consumption. Both types of abnormal nodes are marked, and different optimization actions are triggered respectively. Nodes with excessively high power consumption are given priority for load migration or splitting, while nodes with excessively low power consumption are guided by the scheduler to increase their task allocation to balance the overall power consumption distribution.

[0231] The high-load processing area is calculated by overlaying the coordinates of the data stream hotspots with the current link scheduling policy.

[0232] The evaluation results are then transformed into a set of control parameters to drive incremental optimization. These control parameters include three categories: processing priority adjustment coefficient, data stream weight penalty factor, and transmit power adjustment command. The transformation method involves mapping the power consumption anomaly evaluation results to specific numerical values.

[0233] Specifically, for nodes marked with abnormal power consumption, if the power consumption is too high, the processing priority of the P1 / P2 level data streams running on it is reduced by 2 levels (such as P1-P3), and the cost function weight factor of the data streams associated with the node is increased by 30%, guiding the optimization engine to actively avoid it.

[0234] If a node has excessively low power consumption, reduce the weight factor of the cost function of its data flow by 20% to encourage the scheduler to utilize the node.

[0235] For transmit power adjustment commands, when a decrease in received signal quality is detected (increased bit error rate or signal-to-noise ratio below 12dB), the transmit power will be increased by 3dB.

[0236] When channel quality recovers or the receive link is idle, the transmit power will be reduced to the minimum sustain level.

[0237] Specifically: the priority adjustment coefficient for processing nodes with abnormal power consumption, the data flow weight penalty factor for hot spots, and the power adjustment command for the transmit / receive coordination mechanism are all dynamically updated periodically with the data packet arrival interval to ensure that the optimized response speed can match the rate of change of business traffic.

[0238] Subsequently, based on the control parameters generated from the evaluation, incremental optimization is performed on the data processing flow without interrupting communication or changing the main processing architecture. Specifically, for marked critical data flows, the processing priority and resource allocation weight of the data flow are dynamically adjusted according to the real-time load status of its processing node. For non-critical data flows, their cost weight in the global scheduling algorithm is dynamically adjusted based on the real-time power consumption and congestion data of their respective processing channels. For example, the weight of flows in low-load areas is reduced to save processing resources, while the weight of flows in high-load or high-power areas is increased to guide scheduling away from hotspots.

[0239] Meanwhile, a linkage adjustment strategy between the receive link status and the transmit power is introduced to optimize the transmit-receive coordination mechanism. For example, when a decline in received signal quality is detected (such as an increase in bit error rate or a signal-to-noise ratio below a preset threshold), the transmit power is actively increased to ensure link reliability and avoid power waste caused by retransmission. When the channel quality recovers well or the data throughput demand decreases, the transmit power is reduced in a timely manner to reduce redundancy overhead. When the receive link is in an idle listening state and the data stream hotspot distribution shows no pending tasks, the transmit power is further adjusted to the minimum maintenance level, and the low-power sleep window is extended in combination with a timing margin allocation strategy.

[0240] This coordinated adjustment avoids power waste caused by link asymmetry (such as excessively high transmit power while the receive link is idle), ensuring that global power consumption fluctuations remain stable within a preset range under complex environments and sudden service loads, thus achieving a long-term balance between power consumption and processing load.

[0241] It is worth noting that, regarding the wireless communication optimization method of this embodiment, based on the above exemplary implementations, in specific implementation, as a preferred embodiment, it is... Figure 4 as well as Figure 5 As shown, it may include, for example:

[0242] After receiving a WiFi signal, the wireless communication chip identifies whether a pilot signal exists in the signal and whether a training sequence exists in the packet header. If neither a pilot signal nor a training sequence exists, the default synchronization mechanism is used.

[0243] When pilot signals and training sequences are present, power consumption optimization is performed according to the wireless communication optimization method of this embodiment.

[0244] Specifically, when pilot signals and training sequences are present, real-time phase tracking and frequency offset compensation are performed, and then channel state information is output. This channel state information is essentially estimated using the received signal after frequency offset compensation and has been calibrated. Therefore, this channel state information is the calibrated signal state information.

[0245] The channel quality is then assessed based on the channel state information. When the channel signal-to-noise ratio (SNR) is low, a hard-decision decoding method with high error correction capability (such as LDPC) is switched to. When the channel SNR is high, a soft-decision decoding method with low complexity (such as Viterbi) is preferred. Since the LDPC algorithm has stronger error correction capability than Viterbi but higher complexity, Viterbi is selected when the link quality is high, ensuring decoding performance while improving decoding speed and reducing power consumption. LDPC is only activated when the link quality is low (equivalent SNR is below a preset low threshold of 18dB), utilizing strong error correction capability to ensure demodulation accuracy. This is essentially an on-demand allocation strategy, trading complexity for energy efficiency and avoiding unnecessary power consumption.

[0246] After decoding the signal using the appropriate decoding method, the decoded received signal is output. Then, wavelet denoising is performed on the output decoded received signal, and the characteristics of the denoised data stream are analyzed. The time-constrained model is reconstructed using these characteristics to pre-label each data processing path.

[0247] Then, the simulated annealing algorithm is used to optimize the layout of the data processing paths, that is, to optimize the global data processing topology. After each optimization, it is determined whether the optimized topology meets the latency, load, and congestion constraints. If not, the next iteration continues until the latency, load, and congestion constraints are met. And, if they are met, the global data processing topology is fixed, resulting in the optimal layout of the data processing paths.

[0248] Then, distributed power consumption monitoring can be performed to determine whether there are power hotspots or delay violations. If they exist, the processing priority of key data streams and the resource weight of key data streams can be dynamically adjusted, and optimization and power consumption monitoring can continue. If there are no power hotspots or delay violations, the current optimization state can be maintained to achieve power consumption optimization of the wireless communication chip.

[0249] Among them, the key data streams refer to the data streams pre-labeled as P0 level and P1 level. The P0 level includes control data that directly affects the correctness of decoding, such as the LDPC / Viterbi mode selection control stream and the wavelet denoising module coefficient reconstruction trigger stream. The P1 level includes the aggregated data carrier stream and the real-time video / audio sampling data stream that carries the main business content.

[0250] Non-critical data streams refer to data streams pre-marked as P2 level, including power management wake-up commands, channel status query commands, and background data synchronization management and auxiliary data with low real-time requirements;

[0251] The purpose of adjusting processing priorities is to ensure that critical data flows receive priority processing resources when system resources are strained, preventing delay violations caused by excessive queuing. Specifically, when a processing node's congestion exceeds 75% or a delay violation risk is detected, the priority of non-critical data flows on that node is temporarily reduced by one level (e.g., P2-P3), while critical data flows are promoted to the highest scheduling priority within their reserved 15% extra bandwidth. This adjustment can shorten the queuing delay for critical data flows; P0 level delays can be controlled within 150μs. Non-critical data flows are processed later and restored to their original priority after the system latency margin recovers (≥200μs).

[0252] Adjusting resource weights guides the simulated annealing optimization engine to prioritize low-latency paths for high-weight data streams during iterative search, altering the cost function's focus on different data streams. Specifically, resource weights can be adjusted as follows: when the equivalent signal-to-noise ratio is below 12dB or the instantaneous packet arrival rate exceeds 200 packets / second, the cost coefficient of the corresponding critical data stream is increased by 30%, meaning the latency violation rate for that data stream is amplified by 1.3 times in the cost function; for data streams in low-load areas, their weight is reduced by 20% to conserve processing resources. After adjusting resource weights, high-weight data streams incur higher penalty costs during optimization iterations, forcing the algorithm to prioritize paths with lower congestion and higher processing capacity, while low-weight data streams are migrated to less busy nodes, achieving an overall rebalancing of power consumption and processing load.

[0253] A delay violation refers to a situation where the actual processing time of a data stream exceeds the delay target value specified for that priority level. For example, the P0 level requires a processing delay of no more than 500μs and a queue waiting delay of no more than 150μs. If the actual measured end-to-end delay is 550μs, then a positive delay violation of 50μs will be generated.

[0254] Power hotspots refer to localized high-temperature areas in the physical layout of a chip where multiple processing nodes synchronously switch at high frequencies and transistors switch intensively, resulting in a sudden increase in instantaneous current and a power density significantly higher than the surrounding areas. Power hotspots are caused by a large number of high-speed signal lines crowding into the same chip area, i.e., areas where the node congestion rate continuously exceeds 85% and the real-time power consumption peak exceeds the standard model by more than 15%. They need to be eliminated through load distribution and layout optimization.

[0255] In the preferred embodiment of the above wireless communication optimization method, the specific implementation of each step can be found in the descriptions of the above exemplary embodiments, and the beneficial effects brought about by the design of each step in this preferred embodiment can also be found in the descriptions of the above exemplary embodiments.

[0256] The wireless communication optimization method in this embodiment integrates real-time phase tracking based on pilot signals and frequency offset compensation based on training sequences in the receiving link, enabling the system to maintain stable carrier synchronization even in dense multipath and high-speed mobile scenarios. Simultaneously, by using the least squares method to perform channel estimation after frequency offset compensation, the accuracy of channel state information estimation can be improved, facilitating low bit error rate demodulation in complex environments and fundamentally reducing signal retransmission and power consumption waste caused by channel distortion. Furthermore, this embodiment also utilizes a preset optimization algorithm to optimize the layout of the data processing path to reduce the power consumption of the wireless communication chip, thereby improving the battery life of the wireless communication device.

[0257] Furthermore, in this embodiment, by calculating the equivalent signal-to-noise ratio in real time and setting a configurable dual-threshold hysteresis decision mechanism, it is possible to intelligently switch between the two decoding paths, LDPC and Viterbi. When the channel conditions are good, the low-power Viterbi coprocessor is used first, and the LDPC engine with high error correction capability is enabled under poor channel conditions. Combined with the strategy of dynamically configuring the number of LDPC iterations based on the signal-to-noise ratio level and allocating computing resources as needed, the decoding power consumption under high modulation order is significantly reduced while ensuring communication reliability, thus improving the overall energy efficiency ratio.

[0258] Furthermore, in this embodiment, signal features and noise components are accurately separated by multi-resolution wavelet decomposition and dynamic adjustment of the noise reduction threshold, reducing the frame error rate caused by noise residue. This ensures real-time performance while reducing unnecessary data packet retransmissions, thereby reducing overall system power consumption and communication latency.

[0259] Furthermore, in this embodiment, based on the characteristic parameters such as the arrival interval of data packets, the distribution of effective payload length, and the switching frequency of hybrid decoding mode extracted from the noise-reduced data stream, a timing constraint model that fits the actual working scenario is reconstructed, and the priority of each data processing path is divided accordingly. By transforming dynamic behavior characteristics into precise physical design constraints, the subsequent placement and routing tools are guided to perform targeted optimization, so that the physical design can adapt to the timing and power consumption requirements under different working modes, avoiding over-design or insufficient performance problems under traditional static constraints.

[0260] Furthermore, this embodiment also achieves real-time monitoring of power consumption peaks and data stream hotspot distribution through power consumption monitoring points and closed-loop feedback. It also dynamically fine-tunes the processing priority of critical data streams and the resource weights of non-critical data streams based on feedback data, and introduces a linkage adjustment strategy between receive link status and transmit power. This enables rapid response to sudden changes in service load and channel quality, effectively eliminating power waste caused by localized processing hotspots and link asymmetry.

[0261] An embodiment of the second aspect of this application provides a wireless communication optimization system. Specifically, refer to... Figure 6 The wireless communication optimization system includes a frequency offset compensation module 610, a channel state estimation module 620, a decoding module 630, a noise reduction module 640, and a layout optimization module 650.

[0262] The frequency offset compensation module 610 uses pilot signals to perform real-time phase tracking of the received signal from the wireless communication chip, and compensates for the frequency offset of the received signal using a preset frequency offset compensation method based on the tracked phase. The channel state estimation module 620 uses a least squares algorithm to estimate the channel state of the frequency offset-compensated received signal, obtaining channel state information. The decoding module 630 determines the decoding method of the receiving link based on the channel state information and decodes the received signal using the decoding method. The noise reduction module 640 performs noise reduction and wavelet reconstruction processing on the decoded received signal to obtain a noise-reduced data stream. The layout optimization module 650 determines a timing constraint model based on the characteristics of the noise-reduced data stream, determines the priority of each data processing path in the receiving link based on the timing constraint model, and optimizes the layout of each data processing path according to the priority of each data processing path using a preset optimization algorithm.

[0263] Specifically, in the implementation of the wireless communication optimization system of this embodiment, the above-mentioned modules can be existing module products with data transmission, storage or computing functions.

[0264] In practical applications, the specific implementation process of the functions of each module in the wireless communication optimization system of this embodiment can be found in the relevant descriptions in the above method embodiments, and will not be repeated here.

[0265] The wireless communication optimization system in this embodiment can reduce the power consumption of the wireless communication chip, thereby improving the battery life of the wireless communication device.

[0266] An embodiment of the third aspect of this application provides an electronic device, referring to... Figure 7 , Figure 7 The illustrated electronic device includes a processor 710 and a memory 720. The processor 710 and the memory 720 are connected, for example, via a bus. Optionally, the electronic device may also include a transceiver. It should be noted that in practical applications, the transceiver is not limited to one unit, and the structure of this electronic device does not constitute a limitation on the embodiments of this application.

[0267] The memory 720 is used to store application code that executes the solution of this application, and its execution is controlled by the processor 710. The processor 710 is used to execute the application code stored in the memory 720 to implement the content shown in the foregoing method embodiments.

[0268] The electronic device of this embodiment can reduce the power consumption of the wireless communication chip and improve the battery life of the wireless communication device by executing the wireless communication optimization method in the above method embodiment.

[0269] The above descriptions are merely some embodiments of this application and are not intended to limit this application. The technical features or structures in the foregoing different embodiments can be arbitrarily combined to form other specific technical solutions as needed. For those skilled in the art, this application can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of the claims of this application.

Claims

1. A wireless communication optimization method, characterized in that, include: The received signal of the wireless communication chip is phase tracked in real time using pilot signals, and frequency offset compensation is performed on the received signal based on the tracked phase using a preset frequency offset compensation method. The channel state information is obtained by using the least squares algorithm to estimate the channel state of the received signal after frequency offset compensation. Based on the channel state information, a decoding method is determined, and the received signal is decoded using the decoding method. The decoded received signal is subjected to noise reduction and wavelet reconstruction to obtain the noise-reduced data stream. Based on the characteristics of the denoised data stream, a timing constraint model is determined, and based on the timing constraint model, the priority of each data processing path in the receiving link is determined; Based on the priority of each data processing path, the layout of each data processing path is optimized using a preset optimization algorithm.

2. The wireless communication optimization method according to claim 1, characterized in that, The step of compensating for the frequency offset of the received signal based on the tracked phase using a preset frequency offset compensation method includes: The training sequence is obtained from the header of the received signal data packet, and the phase difference between the beginning and end of the training sequence is calculated. Estimate the channel impulse response in the received link; Based on the channel impulse response and the phase difference between the preceding and following training sequences, the residual frequency offset is estimated, and the received signal is compensated for the frequency offset based on the residual frequency offset.

3. The wireless communication optimization method according to claim 2, characterized in that, The estimation of residual frequency offset and the frequency offset compensation of the received signal based on the residual frequency offset include: The training sequence is cross-correlated with the locally stored historical training sequence to obtain the cross-correlation function and the maximum peak point of the cross-correlation function. Calculate the sample point offset of the maximum peak point relative to the theoretical peak position, where the theoretical peak position is the position of the maximum peak point when it is at a preset ideal zero frequency offset; The residual frequency offset is calculated based on the proportional relationship between the sample point offset and the symbol length of the training sequence; Based on the residual frequency offset, the received signal is reversed in the digital domain to achieve frequency offset compensation.

4. The wireless communication optimization method according to claim 1, characterized in that, The decoding methods include hard-decision decoding and soft-decision decoding; The step of determining the decoding method based on the channel state information includes: Based on the channel state information, calculate the equivalent signal-to-noise ratio of the current receiving link; Based on the relative magnitude of the equivalent signal-to-noise ratio and the preset signal-to-noise ratio threshold, the decoding method corresponding to the receiving link is determined from the hard-decision decoding method and the soft-decision decoding method.

5. The wireless communication optimization method according to claim 1, characterized in that, The process of performing noise reduction and wavelet reconstruction on the decoded received signal to obtain a noise-reduced data stream includes: The decoded received signal is subjected to multi-resolution wavelet decomposition to obtain each sub-band signal and the wavelet coefficients of each sub-band signal; Based on the statistical variance and energy distribution of the wavelet coefficients of each sub-band signal, a noise reduction threshold matching the sub-band signal is determined; Using the noise reduction threshold, noise components in each of the sub-band signals are filtered out. After wavelet reconstruction of each of the filtered sub-band signals, a noise-reduced data stream is obtained.

6. The wireless communication optimization method according to claim 1, characterized in that, The step of optimizing the layout of each data processing path according to its priority and using a preset optimization algorithm includes: The layout of the data processing path is iteratively perturbed and optimized; After each iteration, the cost function value corresponding to the layout of the data processing path after the iteration is calculated, and one iteration is completed; Based on the cost function value, the layout of the data processing path is iterated again using a preset optimization algorithm until the layout of the data processing path after the iteration satisfies the preset delay balance target, and the iteration ends.

7. The wireless communication optimization method according to claim 6, characterized in that, The iterative perturbation optimization of the layout of the data processing path includes: The layout of the current data processing path is subject to a preset random perturbation operation, wherein the preset random perturbation operation includes swapping the processing order of adjacent data streams and adjusting the processing priority of non-critical data streams.

8. The wireless communication optimization method according to claim 1, characterized in that, The wireless communication optimization method further includes: Statistically analyze the arrival intervals of historical signals and predict the arrival time of the signal in the next time period; Determine the predicted idle window based on the predicted arrival time of the signal in the next time period; Within the predicted idle window, the preset module in the wireless communication chip is controlled to enter a preset low-power sleep state; Real-time assessment of the current busy / idle status of the receiving link; Based on the busy / idle state of the receiving link and the arrival interval, a reserved time window is determined between the preset module waking up from a preset low-power sleep state and fully responding to the next signal.

9. A wireless communication optimization system, characterized in that, include: The frequency offset compensation module is used to perform real-time phase tracking of the received signal of the wireless communication chip using pilot signals, and to perform frequency offset compensation on the received signal according to the tracked phase using a preset frequency offset compensation method. The channel state estimation module is used to perform channel state estimation on the frequency offset compensated received signal using the least squares algorithm to obtain channel state information. The decoding module is used to determine the decoding method based on the channel state information, and to decode the received signal using the decoding method. The noise reduction module is used to perform noise reduction and wavelet reconstruction processing on the decoded received signal to obtain a noise-reduced data stream. The layout optimization module is used to determine a timing constraint model based on the characteristics of the noise-reduced data stream, determine the priority of each data processing path in the receiving link based on the timing constraint model, and optimize the layout of each data processing path according to the priority of each data processing path using a preset optimization algorithm.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor is configured to execute the computer program stored in the memory to implement the wireless communication optimization method according to any one of claims 1 to 8.

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