An integrated circuit board anti-static protection circuit system

Abstract

The present application relates to the technical field of integrated circuit static protection, in particular to an integrated circuit board anti-static protection circuit system, a transient waveform acquisition unit acquires a power rail transient voltage waveform, a waveform feature extraction unit extracts a rising edge slope, a peak voltage amplitude and a pulse half-width to form a three-dimensional feature vector, an ESD type matching identification unit matches multiple ESD standard templates through cosine similarity and outputs a matching degree value, a gate bias segmented mapping unit retrieves corresponding segmented linear parameters according to the ESD type, generates a gate drive voltage in combination with the matching degree value, and a discharge clamping execution unit adjusts the conduction depth through a clamping MOS tube to complete static discharge and voltage clamping, the present application can adaptively identify the ESD type and continuously adjust the protection strength, improve the multi-scene ESD protection precision and adaptability, and reduce the probability of false triggering.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection technology for integrated circuits, and more specifically, to an ESD protection circuit system for integrated circuit boards. Background Technology

[0002] Electrostatic discharge (ESD) is a common source of transient overvoltage stress in integrated circuit applications, potentially causing gate oxide breakdown, PN junction damage, and metal interconnect meltdown. Therefore, various integrated circuit ports are typically equipped with ESD protection circuits. Existing power rail ESD clamping circuits often employ an RC detection network combined with a large-size clamping MOSFET. This network uses a resistor-capacitor structure to identify the voltage change rate on the power rail, and once the trigger condition is met, the clamping MOSFET is activated to discharge electrostatic energy. This type of solution provides stable protection under standard ESD testing conditions and is simple in structure and easy to integrate, making it the mainstream solution for on-chip ESD protection. However, as the operating voltage of integrated circuits continues to decrease and the tolerance margin of internal chip circuits to transient overvoltages gradually narrows, existing fixed-parameter ESD clamping solutions are gradually showing certain limitations in practical applications. On the one hand, different types of ESD events, such as human body models, machine models, and charged device models, exhibit varying rise times, pulse widths, and peak values. Significant energy differences make it difficult for clamping circuits with fixed thresholds and fixed gate drive voltages to simultaneously meet the protection requirements of multiple discharge models. Parameter settings optimized for one type of ESD may result in insufficient discharge capacity or delayed response when applied to another type of ESD. On the other hand, existing solutions typically employ a binary control method with all-on and all-off states. After the clamping MOSFET is turned on, the gate voltage remains at a fixed value, and the conduction depth is not adjustable. For low-energy ESD events, there is additional power consumption due to overdrive, while for high-energy events, the discharge strength cannot be further improved. There is a lack of a continuously matching adjustment mechanism between the protection level and the event intensity. Furthermore, the voltage transients caused by normal power-on of the power rail and load jumps may partially overlap with the ESD waveform characteristics. The triggering method based on a single threshold has a probability of false triggering under certain operating conditions, which may affect the normal power supply stability of the circuit. To solve this technical problem, we provide an integrated circuit board anti-static protection circuit system. Summary of the Invention

[0003] The purpose of this invention is to provide an anti-static protection circuit system for integrated circuit boards to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, an anti-static protection circuit system for an integrated circuit board is provided, comprising a transient waveform acquisition unit, a waveform feature extraction unit, an ESD type matching and identification unit, a gate bias segmentation mapping unit, and a discharge clamping execution unit connected in sequence. The transient waveform acquisition unit is used to acquire transient voltage waveforms on the power rail and output them to the waveform feature extraction unit; The waveform feature extraction unit is used to extract the rising edge slope, peak voltage amplitude, and pulse half-width of the transient voltage waveform within a preset time window, and to form a three-dimensional feature vector to be output to the ESD type matching and recognition unit. The ESD type matching and recognition unit has a built-in feature library containing multiple ESD standard templates. It is used to calculate the cosine similarity between the three-dimensional feature vector and each type of ESD standard template, take the ESD type corresponding to the maximum cosine similarity as the recognition result, record the maximum cosine similarity as the matching degree value, and synchronously output the ESD type recognition result and the matching degree value to the gate bias segmentation mapping unit. The gate bias segmented mapping unit has built-in multi-group segmented linear mapping parameters corresponding to the ESD type. It is used to retrieve the segmented linear mapping parameters of the corresponding group according to the ESD type identification result, and perform segmented linear operation in combination with the matching degree value to generate the gate drive voltage amplitude. When the maximum cosine similarity is lower than the judgment threshold, the zero gate drive voltage is directly output. The discharge clamping execution unit includes a clamping MOSFET, which is used to adjust the conduction depth according to the gate drive voltage to perform electrostatic discharge and voltage clamping on the power rail.

[0005] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention identifies the specific type and matching confidence level of ESD events on the power rail by combining transient waveform acquisition with three-dimensional feature extraction and cosine similarity type matching. Then, through piecewise linear mapping, the matching degree value is converted into a continuously adjustable gate drive voltage, driving the clamping MOS transistor to perform electrostatic discharge at the corresponding conduction depth. This solves the technical problems of insufficient adaptability of existing fixed-parameter ESD clamping circuits to different types of ESD events and the inability of the all-on / all-off control mode to match the event intensity. It can automatically determine the discharge model type based on the rise slope, peak amplitude, and pulse width of the ESD pulse, and continuously adjust the conduction depth of the clamping transistor according to the identification confidence level to achieve dynamic matching between protection strength and event energy. It can simultaneously cover the protection needs of multiple ESD scenarios such as human body models, machine models, and charged device models. Low-confidence events are automatically kept off to reduce the probability of false triggering. The continuously adjustable discharge capability takes into account both power consumption control for small energy events and protection reliability for large energy events, thus improving the overall adaptability and protection accuracy of the ESD protection circuit. Attached Figure Description

[0006] Figure 1 This is an overall block diagram of the present invention. Detailed Implementation

[0007] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0008] This invention provides an anti-static protection circuit system for integrated circuit boards. Please refer to [link / reference]. Figure 1 As shown, it includes a transient waveform acquisition unit, a waveform feature extraction unit, an ESD type matching and identification unit, a gate bias segmentation mapping unit, and a discharge clamping execution unit connected in sequence. The transient waveform acquisition unit is used to acquire transient voltage waveforms on the power rail and output them to the waveform feature extraction unit; The waveform feature extraction unit is used to extract the rising edge slope, peak voltage amplitude, and pulse half-width of the transient voltage waveform within a preset time window, and to form a three-dimensional feature vector to be output to the ESD type matching and recognition unit. The ESD type matching and recognition unit has a built-in feature library containing multiple ESD standard templates. It is used to calculate the cosine similarity between the three-dimensional feature vector and each type of ESD standard template, take the ESD type corresponding to the maximum cosine similarity as the recognition result, record the maximum cosine similarity as the matching degree value, and synchronously output the ESD type recognition result and the matching degree value to the gate bias segmentation mapping unit. The gate bias segmented mapping unit has built-in multi-group segmented linear mapping parameters corresponding to the ESD type. It is used to retrieve the segmented linear mapping parameters of the corresponding group according to the ESD type identification result, and perform segmented linear operation in combination with the matching degree value to generate the gate drive voltage amplitude. When the maximum cosine similarity is lower than the judgment threshold, the zero gate drive voltage is directly output. The discharge clamping execution unit includes a clamping MOSFET, which is used to adjust the conduction depth according to the gate drive voltage to perform electrostatic discharge and voltage clamping on the power rail.

[0009] In order to accurately capture the transient electrostatic discharge waveform on the power rail and ensure the accuracy of subsequent feature extraction, the original voltage signal needs to be attenuated and conditioned before trigger sampling is performed.

[0010] First, the voltage signal on the power rail is proportionally attenuated using a resistor divider network. This network consists of two resistors connected in series; the upper resistor is connected to the power rail, and the lower resistor is connected to ground. The output node is located at the junction of the two resistors. According to the voltage divider principle of series resistors, the ratio of the attenuated voltage amplitude to the original voltage amplitude is equal to the ratio of the lower resistor's resistance to the sum of the two resistors' resistances. The corresponding mathematical expression is: in This represents the voltage after voltage division and attenuation, expressed in volts. This represents the initial transient voltage on the power rail, measured in volts. This indicates the resistance value of the upper resistor, in ohms. This indicates the resistance value of the lower resistor, in ohms.

[0011] For example, when the normal operating voltage of the power rail is 3.3 volts and the ESD transient peak may reach tens of volts, if the upper resistor is selected to be 90 kΩ and the lower resistor to be 10 kΩ, the voltage division ratio is one-tenth. The original 30 volt transient voltage is attenuated to 3 volts, which is just right to match the input range of the subsequent analog-to-digital conversion circuit.

[0012] The attenuated voltage signal is fed into a differential signal conditioning circuit. This circuit employs a differential input structure, connecting the attenuated signal voltage and the common-mode reference voltage to the two input terminals of the differential pair, respectively. The common-mode rejection characteristic of the differential amplifier cancels out the common-mode noise component coupled to the power supply rail, retaining only the differential-mode transient signal. Simultaneously, the differential signal conditioning circuit performs level shifting, superimposing a fixed DC bias voltage to shift the bipolar transient signal upwards to the unipolar positive voltage range, ensuring that subsequent sampling circuits can correctly acquire the complete waveform. The output voltage after level shifting is equal to the differentially amplified signal voltage plus the DC bias voltage, and the corresponding mathematical expression is: in This represents the output voltage after level shifting, in volts. This represents the differential-mode gain of the differential amplifier, and is a dimensionless proportionality constant. This represents the common-mode reference voltage, in volts. This represents the DC bias voltage, measured in volts.

[0013] The signal, after differential conditioning and level shifting, is sent to the rising edge trigger detection module. The rising edge triggering mechanism uses a sliding window differential method to calculate the voltage change rate. Specifically, it continuously reads the latest voltage values ​​from multiple sampling points, and averages the difference results from multiple sets of adjacent sampling points to obtain the smoothed rate value. Here, an innovative three-point average differential processing method is introduced: the difference results from three consecutive sets of adjacent sampling points are taken and the arithmetic mean is performed to obtain the smoothed voltage change rate. The corresponding mathematical expression is: After simplification, we can obtain in This represents the instantaneous voltage change rate after smoothing, measured in volts per second. This represents the current sampling voltage, in volts. This represents the voltage at the third sampling time point prior to the given value, in volts. This indicates the sampling period, in seconds.

[0014] This three-point average differential processing method can effectively filter out rate jumps caused by high-frequency noise, improve the reliability of trigger judgment, and avoid false triggering caused by noise spikes at a single sampling point. The smoothed voltage change rate is compared with the preset trigger threshold. When the voltage change rate changes from below the trigger threshold to above the trigger threshold, it is determined that a rising edge trigger event has occurred. The trigger threshold is preset according to the typical rise rate range of the ESD signal, and the unit is volts per second.

[0015] After the trigger event occurs, waveform window sampling for a preset duration is started immediately. The waveform window is divided into two parts: a pre-trigger segment and a post-trigger segment. The pre-trigger segment stores several sampling points that have been collected before the trigger event occurs, which are used to record the baseline state before the ESD pulse arrives. The post-trigger segment records continuous sampling points after the trigger event occurs, which are used to capture the complete pulse rising edge, peak value, and falling edge process. The number of pre-trigger sampling points and the number of post-trigger sampling points are allocated according to a preset ratio, and the sum of the two is the total number of sampling points in the entire waveform window.

[0016] For example, when the sampling period is 1 nanosecond, the pre-trigger depth is set to 50 sampling points, and the post-trigger depth is set to 200 sampling points, the entire waveform window covers a time length of 250 nanoseconds, which is sufficient to completely record the complete waveform of the ESD pulse of the human body model. The discrete voltage values ​​obtained by continuous sampling are arranged in chronological order to form a discrete voltage sequence. Each element in the discrete voltage sequence corresponds to the voltage value at a sampling moment. The discrete voltage sequence is output as a transient voltage waveform to the waveform feature extraction unit for subsequent extraction of rising edge slope, peak voltage amplitude, and pulse half-width. Through the above-mentioned processing method of combining voltage divider conditioning and trigger sampling, the input range of the sampling circuit can be adapted without losing transient details. At the same time, the rising edge triggering mechanism ensures that the complete waveform acquisition is only started when a real ESD event occurs, avoiding invalid data occupying storage and computing resources. The three-point average difference rate calculation method further improves the anti-interference capability of trigger judgment, ensuring that electrostatic discharge events can still be accurately identified in complex electromagnetic environments.

[0017] To extract core feature parameters that characterize the ESD pulse type from discretely sampled transient voltage waveforms, three steps need to be completed sequentially: peak location, rising edge slope calculation, and pulse half-width extraction. These steps are then combined to form a three-dimensional feature vector.

[0018] First, within a preset time window, all sampling points are traversed using a sliding extreme value search. The specific method of the sliding extreme value search is to start from the first sampling point in the waveform window and compare the voltage value of each sampling point with the currently recorded maximum value. If the voltage of the current sampling point is higher than the recorded maximum value, the maximum value and the sampling point number corresponding to the maximum value are updated. After the traversal is completed, the maximum voltage value obtained is the preliminary peak voltage amplitude, and the corresponding sampling point number is the preliminary peak position index.

[0019] To improve the calculation accuracy of peak amplitude and peak position, an innovative three-point quadratic interpolation method is introduced. Three consecutive sampling points are taken: the initial peak position and one sampling point before and after it. A quadratic polynomial function is constructed with the sampling time as the independent variable and the voltage value as the dependent variable. The refined peak voltage amplitude and peak time are obtained by solving for the vertex coordinates of the quadratic function. The mathematical expression for three-point quadratic interpolation is: in This represents the refined peak voltage amplitude, in volts. This indicates the peak time after refinement, in seconds. as well as besides These represent the voltage values ​​at the sampling point before the peak, the peak sampling point, and the sampling point after the peak, respectively, all in volts. This indicates the time corresponding to the peak sampling point, in seconds. This indicates the sampling period, in seconds.

[0020] This three-point quadratic interpolation method can improve the calculation accuracy of peak amplitude and peak time from the integer sampling point level to the sub-sampling point level, reducing the quantization error caused by discrete sampling. After obtaining the peak voltage amplitude, nine-tenths and one-tenths of the peak voltage amplitude are calculated as the upper and lower reference levels, respectively. The upper reference level corresponds to the position near the peak of the rising edge, and the lower reference level corresponds to the position at the beginning of the rising edge. The sampling time corresponding to the two reference levels is located within the rising edge interval, which is defined as the time period between the waveform start point and the peak time. Starting from the waveform start point, the voltage values ​​of two adjacent sampling points are compared sequentially towards the peak. When the value of a certain reference level falls between the voltage values ​​of two adjacent sampling points, it means that the waveform has crossed the corresponding reference level between these two sampling points. At this time, the precise crossing time is calculated by linear interpolation. The mathematical expression for linear interpolation is: in Indicates the precise moment of reference level crossing, in seconds. This indicates the time of the previous sampling point, in seconds. This indicates the reference level value to be located, in volts. This represents the voltage value at the previous sampling point, in volts. This represents the voltage value at the next sampling point, in volts. This indicates the sampling period, in seconds.

[0021] After calculating the upper reference level crossover time and the lower reference level crossover time using the same method, the ratio of the voltage difference to the time difference between the two times is calculated to obtain the rising edge slope. The corresponding mathematical expression is: in This indicates the rise slope, expressed in volts per second. This represents the peak voltage amplitude, in volts. This indicates the crossover time corresponding to the upper reference level, in seconds. This indicates the crossover time corresponding to the lower reference level, in seconds.

[0022] For example, when the peak voltage amplitude is 3 volts, the lower reference level crossover time is 20 nanoseconds, and the upper reference level crossover time is 25 nanoseconds, the time difference is 5 nanoseconds, and the voltage difference is 2.4 volts. The calculated rise slope is 4.8 x 10^8 volts per second, which corresponds to the rise rate of a typical CDM model ESD pulse.

[0023] After completing the rising edge slope calculation, the pulse half-width parameter is extracted. Half of the peak voltage amplitude is used as the half-width reference level. The intersection of the half-width reference level and the waveform is searched from the refined peak position towards the front and back of the waveform, respectively. The half-width point corresponding to the rising edge is searched towards the front of the waveform, and the half-width point corresponding to the falling edge is searched towards the back of the waveform. During the search, the precise time of the two intersection points is determined by linear interpolation. The calculation method is consistent with the interpolation formula for the rising edge reference level positioning.

[0024] After obtaining the half-width at half-maximum (WHM) on the rising side and the half-width at half-maximum (WHM) on the falling side, the time interval between the two moments is calculated, which is the pulse half-width. The corresponding mathematical expression is: in This represents the pulse half-width, in seconds. This indicates the time of high-level crossover on the falling side, in seconds. The half-high pulse width (WHM) represents the time of the rising half-high pulse crossing, in seconds. When the rising half-high pulse is at 22 nanoseconds and the falling half-high pulse is at 180 nanoseconds, the pulse width is 158 nanoseconds, corresponding to the pulse width range of a typical HBM model ESD pulse. Finally, the rising slope, peak voltage amplitude, and pulse width are arranged in a fixed order to form a three-dimensional feature vector. This three-dimensional feature vector is the output of the waveform feature extraction unit and is sent to the ESD type matching and recognition unit for subsequent cosine similarity calculation and type matching. Through the peak extraction method refined by sliding extreme value search combined with three-point quadratic interpolation and the feature calculation method of linear interpolation to correct the timing accuracy, high-precision waveform feature parameters can be obtained under discrete sampling conditions. The three features characterize the ESD pulse shape from the three dimensions of change rate, energy intensity, and duration, respectively, providing sufficient distinguishability for subsequent type recognition. At the same time, the sub-sampling point level interpolation correction effectively reduces the parameter calculation error caused by insufficient sampling rate and ensures the consistency of feature extraction results under different sampling rate conditions.

[0025] To build a template library that can accurately represent the characteristics of various ESD standard waveforms, multiple steps need to be completed sequentially, including sample acquisition, feature extraction, normalization processing, template generation, and finally storage and mapping.

[0026] First, standard transient waveform sample sets corresponding to various ESD standard models are obtained. Each type of ESD standard model corresponds to a set of independent waveform samples. The samples can be obtained by actual acquisition on a standard ESD test platform or generated by circuit simulation software according to the standard model parameters. Each sample set contains multiple independent waveform samples. The number of samples is determined according to the standard requirements. All samples correspond to the same discharge voltage level.

[0027] For each waveform sample in each sample set, the rising edge slope, peak voltage amplitude, and pulse half-width are extracted using an algorithm that is completely consistent with the real-time feature extraction. These parameters form a three-dimensional feature vector for each sample. The order of the three dimensions of the three-dimensional feature vector is consistent with that of the feature vector extracted in real time, ensuring that the dimensional correspondence in the subsequent similarity calculation is correct.

[0028] After obtaining all sample feature vectors for a certain type of ESD, L2 norm normalization needs to be performed on each three-dimensional feature vector. The L2 norm, also known as the Euclidean norm, represents the length of a vector in three-dimensional space. Normalization aims to eliminate the influence of differences in the dimensions and magnitudes of different feature dimensions on the cosine similarity calculation, ensuring that the similarity result only reflects the similarity in vector directions. The specific calculation process for L2 norm normalization is as follows: first, calculate the sum of squares of the values ​​of each dimension of the vector; then, take the square root of the sum to obtain the L2 norm value of the vector; finally, divide each dimension value of the vector by the L2 norm value to obtain the normalized feature vector. The corresponding mathematical expression is: in This represents the normalized three-dimensional eigenvector, which is a dimensionless unit vector. Represents the original three-dimensional feature vector. Denotes the L2 norm of the original vector. as well as besides These represent the raw values ​​of the rise slope, peak voltage amplitude, and pulse half-width, respectively, with the units for the three dimensions being volts per second, volts per second, and seconds.

[0029] To improve the stability and representativeness of the standard template vector, an innovative outlier removal mechanism based on the distance between sample set centers is introduced. Specifically, the initial center vector is obtained by taking the preliminary arithmetic mean of all normalized feature vectors. Then, the Euclidean distance from each sample's normalized vector to the initial center vector is calculated. Samples with a distance greater than a preset screening threshold are marked as outliers and removed from the sample set. The remaining valid samples are used for the final template vector calculation. The mathematical expression for the Euclidean distance is: in Indicates the first The Euclidean distance between each sample vector and the initial center vector is a dimensionless value. as well as besides They represent the first The values ​​of the three dimensions of the normalized vector of each sample. as well as besides These represent the values ​​of the three dimensions of the initial center vector.

[0030] This outlier removal mechanism effectively filters out distorted samples introduced during the acquisition or simulation process, preventing outliers from skewing the feature orientation of the standard template and improving the robustness of the template library. After outlier screening, the arithmetic mean of the normalized feature vectors of all remaining valid samples is taken to generate the standard template vector corresponding to this type of ESD. The arithmetic mean is calculated by summing the values ​​of each dimension of all valid sample vectors, and then dividing the sum of each dimension by the total number of valid samples to obtain the values ​​of each dimension of the standard template vector. The corresponding mathematical expression is: in Indicates the first The standard template vector corresponding to class ESD is a dimensionless unit vector. Indicates the first The number of valid samples after filtering for ESD-like conditions. Indicates the first The normalized feature vector of each valid sample is calculated as follows: When there are 100 waveform samples in the human body model ESD category, and 95 valid samples remain after anomaly screening, the sum of the normalized rising edge slope dimensions of the 95 samples is divided by 95 to obtain the value of the first dimension of the template vector. The other two dimensions are calculated similarly to form the three-dimensional standard template vector corresponding to the human body model. The same processing flow is used to calculate the standard template vectors of all ESD categories in sequence. Finally, a mapping relationship is established between the standard template vectors of each ESD category and the corresponding type identifier. The type identifier is a unique integer number or name code assigned to each ESD category. The mapping relationship is stored in the form of a lookup table in the non-volatile database. In the lossless memory, each row of the lookup table corresponds to a type of ESD, including a type identifier field and a three-dimensional template vector numerical field, ultimately forming a complete ESD standard template feature library. The feature library is used for cosine similarity calculation in the subsequent real-time recognition process. Through the above sample screening combined with the template construction method of normalized averaging, stable and statistically representative ESD standard templates of various types can be obtained. L2 norm normalization ensures that the cosine similarity calculation only reflects the similarity of waveform shape and is not affected by the absolute amplitude. The abnormal sample removal mechanism further improves the anti-interference ability of the template, so that the feature library generated under different batches or different test conditions maintains consistent recognition performance.

[0031] To measure the morphological similarity between the 3D feature vectors acquired in real time and various ESD standard template vectors, a quantified matching value needs to be obtained by calculating the cosine similarity.

[0032] First, the input three-dimensional feature vector is multiplied one by one with the ESD standard template vector to be compared according to the corresponding dimensions. The three-dimensional feature vector contains three dimensions: rising edge slope, peak voltage amplitude, and pulse half width at half maximum (FWHM). The dimensions of the two vectors are in the same order: the first dimension corresponds to the rising edge slope, the second dimension corresponds to the peak voltage amplitude, and the third dimension corresponds to the pulse FWHM. The multiplication operation is performed independently on each of the three dimensions to obtain the product value of the three dimensions.

[0033] To improve the balance of contributions from different feature dimensions to type differentiation, an innovative dimension-weighted approach is introduced. Before summing the dimension products, the product result for each dimension is multiplied by its corresponding weight coefficient. These weight coefficients are pre-determined based on the inter-class dispersion of each type of ESD along the corresponding dimension. Dimensions with strong discriminative power are assigned higher weights, and dimensions with weaker discriminative power are assigned lower weights. The weighted dot product calculation expression is as follows: in This represents the weighted vector dot product, with units determined by the dimensions of each dimension. as well as besides These represent the weight coefficients for the three dimensions, all of which are dimensionless positive real numbers. as well as besides These represent the numerical values ​​of the three dimensions of the input three-dimensional feature vector, respectively, in volts per second and volts per second. as well as besides These represent the numerical values ​​of the three dimensions of the ESD standard template vector, with units consistent with the corresponding dimensions of the input vector.

[0034] The sum of the weight coefficients for the three dimensions is normalized to ensure that the weighted cosine similarity value still falls between -1 and +1. After obtaining the weighted dot product, the magnitudes of the three-dimensional feature vector and the ESD standard template vector are calculated separately. The vector magnitude, also known as the L2 norm, represents the length of the vector in the feature space. It is calculated by squaring the values ​​of each dimension of the vector, summing the results, and then taking the square root of the sum. The mathematical expression for the input vector magnitude is: The mathematical expression for the template vector magnitude is: in This represents the weighted magnitude of the input feature vector. This represents the weighted magnitude of the standard template vector, and the units of both correspond to the units of the weighted dot product.

[0035] Since L2 norm normalization was performed on all standard template vectors during the feature library construction phase, the magnitude of the standard template vector is always equal to one. Therefore, in actual calculations, the step of calculating the template vector magnitude can be skipped, and the value one can be used directly, thereby reducing the amount of computation and improving the calculation speed. Finally, the weighted vector dot product is divided by the product of the magnitudes of the two vectors to obtain the cosine similarity value corresponding to this type of ESD standard template. The corresponding mathematical expression is: in The cosine similarity value represents the similarity between two vectors. It is a dimensionless numerical value that ranges from -1 to +1. The closer the value is to +1, the closer the directions of the two vectors are, and the higher the similarity of the corresponding waveform shapes. When the cosine similarity value calculated between the input feature vector and the standard template vector of the human body model is 0.95, the cosine similarity value calculated with the standard template vector of the machine model is 0.72, and the cosine similarity value calculated with the standard template vector of the charged device model is 0.61, it means that the currently acquired waveform is closest to the shape of the human body model.

[0036] Each type of ESD standard template needs to be calculated once with the input feature vector to obtain multiple similarity values. After all similarity values ​​are calculated, the ESD type corresponding to the largest similarity value is selected as the recognition result. The largest similarity value is also output as the matching degree value to the gate bias segmented mapping unit for subsequent segmented linear mapping calculation.

[0037] By using a dimension-weighted cosine similarity calculation method, the influence of high-discrimination feature dimensions on the matching results can be strengthened, while the interference caused by low-discrimination dimensions can be weakened, thereby improving the accuracy of ESD type recognition. At the same time, by utilizing the pre-normalization feature of template vectors, some calculation steps can be omitted, reducing computational complexity and meeting the speed requirements for real-time processing of transient events.

[0038] To achieve a nonlinear mapping from the matching degree value to the gate drive voltage amplitude, the piecewise linear mapping parameters for each type of ESD consist of three ordered sequences: the segmentation point sequence, the slope sequence, and the intercept sequence.

[0039] The segmentation point sequence consists of multiple matching degree boundary values ​​arranged in ascending order. The values ​​of all segmentation points fall within the valid range of the matching degree values, which range from zero to one, corresponding to the range of cosine similarity values. Multiple segmentation points divide the entire matching degree value range into multiple continuous intervals connected end to end. The number of intervals is equal to the number of segmentation points plus one. The leftmost interval starts from zero and ends at the first segmentation point, and the rightmost interval ends from the last segmentation point to one. The left boundary of each interval is the previous segmentation point, and the right boundary is the next segmentation point.

[0040] To ensure a smooth transition in the mapping results, an innovative design rule is introduced: a continuity constraint on function values ​​at the segmentation points. The gate drive voltage amplitudes calculated for two adjacent intervals at the common segmentation point must be exactly equal. Specifically, the constraint is that the slope value of the previous interval multiplied by the segmentation point value plus the intercept value of the previous interval equals the slope value of the next interval multiplied by the segmentation point value plus the intercept value of the next interval. The corresponding mathematical expression is: in as well as They represent the first interval and the first The slope value of the interval, in volts. Indicates the first The matching degree values ​​for each segment point are dimensionless. as well as They represent the first interval and the first Intercept value of the interval, in volts.

[0041] This continuity constraint ensures that the gate drive voltage does not jump when the matching degree changes, avoiding voltage surges that could impact the clamped MOSFET. The slope sequence contains the slope values ​​of the linear function corresponding to each interval. The slope value represents the change in gate drive voltage for each unit change in the matching degree. All slope values ​​are positive, ensuring that the higher the matching degree, the larger the gate drive voltage amplitude, which conforms to the design logic that the protection strength increases with the confidence level. The intercept sequence contains the intercept values ​​of the linear function corresponding to each interval. The intercept value represents the intercept of the linear function on the vertical axis, which, together with the slope value, determines the complete linear function for each interval.

[0042] The gate drive voltage amplitude within each interval is calculated by multiplying the matching degree value by the slope value of the corresponding interval and adding the intercept value of the corresponding interval. The corresponding general mathematical expression is as follows: in This indicates the gate drive voltage amplitude, in volts. Indicates the first The slope values ​​corresponding to each interval, in volts. This represents the input matching degree value, which is a dimensionless numerical value. Indicates the first The intercept values ​​for each interval are in volts. The piecewise linear mapping parameters for a certain type of ESD include two segmentation points with values ​​of 0.5 and 0.8. The slope values ​​for the three intervals are 2 volts, 5 volts, and 8 volts, respectively. The intercept values ​​for the three intervals are 0 volts, -1.5 volts, and -3.9 volts, respectively. When the input matching degree is 0.3, it falls into the first interval, and the calculated gate drive voltage is 0.3 multiplied by 2 plus 0 equals 0.6 volts. When the input matching degree is 0.6... When the input matching degree is 0.9, it falls into the second interval, and the calculated gate drive voltage is 0.6 multiplied by 5 plus -1.5 equals 1.5 volts. When the input matching degree is 0.9, it falls into the third interval, and the calculated gate drive voltage is 0.9 multiplied by 8 plus -3.9 equals 3.3 volts. It can be seen that the higher the matching degree, the larger the gate drive voltage. Moreover, the calculated result in the two intervals around the segment point 0.5 is 1 volt, and the calculated result in the two intervals around the segment point 0.8 is 2.5 volts, which satisfies the continuity constraint condition.

[0043] All piecewise linear mapping parameters are pre-stored in the parameter memory inside the gate bias piecewise mapping unit. Each type of ESD corresponds to a set of independent parameters. During real-time operation, the parameters of the corresponding group are retrieved according to the ESD type identification result, and then combined with the input matching degree value to complete the piecewise linear operation, generating the final gate drive voltage amplitude output to the discharge clamping execution unit. By combining the parameter organization form of the segment point sequence with the slope sequence and intercept sequence, piecewise linear mapping curves of arbitrary shapes can be flexibly constructed to meet the nonlinear mapping requirements from matching degree to gate voltage under different ESD types. The continuity constraint at the segment point ensures the smooth change of the output voltage, avoids voltage jumps at the gate of the clamped MOS transistor, and improves the stability of the protection process.

[0044] To quickly locate and retrieve the corresponding piecewise linear mapping parameters based on the ESD type identification results, parameter lookup needs to be performed using a base address plus offset addressing method. First, the ESD type identification results are converted into corresponding parameter group index values. The ESD type identification results are type identifier codes, and the parameter group index values ​​are consecutive integer numbers starting from zero. Each type of ESD corresponds to a unique index value. The conversion process is completed through a mapping table from type code to index number, ensuring a one-to-one correspondence between the index values ​​and the physical order of parameter storage.

[0045] To prevent unauthorized address access due to abnormal identification results, an innovative protection mechanism is introduced, combining type identifier validity verification and default parameter rollback. Before calculating the address offset, it is first determined whether the parameter group index value falls within the valid index range. The valid index range extends from zero to the total number of parameter groups minus one. If the index value exceeds the valid range, it is considered an invalid identification result, and the pre-set default parameter group index value is directly used in subsequent calculations. The default parameter group corresponds to the most conservative mapping parameters for the protection level, ensuring basic protection capabilities are still provided even in abnormal situations. The logical expression for validity judgment is as follows: in This represents the valid index value after verification. This represents the index value obtained from the original transformation, and N represents the total number of parameter groups. This represents the index value corresponding to the default parameter group. All index values ​​are dimensionless integers.

[0046] After validity verification, the address offset of the target parameter group is calculated based on the preset storage base address of the piecewise linear mapping parameters. The storage base address is the starting physical address of the first group of parameters in memory. The storage length of a single parameter group is a fixed value, determined by the length of the segment point sequence, the slope sequence length, and the intercept sequence length. The address offset is equal to the valid index value multiplied by the storage length of a single parameter group, and the corresponding mathematical expression is: in This represents the target address offset, in bytes. This indicates the storage length of the parameters for a single-group piecewise linear mapping, in bytes.

[0047] Adding the base address of the piecewise linear mapping parameters to the offset of the target address yields the starting address of the target parameter set. The corresponding mathematical expression is: in This indicates the starting address of the target parameter set, in bytes. This indicates the base address for parameter storage, in bytes.

[0048] After obtaining the starting address, it is sent to the address decoding circuit. The address decoding circuit decodes the input address signal and selects the memory cell corresponding to the address range in the memory. Since a single set of parameters contains multiple values ​​and subsequent piecewise linear operations require the use of all parameters simultaneously, a parallel reading method is adopted. All segment point values, slope values, and intercept values ​​of the group are read from the corresponding memory cell at once. All parameters are output to the subsequent operation circuit simultaneously. When the memory base address is 0x1000, the storage length of a single set of parameters is 32 bytes, and the index value corresponding to the ESD type identification result is 2, the address offset is 2 multiplied by 32 equals 64 bytes, and the target starting address is 0x1000 plus 64 equals 0x1040. After address decoding, all piecewise linear mapping parameters of the group are read in parallel from the 32-byte memory cell starting from 0x1040. If the index value corresponding to the identification result is 5 and the total number of parameter groups is only 3, a backoff mechanism is triggered, and the default index value 0 is used for address calculation.

[0049] All read piecewise linear mapping parameters are directly fed into the piecewise linear operation unit, and together with the simultaneously input matching degree value, the gate drive voltage amplitude is calculated. The parameter can be quickly located by the base address plus offset addressing mode. The target address can be obtained with only one multiplication and one addition operation. The parallel readout structure ensures that all parameters are available at the same time, reducing the operation waiting time. The validity check and default backoff mechanism improve the robustness of the circuit, and the function will not fail even if abnormal identification results occur.

[0050] To calculate the appropriate gate drive voltage amplitude based on the matching degree value, the matching degree value is used as a segmented independent variable. After completing the interval positioning by combining it with the pre-stored segment point sequence, a linear operation is performed. The complete range of the matching degree value is from zero to one. Multiple segment points are arranged in ascending order, and a continuous interval is formed between two adjacent segment points. All intervals are connected end to end and cover the entire value range. The total number of intervals is equal to the number of segment points plus one.

[0051] To improve the computational speed of interval positioning, an innovative approach of binary search is introduced to locate the target interval. Instead of comparing sequentially starting from the first segment point, it quickly locks the interval to which the matching degree value belongs by continuously narrowing the search range. The core logic of binary search is to compare the value of the segment point at the middle position of the current search range with the input matching degree value. If the matching degree value is less than the middle segment point, the search range is narrowed to the first half; if the matching degree value is greater than or equal to the middle segment point, the search range is narrowed to the second half. The above comparison and narrowing steps are repeated until the search range is narrowed to a single pair of adjacent segment points, thus determining the index of the target interval. The time complexity of binary search is proportional to the logarithm of the number of segment points. When the number of segment points is large, it significantly reduces the number of comparisons compared to the sequential comparison method.

[0052] The interval boundaries adopt the convention of left-closed and right-open, that is, each interval includes the value of the left boundary segment point but does not include the value of the right boundary segment point. For the leftmost interval, it is determined that it falls into the interval if the matching degree value is greater than or equal to zero and less than the first segment point. For the j-th interval in the middle, it is determined that it falls into the interval if the matching degree value is greater than or equal to the j-th minus one segment point and less than the j-th segment point. For the rightmost interval, it is determined that it falls into the interval if the matching degree value is greater than or equal to the last segment point and less than or equal to one.

[0053] If the input matching degree value exceeds the range of zero to one due to abnormal circumstances, boundary clamping is performed. If the matching degree value is less than zero, it is treated as zero; if the matching degree value is greater than one, it is treated as one, to avoid situations where there is no corresponding interval.

[0054] After locating the target interval, the slope and intercept values ​​corresponding to the target interval are retrieved from the pre-fetched slope and intercept sequences. The gate drive voltage amplitude is calculated according to a linear function relationship. The calculation method is to multiply the matching degree value by the slope value of the target interval and add the intercept value of the target interval. The corresponding mathematical expression is: in This represents the calculated gate drive voltage amplitude, in volts. Indicates the first The slope values ​​corresponding to each target interval, in volts. This represents the input matching score, which is a dimensionless numerical value. Indicates the first The intercept values ​​corresponding to the target intervals are in volts. The segmentation point sequence of a certain type of ESD contains two values, 0.4 and 0.7, corresponding to three consecutive intervals. The slope values ​​of the three intervals are 1 volt, 4 volts, and 6 volts, respectively, and the intercept values ​​of the three intervals are 0 volts, -1.2 volts, and -2.6 volts, respectively. When the input matching degree is 0.2, it is determined to fall into the first interval through binary search, and the calculated gate drive voltage is 0.2 multiplied by 1 plus 0 equals 0.2 volts. When the input matching degree is 0.5, it is determined to fall into the second interval through binary search, and the calculated gate drive voltage is 0.5 multiplied by 4 plus -1.2 equals 0.8 volts. When the input matching degree is 0.85, it is determined to fall into the third interval through binary search, and the calculated gate drive voltage is 0.85 multiplied by 6 plus -2.6 equals 2.5 volts. The calculation results in all three scenarios increase with the increase of matching degree, which is consistent with the design logic that the protection strength increases with confidence.

[0055] The calculated gate drive voltage amplitude is directly output to the discharge clamping execution unit to control the conduction depth of the clamped MOSFET. The higher the matching degree, the higher the gate drive voltage; the deeper the clamped MOSFET conducts, the stronger the electrostatic discharge capability. The binary search interval positioning method effectively reduces the number of comparison operations and shortens the total delay of piecewise linear operations. The left-closed, right-open boundary convention ensures that each matching degree value uniquely corresponds to an interval. Boundary clamping processing covers abnormal input scenarios. The overall computational structure is simple and robust, and can complete the mapping from matching degree to gate voltage within nanoseconds, meeting the real-time requirements of ESD transient protection.

[0056] To avoid triggering unnecessary protective actions due to low-confidence recognition results, the maximum cosine similarity value needs to be compared with a preset judgment threshold. The final output gate drive voltage form is controlled based on the comparison result. The maximum cosine similarity value, also known as the matching degree value, reflects the degree of similarity between the currently acquired waveform and a certain type of ESD standard template. The closer the value is to one, the higher the similarity and the more reliable the recognition result.

[0057] To prevent frequent output switching caused by small fluctuations in the matching degree value around the threshold, an innovative dual-threshold hysteresis comparison mechanism is introduced. Two different thresholds are set: an upper threshold and a lower threshold. The upper threshold value is higher than the lower threshold value. When the output is currently in a valid state, the lower threshold is used for comparison; when the output is currently in an invalid state, the upper threshold is used. A hysteresis band is formed between the two thresholds. When the matching degree value fluctuates within the hysteresis band, the output state remains unchanged. The state switching logic of the hysteresis comparison is as follows: in This represents the valid identifier at the current moment. It is a dimensionless binary value, where a value of 1 indicates a valid identifier and a value of 0 indicates an invalid identifier. This indicates the valid identifier from the previous moment. This represents the maximum cosine similarity value at the current moment, and is a dimensionless value. This represents the upper threshold value, which is a dimensionless value. This represents the lower threshold value, which is a dimensionless value and satisfies the following conditions: .

[0058] When the valid identification flag is zero, an invalid identification flag signal is generated accordingly. The output gating circuit switches to the zero-value output channel and directly selects the zero-value gate drive voltage. The zero-value gate drive voltage is lower than the threshold voltage of the clamping MOS transistor, so that the discharge clamping execution unit remains in the off state and does not perform electrostatic discharge action.

[0059] When a valid identifier is selected, a valid identifier signal is generated accordingly. The output gating circuit switches to the operation output channel, selects the gate drive voltage amplitude obtained by piecewise linear operation, and sends the calculation result directly to the discharge clamping execution unit.

[0060] The output gating circuit is implemented using a 2-to-1 multiplexer structure. The two data input terminals are connected to the piecewise linear operation result and the zero voltage, respectively, and the selection control terminal is connected to the valid identification signal. Output switching can be completed without additional calculation processing.

[0061] For example, the upper threshold is set to 0.7 and the lower threshold is set to 0.5. The initial state is invalid output. When the matching degree value gradually rises from 0.3 to 0.75, it crosses the upper threshold, the identification mark switches to valid, and the output gating circuit outputs the gate drive voltage calculated by piecewise linear calculation. If the matching degree value drops to 0.6, the output state remains valid because it is still higher than the lower threshold of 0.5. The identification mark switches to invalid only when the matching degree value continues to drop to 0.4 and is lower than the lower threshold, and the output gating circuit switches to zero value output. The final output gate drive voltage amplitude directly acts on the gate of the clamp MOSFET in the discharge clamping execution unit, determining the conduction depth and discharge capability of the clamp MOSFET. The protection action is only activated when the confidence of the identification result is high enough, and it remains off when the confidence is insufficient, avoiding additional power consumption and circuit interference caused by false triggering. The dual threshold hysteresis comparison judgment mechanism can effectively eliminate the output jitter problem caused by the critical fluctuation of the matching degree value, and improve the stability of the protection trigger. The two-to-one selection structure ensures that the output switching process is simple and direct, with extremely low operation delay, which can meet the requirements of rapid response to ESD transient events.

[0062] To achieve electrostatic discharge and voltage clamping functions on the power rails, the discharge clamping execution unit uses a clamping MOSFET as its core device. The discharge capability is adjusted by controlling the conduction depth through the gate drive voltage. The clamping MOSFET employs a common-source connection structure, with the drain connected to the power rail and the source connected to ground. The gate receives the gate drive voltage from the gate bias segmentation mapping unit, which is directly applied between the gate and source of the clamping MOSFET as the input to control the conduction state. When the gate drive voltage is lower than the threshold voltage of the clamping MOSFET, an inversion layer cannot form on the semiconductor surface below the gate, the conductive channel is not established, the clamping MOSFET is in the off state, the resistance between the drain and source is in the megaohm range, almost no current flows, and the power rail remains isolated from the ground, without affecting the normal operation of the circuit. When the gate drive voltage exceeds the threshold voltage, the positive electric field of the gate attracts carriers on the semiconductor surface to form an inversion layer, and a conductive channel appears below the gate. The clamped MOSFET enters the linear operating region. In the linear operating region, the drain-source current and drain-source voltage are approximately linearly related. The clamped MOSFET is equivalent to a variable resistor controlled by the gate-source voltage. The on-resistance decreases as the gate-source overdrive voltage increases, and the quantitative relationship is as follows: in This represents the on-resistance of the clamped MOSFET in the linear region, expressed in ohms. This indicates the channel length of the clamped MOSFET, in meters. Electron mobility is expressed as square meters per volt-second. This represents the gate oxide capacitance per unit area, expressed in farads per square meter. This indicates the channel width of the clamped MOSFET, in meters. This represents the gate-source voltage, also known as the gate drive voltage, and is measured in volts. This indicates the threshold voltage of the clamped MOSFET, in volts.

[0063] To ensure the clamped MOSFET always operates in the linear region to maintain its variable resistance characteristics, an innovative gate voltage fine-tuning compensation mechanism based on drain-source voltage monitoring is introduced. The drain-source voltage of the clamped MOSFET is acquired in real time. When the drain-source voltage approaches the gate-source overdrive voltage, it indicates the device is about to enter the saturation region. At this point, the gate drive voltage is appropriately increased to increase the gate-source overdrive voltage, expanding the operating range of the linear region. This ensures the clamped MOSFET maintains its linear resistance characteristics during high-current discharge, avoiding the clamping voltage increase caused by the constant current effect in the saturation region. The higher the gate drive voltage, the greater the gate-source overdrive voltage, the higher the carrier concentration in the channel, the lower the on-resistance, and the stronger the electrostatic discharge capability, thus achieving continuous adjustment of the conduction depth. The clamped MOSFET is connected between the power rail and ground. When an electrostatic discharge event occurs, causing an abnormal increase in the power rail voltage, the clamped MOSFET, in the conducting state, forms a low-impedance discharge channel. The electrostatic charge accumulated on the power rail flows along the drain of the clamped MOSFET to the source and then into the ground, completing the electrostatic energy discharge process. During electrostatic discharge, the on-resistance of the clamping MOSFET and the discharge current flowing through it together determine the voltage difference across the drain and source, i.e., the clamping voltage drop. The clamping voltage on the power rail is equal to the ground potential plus the clamping voltage drop. The quantitative relationship is as follows: in This indicates the voltage amplitude after the power rail is clamped, in volts. This indicates the amplitude of the electrostatic discharge current, measured in amperes. This indicates the on-resistance of the clamped MOSFET, measured in ohms.

[0064] The clamping voltage can be controlled by adjusting the on-resistance. The greater the conduction depth, the smaller the on-resistance and the lower the clamping voltage, resulting in better protection for the internal circuitry. When the threshold voltage of the clamping MOSFET is 1 volt and the gate drive voltage is 1.5 volts, the on-resistance is approximately 20 ohms. If the ESD discharge current is 1 ampere at this time, the clamping voltage is 1 ampere multiplied by 20 ohms, which equals 20 volts. When the gate drive voltage increases to 3 volts, the on-resistance decreases to 5 ohms. At the same discharge current of 1 ampere, the clamping voltage is 5 volts, significantly improving the protection strength.

[0065] The clamping voltage is always limited to a safe range that the internal circuit can withstand, preventing electrostatic high voltage from damaging sensitive devices such as the gate oxide layer and PN junction. The working mode of continuously adjusting the on-resistance by the gate voltage can dynamically adjust the discharge intensity according to the ESD type and matching confidence level. The gate voltage fine-tuning mechanism with drain-source voltage feedback ensures that the linear region working characteristics are maintained even in high current scenarios, so that the clamping voltage and conduction depth maintain a stable correspondence, balancing protection reliability and adjustment flexibility.

[0066] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. An anti-static protection circuit system for an integrated circuit board, characterized in that, It includes a transient waveform acquisition unit, a waveform feature extraction unit, an ESD type matching and identification unit, a gate bias segmentation mapping unit, and a discharge clamping execution unit connected in sequence. The transient waveform acquisition unit is used to acquire transient voltage waveforms on the power supply rail and output them to the waveform feature extraction unit; The waveform feature extraction unit is used to extract the rising edge slope, peak voltage amplitude, and pulse half-width of the transient voltage waveform within a preset time window, and to form a three-dimensional feature vector to be output to the ESD type matching and recognition unit. The ESD type matching and recognition unit has a built-in feature library containing multiple types of ESD standard templates. It is used to calculate the cosine similarity between the three-dimensional feature vector and each type of ESD standard template, take the ESD type corresponding to the maximum cosine similarity as the recognition result, record the maximum cosine similarity as the matching degree value, and synchronously output the ESD type recognition result and the matching degree value to the gate bias segmentation mapping unit. The gate bias segmented mapping unit has built-in multi-group segmented linear mapping parameters corresponding to the ESD type. It is used to retrieve the segmented linear mapping parameters of the corresponding group according to the ESD type identification result, and perform segmented linear operation in combination with the matching degree value to generate the gate drive voltage amplitude. When the maximum cosine similarity is lower than the judgment threshold, the zero gate drive voltage is directly output. The discharge clamping execution unit includes a clamping MOS transistor, which is used to adjust the conduction depth according to the gate drive voltage to perform electrostatic discharge and voltage clamping on the power rail.

2. The anti-static protection circuit system for an integrated circuit board according to claim 1, characterized in that: The specific process for acquiring transient voltage waveforms is as follows: The voltage signal of the power supply track is proportionally attenuated by a resistor voltage divider network, and then common-mode noise suppression and level shifting are performed by a differential signal conditioning circuit. A rising edge triggering mechanism is introduced. When the voltage change rate crosses the preset trigger threshold, sampling is started. The waveform window with a preset duration before and after the trigger point is continuously sampled to obtain a discrete voltage sequence. The discrete voltage sequence is output as a transient voltage waveform to the waveform feature extraction unit.

3. The anti-static protection circuit system for an integrated circuit board according to claim 1, characterized in that: The specific process for extracting the rising edge slope, peak voltage amplitude, and pulse half-width of the transient voltage waveform is as follows: First, within a preset time window, all sampling points are traversed through a sliding extreme value search. The maximum voltage value is taken as the peak voltage amplitude. Nine-tenths and one-tenths of the peak voltage amplitude are used as upper and lower reference levels. The sampling times corresponding to the two reference levels on the rising edge are located respectively. After correcting the timing accuracy through linear interpolation, the ratio of the voltage difference to the time difference between the two times is calculated to obtain the rising edge slope. Half of the peak voltage amplitude is used as the half-height reference level. From the peak position, the intersection points of the half-height reference level and the waveform are searched on both sides before and after the waveform. The times of the two intersection points are determined by linear interpolation. The time interval between the two times is calculated to obtain the pulse half-width. The rising edge slope, peak voltage amplitude, and pulse half-width are combined to form a three-dimensional feature vector.

4. The anti-static protection circuit system for an integrated circuit board according to claim 1, characterized in that: The feature library containing multiple types of ESD standard templates is constructed through the following process: Standard transient waveform sample sets corresponding to various ESD standard models are obtained respectively. For each waveform sample in the standard transient waveform sample set, the rising edge slope, peak voltage amplitude, and pulse half-width are extracted as three-dimensional features. L2 norm normalization is performed on each three-dimensional feature vector to obtain a feature vector set. Then, the arithmetic mean of the feature vector set is taken to generate the standard template vector corresponding to the ESD type. Finally, the standard template vectors of various ESD types are mapped to the corresponding type identifiers and stored to form the feature library.

5. The anti-static protection circuit system for an integrated circuit board according to claim 1, characterized in that: The specific process of calculating the cosine similarity between the three-dimensional feature vector and various ESD standard templates is as follows: The three-dimensional feature vector is multiplied one by one with the ESD standard template vector to be compared according to the corresponding dimensions. The sum of the product results of the three dimensions is used to obtain the vector dot product. Then, the magnitude of the three-dimensional feature vector and the ESD standard template vector is calculated separately. That is, the values ​​of each dimension of the vector are squared and summed. The square root of the sum is then taken. Finally, the vector dot product is divided by the product of the magnitudes of the two vectors to obtain the cosine similarity value corresponding to this type of ESD standard template.

6. The anti-static protection circuit system for an integrated circuit board according to claim 1, characterized in that: Each set of piecewise linear mapping parameters includes a segmentation point sequence, a slope sequence, and an intercept sequence. The segmentation point sequence consists of multiple matching degree boundary values ​​arranged in ascending order, used to divide the range of matching degree values ​​into multiple continuous intervals. The slope sequence and the intercept sequence respectively contain the linear function slope value and intercept value corresponding to each interval. The gate drive voltage amplitude in each interval is calculated by multiplying the matching degree value by the corresponding slope value and adding the corresponding intercept value.

7. The anti-static protection circuit system for an integrated circuit board according to claim 1, characterized in that: The specific process of retrieving the piecewise linear mapping parameters of the corresponding group based on the ESD type identification result is as follows: The ESD type identification result is converted into the corresponding parameter group index value. Based on the preset storage base address of the piecewise linear mapping parameter, the parameter group index value is multiplied by the storage length of the single piecewise linear mapping parameter to obtain the target address offset. The storage base address of the piecewise linear mapping parameter and the target address offset are added to obtain the starting address of the target parameter group. After address decoding, all piecewise linear mapping parameters of the group are read in parallel from the corresponding storage unit for use in subsequent piecewise linear operations.

8. The anti-static protection circuit system for an integrated circuit board according to claim 1, characterized in that: Using the matching degree value as the segmentation independent variable, the complete range of the matching degree value is divided into multiple continuous intervals with one end connected by multiple segmentation points arranged from smallest to largest. The current input matching degree value is compared with each segmentation point in turn to locate the target interval to which it belongs. The slope value and intercept value corresponding to the target interval are retrieved. The matching degree value is multiplied by the slope value and added to the intercept value to calculate the gate drive voltage amplitude corresponding to the interval.

9. The anti-static protection circuit system for an integrated circuit board according to claim 1, characterized in that: The specific process of directly outputting a zero-value gate drive voltage when the maximum cosine similarity is lower than the determination threshold is as follows: The maximum cosine similarity value is compared with a preset judgment threshold. When the maximum cosine similarity value is less than the judgment threshold, an invalid identification signal is generated. The calculation result of the piecewise linear operation is shielded by the output gating circuit, and the zero-value gate drive voltage is directly selected to keep the discharge clamping execution unit in the off state. When the maximum cosine similarity value is greater than or equal to the judgment threshold, an valid identification signal is generated, and the gate drive voltage amplitude obtained by the piecewise linear operation is selected.

10. The anti-static protection circuit system for an integrated circuit board according to claim 1, characterized in that: The specific process of adjusting the conduction depth according to the gate drive voltage is as follows: A gate drive voltage is applied between the gate and source of the clamped MOSFET. When the gate drive voltage is lower than the threshold voltage of the clamped MOSFET, no channel is formed and the clamped MOSFET is in the off state. When the gate drive voltage is higher than the threshold voltage, a conductive channel is formed below the gate, and the clamped MOSFET enters the linear operating region. This makes the gate drive voltage proportional to the carrier concentration in the channel and the on-resistance inversely proportional to the electrostatic discharge capability, thereby achieving continuous adjustment of the conduction depth and performing voltage clamping and electrostatic discharge on the power rail. The clamping MOSFET is connected between the power rail and the ground line. When an electrostatic discharge event causes the power rail voltage to rise abnormally, the conducting clamping MOSFET forms a low-impedance discharge channel, allowing the electrostatic charge on the power rail to flow to the ground line through the clamping MOSFET, thus achieving electrostatic discharge. At the same time, the on-resistance of the clamping MOSFET and the discharge current together determine the clamping voltage drop, limiting the power rail voltage to a safe range that the internal circuit can withstand.

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