Component carrier and method of manufacturing the same

Abstract

A component carrier (100) comprising: a stack (102) comprising at least one electrically conductive layer structure (104) and a plurality of electrically insulating layer structures (106, 108), at least a portion of the at least one electrically conductive layer structure (104) being arranged on and / or in a main surface (110) of one of the plurality of electrically insulating layer structures (106, 108); and a surface treatment layer (118) at least partially covering an exposed surface of the at least one electrically conductive layer structure (104); wherein the main surface (110) of the one of the plurality of electrically insulating layer structures (106, 108) is configured to inhibit attraction and adhesion of metal ions and / or metal particles on the main surface (110). The application also provides a method of manufacturing a component carrier (100).

Description

Technical Field

[0001] This invention relates to a component carrier and a method for manufacturing the component carrier. Background Technology

[0002] With the increasing functionality of products equipped with component carriers containing one or more electronic components, the miniaturization of these electronic components, and the growing number of components to be mounted on component carriers, such as printed circuit boards, increasingly robust array-shaped components or packages with multiple electronic components and numerous contacts or connections with increasingly smaller spacing between them are being adopted. Removing the heat generated by these electronic components and the component carrier itself during operation is becoming an increasingly serious problem. Simultaneously, the component carrier must be mechanically robust and electrically reliable to enable operation, even under harsh conditions. Summary of the Invention

[0003] The purpose of this invention is to provide a reliable component carrier.

[0004] To achieve the aforementioned objectives, a component carrier and a method for manufacturing the component carrier are provided according to the independent claims.

[0005] According to an exemplary embodiment, a component carrier is provided, comprising: a stacked member including at least one electrically conductive layer structure and a plurality of electrically insulating layer structures, wherein at least a portion of the at least one electrically conductive layer structure is disposed on the main surface of one of the plurality of electrically insulating layer structures and / or disposed in the main surface of one of the plurality of electrically insulating layer structures; and a surface treatment layer that at least partially covers the exposed surface of the at least one electrically conductive layer structure; wherein the main surface of one of the plurality of electrically insulating layer structures is configured to suppress the attraction and adhesion of metal ions and / or metal particles on the main surface.

[0006] According to another exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, wherein the method includes: providing a stack comprising at least one electrically conductive layer structure and a plurality of electrically insulating layer structures, at least a portion of the at least one electrically conductive layer structure being disposed on a main surface of one of the plurality of electrically insulating layer structures and / or disposed in the main surface of one of the plurality of electrically insulating layer structures; covering at least a portion of the exposed surface of the at least one electrically conductive layer structure with a surface treatment layer; and configuring the main surface of one of the plurality of electrically insulating layer structures to suppress the attraction and adhesion of metal ions and / or metal particles on the main surface.

[0007] In the context of this application, the term "component carrier" may specifically refer to any support structure capable of accommodating one or more components thereon and / or therein to provide mechanical support and / or electrical connectivity and / or thermal conductivity. In other words, a component carrier can be configured as a mechanical and / or electronic and / or thermal support for a component. Specifically, a component carrier can be one of a printed circuit board, an organic intermediate, and an IC (integrated circuit) substrate. For example, a component carrier can be a rigid-flexible carrier or a flexible substrate. A component carrier can also be a hybrid board combining different component carriers of the types described above. In particular, a component carrier may include a stack comprising multiple electrically conductive layer structures and / or electrically insulating layer structures.

[0008] In the context of this application, the term "stack" may specifically refer to a flat or planar sheet-like body. For example, a stack can be a layered stack, particularly a laminated stack or laminate. Such a laminate can be formed by applying mechanical pressure and / or heat to join multiple layers together, the multiple layers preferably arranged in parallel.

[0009] In the context of this application, the term "layer structure" may specifically refer to a continuous layer, a patterned layer, or a plurality of discontinuous islands in a common plane.

[0010] In the context of this application, the term "surface treatment layer" may specifically refer to a layer of material, such as a thin film of material, selectively applied to the exposed surface of an electrically conductive layer structure of a component carrier. The surface treatment layer can protect the underlying metal (particularly copper) from oxidation and / or can improve the wettability of contact areas, such as those used for soldering. Such a surface treatment layer can be an electrically conductive covering material located on one or more exposed electrically conductive layer structures (such as pads, conductive tracks, etc., particularly electrically conductive layer structures comprising or made of copper) at the surface of the component carrier. If such exposed electrically conductive layer structures are not protected, the exposed electrically conductive component carrier material (particularly copper) may oxidize, reducing the reliability of the component carrier. The surface treatment layer can be formed, for example, as an interface between a surface-mount component and a component carrier. The surface treatment layer functions to protect one or more exposed electrically conductive layer structures (particularly copper circuitry) and to enable a connection process, such as a connection process with one or more components via soldering. Examples of suitable materials for surface treatment are electroless nickel plating, electroless palladium immersion gold plating (ENEPIG), electroless nickel immersion gold plating (ENIG), electroless nickel immersion palladium immersion gold plating (ENIPIG), gold (especially hard gold), electroless tin, nickel-gold, nickel-palladium, etc.

[0011] In the context of this application, the term "suppression of the attraction and adhesion of metal ions and / or metal particles" can specifically refer to the following characteristic of an exposed electrical insulating layer structure: the exposed electrical insulating layer structure is functionalized or constructed to actively prevent the accumulation of metal residues on the main surface of the electrical insulating layer structure. In a sense, the suppression can be partial or complete, i.e., the amount of metal residue is reduced compared to the unfunctionalized or unconstructed case, or any metal residue is eliminated from the main surface of the electrical insulating layer structure. Therefore, suppression of the attraction and adhesion of metal ions and / or metal particles can be the suppression or even elimination of metal residues on the main surface. This suppression or inhibition can be accomplished, for example, by the selection of materials for the electrical insulating layer structure and its main surface and / or by adjusting the surface morphology or topography of the electrical insulating layer structure and its main surface. For example, the metal ions and / or metal particles can be any metal particles, charged metal ions, and / or metal compositions. For example, the metal ions and / or metal particles can be in the form of residues on the exposed electrical insulating layer structure and / or ultrathin regions on the exposed electrical insulating layer structure. In fact, such metal particles or ions can also originate from a seed layer formed by chemical plating during the fabrication of at least a portion of the electrically conductive layer structure, and such metal particles or ions can migrate to one or more adjacent layers.

[0012] In the context of this application, the term "main surface" of a body may specifically refer to one of the two largest opposing surfaces of the body or the outermost opposing surface of the body. Main surfaces may be connected by circumferential sidewalls. The thickness of the body, such as a component carrier or a stack or layer of component carriers, may be defined by the distance between the two opposing main surfaces.

[0013] According to an exemplary embodiment, a component carrier (such as a printed circuit board or integrated circuit substrate) may include a stack (such as a laminate). The stack may be made of one or more electrically conductive layer structures (e.g., including pads, traces, vertical through-connections, etc.) and electrically insulating layer structures (e.g., resin sheets, optionally including reinforcing structures such as glass fibers or glass spheres and / or filler particles, for example, to regulate thermal conductivity). At least one of the electrically conductive layer structures may be partially or wholly (e.g., in the form of one or more pads) disposed on and / or in the main surface of one of the plurality of electrically insulating layer structures exposed. A surface treatment layer may cover the exposed surface of the electrically conductive layer structure, particularly for protective purposes and / or to facilitate electrical connections on the exposed surface. Advantageously, the main surface of the electrically insulating layer structure may be configured or functionalized to inhibit or eliminate the attraction and adhesion of parasitic metal residues on the main surface. For example, such metal residues or media may be retained as residues of previous processes, such as the formation of a seed layer for forming a portion of at least one electrically conductive layer structure and / or the formation of a surface treatment layer. For example, palladium ions from the seed layer deposition process and / or gold from the surface treatment process may tend to remain, intentionally or undesirably, on the surface portions of the dielectric surface after seed layer formation and / or surface treatment layer formation, and may serve as the basis for creating an electrically conductive layer structure. By specifically constructing or functionalizing at least a surface portion of at least one electrically insulating layer structure adjacent to the main surface, the accumulation of metal ions or particles at undesirable surface portions, such as accumulation on the dielectric surface between adjacent pads, can be prevented. The inventors have discovered various options for constructing or functionalizing the main surface portions. For example, the material of at least one electrically insulating layer structure juxtaposed with said main surface can be selected accordingly; for example, at least one electrically insulating layer structure may be made of a low Df material. The surface morphology or shape of the main surface can also be adjusted to suppress or prevent the accumulation of metal particles there, for example, by adjusting the roughness Rz, filler particle content, and / or surface coverage, etc. By preventing metal accumulation between substructures of at least one electrically conductive layer structure onto the electrically insulating surface between substructures of at least one electrically conductive layer structure, the distance between adjacent electrically conductive portions (e.g., pads) can be advantageously reduced. The advantage is that this allows for the miniaturization of component carriers and the creation of fine line structures.

[0014] Further exemplary embodiments of the component carrier and method will be explained below.

[0015] In an embodiment, the main surface is configured to suppress attraction and adhesion by setting one of the plurality of electrical insulating layer structures to an electrical insulating layer structure of a low-Df material. Df, also known as loss tangent, is a measure of a material's ability to dissipate electrical energy as heat when exposed to an alternating electric field. Df (also expressed as dissipation factor) is a measure of energy loss during polarization reversal in a dielectric material. Df is expressed as fractional energy loss. Low-Df materials can refer to materials with a lower Df value and lower loss than standard prepregs, particularly those with a Df value less than 0.022. The smaller the value, the less energy loss during transmission. Therefore, low-Df materials are particularly important in high-frequency and high-speed applications because they can efficiently ensure the integrity of signal transmission and the superior functionality of the product. Using low-Df materials in exposed electrical insulation layer structures that are in direct physical contact with the exposed pads of laminated components has proven to be a powerful mechanism for suppressing the attraction and adhesion of metal ions and / or metal particles on the main surface of the electrical insulation layer structure.

[0016] In an embodiment, the main surface is configured to suppress attraction and adhesion by setting one of the plurality of electrical insulating layer structures to a material with a Df value less than 0.022. More specifically, the main surface is configured to suppress attraction and adhesion by setting one of the plurality of electrical insulating layer structures to a material with a Df value less than 0.018. More particularly, the main surface is configured to suppress attraction and adhesion by setting one of the plurality of electrical insulating layer structures to a material with a Df value in the range of 0.002 to 0.022. For example, GL107 Ajinomoto Build-up Film (ABF) is an excellent choice for such an electrical insulating layer structure with a low Df value. This effectively suppresses the attraction and adhesion of metal ions and / or metal particles on the main surface of the electrical insulating layer structure. Therefore, very small pad sizes and pad-to-pad distances can be achieved without compromising electrical performance.

[0017] In one embodiment, the main surface is configured to suppress attraction and adhesion by setting one of the plurality of electrical insulating layer structures to have a high content of filler particles. A large number of filler particles, especially when the filler particles are made of glass, can reduce the accumulation of charge at the exposed dielectric main surface and can thus prevent the accumulation of metal particles at such a surface.

[0018] In an embodiment, the main surface is configured to suppress attraction and adhesion by setting one of the plurality of electrical insulating layer structures to have a filler particle content of at least 70% of the total volume of the one of the plurality of electrical insulating layer structures. Preferably, the filler particle content can even be at least 80% of the volume. With such a high filler particle content, metal buildup at the dielectric main surface of the laminate can also be effectively prevented. The high volume of filler particles distributed in the insulating layer structure can also affect the polarity of the insulating material, which can ultimately affect the Df characteristic of the insulating material.

[0019] In an embodiment, the main surface is configured to suppress attraction and adhesion by setting the main surface to have a low roughness Rz. Specifically, the main surface can be configured to suppress attraction and adhesion by setting the main surface to have a roughness Rz of less than 1000 nm. Preferably, the roughness Rz can even be less than 800 nm. A correspondingly smooth surface can also positively influence the suppression of attraction and adhesion of metal ions and / or metal particles on the main surface. Since a higher roughness Rz value can indicate a larger peak-valley variation on the surface, this can increase the overall surface area. The increased surface area can enhance ion adsorption because there are more sites available for ion interaction. Furthermore, surface roughness can produce interference effects that can alter the adsorption properties of the surface, thereby affecting the adsorption and distribution of ions on the surface. Alternatively or concurrently, a rough surface may have more defect sites, which can act as ion traps, thereby enhancing adsorption. Furthermore, roughness can also affect surface energy, where higher roughness can result in higher surface energy, which can more effectively attract and retain ions.

[0020] In an embodiment, one of the plurality of electrical insulating layer structures having the main surface is made of a material having a Df value at least 10% smaller than that of another electrical insulating layer structure located below the main surface. Preferably, the difference can be at least 20%. For example, an electrical insulating layer structure that is in direct physical contact with an exposed pad and is itself exposed can provide a dielectric resin with a lower Df value compared to another electrical insulating layer structure inside the stack. Therefore, the other electrical insulating layer structure can be manufactured with a standard dielectric material with less work, while the exposed electrical insulating layer structure can be manufactured with a sufficiently low Df value to prevent undesirable accumulation of metal particles on the surface of the stack. With this product configuration, high-density, fine-line structures can be produced at a lower cost. Alternatively or alternatively, in the case where different dielectric materials are used in different layers of the component carrier, warpage can also be reduced by compensating for the Young's modulus of the different materials.

[0021] In embodiments, the ratio of the surface area of ​​a portion of the filler to the surface area of ​​a portion of the resin on the main surface of one of the plurality of electrical insulating layer structures is in the range of 10% to 80%, particularly at least 60%. Therefore, the ratio of the area of ​​the main surface exposed by the filler to the area of ​​the main surface occupied by the resin material of the electrical insulating layer structure can be within the aforementioned range. Descriptively speaking, a high local area of ​​the filler on the main surface (especially when the filler is made of glass) can advantageously result in a low tendency for metal particles to accumulate on the main surface. Since a high local area of ​​the filler with a very smooth surface may exist on the main surface after an etching process (such as dry etching or wet etching), metal particles may find it difficult to adhere to the smooth surface of the filler. Therefore, a high local area of ​​the filler in the insulating layer structure can affect the attraction and adhesion of metal particles on the main surface.

[0022] In an embodiment, the main surface is configured to suppress attraction and adhesion by dissipating charge carriers on the main surface; specifically, the main surface is configured to suppress attraction and adhesion by setting the main surface to be free of charge carriers. Any measures employed to reduce the amount of charge carriers at or near the main surface can help suppress the attraction and adhesion of metal ions and / or metal particles on the main surface. Therefore, fine-line structures can be formed without additional processing to reduce the risk of charge and short circuits between the two connected pads.

[0023] In this embodiment, the main surface is configured to suppress attraction and adhesion by making it hydrophobic. For example, this hydrophobic property can be achieved by a corresponding surface treatment of the main surface or by a hydrophobic coating. Hydrophobic materials tend to be other neutral materials rather than charged materials. The non-polar properties at the main surface can reduce the undesirable accumulation of metal ions in this region by enhancing hydrophobicity. The hydrophobic morphology at the main surface also reduces the risk of metal growth on the surface, which ensures that the two pads do not bond due to the reaction of metal ions with other chemicals during chemical processes.

[0024] In this embodiment, the main surface is configured to suppress attraction and adhesion by treating the main surface to generate low van der Waals forces. For example, such surface properties can be achieved by performing appropriate surface treatments on the main surface. Without large van der Waals forces on the main surface, the undesirable accumulation of metal ions at that surface can be effectively suppressed.

[0025] Low van der Waals forces can be considered the fundamental reason for suppressing the attraction of metal ions. The ability of nonpolar molecules to undergo charge-dissociative polarization induced by an electric field can indirectly affect adsorption on the palladium surface for the following reasons: when a nonpolar molecule is placed in an electric field, the electron cloud within the molecule may be distorted. This may cause temporary charge separation, which in turn can lead to an induced dipole moment. Furthermore, van der Waals forces can be considered to influence palladium surface interactions because the palladium surface may have a localized charge distribution, or an electric field may be generated due to its electronic structure. In addition, van der Waals forces can affect electrostatic interactions because the induced dipole moment in the nonpolar molecule can interact with the electric field or charge distribution on the palladium surface. Moreover, these electrostatic interactions can promote the overall forces that manage the adsorption of molecules on the palladium surface. Compared with other forces such as van der Waals forces or specific chemical interactions, the effect of induced dipole moments on adsorption may generally be weaker. The main factors affecting adsorption can be the overall molecular structure and the presence of functional groups that can specifically interact with the palladium surface. Furthermore, the actual adsorption process can involve complex interactions of various forces, and the contribution of the induced dipole moment can vary depending on the specific molecule and the experimental conditions of the adsorption experiment. In short, while the ability of nonpolar molecules to be polarized by an electric field contributes to the interaction between nonpolar molecules and the palladium surface, this ability is likely a secondary factor compared to other intermolecular forces.

[0026] In an embodiment, at least one of the electrically conductive layer structures includes a seed layer and at least one plating layer. The seed layer may be a thin film of electrically conductive material deposited directly on a dielectric surface, serving as the base for a subsequently deposited electrically conductive plating layer, which can be formed by electroplating. For example, such a seed layer may include palladium, which is suitable for depositing copper thereon. The plating layer may be formed on the seed layer by electrodeposition, for example. Palladium ions can migrate to and remain on adjacent dielectric layers, making it highly likely that palladium ions next to the pads will react with metal ions in the ENEPIG chemical, causing overplating between the two metal pads. This could ultimately lead to a short circuit between the two pads.

[0027] In embodiments, the metal ions and / or metal particles have at least one component forming at least one of the electrically conductive layer structures and / or at least one component forming the surface treatment layer. Specifically, the metal ions and / or metal particles have at least one component forming a seed layer for at least one of the electrically conductive layer structures and / or at least one component forming the surface treatment layer. In particular, the at least one component includes palladium. While palladium may be helpful as a seed layer for subsequent copper deposition, palladium residue on undesirable surface portions of the exposed electrical insulating layer structure of the stack can lead to undesirable metal formation on that main surface (e.g., causing overplating between inner pads of an opening during the surface treatment process, which then leads to electrical performance problems such as short circuits). According to exemplary embodiments, the configuration or functionalization of the main surface can advantageously prevent such undesirable phenomena. Therefore, for fine-line structures and high-density products, risks to product electrical performance can be avoided with minimal effort.

[0028] In an embodiment, the main surface of one of the plurality of electrically insulating layer structures is configured to suppress the attraction and adhesion of palladium ions and / or palladium particles on the main surface. Since such palladium particles on the portion of the main surface outside the pad region may cause metal (especially gold) deposition during surface treatment, potentially unintentionally connecting electrically decoupled pads to each other, the measures taken according to an exemplary embodiment of the invention to suppress the attraction and adhesion of metal ions and / or metal particles on the main surface may have the greatest advantage. This measure may result in very little or even minimal workload, thus manufacturing workload can be controlled while ensuring good quality. This can provide significant advantages for the mass production of high-performance computing products.

[0029] In one embodiment, one of the plurality of electrically insulating layer structures includes filler particles at its main surface. These filler particles are configured to promote the inhibition of attraction and adhesion. Therefore, these filler particles can serve a dual function. On one hand, the filler particles can be added to the base resin of the electrically insulating layer structure to fine-tune the physical properties of the structure, such as enhancing thermal connectivity, robustness, or flexibility. Simultaneously, the filler particles can synergistically hinder the attraction and adhesion of metal particles to the exposed main surface of the electrically insulating layer structure, because the filler particles—especially when they are close to or present on the main surface—can reduce the localized presence of charge carriers.

[0030] In an embodiment, the main surface of one of the plurality of electrically insulating layer structures is configured such that the suppression of attraction and adhesion of metal ions and / or metal particles on the main surface is stronger than the suppression of attraction and adhesion of metal ions and / or metal particles on the other main surface of the same electrically insulating layer structure. Therefore, the configuration or functionalization of the exposed main surface of the electrically insulating layer structure of the stack that suppresses the attraction and adhesion of metal ions and / or metal particles on the main surface may be absent on the opposite main surface of the electrically insulating layer structure facing the interior of the stack. In addition to the exposed electrically insulating layer structure having its main surface, such a configuration or functionalization may also be absent on the main surface of the other electrically insulating layer structure of the stack.

[0031] In one embodiment, on the back side, an electrically insulating layer may be configured to inhibit the attraction and adhesion of metal ions and / or metal particles to the exposed surface. An opening may include two or more pads, all of which are fully exposed within the opening of the solder resist material. The opposite surface of the electrically insulating layer may include an electrically insulating layer, which may be, for example, a common prepreg or resin. An opening in the solder resist layer may include only one pad, wherein at least a portion of the pad may be embedded in an electrically insulating layer. This design allows for the realization of high-density and fine-line structure component carriers with low manufacturing cost and high quality.

[0032] In this embodiment, both the front and back sides of the stacked component may comprise a low-Df material in the outer layer (particularly the layer below the solder resist layer). Furthermore, more than one pad may be formed on the main surface exposed in the openings of the solder resist layer. Advantageously, this design allows for high-density and fine-line structures.

[0033] In this implementation, the entire dielectric material of the stacked layer can be made of a low-Df material, and a metal-defined pad can be provided only on the back side of the main surface. This design can significantly improve the integrity of high-frequency signal transmission. This implementation is particularly advantageous for high-performance computing.

[0034] In an embodiment, the exposed material of one of the plurality of electrical insulating layer structures defining at least a portion of the main surface differs from the material of another electrical insulating layer structure. Advantageously, the dielectric materials of the different electrical insulating layer structures of the stack can be selected differently. For example, an electrical insulating layer structure having an outer main surface with one or more metal pads can be made of a material having a lower Df value compared to another electrical insulating layer structure arranged inside the stack away from the outer main surface. This allows for specific adjustments to the dielectric layer with the exposed main surface to suppress undesirable metal buildup between the metal pads, while having the freedom to select the dielectric material of another electrical insulating layer structure (particularly another electrical insulating layer structure directly connected to the electrical insulating layer structure with the exposed main surface) in a different manner. This allows for the selection of the other materials according to other objectives, such as reducing manufacturing effort and mitigating the risk of electrical performance problems in more advanced products, and / or enhancing thermal conductivity, rigidity, or flexibility. To ensure proper warpage performance of the component's load-bearing parts, different insulation layers can be configured with different Young's moduli. This allows for the selection of combinations of different materials with varying Young's moduli to compensate for misregistration of the CTE (coefficient of thermal expansion) between the materials. Therefore, proper control of warpage is possible.

[0035] In an embodiment, one electrically insulating layer structure defining the main surface of the electrically insulating layer structure, together with at least one of the electrically conductive layer structures, forms part of a redistribution structure. This redistribution structure can be electrically conductive lines in a dielectric matrix, serving as an electrical transition structure between a first interface (e.g., an electronic component to be surface-mounted on a component carrier) and a second interface (e.g., a mounting base for mounting the component carrier, such as a printed circuit board). For example, the redistribution structure (particularly a redistribution layer) can be an electrical interface between regions with higher integration density (e.g., to be coupled to a semiconductor wafer) and regions with lower integration density (e.g., to be coupled to a printed circuit board). By at least partially embedding the redistribution structure in a low-Df material, low loss can be combined with the desired tendency to suppress the attraction and adhesion of metal ions and / or metal particles on the main surface of the low-Df material.

[0036] In one embodiment, the redistribution structure includes another electrically insulating layer structure within the plurality of electrically insulating layer structures. This other electrically insulating layer structure has a different material and / or different main surface interaction properties compared to the first electrically insulating layer structure defining the main surface. Therefore, another portion of the redistribution structure can be embedded in another dielectric material different from the low-Df material. Thus, a redistribution structure with a non-uniform dielectric periphery can be obtained, allowing for the adjustment of different properties in different regions.

[0037] In this embodiment, the surface treatment layer is in contact with the main surface. Specifically, the surface treatment layer may be in partial direct physical contact with the main surface of the exposed electrical insulating layer structure and may also be in partial direct physical contact with the exposed surfaces (particularly the exposed pad surfaces) of the electrically conductive layer structure of the stack. Although the surface treatment layer may be primarily formed on the electrically conductive layer structure, the annular end portion of the surface treatment layer may extend upward to the dielectric stack surface.

[0038] In one embodiment, at least one of the electrically conductive layer structures comprises at least two sub-parts arranged side-by-side, wherein a portion of the main surface located between the different sub-parts defines a first region of metallic material having a surface-treated layer. Alternatively or concurrently, at least one of the electrically conductive layer structures comprises at least two sub-parts arranged side-by-side, wherein a portion of the main surface located between the different sub-parts defines a second region free of metallic material. For example, the different sub-parts relate to adjacent exposed pads covered with a surface-treated material. Between them, an exposed portion of the main surface of the outermost electrically insulating layer structure located in the central region between adjacent pads can form a second region free of metallic material, thereby electrically decoupling the adjacent pads. Between the pads and such metal-free dielectric surface portions, the surface-treated material on the dielectric main surface can form a corresponding first region. This design offers the advantage that the electrically conductive layer structure (particularly including pads) can be welded over a wider area because it can be welded not only to the entire surface of the electrically conductive layer structure but also to its sidewalls. Therefore, bonding performance can be improved, and cracking issues between the electrically conductive layer structures can be controlled.

[0039] In one embodiment, the second region is arranged between two first regions within the first region. Advantageously, such a metal-free second region can electrically decouple laterally adjacent sub-parts of at least one electrically conductive layer structure, for example, by separating different pads from each other. This ensures the proper electrical function of the component carrier. Furthermore, this design allows for smaller pads and can increase the density of the milled layers. This can also distribute stress between the insulating material and the metal, thereby reducing the tendency for delamination or cracking caused by heat treatment.

[0040] In this implementation, the second region has a larger planar extension than the first region. Therefore, the planar extension between the two sub-regions can be largely free of unwanted metal coverage. When this planar extension is sufficiently large, high electrical reliability can be achieved.

[0041] In this implementation, each of the first and second regions is covered by a protective structure. Specifically, the protective structure can be the outermost insulating protective layer of the stack, particularly solder resist. Alternatively, the protective structure can be a molding compound molded around the at least two sub-parts. Such an electrically insulating protective structure can protect the stack relative to the environment, for example, from mechanical shock, oxidation, and / or undesirable coverage by materials such as solder. This can increase design freedom during manufacturing and even allow the use of component carriers under harsh conditions.

[0042] In embodiments, the first and second regions are configured to prevent electrical conduction between the two sub-parts. Specifically, the at least two sub-parts may include metal pads. A second region, located between the pads and associated with the dielectric master surface of the first region, and reliably free of parasitic metal coverage, can reliably ensure the electrical integrity of the component carrier. Typically, the ends of the pads may be embedded in an insulating material, thus the pads may be subject to thermal stress at the junction between the insulating material and the metal pad. However, exemplary embodiments of the present invention can reduce or even eliminate this effect, thereby avoiding delamination or cracking at the junction between the insulating material and the metal pad.

[0043] In embodiments, the distance between the pads is less than 130 μm, particularly in the range of 30 μm to 70 μm. Preferably, the distance can be in the range of 30 μm to 50 μm. This can be the distance between two sub-parts. More specifically, this can be the lateral or horizontal distance from the sidewall of a pad to the adjacent sidewall of an adjacent pad. Advantageously, the distance can be very small and can be smaller than the distance in conventional methods. This is due to the fact that, with regard to the configuration and functionalization of the exposed main surface of the exposed electrical insulating layer surface structure for suppressing the attraction and adhesion of metal ions and / or metal particles on the main surface, undesirable parasitic or artificial electrical coupling between adjacent pads on the main surface caused by undesirable parasitic or artificial metals located between the pads on the main surface can be reliably prevented.

[0044] In this embodiment, the diameter of the pad is less than 300 μm, particularly less than 100 μm. This can be the maximum horizontal diameter of the corresponding pad. Advantageously, the diameter can be very small and can be smaller than the diameter in conventional methods. This is because the size of the metal structure of the component carrier can be significantly reduced without affecting electrical reliability, in terms of the configuration and functionalization of the exposed main surface of the exposed electrical insulation layer surface structure for suppressing the attraction and adhesion of metal ions and / or metal particles on the main surface.

[0045] In an embodiment, the method includes removing metal ions and / or metal particles from at least a portion of the main surface. Specifically, the method includes removing palladium ions and / or palladium particles from at least a portion of the main surface. Furthermore, the method includes stripping metal ions and / or metal particles from at least a portion of the main surface. Advantageously, due to the configuration or functionalization of the main surface that inhibits the attraction and adhesion of metal ions and / or metal particles, a very simple metal stripping process can be performed on the main surface. For example, a simple or single (or single-stage) metal stripping process can be performed on the main surface.

[0046] In one embodiment, the component carrier comprises a stack of multiple electrically insulating layer structures and at least one electrically conductive layer structure. For example, the component carrier can be a laminate of one or more of the electrically insulating layer structures and one or more of the electrically conductive layer structures, particularly a laminate of one or more of the electrically insulating layer structures and one or more of the electrically conductive layer structures formed by applying mechanical pressure and / or thermal energy. The stack can provide a plate-shaped component carrier, which can provide a large mounting surface for other components while remaining very thin and compact.

[0047] In this implementation, the component carrier is shaped like a plate. This facilitates a compact design, where the component carrier still provides a large base for mounting components. In particular, a bare die, as an example of an electronic component, can be surface-mounted on a thin plate such as a printed circuit board.

[0048] In one embodiment, the component carrier is configured as one of a printed circuit board, a substrate (particularly an IC substrate), and an intermediate layer.

[0049] In the context of this application, the term "printed circuit board" (PCB) can specifically refer to a board-shaped component carrier formed by laminating multiple electrically conductive layer structures with multiple electrically insulating layer structures, for example, a board-shaped component carrier formed by laminating multiple electrically conductive layer structures with multiple electrically insulating layer structures by applying pressure and / or by industrial heat. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may include resin and / or glass fiber, i.e., so-called prepreg or FR4 material. Various electrically conductive layer structures can be connected to each other in a desired manner by forming through-holes in the laminate, for example by laser drilling or mechanical drilling; and by partially or completely filling these holes with an electrically conductive material (partially copper), thereby forming vias or any other through-hole connections. Filled holes can connect the entire stack (through-hole connections extending through several layers or the entire stack), or filled holes can connect at least two electrically conductive layers, referred to as vias. Similarly, to receive an optoelectronic circuit board (EOCB), optical interconnects can be formed by stacking the individual layers. Printed circuit boards are typically constructed to house one or more components on one or both opposite surfaces of a slab-shaped printed circuit board. One or more components can be soldered to their respective main surfaces. The dielectric portions of the PCB can be composed of resin with reinforcing fibers such as glass fiber.

[0050] In this embodiment, the component carrier is an integrated circuit substrate. In the context of this application, the term "integrated circuit substrate" (IC substrate) can specifically refer to a component carrier having dimensions and spacing adjusted according to the requirements of integrated circuit components (particularly semiconductor chips) mounted on it. In the case of a PCB, an IC substrate can be a relatively small component carrier on which one or more integrated circuit components can be mounted, and the IC substrate can act as a connector between one or more chips and the PCB, or be inserted into a socket mounted on the PCB. For example, an IC substrate can have substantially the same size as the electronic component to be mounted on it (e.g., in the case of a chip-scale package (CSP)). In another embodiment, an IC substrate can be larger than the specified component (e.g., in flip-chip ball grid arrays, FCBGA configurations). More specifically, an IC substrate can be understood as a carrier for electrical connections or electrical networks, and a component carrier equivalent to a printed circuit board (PCB), but with a considerably high density of lateral and / or vertically arranged connections. For example, lateral connections are conductive paths, while vertical connections can be drilled holes. These lateral and / or vertical connections are arranged within the IC substrate and can be used to provide electrical, thermal, and / or mechanical connections between accommodating or non-accommodating components (such as bare wafers), particularly IC chips, and printed circuit boards or intermediate layers. The dielectric portions of the IC substrate may be composed of resin with reinforcing particles (e.g., reinforcing spheres, particularly glass spheres). The spacing of the IC substrate, i.e., the distance between corresponding edges of two adjacent metal structures, may not exceed 150 μm, and particularly not exceed 100 μm. In contrast, the spacing of some PCBs may be at least 200 μm, and particularly at least 300 μm.

[0051] The substrate or intermediate may include or consist of at least glass, silicon (Si) and / or photo-imaging or dry-etching organic materials, such as epoxy-based stacked materials (e.g., epoxy-based stacked films) or polymer compounds (which may or may not include photosensitive molecules and / or thermosensitive molecules), such as polyimide or polybenzoxazole.

[0052] In embodiments, at least one electrical insulating layer structure comprises at least one of the following: resins or polymers, such as epoxy resins, cyanate ester resins, benzocyclobutene resins, melamine derivatives, polybenzoxazole (PBO), bismaleimide-triazine resins, polystyrene derivatives (e.g., based on polyphenylene ether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymers (LCP), polytetrafluoroethylene (PTFE), bisbenzocyclobutene (BCB), and / or combinations thereof. Reinforcing layer structures, such as meshes, fibers, spheres, or other types of filler particles, may also be used, for example, reinforcing layer structures made of glass (multilayer glass), to form composite materials. The semi-cured resin combined with the reinforcing agent, such as fibers impregnated with the aforementioned resins, is called a prepreg. These prepregs are typically named according to their properties, such as FR4 or FR5, which describes their flame-retardant properties. While prepregs, particularly FR4, are generally preferred for rigid PCBs, other materials may also be used, particularly epoxy-based stacking materials (such as stacked films) or photo-imaging dielectric materials. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate resins are preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, very low, or ultra-low DK materials can be used as electrical insulation structures in component carriers.

[0053] In embodiments, at least one of the electrically conductive layer structures comprises at least one of copper, aluminum, nickel, silver, gold, palladium, tungsten, titanium, molybdenum, and magnesium. While copper is generally preferred, other materials or coating versions thereof are also possible, particularly coatings with superconducting materials or electrically conductive polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT).

[0054] At least one of the components may be selected from at least one of the following: non-conductive inlays, conductive inlays (e.g., metallic inlays, preferably including copper or aluminum), heat transfer units (e.g., heat pipes), light guiding elements (e.g., optical waveguides or optical conductor connectors), electronic components, or combinations thereof. The inlay may be, for example, a metal block, with or without an insulating material coating (IMS-inlay), and may be surface-mounted to facilitate heat dissipation. Suitable materials are defined by their thermal conductivity, which should be at least 2 W / mK. These materials are typically based on, but not limited to, metals, metal oxides, and / or ceramics, such as copper, alumina (Al₂O₃), or aluminum nitride (AlN). Other geometries that increase surface area are also frequently used to increase heat exchange capacity. In addition, components can be active electronic elements (implementing at least one pn junction), passive electronic elements such as resistors, inductors or capacitors, electronic chips, memory devices (e.g., DRAM or other data memory), filters, integrated circuits (e.g., field-programmable gate arrays (FPGAs), programmable array logic (PALs), general-purpose array logic (GALs) and complex programmable logic devices (CPLDs)), signal processing components, power management components (e.g., field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS), junction field-effect transistors (JFETs) or insulated-gate field-effect transistors (IGFETs)). All of these are based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), indium phosphide (InP), and / or any other suitable inorganic compound), optoelectronic interface elements, light-emitting diodes, optocouplers, voltage converters (e.g., DC / DC converters or AC / DC converters), cryptographic components, transmitters and / or receivers, electromechanical transducers, sensors, actuators, microelectromechanical systems (MEMS), microprocessors, capacitors, resistors, inductors, batteries, switching components, cameras, antennas, logic chips, and energy harvesting units. However, other components can be surface-mounted onto component carriers. For example, magnetic elements can be used as components. Such magnetic elements can be permanent magnetic elements (e.g., ferromagnetic elements, antiferromagnetic elements, multiferromagnetic elements, or ferromagnetic elements, such as ferrite cores), or they can be paramagnetic elements. However, the component can also be an IC substrate, intermediate, or other component carrier, such as a board-in-board configuration. The component can be surface-mounted onto the component carrier. Alternatively, other components may be used, particularly those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment.

[0055] In one embodiment, the component carrier is a laminated component carrier. In such an embodiment, the component carrier is a multilayered compound that is stacked and connected together by applying pressure and / or heat.

[0056] After processing the inner layer structure of the component carrier, one or more additional electrically insulating and / or electrically conductive layer structures (particularly by lamination) can be used to symmetrically or asymmetrically cover one main surface or both opposite main surfaces of the processed layer structure. In other words, stacking can continue until the desired number of layers is obtained.

[0057] After the stacked components of the electrical insulation layer structure and the electrical conductivity layer structure are formed, the obtained layer structure or component carrier can be surface treated.

[0058] Specifically, in terms of surface treatment, electrically insulating solder resist can be applied to one or both opposing main surfaces of a laminate or component carrier. For example, such a solder resist can be formed over the entire main surface and subsequently patterned to expose one or more electrically conductive surface portions used to electrically couple the component carrier to electronic peripherals. The surface portions of the component carrier still covered by the solder resist, particularly those containing copper, can be effectively protected against oxidation or corrosion.

[0059] Regarding surface treatment, a surface treatment portion can be selectively applied to the exposed electrically conductive surface portion of the component carrier. Such a surface treatment portion can be an electrically conductive covering material on an exposed electrically conductive layer structure (e.g., pads, conductive tracks, etc., particularly including or composed of copper) on the surface of the component carrier. If this exposed electrically conductive layer structure is not protected, the material of the exposed electrically conductive component carrier (particularly copper) may oxidize, reducing the reliability of the component carrier. The surface treatment portion can then be formed, for example, as an interface between a surface-mount component and the component carrier. The surface treatment portion functions to protect the exposed electrically conductive layer structure (particularly copper circuitry) and to enable a connection process with one or more components, such as by soldering. Examples of suitable materials for the surface treatment portion include organic solderable corrosion inhibitors (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), gold (particularly hard gold), electroless tin, nickel-gold, nickel-palladium, etc. Attached Figure Description

[0060] The foregoing limitations and other aspects of the invention will become apparent from examples of embodiments described below, and will be interpreted with reference to these embodiments.

[0061] Figure 1 A cross-sectional view of a component carrier according to an exemplary embodiment of the present invention is shown.

[0062] Figure 2 A cross-sectional view of a component carrier according to another exemplary embodiment of the present invention is shown.

[0063] Figures 3 to 8 A plan view of a component carrier according to an exemplary embodiment of the present invention is shown.

[0064] Figure 9 and Figure 10 A schematic diagram is shown indicating the metal present on the surface of a component carrier according to an exemplary embodiment of the present invention.

[0065] Figure 11 A manufacturing architecture for a manufacturing component carrier according to an exemplary embodiment of the present invention is shown. Detailed Implementation

[0066] The illustrations in the accompanying drawings are schematic. In different drawings, similar or identical elements are given the same reference numerals.

[0067] When creating metal-defined pads (especially on the back side) for component carriers, conventional methods require large pad sizes and spacing. Considering the palladium stripping process, which can be performed as a two-times process, small pad sizes and spacings are difficult, if not impossible, to achieve in conventional methods. In this case, the palladium stripping process can be difficult and cumbersome in the context of seed layer formation. Furthermore, the two-times palladium process not only increases manufacturing workload due to the need for more chemicals but also potentially increases the risk to product quality due to an additional chemical impregnation. Resin sheet materials can be used for electrical insulation layers. In particular, the same resin sheet material can be used for all electrical insulation layers.

[0068] However, there is a trend towards smaller packages designed for increasingly smaller pitches used to mount devices. Correspondingly, component carriers such as integrated circuit (IC) substrates need to be improved and upgraded to have smaller dimensions. Specifically, on the back side of such component carriers, the size and spacing of the metal-defined pads must be reduced to meet stringent specification requirements. However, this is difficult, if not impossible, to achieve using conventional methods. Furthermore, the design of the metal-defined pads on the back side can simplify the assembly between the IC substrate and the motherboard, as the metal-defined pads can be mounted via pins instead of soldering.

[0069] According to an exemplary embodiment of the invention, a component carrier (e.g., a PCB) may include (preferably laminated) a stack. The stack may include electrically conductive layer structures (e.g., pads that will be interconnected with other electronic systems, such as surface-mount electronic components, by means of soldering). The stack may also include one or more electrically insulating layer structures (e.g., organic sheets with inorganic fillers). Surface treatment layers, such as those formed from ENEPIG, may coat and protect the outer surfaces of one or more electrically conductive layer structures. Advantageously, the exposed main surfaces of the electrically insulating layer structures between the portions of the electrically conductive layer structures covered by the surface treatment may be specifically configured or functionalized to prevent the attraction and adhesion of metal ions and other metal particles on the exposed dielectric main surfaces. Such metal ions and other metal particles may be a side effect of the seed layer formation and / or surface treatment layer formation processes. By selecting and correspondingly adjusting the surface region characteristics of at least one electrically insulating layer structure defining the main surface, any undesirable metallization between the portions of the electrically conductive layer structures can be partially or completely prevented. For example, this can be achieved by correspondingly selecting the material of at least one electrically insulating layer structure adjacent to the main surface, such as selecting a low-Df material. Appropriate configuration of the surface topography and morphology of the main surface can also be effective, for example, by adjusting the surface properties of filler particles in the resin matrix of the exposed electrically insulating layer structure. By preventing metals (e.g., palladium from the seed process and / or gold from the surface treatment process) from being present around at least one electrically conductive layer structure on the electrically insulating surface, the line space ratio and / or one or more other feature dimensions of the component carrier and, in particular, the pads of the component carrier can be reduced, thus also reducing or even eliminating the risk of electrical defects, such as short circuits between two pads connected by metal deposition due to the catalytic reaction of other metals by palladium remaining on the insulating layer. This allows for the provision of component carriers with fine line structures with less effort.

[0070] According to an exemplary embodiment, on a component carrier, particularly on the back side of a component carrier such as an integrated circuit substrate, a metal-defined pad can be formed using a low-Df resin sheet on an underlying layer. For example, such a resin sheet can be an Ajinomoto polymer film with low Df properties. (ABF) or other insulating materials with low Df performance. By selecting the material of one or more electrically insulating layers beneath the exposed pad of one or more electrically conductive layers, the attraction and adhesion of metal ions and / or metal particles on the main surface of each electrically insulating layer can be significantly suppressed.

[0071] Exemplary embodiments of the present invention can have advantages: in particular, by suppressing or hindering metal formation on the main surface of an electrically insulating layer structure adjacent to one or more metal-defined pads, the spacing between pads can be reduced, for example, to 30 μm or even less. The size of the metal-defined pads can also be reduced to 77 μm or even less. Furthermore, such a manufacturing architecture can eliminate a palladium stripping process, or at least significantly simplify palladium stripping. Additionally, the size of the substrate and components can be reduced. This can also lead to a reduction in manufacturing workload due to the smaller size of the component carriers and their substructures. Advantageously, this can also lead to lower power consumption.

[0072] To avoid being bound by a specific theory, it is currently believed that there may be an indirect relationship between the dielectric constant (Df) of a material and its ability to adsorb palladium colloids in the absence of an electrostatic field. This can be attributed to the fact that the dielectric constant (or permittivity) of a material reflects its ability to store electrical energy in an electric field. This is thought to be related to the polarizability of the material, i.e., how easily the electron distribution of the material is distorted by an external field. There is also an indirect effect on adsorption: although it may not be the primary driving factor, a higher dielectric constant generally implies a higher polarizability. This may affect the strength of van der Waals forces, which may play a role in palladium adsorption. Regarding surface charge, a higher dielectric constant may be associated with a higher surface charge density. This, in turn, can affect the electrostatic interaction with palladium colloids. However, other factors may dominate palladium adsorption: in many cases, van der Waals forces may be the most important driving force for adsorption. For nonpolar surfaces and media, hydrophobic interactions may be important. If the surface contains aromatic groups, (pi-pi) interactions likely play a major role. Surface chemistry and morphology may also significantly influence adsorption. In summary, while the dielectric constant can indirectly affect palladium adsorption, it cannot be considered the primary determinant. The main factors are considered to be various intermolecular forces, surface properties, and the nature of the surrounding medium. Therefore, the relationship between the dielectric constant and palladium adsorption may be mild and can be masked by other, more important factors governing the adsorption process.

[0073] It can be considered that the dielectric constant (Df) of the electrical insulation layer structure material of a component carrier can affect the attraction and adhesion of metal ions and / or metal particles on the exposed main surface of the electrical insulation layer structure. For example, the GX, GY, and GL series from Ajinomoto Fine-Techno are various types of stacked film (ABF) that can be advantageously used in the manufacture of printed circuit boards (PCBs) and other component carriers. Different series of materials can have different properties. The GX series uses epoxy-based resins. This material is characterized by a good balance of performance and suitability for general applications. This material can be used in a variety of PCB applications. The GY series materials can use a base resin in the form of a mixture of epoxy and cyanate ester resins. Compared to the GX series, this material in the GY series may result in enhanced thermal stability and a lower dielectric constant (Dk), making the GY series more suitable for high-frequency applications. In particular, this material can be used in applications where signal integrity is critical, such as high-speed digital circuits and microwave devices. The GL series materials can use a proprietary blend focused on low dielectric loss (Df) as the base resin. This material is characterized by its very low Df value, which reduces signal transmission loss and makes it suitable for high-frequency and high-speed applications. Exemplary applications using this material are those with extremely high requirements for signal integrity and low loss, such as 5G communication equipment and high-performance computing systems. In summary, GX materials can be used for general purposes and allow for a good performance balance. For high-frequency applications, GY materials can improve thermal stability and reduce the Dk value. GL materials can result in ultra-low Df values ​​and can achieve critical signal integrity in high-speed applications.

[0074] In view of the above, exemplary embodiments of the present invention can use different dielectric materials with different Df values ​​for different dielectric layers of the component carrier to suppress the attraction and adhesion of metal ions and / or metal particles on the exposed host surface of the dielectric material. Descriptively speaking, the Df value can represent how stable the behavior of the dielectric material is in an electric field. The lower the Df value, the more stable the behavior. When the electric cloud mobility in the dielectric material is low, the unwanted movement of charge carriers to palladium on the dielectric surface can be prevented, thereby reducing the adsorption of palladium on the host surface of the electrically insulating layer structure. Therefore, palladium can be removed more easily in subsequent processes. Thus, pads can be manufactured to be smaller and / or arranged closer together. For the production of copper pads, palladium can act as a catalyst for seed layer deposition. However, such palladium can migrate to the insulating layer and may remain on it, which can interfere with subsequent surface treatment formation. This can generally limit the achievable pad-to-pad distance. By using a low-Df dielectric material for at least a portion of the electrically insulating layer structure of the stack, the interaction of charge with palladium can be prevented, thus enabling a small pad-to-pad distance.

[0075] However, adjusting the dielectric constant (Df) of one or more electrical insulating layers in a component carrier is merely an implementation that hinders or suppresses the attraction and adhesion of metal ions and / or metal particles to the main surface of the outer electrical insulating layer. In this case, the value of the low-Df dielectric material can preferably be less than or equal to 0.018. It can also be advantageous when the Df value of the exposed electrical insulating layer is at least 10% smaller than the Df value of the underlying electrical insulating layer. Alternatively or alternatively, one or more additional measures can be taken for this purpose. For example, a large amount of exposed filler on the exposed main surface of the electrical insulating layer can also allow for hindering or suppressing the attraction of metal particles to the dielectric surface. For example, the exposed electrical insulating layer can have at least 70% volume of particles, particularly glass particles. The volume and distribution of glass particles will change the polarity of the material and then affect the Df of the material. It can also be advantageous when the ratio between the partial filler area of ​​the exposed electrical insulating layer and the surface area defined by the resin can be in the range of 10% to 80%. For example, exposed glass particles may have a positive effect because there is essentially no charge regulation on such a glass surface. Furthermore, a low roughness Rz on the exposed dielectric host surface can have a positive effect because it can improve the efficiency of palladium stripping. For example, a roughness Rz below 1000 nm can be advantageous. Therefore, adjusting the surface morphology can also allow for the suppression or inhibition of the attraction and adhesion of metal particles on the exposed electrically insulating host surface.

[0076] Specifically, exemplary embodiments may provide a component carrier with a metal-defined pad design combined with different laminated electrical insulating layer structures, such as a combination of ABF and / or low-Df materials at least on the exposed main surface. More generally, exemplary embodiments of the invention may reduce the back-side metal-defined pad spacing using a hybrid structure substrate. For example, an electrical insulating layer structure with a low-Df resin may be disposed on the exposed back side of the component carrier. This may allow for a smaller spacing of the metal-defined pads. Therefore, improvements in signal transmission capabilities can be achieved. Advantageously, less filler dielectric material can be used due to the smaller spacing of the metal-defined pads. The desired Df value of at least one of the electrical insulating layer structures (particularly the exposed electrical insulating layer structure) may be, for example, in the range of 0.003 to 0.0022, particularly less than 0.0022. A key aspect of exemplary embodiments may be the use of low-Df ABF on the substrate to reduce or even minimize the spacing of the metal-defined pads. Exemplary embodiments may provide the possibility of removing palladium stripping processes with large metal-defined pad designs. This may help improve throughput and trigger savings in manufacturing work. Furthermore, fine-line structures for substrates may become possible.

[0077] According to an exemplary embodiment of the present invention, a component carrier is provided, comprising a stacked member, the stacked member including at least one electrically conductive layer structure and a plurality of electrically insulating layer structures. At least one of the electrically conductive layer structures may be disposed on the main surface of one of the plurality of electrically insulating layer structures or disposed within the main surface of one of the plurality of electrically insulating layer structures, and may include an exposed surface at least partially covered by a surface treatment layer. The main surface of one of the plurality of electrically insulating layer structures may be configured to hinder the attraction and adhesion of metal ions and / or metal particles on the surface.

[0078] In this implementation, the attraction and adhesion of metal ions and / or metal particles can be hindered. The types of exposed materials may include low-Df materials (which can enhance the hindering effect) and / or fillers (which can reduce the hindering effect). The types of exposed surfaces can be adjusted according to roughness and may include low-charge or uncharged surfaces, surfaces that experience low van der Waals forces, and / or hydrophobic surfaces.

[0079] In an embodiment, at least one electrically conductive layer structure may include a seed layer (wherein a metallic material (e.g., particles) forming the seed layer may be deposited or disposed on the main surface of an electrically insulating layer structure, and the main surface may be configured to impede the attraction and adhesion of metal ions) and at least one plating layer. For example, the ions may be a metal that is at least one component of the at least one electrically conductive layer structure on the main surface. The ions may also be a metal that is at least one component of the seed layer. Alternatively or additionally, the ions may be a component of a surface treatment layer. For example, the ions may include or be composed of palladium.

[0080] For example, the filler (or filler particles) at the main surface may affect the resistance to the attraction and adhesion of metal ions. In an embodiment, the main surface of one of the plurality of electrically insulating layer structures is configured such that the inhibition of the attraction and adhesion of metal ions on that surface is stronger than the inhibition of the attraction and adhesion of metal ions on another main surface or main surface of another (i.e., adjacent) electrically insulating layer structure of the stack. For example, the exposed material defining the main surface of the electrically insulating layer structure is different from the material of another (i.e., adjacent) electrically insulating layer structure constituting the stack. In an embodiment, the electrically insulating layer structure defining the main surface is part of a redistribution layer. In particular, the redistribution layer includes at least one additional electrically insulating layer structure having a different material and / or different main surface interaction than the electrically insulating layer structure defining the main surface of the plurality of electrically insulating layer structures. For example, a surface treatment layer is in contact with the main surface. For example, on the main surface of one of the plurality of electrical insulating layer structures, or at least one electrically conductive layer structure on the main surface, at least two sub-parts are arranged side-by-side, wherein, in particular, the main surface between these two sub-parts includes a first region having a composition of low amounts of metal particles and / or metal ions and / or surface treatment layers. In an embodiment, on the main surface of one of the plurality of electrical insulating layer structures, or at least one electrically conductive layer structure on the main surface, at least two sub-parts are arranged side-by-side, wherein, in particular, the main surface between these two sub-parts includes a second region free of particles and / or metal ions and / or surface treatment layers. For example, the second region may be arranged between two first regions. For example, the second region has a planar extension larger than the first region. In an embodiment, each of the first and second regions is covered by a protective structure. For example, the protective material may be from the outermost insulating layer of the stack (e.g., a protective layer, such as a solder resist layer). Advantageously, a molding material may be formed around the at least two sub-parts. In an embodiment, the sub-parts include pads. For example, the extensions and distribution of the first and second regions prevent electrical conductivity between the two sub-parts. In implementation, the relationship between the diameter, thickness, and distance of the pads, copper, and Pd-Au layers can be adjusted to ensure they are registered with each other.

[0081] Figure 1 A cross-sectional view of a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0082] The component carrier 100 may be an integrated circuit (IC) substrate or a printed circuit board (PCB). The component carrier 100 may include a laminated stack 102, which includes an electrically conductive layer structure 104 and electrically insulating layer structures 106, 108. For example, the electrically conductive layer structure 104 may include a patterned metal layer (such as a patterned copper foil or a patterned deposited copper layer) and vertical through-connections, such as copper-filled vias, which can be created by drilling and plating. The electrically insulating layer structures 106, 108 may include a suitable resin (such as a suitable epoxy resin), preferably the resin including reinforcing particles (e.g., glass fibers or glass beads) in the resin. For example, the electrically insulating layer structures 106, 108 may be made of prepreg or FR4 or ABF. The electrically insulating layer structures 106, 108 may also include a resin layer that does not contain glass (especially glass fibers).

[0083] like Figure 1 As shown, the uppermost conductive layer structure 104 of the stack 102 extends upward and vertically beyond the exposed main surface 110 of the electrically insulating layer structure 106. More specifically, the conductive layer structure 104 may include an externally accessible pad 150 located vertically above a vertically penetrating connection 152, which may be embodied as a copper-filled laser via embedded in the electrically insulating layer structures 106, 108. In the illustrated embodiment, an additional embedded pad 154 is disposed below the vertically penetrating connection 152 and vertically connected to it. The electrically insulating layer structures 106, 108 defining the main surface 110 may form a redistribute structure 120 together with the conductive layer structure 104.

[0084] Now for reference Figure 1 Detail 158, the uppermost electrically conductive layer structure 104, and more specifically the pad 150 of the uppermost electrically conductive layer structure 104, includes a seed layer 114 directly located on the electrically insulating layer structure 106, and includes one or more plating layers 116 thereon. For example, the seed layer 114 can be formed by chemical plating. For example, one or more plating layers 116 can be formed by electroplating, for example by electroplating.

[0085] Still referencing Figure 1A surface treatment layer 118 is provided, which covers the exposed surface of the pad 150 of the electrically conductive layer structure 104. The surface treatment layer 118 may also cover a portion of the partially exposed main surface 110 of the electrically insulating layer structure 106. In other words, the surface treatment layer 118 is in contact with the main surface 110. For example, the surface treatment layer 118 may be made of an electrically conductive material, thereby protecting the surface of the pad 150 from oxidation and promoting the solderability of the pad 150 with solder (not shown). For example, the surface treatment layer 118 may be an ENEPIG (electroless nickel-plated palladium-plated gold) layer, which may have an intermediate layer including palladium.

[0086] Metal ions and / or metal particles that may unintentionally accumulate at the main surface 110 may contain metals (e.g., palladium) that form the seed layer 114 and / or metals (e.g., gold) that form the surface treatment layer 118. To prevent this undesirable phenomenon, the main surface 110 of the exposed electrically insulating layer structure 106 can be configured to suppress the attraction and adhesion of palladium ions and / or palladium particles and / or gold ions and / or gold particles on the main surface 110. This can be achieved by taking one or more of the measures described below.

[0087] Furthermore, a patterned electrical insulating solder resist forms a protective structure 130 and is formed on a portion of the exposed main surface 110 of the uppermost electrical insulating layer structure 106. The openings in the patterned protective structure 130 may have lateral extensions larger than the lateral extensions of any one of the pads 150, and even larger than the lateral extensions of both pads 150 together. Surface portions of the component carrier 100 still covered with the solder resist-type protective structure 130 can be protected from oxidation or corrosion, particularly copper-containing surface portions (not shown). The protective structure 130 forms the outermost insulating protective layer of the stack 102 in the form of solder resist. Alternatively, the protective structure 130 may be a molding compound molded around sub-parts 122, 124 of the electrically conductive layer structure 104 (not shown).

[0088] During the manufacture of component carrier 100, particularly considering the seeding process for forming a seed layer 114 (e.g., including palladium) for pad 150 and / or the process for forming a surface treatment layer 118 (e.g., including gold), there is a risk of metal particles, metal ions, etc., depositing or accumulating on the main surface 110. This can reduce the electrical reliability of component carrier 100 during routine manufacture because (e.g., through an unintentional short circuit in pad 150) incorrect electrical connections are formed. Furthermore, this can make it conventionally impossible to achieve pads 150 with very small horizontal dimensions and very small horizontal spacing when superior electrical reliability is desired.

[0089] In order to utilize the exemplary embodiments of the present invention Figure 1 The component carrier 100 overcomes this conventional drawback by configuring or functionalizing the main surface 110 of the partially exposed electrically insulating layer structure 106 to suppress the attraction and adhesion of metal ions and / or metal particles on the main surface 110. Generally, the main surface 110 can be functionalized or configured to suppress the attraction and adhesion by dissipating the charge carriers on the main surface 110, preferably by making the main surface 110 free of charge carriers. While not wishing to be bound by specific theories, it is currently believed that charge carriers on the main surface 110 are often the cause of undesirable adhesion and attraction of metal particles on the main surface.

[0090] One measure to achieve the aforementioned configuration or functionalization is to suppress the undesirable attraction and adhesion of metal on the main surface 110 by providing a partially exposed electrically insulating layer structure 106 with a low Df material. For example, the dielectric material can be selected to have a Df value less than 0.018, such as a Df value in the range of 0.002 to 0.010. For example, a resin material can be selected accordingly for the electrically insulating layer structure 106. Describingly, the low Df material of the partially exposed electrically insulating layer structure 106 can prevent the accumulation of charge at the main surface 110, which can have a positive effect on preventing the formation of metal particles on the main surface 110. In particular, it may be advantageous and sufficient to provide a partially exposed electrically insulating layer structure 106 having a Df value at least 10%, for example, at least 20%, smaller than the Df value of the internal electrically insulating layer structure 108 located below the main surface 110. Therefore, the outermost electrical insulation layer structure 106 can be functionalized to prevent the accumulation of metal particles at the main surface 110, while the simple and inexpensive inner electrical insulation layer structure 108 can be acceptable.

[0091] Now for reference Figure 1Detail 156, another measure to hinder the attraction and adhesion of metal ions and / or metal particles on the main surface 110, is to include a high content of filler particles 112 in the partially exposed electrical insulating layer structure 106. For example, such filler particles 112 may comprise glass or ceramic particles, such as spherical particles or beads. Such filler particles 112 can be used to fine-tune the characteristics of the electrical insulating layer structure 106, for example, to enhance the thermal conductivity and / or mechanical stability of the electrical insulating layer structure 106. However, the inventors have found that the amount of filler particles 112, particularly a sufficiently large amount, can also help prevent the accumulation of metal particles at the main surface 110. More specifically, the exposed electrical insulating layer structure 106 may be provided with a filler particle content of at least 70% of the total volume of the electrical insulating layer structure 106. Such filler particles 112, particularly when the filler particles 112 are made of glass, can also prevent the accumulation of charge at the main surface 110, because the filler particles 112 themselves do not readily carry charge carriers. In order to obtain a significant positive effect from the filler particles 112 (especially those made of glass), the main surface 110 of the exposed electrical insulating layer structure 106 may be defined as a ratio of at least 30% of the surface area A1 of the filler to the surface area A2 of the resin, preferably at least 60%, see detail 156.

[0092] Another measure to suppress the accumulation of metal particles on the main surface 110 is to adjust the surface morphology of the main surface 110 accordingly. Specifically, the main surface 110 can be configured to suppress attraction and adhesion by providing a main surface 110 with a low roughness Rz, particularly by providing a main surface 110 with a roughness Rz of less than 1000 nm. Clearly, a sufficiently smooth main surface 110, with respect to roughness Rz, may have a positive effect on suppressing the accumulation of metal particles on the main surface.

[0093] Physical and / or chemical surface treatments or surface activation of the main surface 110 can also enhance its ability to hinder the attraction and adhesion of the metal particles. In particular, this can be achieved by making the main surface 110 hydrophobic. The ability of the electrically insulating layer structure 106 and its main surface 110 to suppress attraction and adhesion can also be further enhanced by treatment to generate low van der Waals forces, as this also tends to drive charge carriers away from the main surface 110.

[0094] Due to the described function or configuration of the main surface 110, the exposed main surface 110 of the electrical insulating layer structure 106 is configured to exert stronger inhibition of attraction and adhesion on the main surface 110 than on the opposite main surface 132 of the electrical insulating layer structure 106. This difference on the opposite main surfaces 110, 132 can be considered a fingerprint of the aforementioned function or configuration.

[0095] During the manufacturing process, metal ions and / or metal particles can be removed from the exposed main surface 110, particularly by stripping. However, this may result in a reduction of metal at undesirable surface portions of the main surface 110. Nevertheless, this stripping process (particularly palladium stripping) can be quite simple in terms of the aforementioned measures to prevent the attraction and adhesion of metal particles to the main surface 110. In another embodiment, palladium stripping can also be omitted. This can reduce the manufacturing workload of the component carrier 100.

[0096] Still referencing Figure 1 The electrically conductive layer structure 104 includes side-by-side sub-parts 122, 124. A portion of the main surface 110 located between the different sub-parts 122, 124 defines a first region 126, which has residues of the metallic material of the surface treatment layer 118 (in... Figure 1 (Not visible in the image). Another portion of the main surface 110, located between the different sub-parts 122, 124, defines a second region 128 free of metallic material. The second region 128 is arranged between the two first regions 126 and may have a larger planar extension than the first regions 126. Advantageously, due to measures for suppressing the attraction and adhesion of metallic particles on the main surface 110, the first region 126 and the second region 128 are configured such that electrical conduction is impossible between the two sub-parts 122, 124. Therefore, the pads 150 of the two sub-parts 122, 124 can remain electrically decoupled from each other, thereby obtaining a component carrier 100 with high electrical reliability.

[0097] Figure 2 A cross-sectional view of a component carrier 100 according to another exemplary embodiment of the present invention is shown. Also referenced is... Figure 1 The corresponding element in.

[0098] Metal depletion between horizontally adjacent pads 150 (particularly in the second region 128) allows for the provision of small pads 150, where adjacent pads 150 have a small mutual distance. For example... Figure 2As shown, the distance d between the pads 150 can be less than 130 μm, preferably in the range of 30 μm to 70 μm. The diameter D of the pads 150 can be less than 300 μm, preferably less than 100 μm, see again. Figure 2 Therefore, exemplary embodiments of the present invention can allow for the manufacture of component carriers 100 with very small metal structures in a compact manner.

[0099] according to Figure 2 The two outermost laminated electrical insulating layer structures 106 and 108 are shown in detail. In this embodiment, the outer electrical insulating layer structure 106 may be made of a dielectric material having a lower Df value than the directly connected inner electrical insulating layer structure 108. For example, the electrical insulating layer structure 108 may be made of a standard ABF material, while the electrical insulating layer structure 106 may be made of a low-Df ABF material (e.g., GL series ABF materials, such as GL107). This combines the low manufacturing effort of the electrical insulating layer structure 108 with the enhanced ability of the electrical insulating layer structure 106 to suppress the attraction and adhesion of metal ions and / or metal particles on the main surface 110. Therefore, the exposed material defining the main surface 110 of the electrical insulating layer structure 106 differs from the material of the adjacent electrical insulating layer structure 108. Thus, the redistribution structure 120 is partially embedded in the low-Df electrical insulating layer structure 106 and partially embedded in the electrical insulating layer structure 108 made of different materials with different main surface interaction properties. Furthermore, the main surface 110 of the electrical insulating layer structure 106 is configured such that the suppression of attraction and adhesion on the main surface 110 is stronger than the suppression of attraction and adhesion on the opposite main surface 132 of the electrical insulating layer structure 106, and the suppression of attraction and adhesion on the main surface 110 is stronger than the suppression of attraction and adhesion on any main surface 134 of the other electrical insulating layer structures 108.

[0100] By according to Figure 2 This configuration allows for smaller pad size (D) and smaller pad spacing (d) on the back side of the component carrier 100. In particular, this can be achieved by using a low-Df dielectric material (e.g., low-Df ABF) on the EP layer, and by reducing the amount of work involved in palladium stripping.

[0101] For example, a hybrid low-Df ABF material can be used on the EP layer, such as a material having a Df value less than 0.0022, particularly a Df value in the range of 0.003 to 0.0022. Through exemplary embodiments, the metal-defined pad spacing (d) can reach 30 μm. The metal-defined pad size (D) can reach 77 μm. Furthermore, exemplary embodiments provide the possibility of removing a palladium stripping process with a large spacing, for example, a single palladium stripping process can be performed.

[0102] The lateral distance H between the sidewall of the protective structure 130 and the sidewall of the surface treatment layer 118 on the pad 150 can be less than 80 μm, for example, less than 60 μm. The vertical height h of the pad 150 can be less than 30 μm, for example, less than 15 μm. The vertical height b of the surface treatment layer 118 can be less than 15 μm, for example, less than 7 μm. The vertical distance L between the top surface of the protective structure 130 and the top surface of the surface treatment layer 118 can be less than 30 μm, for example, less than 21 μm.

[0103] Figures 3 to 8 A plan view of a component carrier 100 according to an exemplary embodiment of the present invention is shown. The number of gold particles is an indicator of the performance characteristics of dielectric resin (e.g., ABF) materials. Figures 3 to 8 The gold distribution shown conforms to... Figure 1 , Figure 10 and Figure 11 The ion deposition mechanism. Based on Figures 3 to 8 The gold test revealed three regions with different gold (or more generally, metal, since other seed layers and / or surface treatment materials are permissible) densities: a gold or metal-rich region 180, in which the density of metal or gold particles is the highest; a gold or metal intermediate region 182, in which the density of metal or gold particles is lower; and a gold or metal-poor region 184, in which metal or gold particles are only sporadically present and can be distinguished.

[0104] refer to Figure 3 ABFGL107 with low Df, 30 μm pitch and 2.0 m / min solder resist palladium stripper conveyor speed (POR and GXT31) have been used on the EP layer (which can be a layer under the solder resist).

[0105] refer to Figure 4 Low-Df ABF GL107 has been used on the EP layer with a 30μm pitch and a solder resist palladium stripper delivery speed of 2.0m / min (POR and GL107).

[0106] refer to Figure 5 ABF GL107 with low Df has been used on the EP layer, with a pitch of 30 μm and a solder resist palladium stripper delivery speed of 1.0 m / min (POR and GXT31).

[0107] refer to Figure 6 Low-Df ABF GL107 has been used on the EP layer with a 40μm pitch and a solder resist palladium stripper delivery speed of 1.0m / min (POR and GXT31).

[0108] refer to Figure 7 Low-Df ABF GL107 has been used on the EP layer with a 30μm pitch and a solder resist palladium stripper delivery speed of 1.0m / min (POR and GL107).

[0109] refer to Figure 8 Low-Df ABF GL107 has been used on the EP layer with a 40μm pitch and a solder resist palladium stripper delivery speed of 1.0m / min (POR and GL107).

[0110] The experiment shown concludes that ABF GL107 with a low Df value of less than 0.003 exhibits suitable performance in all metal-defined pad spacing conditions.

[0111] Figure 9 and Figure 10 Figures 200 and 210 show the presence of metal on the surface of the component carrier 100 according to an exemplary embodiment of the present invention.

[0112] refer to Figure 9 Figure 200 shows the physical dimensions on the horizontal axis 202. Positive charge carriers 202 and negative charge carriers 204 are plotted. Reference numeral 206 indicates a surface, reference numeral 207 indicates the Stern plane, and reference numeral 208 indicates the shear plane. The Stern layer 203 and the diffusion layer 205 are also shown.

[0113] refer to Figure 10 In the chart 210, the horizontal axis 212 represents distance or physical dimension, while the vertical axis 114 represents electric potential.

[0114] refer to Figure 9 , Figure 10 and Figure 1 The following will explain why the low-Df dielectric material of the electrical insulating layer structure 106 has advantageous properties for the design of metal-defined pads. In this case, the metal-defined design of pad 150 describes a configuration in which air flows laterally around pad 150, see [link to relevant documentation]. Figure 1Reference numeral 162 in the figures. This is the opposite of the following configuration: the solder resist type protective structure 130 is laterally stacked with the pad 150 to cover at least a portion of the sidewall (not shown) of the pad 150. During the manufacture of the metal-defined pad 150, the palladium seed used to form the pad 150 may also inadvertently act as a seed for the surface treatment section 118. This may lead to the accumulation of metal particles on the exposed portion of the main surface 110 of the outer electrical insulation layer structure 106, which can be suppressed by using a low-Df dielectric for the outer electrical insulation layer structure 106.

[0115] The ions have a defined size, and the center of the ion can only approach a surface within the ion's hydration radius. Furthermore, the ions are temporarily attached to the surface by electrostatic forces sufficient to overcome thermal agitation. Considering these configurations, the following phenomena may arise in exemplary embodiments that improve upon the aspect of hindering the accumulation of metal particles on the main surface 110: low-Df resins (such as ABF) can store more ions than dielectrics with higher Df values, thus preventing the diffusion or migration of charge to the main surface 110. Therefore, after the formation of the surface treatment layer 118 (especially ENEPIG), the adsorption of metals (especially palladium) by surface ions can be less. Consequently, the deposition of gold particles on the main surface 110 can also be less.

[0116] Typically, the charge in the dielectric material of the electrically insulating layer structure 106 moves toward the main surface 110 based on electromagnetic dynamics. Ultimately, such charge can generate surface charge.

[0117] However, Df is one of the main properties of dielectric materials and can affect dielectric loss because Df represents the ability to impede the movement of charge to the surface or to store charge (see [reference]). Figure 9 Charge on the main surface 110 can accumulate in a region, such as the region between the metal-defined pads 150.

[0118] Typically, palladium ions act as a catalyst in the electroless plating process, thus electroless plating of Pd... + This can enhance the adhesion between the dielectric material and the seed layer of the electrically insulating layer structure 106. Therefore, this may promote the deposition of metals such as nickel, copper, or gold on the dielectric surface or other metal surfaces. This catalytic activity may contribute to the formation of strong bonds between the seed layer and the dielectric layer, thus palladium ions can form strong chemical bonds with both the seed layer and the dielectric material. This bonding improves the overall adhesion and stability of the layer. Furthermore, the presence of palladium ions can activate the surface of the dielectric layer, making it more receptive to seed layer deposition. This activation process helps create a uniform and adherent metal layer. Pd +It can be attracted by the charge on the main surface 110 of the electrically insulating layer structure 106. If this occurs, it may be necessary to remove the remaining Pd afterwards. + .

[0119] During the ENEPIG process, Ní + and / or Au + With Pd + The reaction may cause over-plating of gold on the solder resist layer, thus potentially requiring or desiring palladium stripping. However, in the presence of fine patterns, Pd removal may also be difficult. + .

[0120] Advantageously, the low Df dielectric of the electrical insulating layer structure 106 can store more ions to prevent ion diffusion. Based on the above considerations, it can be concluded that using a low Df dielectric material for the outer electrical insulating layer structure 106 can suppress charge movement to the main surface 110 of the electrical insulating layer structure 106, thereby allowing for better charge storage in the material.

[0121] Figure 11 A manufacturing architecture for manufacturing a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0122] Figure 11 Additional options for suppressing the attraction and adhesion of metal ions and / or metal particles on the main surface are shown. According to this option, which can be combined with any of the options described above, the speed of the palladium resist stripping conveyor can be reduced. Figure 11 Multiple test condition combinations 220 are shown (test condition combinations 1 to 4 in the example shown). Furthermore, different palladium stripping delivery speeds are indicated by reference numeral 222 (1 m / mL for test condition combination 1, 1.3 m / mL for test condition combination 2, 1.6 m / mL for test condition combination 3, and 2.0 m / mL for test condition combination 4).

[0123] It should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "the" does not exclude multiple. Furthermore, elements described in association with different embodiments may be combined.

[0124] It should also be noted that the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

[0125] The implementation of this invention is not limited to the preferred embodiments shown in the figures and described above. On the contrary, even in fundamentally different embodiments, there may be various variations using the solutions shown and the principles of the invention.

Claims

1. A component carrier (100), the component carrier (100) comprising: A stack (102) comprising at least one electrically conductive layer structure (104) and a plurality of electrically insulating layer structures (106, 108), wherein at least a portion of at least one of the electrically conductive layer structures (104) is disposed on the main surface (110) of one of the plurality of electrically insulating layer structures (106, 108) and / or is disposed in the main surface (110) of one of the plurality of electrically insulating layer structures (106, 108); as well as A surface treatment layer (118) at least partially covers at least one exposed surface of the electrically conductive layer structure (104); The main surface (110) of one of the plurality of electrically insulating layer structures (106, 108) is configured to suppress the attraction and adhesion of metal ions and / or metal particles on the main surface (110).

2. The component carrier (100) according to claim 1, wherein, The main surface (110) is configured to suppress attraction and adhesion by setting one of the plurality of electrical insulating layer structures (106, 108) to a low Df material.

3. The component carrier (100) according to claim 1 or 2, wherein, The main surface (110) is configured to suppress attraction and adhesion by setting one of the plurality of electrically insulating layer structures (106, 108) to a material with a Df value less than 0.

022. In particular, the main surface (110) is configured to suppress attraction and adhesion by setting one of the plurality of electrically insulating layer structures (106, 108) to a material with a Df value less than 0.

018. More particularly, the main surface (110) is configured to suppress attraction and adhesion by setting one of the plurality of electrically insulating layer structures (106, 108) to a material with a Df value in the range of 0.002 to 0.

022.

4. The component carrier (100) according to any one of claims 1 to 3, wherein, The main surface (110) is configured to suppress attraction and adhesion by setting one of the plurality of electrical insulating layer structures (106, 108) to have a high content of filler particles (112), and / or wherein the main surface (110) is configured to suppress attraction and adhesion by setting one of the plurality of electrical insulating layer structures (106, 108) to have a content of filler particles (112) accounting for at least 70% of the total volume of the one of the plurality of electrical insulating layer structures (106, 108), and / or wherein the one of the plurality of electrical insulating layer structures (106, 108) includes filler particles (112) configured to promote suppression of attraction and adhesion at the main surface (110).

5. The component carrier (100) according to any one of claims 1 to 4, wherein, The main surface (110) is configured to suppress attraction and adhesion by setting the main surface (110) to have a low roughness Rz, and / or wherein the main surface (110) is configured to suppress attraction and adhesion by setting the main surface (110) to have a roughness Rz of less than 1000 nm.

6. The component carrier (100) according to any one of claims 1 to 5, wherein, The main surface (110) is configured to suppress attraction and adhesion by dissipating the charge carriers (202, 204) on the main surface (110). In particular, the main surface (110) is configured to suppress attraction and adhesion by setting the main surface (110) to be free of charge carriers (202, 204).

7. The component carrier (100) according to any one of claims 1 to 6, wherein, The main surface (110) is configured to suppress attraction and adhesion by making the main surface (110) hydrophobic.

8. The component carrier (100) according to any one of claims 1 to 7, wherein, The main surface (110) is configured to suppress attraction and adhesion by treating the main surface (110) to generate low van der Waals forces.

9. The component carrier (100) according to any one of claims 1 to 8, wherein, The metal ions and / or metal particles have at least one component of forming at least one of the electrically conductive layer structures (104) and / or at least one component of forming the surface treatment layer (118), particularly, the metal ions and / or metal particles have at least one component of forming at least one seed layer (114) of at least one of the electrically conductive layer structures (104) and / or at least one component of forming the surface treatment layer (118), wherein, in particular, the at least one component includes palladium.

10. The component carrier (100) according to any one of claims 1 to 9, wherein, The main surface (110) of one of the plurality of electrically insulating layer structures (106, 108) is configured such that the suppression of the attraction and adhesion of metal ions and / or metal particles on the main surface (110) is stronger than the suppression of the attraction and adhesion of metal ions and / or metal particles on another main surface (132) of the plurality of electrically insulating layer structures (106, 108), and / or the suppression of the attraction and adhesion of metal ions and / or metal particles on the main surface (110) is stronger than the suppression of the attraction and adhesion of metal ions and / or metal particles on the main surface (134) of the other electrically insulating layer structure (106, 108).

11. The component carrier (100) according to any one of claims 1 to 10, wherein, The material exposed in one of the plurality of electrical insulating layer structures (106, 108) that defines at least a portion of the main surface (110) is different from the material of the other electrical insulating layer structure (106, 108).

12. The component carrier (100) according to any one of claims 1 to 11, wherein, One of the electrical insulating layer structures (106, 108) defining the main surface (110) forms part of a redistribution structure (120) together with at least one of the electrical conductive layer structures (104), wherein, in particular, the redistribution structure (120) includes another electrical insulating layer structure in the electrical insulating layer structures (106, 108) that has a different material and / or different main surface interaction characteristics compared to the one electrical insulating layer structure defining the main surface (110) in the plurality of electrical insulating layer structures (106, 108).

13. The component carrier (100) according to any one of claims 1 to 12, wherein, The surface treatment layer (118) is in contact with the main surface (110).

14. The component carrier (100) according to any one of claims 1 to 13, wherein, At least one of the electrically conductive layer structures (104) includes at least two sub-parts (122, 124) arranged side by side, wherein a portion of the main surface (110) located between the different sub-parts (122, 124) defines a first region (126) of metallic material having the surface treatment layer (118), and / or wherein at least one of the electrically conductive layer structures (104) includes at least two sub-parts (122, 124) arranged side by side, wherein a portion of the main surface (110) located between the different sub-parts (122, 124) defines a second region (128) without metallic material.

15. The component carrier (100) according to claim 14, wherein, The second region (128) is arranged between the two first regions in the first region (126).

16. The component carrier (100) according to claim 14, wherein, The second region (128) has a larger planar extension than the first region (126).

17. The component carrier (100) according to claim 14, wherein, Each of the first region (126) and the second region (128) is covered by the protective structure (130).

18. The component carrier (100) according to claim 17, wherein, The protective structure (130) is the outermost insulating protective layer of the stack (102), and in particular, the protective structure (130) is a solder resist.

19. The component carrier (100) according to claim 14, wherein, The first region (126) and the second region (128) are configured such that electrical conduction is not possible between the two sub-parts (122, 124).

20. The component carrier (100) according to any one of claims 14 to 19, wherein, At least two of the said sub-parts (122, 124) include pads (150), wherein, in particular, the distance (d) between the pads (150) is less than 130 μm, and in particular, the distance (d) between the pads (150) is in the range of 30 μm to 70 μm, and / or wherein, Specifically, the diameter (D) of the pad (150) is less than 300 μm, and more specifically, the diameter (D) of the pad (150) is less than 100 μm.

21. A method for manufacturing a component carrier (100), wherein, The method includes: A stack (102) is provided, the stack (102) including at least one electrically conductive layer structure (104) and a plurality of electrically insulating layer structures (106, 108), wherein at least a portion of at least one of the electrically conductive layer structures (104) is disposed on the main surface (110) of one of the plurality of electrically insulating layer structures (106, 108) and / or is disposed in the main surface (110) of one of the plurality of electrically insulating layer structures (106, 108); At least a portion of the exposed surface of at least one of the electrically conductive layer structures (104) is covered by a surface treatment layer (118); and The main surface (110) of one of the plurality of electrically insulating layer structures (106, 108) is configured to suppress the attraction and adhesion of metal ions and / or metal particles on the main surface (110).

22. The method according to claim 21, wherein, The method includes removing metal ions and / or metal particles from at least a portion of the main surface (110), particularly, the method includes removing palladium ions and / or palladium particles from at least a portion of the main surface (110), particularly, the method includes stripping metal ions and / or metal particles from at least a portion of the main surface (110), particularly, the method includes stripping palladium ions and / or palladium particles from at least a portion of the main surface (110).

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