Component carrier and method for manufacturing a component carrier

Abstract

A component carrier and a method for manufacturing a component carrier are described. The component carrier comprises: a stack (101) comprising at least one electrically conductive layer structure (120) and a plurality of electrically insulating layer structures; a cavity (110) formed in the stack (101), the cavity being bounded by a bottom wall (111) and a side wall (112); wherein the bottom wall is partially bounded by a first main surface (106) of a first electrically insulating layer structure (102) of the plurality of electrically insulating layer structures; wherein the at least one electrically conductive layer structure is disposed in or on the first main surface; wherein the at least one electrically conductive layer structure comprises a first portion (121) exposed to the cavity and a second portion (122) covered by a second electrically insulating layer structure (108) of the plurality of electrically insulating layer structures; and wherein the first portion of the at least one electrically conductive layer structure comprises, in addition to the structure comprising the second portion, a cover electrically conductive layer structure (150).

Description

Technical Field

[0001] This invention relates to a component carrier having a stack and a cavity formed therein, the stack including at least one electrically conductive layer structure and a plurality of electrically insulating layer structures, the cavity being defined by a bottom wall and side walls, wherein the at least one electrically conductive layer structure includes a first portion exposed in the cavity and a second portion covered by a second electrically insulating layer structure of the plurality of electrically insulating layer structures, wherein the first portion of the at least one electrically conductive layer structure includes a covering electrically conductive layer structure. The invention also relates to a method of manufacturing the component carrier.

[0002] Therefore, the present invention can relate to the technical field of component carriers such as printed circuit boards or IC substrates, and the manufacture of such component carriers. Background Technology

[0003] Against the backdrop of increasingly sophisticated product functionality, miniaturization of component carriers containing one or more electronic components, and a growing number of electronic components to be mounted on component carriers such as printed circuit boards, increasingly robust array-shaped components or packages with multiple electronic components and numerous contacts or connections with decreasing spacing are being adopted. Simultaneously, the component carrier must be mechanically robust and electrically reliable to operate, even under harsh conditions. In particular, embedding and electrically connecting components within the cavities of the stacked components of the component carrier can be considered a challenge.

[0004] Figure 5 An example of a conventional circuit board 200 including a stack 201 is shown. Components 230 are embedded in corresponding cavities within the stack 201. Typically, in industry, components embedded in a stack are connected to a component carrier only via interconnects on one side. As shown on the right, component 230 is secured to the bottom of the cavity by an adhesive layer 251.

[0005] However, due to market trends towards high-performance computing and high-frequency applications, the single-sided interconnect between component carriers and components may be insufficient to meet the requirements of dense signal transmission. Therefore, double-sided interconnects between components and component carriers may be an effective technical solution to meet such requirements.

[0006] As shown on the left, resin 240 is disposed at the bottom of the cavity, and component 230 is placed on the resin 240. An electrical connection 250 is formed through the resin 240 to electrically contact an electrical pad located at the bottom of component 230. In this example, solder balls 270 are disposed between the electrical connection 250 and the electrical pad of component 230. To provide solderability, the upper surface of the electrical connection 250 is treated with electrolytic palladium / gold (Pd / Au) prior to cavity formation.

[0007] However, providing such treatment can be costly and cumbersome. For example, electrolytic Pd / Au can result in drawbacks in terms of elasticity, solderability, cost, and yield. Summary of the Invention

[0008] It may be necessary to provide cavities for component carriers, especially cavities for embedded components, in an efficient and reliable manner.

[0009] According to an exemplary embodiment of the present invention, a component carrier and a manufacturing method are described.

[0010] According to one aspect of the present invention, a component carrier (e.g., a printed circuit board, an IC substrate, an interposer, etc.) is described, the component carrier comprising:

[0011] i) A (multi-layer) stack, the (multi-layer) stack comprising at least one electrically conductive layer structure (e.g., trace, pad, via, etc.) and multiple electrically insulating layer structures (e.g., reinforced or unreinforced resin);

[0012] ii) A cavity formed in the stack and defined by a bottom wall and side walls (e.g., defined by at least one electrical insulating layer structure in the electrical insulating layer structure).

[0013] The bottom wall is partially defined by the first main surface of the first electrical insulating layer structure (arranged below the cavity) of the plurality of electrical insulating layer structures.

[0014] The at least one electrically conductive layer structure is disposed in or on the first main surface (e.g., by plating).

[0015] The at least one electrically conductive layer structure includes:

[0016] a) The first part, the first part is exposed in the cavity, and

[0017] b) The second part is covered by a second electrical insulating layer structure among the plurality of electrical insulating layer structures (in particular, the second electrical insulating layer structure at least partially defines the lateral walls of the cavity).

[0018] Furthermore, the first portion of the at least one electrically conductive layer structure includes a covering electrically conductive layer structure (e.g., a finish layer and / or other organic protective layer) (in addition to the structure including the second portion).

[0019] According to another aspect of the present invention, a method for manufacturing a component carrier is described, the method comprising:

[0020] i) Provide a stack comprising at least one electrically conductive layer structure and a plurality of electrically insulating layer structures;

[0021] ii) A cavity is formed in the stack, the cavity being defined by a bottom wall and side walls, wherein the bottom wall is partially defined by a first main surface of a first electrical insulating layer structure of the plurality of electrical insulating layer structures, and wherein at least one electrical conductive layer structure is disposed in or on the first main surface.

[0022] iii) Provide a cover (electrically conductive) layer structure (e.g., a surface treatment layer and / or an organic solder protective layer) on the at least one electrically conductive layer structure (particularly, after cavity formation) such that the at least one electrically conductive layer structure comprises:

[0023] The first part, exposed within the cavity, includes, in addition to the structure comprising the second part, a covering (electrically conductive) layer structure, and

[0024] The second part is covered by the second electrical insulation layer structure among the plurality of electrical insulation layer structures.

[0025] In the context of this document, the term "conductive layer structure" can specifically refer to any electrically conductive layer structure, such as a metallic (e.g., copper) layer structure. Such an electrically conductive layer structure may include at least one of a metallic structure, traces, pads, electrical connections, vias, terminals, foils, patterned layers / foils, or protrusions. In an embodiment, the electrically conductive layer structure is configured as a plurality of electrically conductive structures (in the same horizontal / planar layer) located on a first main surface. In an embodiment, a (isolated / separated) trace / pad layer is provided on the first main surface as an electrically conductive layer structure (e.g., by plating). In this example of a separated / isolated structure, free space (gap) may exist between the separated / isolated structures, thereby exposing the first main surface. At least one electrically conductive layer structure (structure of an electrically conductive layer junction) may be exposed at the bottom of the cavity. Furthermore, at least one electrically conductive layer structure (structure of an electrically conductive layer structure) may be covered by a (second) electrically insulating layer structure. In an embodiment, at least one exposed electrically conductive layer structure (the structure of the electrically conductive layer structure) may be referred to as the first part, and at least one electrically conductive layer structure (the structure of the electrically conductive layer structure) covered by (insulating material) may be referred to as the second part.

[0026] In the context of this document, the term "covering conductive layer structure" may specifically refer to any conductive layer structure suitable for covering the aforementioned conductive layer structure. Therefore, the covering conductive layer structure may include materials different from (or the same as) the conductive layer structure. In embodiments, the covering conductive layer structure covers the (upper) main surface and / or lateral surfaces of the conductive layer structure. In embodiments, the covering conductive layer structure covers only / exclusively the exposed conductive layer structure (the first portion of the conductive layer structure). In another embodiment, the covering conductive layer structure covers at least a portion of the conductive layer structure that is covered by (insulating material) (the second portion of the conductive layer structure); in other words, the covering conductive layer structure partially extends between the conductive layer structure (the second portion of the conductive layer structure) and the (second) electrically insulating layer structure.

[0027] In one embodiment, the conductive layer structure comprises structures / traces / pads, and each structure in the structure (the structure in the first part) is individually covered by a material covering the conductive layer structure. In another embodiment, the conductive layer structure is configured as a surface-treated section, for example, the conductive layer structure is configured as ENIG, ENEPIG, or ENIG-LP (consisting of a low-phosphorus electroless nickel plating layer and a subsequent immersion gold layer). In yet another embodiment, the conductive layer structure comprises two or more layers, for example, the conductive layer structure comprises a seed layer and a plating layer, and / or, the conductive layer structure comprises an intermediate layer and a protective layer. In a particular embodiment, specifically referring to the manufacturing method, a cover layer structure is used that can be (at least partially) organic, for example, the cover layer structure can be organic solder protection (OSP).

[0028] In one embodiment, the conductive overlay includes an IMC (intermetallic compound) layer. The IMC layer may include components of the conductive layer structure (e.g., copper) because the conductive material can migrate in a very small volume and merge with the surface treatment layer (overlay conductive layer structure). The IMC layer may include components of the component soldering or bonding structure (e.g., Sn) because the soldering material and the material in the surface treatment layer can react with each other and be incorporated into the IMC layer. The IMC layer may include a small amount of gold, or may not include gold, because gold is a very stable metal and gold will not migrate or merge into another layer. In another embodiment, the IMC layer may include a small amount / small volume of phosphorus.

[0029] In the context of this document, the term "primary surface" may specifically refer to a surface oriented along a plane parallel to the primary extension (planar extension, horizontal plane, xy) and perpendicular to the thickness direction (vertical direction, z). In embodiments, a component carrier may include two primary extension directions (length, width) in the horizontal direction and a vertical extension direction (thickness) in the vertical direction (the vertical extension direction is not a primary extension direction). In embodiments, such a primary surface of the component carrier may be an external surface. For example, an upper primary surface may be an upper external surface, and a lower primary surface may be an opposite lower external surface. In other embodiments, the layer structure of a stack may also include a primary surface. For example, a first electrical insulating layer structure may include (at least partially) an (upper) primary surface defining the bottom of a cavity.

[0030] In the context of this document, the term "component carrier" may specifically refer to any support structure capable of accommodating one or more components on and / or within a component carrier to provide mechanical support and / or electrical connection. In other words, a component carrier can be configured as a mechanical and / or electronic carrier for a component. Specifically, a component carrier can be one of the following: a printed circuit board (PCB), an organic interposer, and an integrated circuit (IC) substrate. A component carrier can also be a hybrid board combining different types of component carriers from the above-described types.

[0031] In the context of this document, the term "stack" may specifically refer to a flat or planar sheet-like body. For example, a stack can be a multilayer stack, and more particularly, a laminated or rolled multilayer stack. Such a laminate can be formed by joining multiple layers together by applying mechanical pressure and / or heat. Preferably, the multiple layers are arranged parallel to each other vertically. The stack may include electrically conductive layer structures and at least one electrically insulating layer structure.

[0032] In the context of this document, the term "layer structure" may specifically refer to a continuous layer, a patterned layer, or multiple discontinuous islands (discontinuous layers) within a common plane, and the "layer structure" may perform the functions of electrical conduction and / or electrical insulation. A layer structure may also include interconnect structures protruding from the planar surfaces of the layer structure.

[0033] According to an exemplary embodiment, the present invention can be based on the concept that a functional component carrier cavity can be provided in an efficient and reliable manner when a first portion of an electrically conductive layer structure is exposed at the bottom of the cavity and covered by a covering electrically conductive layer structure, while a second portion of the electrically conductive layer structure is not exposed but is covered by an electrically insulating layer structure (which at least partially defines the sidewalls of the cavity). This electrically conductive layer structure can be highly functional and robust, allowing multiple different components / applications to be placed into the cavity. The covering electrically conductive layer structure effectively protects the first portion and enables effective electrical contact with the component to be embedded. In particular, the covering electrically conductive layer structure can provide effective solderability (e.g., for additional solder material). The electrically insulating material surrounding the cavity effectively protects the second portion, thereby enabling electrical connections in the stack, and particularly, electrical connections with the component to be embedded.

[0034] Furthermore, the electrical insulating material surrounding the cavity can first fill the gaps between the exposed conductive layers, providing the advantage that the gaps can be completely filled without any voids. This ensures reliability and quality.

[0035] Conventional (comparison) Figure 5 In some cases, exposed electrical contacts within a cavity are isolated and unprotected or protected in a cumbersome manner (e.g., by Pd / Au, which can lead to defects in elasticity, solderability, cost, and yield). The inventors have now discovered that highly efficient and robust electrical connections can be achieved by covering the electrically conductive layer structure at the bottom of the cavity in two different ways: i) with an electrically insulating laminate that defines the cavity; and ii) a surface-treated layer to be configured as an inner layer within the cavity, thus fully utilizing mature and efficient component carrier technology. While a suitable surface-treated layer is conventionally applied only to the outermost surface of the laminate, it has now been found that a surface-treated portion can be effectively used inside the laminate, i.e., at the bottom of the cavity.

[0036] The advantages of this architecture include fewer manufacturing steps, less impact on yield loss (especially when forming a conductive overlay structure after cavity formation), improved solderability, and higher reliability. The design can be easily implemented in existing component carrier production lines, for example, when surface treatment processes for external stacked components already exist.

[0037] Exemplary Implementation

[0038] In one embodiment, the overlay conductive layer structure covers the main surface and / or lateral surface of the at least one conductive layer structure (at least one structure / trace of the at least one conductive layer structure in the first portion). This provides the advantage that the conductive layer structure is protected (e.g., to prevent alteration / corrosion / oxidation) and can still be effectively electrically connected. Furthermore, solderability / bonding performance / signal integrity can be improved. By covering the main surface (top surface) and lateral surfaces, protection / functionalization can be particularly effective. In another embodiment, the conductive layer structure in the first portion includes multiple structures (e.g., traces, pads, vias, protrusions, etc.), one or each of which is covered by the overlay conductive layer structure.

[0039] In general, the protective layer structure not only safeguards the conductive layers used in the final product but also protects the conductive layers of semi-finished products, as there is always a queuing time (waiting time) for semi-finished products on the production line before welding. Without the protective conductive layer structure, the exposed conductive layers may be susceptible to oxidation and corrosion, potentially leading to a decline in overall product quality and reliability issues. In such cases, the entire product may be scrapped because it is irreparable, resulting in significant production losses and high costs associated with mass production.

[0040] In this implementation, the conductive cover structure covers the structure of the first portion that is not covered by the first main surface (lower surface) (upper main surface, lateral surfaces). In other words, the cover layer covers all exposed portions of the first electrical insulation structure except for the surface on which the first portion is disposed. This provides the advantage that the conductive cover structure within the cavity is well protected and reliable because it not only prevents corrosion and oxidation of the first portion but also utilizes a very robust IMC layer to provide a good soldering surface for bonding structures (e.g., solder balls) to connect with the component.

[0041] In this implementation, the conductive layer structure comprises at least two layers, and more particularly, exactly two layers. By providing two or more layers, different properties / advantages can be provided, which can advantageously synergize and / or complement each other.

[0042] In one embodiment, the (covering) electrically conductive layer structure includes a seed layer and a plating layer. The seed layer can thus be used to achieve an efficient plating process. This seed layer can be provided in a non-electrical manner; for example, it can be provided by physical / chemical vapor deposition; for example, Ti / Cu can be used to provide the seed layer. The plating can, for example, be done using copper. In another embodiment, a nickel layer can be plated. Typically, the plating layer is (significantly) thicker than the seed layer.

[0043] In embodiments, the overlay conductive layer structure includes an intermediate layer (specifically, the intermediate layer includes nickel deposited on the conductive layer structure), and / or may include an additional layer located on the intermediate layer (the additional layer includes palladium deposited on the nickel to protect the nickel layer and configured as a catalyst for protective layer deposition) and / or includes a protective layer (the protective layer includes gold that can be deposited on the palladium or nickel layer). The protective layer can provide effective shielding to prevent alteration and / or oxidation and / or corrosion. Because protective materials such as gold can be expensive, the protective layer can be formed very thin (e.g., less than 100 nm). The intermediate layer (e.g., nickel) can provide sufficient stability / adhesion for the protective layer. In embodiments, the overlay conductive layer structure can be configured as an ENIG layer, or an ENIPIG or ENEPIG layer, wherein the intermediate layer can correspond to unplated nickel, and the protective layer can correspond to immersion gold, and / or the additional layer can correspond to unplated palladium or immersion palladium. ENIG can be low-phosphorus ENIG, which includes a low phosphorus content, and the low phosphorus content can provide good solderability and conductivity at low cost. Therefore, proven and reliable materials (typically used on the outer surface) can be effectively used within cavities for component carrier connections. In embodiments, a protective layer is disposed on the side opposite to the seed layer, and specifically, an intermediate layer is located between the protective layer and the seed layer.

[0044] In this implementation, the protective layer faces the interior space of the cavity; specifically, the protective layer is exposed within the interior space of the cavity. In other words, the protective layer can be the outermost / outermost layer covering the electrically conductive layer structure. Therefore, it can provide effective and reliable protection for other layers covering the electrically conductive layer structure and the electrically conductive layer structure itself, because the protective layer can be made of a very stable material and can have good conductivity.

[0045] In this implementation, the intermediate layer is thicker than the protective layer. This measure saves on cost and effort, as the material of the protective layer (e.g., gold) can be very expensive. Furthermore, the intermediate layer prevents the conductive layer from migrating to the surface, ensuring that the conductive layer does not react with the welding material and affect the weld quality, thus allowing the intermediate layer to provide reliable support for the protective function.

[0046] In implementations, after soldering with another metallic element such as tin, the overlay conductive layer may become an IMC layer containing Sn (IMC layers primarily consist of Ni and Sn; gold and / or palladium may even be present, as both materials are present only in very low amounts, e.g., layers smaller than 50 nm each). The interlayer can react with the solder material to form a stable IMC layer that exhibits good adhesion without cracking. The interlayer not only prevents copper migration during product manufacturing and provides a mechanically stable surface for soldering, but also influences solder reliability, corrosion resistance, and long-term signal integrity.

[0047] In examples (e.g., ENIG), nickel can be used as a barrier and adhesion layer between the metal (copper) and the gold layer. The nickel layer can act as a diffusion barrier to prevent copper from diffusing into the next layer or diffusing with the next layer, and can also act as an antioxidant to prevent copper from being oxidized; thus ensuring long-term solderability and the integrity / conductivity of the copper. Furthermore, the nickel layer can act as a stabilizing base for the gold layer, thus ensuring a smooth and uniform surface (adhesion). Nickel is mechanically more stable and can support strong weld joints. In embodiments, the component carrier preform is immersed in a nickel-phosphorus (Ni-P) plating bath to provide electroless nickel plating. In embodiments, gold is generally a very stable element and does not migrate or react with other metals. Gold can maintain good protection for the underlying layers. Nickel can be used to prevent copper migration or to extend to the outside and fuse with the NiSn IMC layer.

[0048] In this embodiment, no additional layer is disposed between the intermediate layer and the protective layer. In this embodiment, no additional layer is disposed between the electrically conductive layer structure of the first portion and the intermediate layer. These embodiments can describe a double-layer covered electrically conductive layer structure, wherein the intermediate layer is disposed directly on the first portion, and the protective layer is disposed directly on the intermediate layer. By providing only these layers, cost / workload can be saved, while efficiency can be high.

[0049] In one embodiment, the conductive layer structure defines a foot structure at the bottom wall of the cavity; specifically, the intermediate layer defines a foot structure at the bottom wall of the cavity, and specifically, this foot structure is a nickel foot. This foot-like structure (protrusion) can provide a footprint for the intermediate (nickel) layer during the manufacturing process. For example, the conductive layer structure can be immersed in a nickel bath to deposit an electroless nickel layer. The nickel material can flow around the sidewalls of the conductive layer structure and remain as a residue at the bottom of said sidewalls.

[0050] In this embodiment, the foot structure is disposed at the junction of the first main surface and the (covering) conductive layer structure. Therefore, the foot structure can provide a larger contact surface with the first main surface, thereby increasing the stability of the covering conductive layer structure, as well as the adhesion between the covering conductive layer structure, the conductive layer structure, and the first main surface. Thus, a foot of a certain height (less than 2 μm) can provide anchoring points for adhesion to other layers.

[0051] In one embodiment, the bottom wall of the cavity is defined by a first portion of the at least one electrically conductive layer structure and an exposed portion of the first main surface of the first electrically insulating layer structure. The first main surface may be the upper / outer main surface of a second electrically insulating layer structure located below the cavity. The electrically conductive layer structure may be directly disposed on the first electrically insulating layer structure. Therefore, no additional materials / means are required to define the bottom wall of the cavity. In another embodiment, the portion covering the electrically conductive layer structure may also define the bottom wall; for example, the portion covering the electrically conductive layer structure may also define the bottom wall via a foot structure.

[0052] In this implementation, the component is designed so that, after being embedded in the cavity and interconnected with the component carrier inside the cavity, it can be directly connected to the component carrier on both sides. Therefore, the direct connection between the component and the component carrier achieved through the interconnection structure provides a short electrical signal transmission path, thereby improving signal integrity and reducing signal loss; simultaneously, it increases the transmission speed between the component and the component carrier, which is advantageous for high-performance computing applications such as AI servers.

[0053] In one embodiment, the sidewalls of the cavity are laterally defined by at least one layer structure of the stack, preferably by multiple layer structures of the stack. In another embodiment, at least one additional electrically conductive layer structure and / or a second electrically insulating layer structure is in direct contact with the first main surface (of the first electrically insulating layer structure). In another embodiment, the sidewalls are at least partially defined by a second electrically insulating layer structure of the multiple electrically insulating layer structures. In other words, the cavity can be formed in exactly one layer structure of the stack, or it can be formed in two or more layer structures (e.g., a stack). In one example, the cavity is formed in exactly one electrically insulating layer structure. In another example, electrically conductive layer structures and electrically insulating layer structures (alternating) can form the sidewalls of the cavity. This can increase design flexibility and enable many different applications.

[0054] In one embodiment, an additional electrically conductive layer structure is disposed on the surface of one of the plurality of electrically insulating layer structures, specifically, the additional electrically conductive layer structure is disposed on the main surface of one of the plurality of electrically insulating layer structures. In another embodiment, the additional electrically conductive layer structure at least partially defines a sidewall, or the additional electrically conductive layer structure is disposed below the cavity. In another embodiment, the additional electrically conductive layer structure includes a separate covering electrically conductive layer structure different from the covering electrically conductive layer structure located on the first portion. In another embodiment, the additional electrically conductive layer structure may not have a covering electrically conductive layer structure, because the additional electrically conductive layer structure may only be configured as a laser stopping layer and the component may not be connected to the additional electrically conductive layer structure.

[0055] In one embodiment, the additional (electrically conductive) layer structure is the outermost (electrically conductive) layer structure of the stack. In another embodiment, the outermost electrically conductive layer structure is located at the opening side of the cavity. In another embodiment, this additional layer structure is the outermost layer, and for example, it is at least one of a solder resist portion, a surface treatment portion, and an OSP portion. In yet another embodiment, this additional layer structure is at least partially covered by an additional cover (electrically conductive) layer structure, for example, the additional cover (electrically conductive) layer structure includes a surface treatment portion and / or an OSP portion. In another embodiment, the additional cover layer structure may be similar to or different from the cover electrically conductive layer structure.

[0056] In one embodiment, the additional conductive layer structure includes via connections and / or pads / traces. In another embodiment, the additional conductive layer structure is at least partially disposed within the solder mask (extending at least partially through the solder mask (e.g., the additional layer structure)). In yet another embodiment, an additional cover (conductive) layer structure is disposed on the via connections and / or pads / traces, thereby providing effective protection and / or improving solderability for exposed electrical connections. Therefore, components with high-performance computing capabilities can be combined with the additional conductive layer structure with good solder quality, and a final IC package with good reliability and quality can be produced.

[0057] In one embodiment, the additional cover (electrically conductive) layer structure includes a surface treatment portion, for example, the additional cover (electrically conductive) layer structure includes ENIG or ENEPIG. In another embodiment, the cover electrically conductive layer structure and the additional cover electrically conductive layer structure may be similar or different. This provides the advantage that established surface treatment technologies can be applied to both the outer surface of the stack and the internal cavities of the stack.

[0058] In another embodiment, the additional cover layer structure includes or is composed of an organic layer structure, such as an organic solder protectant (OSP) or an organic solder protectant (OSP). This cover material may be different from or the same as the electrically conductive cover material in the cavity and can improve solderability.

[0059] In this implementation, considering that the conductive cover structure is embedded in the stack of the component carrier, after the final product is assembled, the conductive cover structure is not exposed to the environment and is not affected by air, thus allowing the lower-cost ENIG or OSP to be sufficient to provide a protective cover. However, for additional cover structures on the outer surface of the stack, these additional cover structures are exposed to the environment and may require further protection; therefore, ENEPIG or ENIPIG, which includes additional palladium metal at a higher cost, may be required.

[0060] In an embodiment, the at least one electrically conductive layer structure located in or on the first main surface includes an edge portion positioned through the sidewall of the cavity, specifically such that a first sub-part of the edge portion is exposed within the cavity, and a second sub-part of the edge portion is not exposed within the cavity and is embedded in the stack (specifically embedded in the second electrically insulating layer structure). The edge portion may refer to an area where a portion (the second portion) of the structure / trace of the electrically conductive layer structure is covered by an electrically insulating material, while another portion (the first portion) is not. Therefore, the distinction between the first and second portions can also apply to a single structure / trace. Partial embedding of the electrically conductive layer structure can increase stability.

[0061] In one implementation, the first sub-part can be configured as a laser stop layer to prevent laser energy from damaging the dielectric layer located at the bottom of the cavity; the second sub-part can be an extension of the first sub-part. Therefore, during etching, the two portions remaining at the edge can also leave an undercut between the sidewall and the bottom wall, which, being too small to be filled, can be cased / sealed during encapsulation.

[0062] In one embodiment, the first sub-part includes a covering conductive layer structure. In another embodiment, the second sub-part does not include a covering conductive layer structure. In yet another embodiment, the second sub-part includes a portion of the covering conductive layer structure. In one embodiment, the covering conductive structure partially extends beyond the sidewall of the cavity. In one embodiment, the covering conductive structure is partially embedded in and / or covered by at least one electrically insulating layer structure of the stack. Corresponding embodiments include, for example, in... Figure 7A and Figure 7B As shown in the image.

[0063] In one embodiment, the electrically insulating layer structure located on the sidewall of the cavity can define a clear division between the first sub-part and the second sub-part, wherein the covering conductive layer structure is not located in the sidewall. In another embodiment, a portion of the covering conductive layer structure extends into the sidewall, such that the first sub-part partially extends into and is covered by the sidewall. If the covering layer extends into the sidewall, it can increase the protective function.

[0064] In an embodiment, the conductive layer structure and / or the first electrical insulating layer structure includes a low-phosphorus material / surface, for example, the conductive layer structure and / or the first electrical insulating layer structure includes an ENIG with low phosphorus in an electroless nickel plating layer. The low-phosphorus component can diffuse into the IMC layer as nickel and tin react. Therefore, low phosphorus can be retained on the top surface of the conductive layer and partially on the sidewalls of the conductive layer. Therefore, solderability can be improved, particularly due to at least one of better wettability, reduced oxidation, and reduced brittleness. Furthermore, the low phosphorus content can increase conductivity and resistance to thermal fatigue (components embedded in cavities of stacked components may generate significant amounts of heat without a channel for dissipation), thereby improving the reliability / lifespan and functionality of the component carrier.

[0065] In this implementation, the conductive layer structure includes ENIG or ENEPIG. ENIG or ENEPIG are examples of mature and reliable surface treatments. In this implementation, the conductive layer structure is (substantially) palladium-free (e.g., in the case of ENIG). Palladium (e.g., Pd / Au) can be expensive and cumbersome to handle during manufacturing (see above). Using a mature surface treatment process (e.g., ENIG) can save costs / workload and improve efficiency.

[0066] In one embodiment, the component carrier further includes additional material on the upper surface of the overlay conductive layer structure. This additional material improves the electrical connection between the stack (the conductive layer structure with the overlay conductive layer structure) and the component pads. In another embodiment, the additional material is solder material, specifically solder bumps. With the solder bumps attached to the overlay conductive layer, soldering can be performed in reflow. Then, due to a suitable surface treatment process performed at a high temperature on the underside of the solder bumps, an IMC layer with good bonding properties can be formed by utilizing the reaction between the nickel and tin of the solder bumps. Therefore, a good foundation can be provided for the connection between the component and the soldered structure.

[0067] In implementations, the additional material may include solder, for example, solder bumps / balls (e.g., made of tin or a tin-based alloy). The additional material can form a conductive bridge between two electrical contacts, ensuring a reliable electrical connection. The additional material can provide a low-resistance path for current flow, which is crucial for electronic performance. The additional material can create a strong mechanical attachment between components (e.g., in FCBGA: Flip Chip Ball Grid Array (BGA)). The additional material can prevent movement and maintain contact, even under pressure or vibration. The additional material can also act as a buffer for thermal expansion, absorbing mechanical stress and preventing cracking of the solder joint. The additional material can melt at high temperatures, and surface tension can pull the components to perfect alignment with the pads. In implementations, the solder joint can transfer heat from components (e.g., chips, processors) to the PCB, thus aiding in thermal management. In another implementation, the additional material can provide a protective layer that prevents oxidation of the underlying metal, ensuring long-term reliability. Because of the well-defined IMC described earlier formed on the bond surface of the protrusion and at the electrically conductive layer covering the component carrier, the component carrier can bond to the component in a very good manner without peeling or cracking.

[0068] In some embodiments, additional material is disposed only on the upper surface. In others, the lateral surfaces of the at least one electrically conductive layer structure in the first portion and the corresponding covering electrically conductive layer structure have no additional material. In these embodiments, additional material may be disposed on the main / upper surface, while, in particular, the lateral surfaces remain untouched. This saves material costs because additional material is unnecessary on the lateral surfaces (especially those already protected by the covering electrically conductive layer structure).

[0069] In one embodiment, the additional material incorporated in conjunction with the conductive overlay structure may include phosphorus. In another embodiment, the additional material may have a non-constant thickness (e.g., a spherical or protruding shape). In yet another embodiment, phosphorus may improve the properties of the additional material / welding material, for example, by reducing surface tension, minimizing oxidation, and enhancing mechanical properties.

[0070] In one embodiment, the component carrier further includes a third electrically insulating layer structure disposed within the cavity on at least one electrically conductive layer structure of the first portion and / or on an exposed portion of the first main surface. This provides the advantage of effectively protecting delicate electrical contacts. The third electrically insulating layer structure can be used as an embedding / encapsulation material for embedding the electrically conductive layer structure (and covering the electrically conductive layer structure). The third electrically insulating layer structure can also cover the exposed first main surface. In another embodiment, the third electrically insulating layer structure can also encapsulate additional material. In yet another embodiment, the third electrically insulating layer structure can (at least partially) embed / encapsulate (electrically connected) components. In yet another embodiment, the third electrically insulating layer structure can partially or completely fill the cavity.

[0071] In an embodiment, the third electrical insulating layer structure includes a different composition and / or a different structure than another electrical insulating layer structure among the plurality of electrical insulating layer structures. For example, the third electrical insulating layer structure may be optimized for encapsulation, for example, by using a resin without filler particles so that the resin flows better around the component to be embedded.

[0072] In this embodiment, the third electrical insulating layer structure is disposed only between the structures (i.e., gaps) of the first portion. In this embodiment, the third electrical insulating layer structure is disposed on the exposed portion of the first main surface. Therefore, the free space (the location where the first main surface is exposed) between the structures / traces of the first portion can be filled first in an efficient and reliable manner. This improves stability and performance. Furthermore, filling the gaps first ensures that they are completely filled without voids before the component is inserted.

[0073] In a particular embodiment, the component may include material for forming a third electrically insulating layer structure when the component is placed in the cavity. The component may have a membrane attached to the side that connects to the electrically conductive layer structure located in the cavity. When the component is placed in the cavity and aligned with the electrically conductive layer structure, thermocompression bonding combines the component with a component carrier within the cavity; simultaneously, thermocompression bonding also melts the membrane attached to the component. The liquid then flows into and fills the gap. After bonding, the gap is also filled. This technique offers the advantages that gap filling and component embedding are accomplished efficiently and with high quality.

[0074] In this embodiment, at least a portion of the first part (the structure of the first part) is defined as an electrical contact portion. In particular, at least a portion of the first part (the structure of the first part) is defined as at least one of a pad, a terminal, a trace, etc. Therefore, the electrical contact portion of the first part can be used for direct electrical connection to components located in the cavity.

[0075] In one embodiment, the component carrier includes a component connected to the at least one electrically conductive layer structure. Specifically, the component is electrically connected to at least one electrical contact of a first portion (covered by the electrically conductive layer structure). The component can be directly coupled to the electrically conductive layer structure. Direct connection between the component and the component carrier, achieved through an interconnect structure, can provide a short electrical signal transmission path, thereby improving signal integrity and reducing signal loss; simultaneously, it can increase the transmission speed between the component and the component carrier, which is advantageous for high-performance computing applications such as AI servers.

[0076] In this embodiment, additional material is disposed between the electrical contacts of the component and the electrical contacts of the stack (the additional material may be disposed on the component carrier, or on the component, or on both elements). Therefore, since the additional material provides a good interface between the component carrier and the component, efficient and reliable electrical connections within the cavity can be achieved.

[0077] In this implementation, the components are configured as bridging elements. This provides the advantage that surface-mounted components can be electrically connected via bridging elements. Therefore, critical functional components can be efficiently embedded within the stack. Consequently, the signal transmission or communication paths between components within the package can be significantly reduced, and the electrical integrity of the entire package can be improved. Furthermore, the bridging element can have a high-density and very fine wire structure, thereby reducing the density and width / space of the component carrier in which the bridging element will be embedded. The bridging element can be made of silicon or glass, which, compared to organic materials used in component carriers, offers advantages in achieving high-density and fine wire structures as well as very good electrical properties, thus enabling the bridging element to increase the yield of high-density and fine-wire structure packages. Therefore, this bridging element may be well-suited for high-performance computing.

[0078] In the context of this document, the term "bridging element" may specifically refer to any element that can be used as an electrical interconnect between (active / passive) components, particularly electrical / electronic components. In examples, a bridging element may require at least two (exposed) electrically conductive terminals to connect to components respectively. In more complex examples, a bridging element may include multiple terminals for connecting two or more components (to each other). The electrically conductive terminals (preferably exposed on the same main surface (top main surface) of the bridging element) can be interconnected via electrical interconnects arranged within the bridging element.

[0079] A bridging element can specifically refer to a component configured to provide electrical interconnections. A bridging element may include multiple high-density electrical conductive structures configured to establish an electrical conductive connection between components to be mounted on a component carrier and / or mounted on the upper side of an interposer. The bridging element may be made of organic materials or inorganic materials such as silicon, ceramics, glass, or other inorganic materials. The bridging element can have a high-density and very fine wire structure, thus reducing the density and width / space of the component carrier in which it will be embedded. In embodiments, the bridging element is made of silicon or glass, which has significant advantages over organic materials used in component carriers in achieving a high-density and fine wire structure and very good electrical performance. Therefore, when viewed in a (specific) cross-section of the bridging element, the electrical conductive terminals and electrical interconnections can be arranged in a "U" shape. In particular, the bridging element may include multiple "U" shapes, wherein a larger "U" surrounds a smaller "U". (Organic or inorganic) bridging elements may include additional structures that have functions such as resistance measurement, grounding, and heat dissipation in addition to interconnection between components.

[0080] In one embodiment, the component carrier further includes an encapsulation material for encapsulating the component. In another embodiment, the encapsulation material is in contact with the third electrically insulating layer structure. In yet another embodiment, the encapsulation material (at least partially) comprises the third electrically insulating layer structure. Encapsulation of the electrical contacts and / or components can improve the stability and reliability of the stacked component's function. The encapsulation material can be the same material as the first and / or second electrically insulating layer structures to directly encapsulate the cavity and the gap between the electrically conductive layer structures located on the first surface within the cavity. This provides the advantage that encapsulation can be efficiently completed in a single step, together with the formation of the second electrically insulating layer structure.

[0081] In an embodiment, forming a cavity includes at least one of the following features: i) partially covering the at least one electrically conductive layer structure with a release layer; ii) providing at least a second electrically insulating layer structure on the release layer and / or on a first main surface of the first electrically insulating layer structure; iii) removing a portion of the at least second electrically insulating layer structure located on the release layer to form a cavity. In an embodiment, the method further includes removing the release layer (subsequently). This embodiment provides an efficient and reliable technique for providing a cavity with an exposed electrically conductive layer structure (first portion). The release layer can define which portion of the electrically conductive layer structure will be the first portion and which portion will be the second portion. The second portion may be a portion of the second electrically insulating layer structure that has not been removed, while the first portion may be a portion of the second electrically insulating layer structure that has been removed. To separate the portion to be removed, the second electrically insulating layer structure can be cut, for example, by drilling, particularly by laser drilling. The drilling location can further define the locations where the first and second portions will be positioned. The drilling location can be defined by the lateral edge of the release layer (e.g., release ink).

[0082] In one embodiment, the method further includes forming a covering conductive layer structure on the exposed electrically conductive layer structure after cavity formation. In another embodiment, the covering conductive layer structure is formed before the cavity is formed in the second electrically insulating layer structure. Depending on the desired application, one of these methods may be preferred. The first case may require fewer process steps.

[0083] In one embodiment, the method further includes providing a third electrically insulating layer structure and / or encapsulating material in the free space between the structures / traces of the first portion of the at least one electrically conductive layer structure and / or on the exposed portion of the first main surface. This embedding of the electrically conductive structure enhances performance and stability.

[0084] In an exemplary embodiment, the embedded component has a resin film (a type of resin) attached to the surface of the component, and the resin melts when the component is bonded to an exposed pad in the cavity via a thermosetting bonding process. The (partially) melted resin then flows into the gap, thereby filling and encapsulating the electrically conductive layer structure and the first primary surface. This process allows for a particularly efficient distribution of the encapsulation material.

[0085] In an exemplary embodiment, components are first arranged in the cavity, and then a dielectric material is laminated to encapsulate the entire free space, which includes gaps between the pads. Therefore, a third electrically insulating layer structure, as the encapsulation material, can be formed simultaneously by laminating it onto the surface of the cavity's sidewalls.

[0086] In one embodiment, the method further includes placing the component into the cavity and onto the covering conductive layer structure, wherein, in particular, an additional material is placed between the component and the covering conductive layer structure. This allows for effective embedding and electrical connection. In another embodiment, the method further includes filling the cavity with an encapsulation material, thereby encapsulating the component within the cavity. The component (and the electrical connection) can be well protected through this encapsulation.

[0087] In one implementation, the method includes covering an electrically conductive layer structure with a capping layer structure. In one example, the capping layer structure is a structure that covers the electrically conductive layer structure. In another example, the capping layer structure includes an organic material, such as organic solder protectant (OSP), or ENIG, ENIPIG, or ENEPIG. The material may be present only during the manufacturing process and not in the final component carrier product.

[0088] In this implementation, the electrical insulation layer structure covering the second portion differs from the plurality of electrical insulation layer structures. For example, the electrical insulation layer structure covering the second portion may comprise a different material and / or a different thickness compared to one or more other electrical insulation layer structures of the stack. If the electrical insulation layer structure covering the second portion is thicker and / or more robust (e.g., configured as a reinforced layer structure and / or core layer), the cavity for the component can be formed more efficiently and reliably.

[0089] In this embodiment, the electrically conductive layer structure defines sidewalls at the edge region located between the sidewalls and the bottom wall (of the cavity). This design can serve as a laser stop layer during cavity formation, thereby preventing laser energy from damaging the main surface of the first electrically insulating layer structure. Simultaneously, this design allows for the creation of an undercut between the sidewalls and the bottom wall during etching, which, since the undercut may be too small to be filled, can then be sealed (sealed, encapsulated) during packaging.

[0090] In one embodiment, the sidewalls of the cavity are laterally defined by a second portion of a second electrically insulating layer structure and an electrically conductive layer structure. The second portion of the electrically conductive layer structure is embedded in (covered by) the electrically insulating material of the second electrically insulating layer structure, and thus the second portion of the electrically conductive layer structure also defines a portion of the sidewalls of the cavity.

[0091] In one embodiment, the sidewalls of the cavity are also laterally bounded by (on top of the second portion of the conductive layer structure) the boundary of the conductive layer structure (besides the second electrically insulating layer structure and / or the second portion of the conductive layer structure). In this embodiment, the portion of the conductive layer structure covering the conductive layer structure extends vertically along the sidewall (see contrast). Figure 7BThis defines the sidewall portion of the cavity.

[0092] In one embodiment, the component carrier is configured as one of a printed circuit board, a substrate (particularly an IC substrate), and an interposer.

[0093] In the context of this application, the term "printed circuit board (PCB)" may specifically refer to a plate-shaped component carrier formed by laminating multiple electrically conductive layer structures with multiple electrically insulating layer structures, for example, by applying pressure and / or by supplying heat. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may include resin and / or glass fiber, so-called prepreg, or FR4 material. The various electrically conductive layer structures can be connected to each other in a desired manner by forming holes through the laminate, for example, by laser drilling or mechanical drilling, and by partially or completely filling these holes with an electrically conductive material (particularly copper), thereby forming vias or any other through-hole connections. The filled holes connect the entire stack (i.e., through-hole connections extending through multiple layers or the entire stack), or the filled holes connect at least two electrically conductive layers, i.e., so-called vias. Similarly, optical interconnects may be formed through the various layers of the stack to receive electro-optical circuit boards (EOCBs). Printed circuit boards (PCBs) are typically configured to house one or more components on one or both opposite surfaces of a board-shaped PCB. The one or more components can be soldered to their respective main surfaces. The dielectric portions of the PCB may include resin with reinforcing fibers (e.g., glass fiber).

[0094] In the context of this application, the term "substrate" can specifically refer to a small component carrier, particularly an IC substrate. An IC substrate can be a relatively small component carrier relative to a PCB, on which one or more components can be mounted, and which can serve as a connection medium between one or more chips and another PCB. For example, an IC substrate can have approximately the same size as the components (particularly electronic components) to be mounted on it (e.g., in the case of chip-scale packages (CSP)). More specifically, an IC substrate can be understood as a carrier for electrical connections or electrical networks, and a component carrier with a relatively high density of lateral and / or vertical connections, comparable to a printed circuit board (PCB). Lateral connections are, for example, conductive paths, while vertical connections can be, for example, drilled holes. These lateral and / or vertical connections can be particularly arranged within the IC substrate and can be used to provide electrical, thermal, and / or mechanical connections between accommodated or unaccommodated components (e.g., bare wafers), particularly IC chips, and printed circuit boards or intermediate printed circuit boards.

[0095] In the context of this application, the term "substrate" is particularly advantageous for electrical connectivity and / or heat dissipation and / or providing mechanical strength. Therefore, the term "substrate" is specifically used as a synonym for "IC substrate" in the context of this application. It must be noted that the term "substrate" should not be confused with the term "base," as "base" is typically used in a wafer context, where it generally refers to the substrate material used in wafer fabrication as the basic material for constructing devices or circuits and forming the foundational layer supporting the electronic or photonic structures integrated into the wafer. This is not the meaning of "substrate" in the context of this application.

[0096] The substrate or interlayer may include or be composed of at least one of the following: glass; silicon (Si) and / or photoimageable or dry-etchable organic materials, such as epoxy-based stacked materials (e.g., epoxy-based stacked films); or polymer compounds (polymer compounds may or may not include photosensitive and / or thermosensitive molecules), such as polyimide or polybenzoxazole.

[0097] In embodiments, the at least one electrically insulating layer structure comprises at least one of the following: resins or polymers, such as epoxy resins, cyanate ester resins, benzocyclobutene resins, melamine derivatives, poly(p-phenylenebenzodioxazole) (PBO), bismaleimide-triazine resins, polyphenylene derivatives (e.g., based on polyphenylene ether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymers (LCP), polytetrafluoroethylene (PTFE), bisbenzocyclobutene (BCB), and / or combinations thereof. Reinforcing structures, such as meshes, fibers, spheres, or other types of filler particles made of glass (multilayer glass), may also be used to form the composite. The semi-cured resin combined with the reinforcing agent, such as fibers impregnated with the aforementioned resins, is called a prepreg. These prepregs are typically named according to their properties, such as FR4 or FR5, which describe their flame-retardant properties. While prepregs, particularly FR4, are generally preferred for rigid PCBs, other materials, especially epoxy-based stacked materials (e.g., stacked films) or photosensitive dielectrics, can also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate resins are preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, very low, or ultra-low DK materials can be used as electrical insulation structures in component carriers.

[0098] In embodiments, the at least one electrically conductive layer structure comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium, tungsten, titanium, and magnesium. Although copper is generally preferred, other materials or coating variations thereof, particularly those coated with superconducting materials or conductive polymers, are also possible, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT).

[0099] At least one component (particularly an embedded component) that can be surface-mounted on and / or embedded in a component carrier can be selected from at least one of the following: non-electrically conductive inlays, electrically conductive inlays (e.g., metallic inlays, preferably copper or aluminum), heat transfer units (e.g., heat pipes), optical guiding elements (e.g., optical waveguides or optical conductor connectors), electronic components, or combinations thereof. The inlay can be, for example, a metal block (IMS-inlay) with or without an insulating material coating, which can be surface-mounted to facilitate heat dissipation. Suitable materials are defined by their thermal conductivity, which should be at least 2 W / mK. Such materials are typically based on, but not limited to, metals, metal oxides, and / or ceramics, such as copper, alumina (Al₂O₃), or aluminum nitride (AlN). Other geometries with increased surface area are also frequently used to improve heat exchange capacity. In addition, components can be active electronic components (implemented with at least one pn junction), passive electronic components such as resistors, inductors, or capacitors, electronic chips, storage devices (e.g., DRAM or other data memories), filters, integrated circuits (e.g., field-programmable gate arrays (FPGAs), programmable array logic (PALs), general-purpose array logic (GALs), and complex programmable logic devices (CPLDs)), signal processing components, power management components (e.g., field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, junction field-effect transistors (JFETs), or insulated-gate field-effect transistors). These include transistors (IGFETs), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), and / or any other suitable inorganic compound; optoelectronic interface elements; light-emitting diodes; optocouplers; voltage converters (e.g., DC / DC converters or AC / DC converters); cryptographic components; transmitters and / or receivers; electromechanical transducers; sensors; actuators; microelectromechanical systems (MEMS); microprocessors; capacitors; resistors; inductors; batteries; switches; cameras; antennas; logic chips; and energy harvesting units. However, other components can also be surface-mounted onto component carriers. For example, magnetic elements can be used as components. Such magnetic elements can be permanent magnetic elements (e.g., ferromagnetic, antiferromagnetic, multiferroic, or ferrimagnetic elements, such as ferrite cores) or paramagnetic elements. However, the component can also be an IC substrate, an interposer, or another component carrier, such as a board-in-board configuration. The component can be surface-mounted onto the component carrier. In addition, other components, particularly those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment, may be used as components.

[0100] In one embodiment, the component carrier is a laminated component carrier. In this embodiment, the component carrier is a multilayer composite structure that is stacked and connected together by applying pressure and / or heat.

[0101] After the internal layer structure of the component carrier has been treated, one or more additional electrically insulating and / or electrically conductive layer structures (particularly, through lamination) can be used to symmetrically or asymmetrically cover one main surface or two opposite main surfaces of the treated layer structure. In other words, stacking can continue until the desired number of layers is obtained.

[0102] After the formation of the stacked component with an electrically insulating layer structure and an electrically conductive layer structure is completed, the obtained layer structure or component carrier can be surface treated.

[0103] Specifically, in terms of surface treatment, an electrically insulating solder resist can be applied to one or both opposing main surfaces of the laminate or component carrier. For example, such a solder resist can be formed across the entire main surface and then the solder resist layer can be patterned to expose one or more electrically conductive surface portions, which will be used to electrically connect the component carrier to electronic peripherals. The surface portions of the component carrier covered by the solder resist, particularly those containing copper, can be effectively protected against oxidation or corrosion.

[0104] In terms of surface treatment, a surface treatment portion can be selectively applied to the exposed electrically conductive surface portion of the component carrier. This surface treatment portion can be an electrically conductive covering material on the exposed electrically conductive layer structure (e.g., pads, conductive traces, etc., particularly including or composed of copper) on the surface of the component carrier. If this exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (especially copper) will oxidize, resulting in lower reliability of the component carrier. Furthermore, the surface treatment portion can be formed, for example, as a joint between a surface mount component and the component carrier. The surface treatment portion functions to protect the exposed electrically conductive layer structure (especially copper circuitry), and the surface treatment portion can achieve bonding processing with one or more components, for example, by soldering. Examples of suitable materials for the surface treatment portion are organic solder protectant (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), electroless nickel and electroless palladium immersion gold (ENEPIG), gold (especially hard gold), electroless tin, nickel-gold, nickel-palladium, etc.

[0105] The foregoing limitations and other aspects of the present invention will become apparent by way of examples of embodiments described below and will be explained with reference to these examples. Attached Figure Description

[0106] Figure 1 A cross-section of a cavity in a component carrier according to an exemplary embodiment of the present invention is shown.

[0107] Figure 2 A component carrier having a component embedded in a cavity is shown according to an exemplary embodiment of the present invention.

[0108] Figure 3 An exemplary embodiment of the invention is shown as part of a multilayer stack. Figure 1 The component carrier.

[0109] Figure 4A , Figure 4B and Figure 4C A microscopic image of a conductive layer structure according to an exemplary embodiment of the present invention is shown.

[0110] Figure 5 A conventional circuit board with embedded components is shown.

[0111] Figure 6A , Figure 6B , Figure 6C and Figure 6D The process of manufacturing a component carrier according to an exemplary embodiment of the present invention is illustrated.

[0112] Figure 7A and Figure 7B The cavity edge portions according to exemplary embodiments of the present invention are shown respectively. Detailed Implementation

[0113] Figure 1 A cross-section of a component carrier cavity 110 in a component carrier stack 101 according to an exemplary embodiment of the present invention is shown. The stack 101 includes electrically conductive layer structures 104, 120 and electrically insulating layer structures 102, 108 (also shown in contrast). Figure 3 Cavity 110 is formed in stack 101 and is defined by bottom wall 111 and side wall 112. Bottom wall 111 is partially defined or defined by a first main surface 106 of the first electrical insulating layer structure 102 (shown schematically in the figure), one of a plurality of electrical insulating layer structures 102, 108. At least one electrically conductive layer structure 120 is provided on the first main surface 106, the at least one electrically conductive layer structure 120 comprising horizontal / planar insulating islands (constructed as traces and / or pads).

[0114] The conductive layer structure 120 includes a first portion 121 exposed within the cavity 110. The first portion 121 includes a plurality of first structures (traces), all of which are exposed at the bottom of the cavity 110, i.e., none of the first structures (traces) are covered by the electrically insulating layer structure 102. The conductive layer structure 120 also includes a second portion 122 covered by a second electrically insulating layer structure 108 of the plurality of electrically insulating layer structures 102, 108. The second electrically insulating layer structure 108 at least partially defines a sidewall / sidewall 112 of the cavity 110. The second portion 122 includes a plurality of second structures (traces), all of which are not exposed at the bottom of the cavity 110, i.e., all of the second structures (traces) are covered by the second electrically insulating layer structure 108.

[0115] The first portion 121 of the conductive layer structure 120 includes (each structure / trace in the first portion 121 includes) a covering conductive layer structure 150. In this example, the second portion 122 does not include (does not include) a covering conductive layer structure 150. Therefore, the covering conductive layer structure 150 covers the main surface and lateral surfaces of the conductive layer structure 120 of the first portion 121, and the covering conductive layer structure 150 covers the structures of the first portion 121 not covered by the first main surface 106 (in other words, all portions of the first portion 121 except for the bottom surface).

[0116] The bottom wall 111 of cavity 110 is defined by a first portion 121 of electrically conductive layer structure 120 and an exposed portion of the first main surface 106. In this example, there are no other structures defining the bottom wall 111 of cavity 110. The sidewalls 112 of cavity 110 are laterally defined by a second electrically insulating layer structure 108 (or one or more layers) of stack 101, or laterally defined by the second electrically insulating layer structure 108 and a second portion 122 of the electrically conductive layer structure. The second electrically insulating layer structure 108 is in direct contact with the first main surface 106, and the sidewalls 112 are defined by the second electrically insulating layer structure 108.

[0117] Figure 2 A component carrier 100 having a component 130 embedded in a cavity 110 is shown according to an exemplary embodiment of the present invention. The cavity 110 can be coupled with... Figure 1The implementation is constructed in a similar manner. Furthermore, a first electrically insulating layer structure 102 (defining the first main surface 106) located below the bottom wall 111 of the cavity is schematically shown. An additional material (e.g., solder material, specifically tin) 170 is provided on top of the electrically conductive layer structure 150 covering the first portion 121. The first portion 121 is defined as an electrical contact (pad) that can be electrically contacted via the electrically conductive layer structure 150 and the additional material 170.

[0118] The component 130 is placed in the cavity 110, and the component 130 is electrically connected to the electrically conductive layer structure 120 (electrically connected to at least one electrical contact of the first portion 121) via the electrical pad 131 of the component 130 through the additional material 170 and the covering electrically conductive layer structure 150.

[0119] Figure 3 An exemplary embodiment of the invention is shown as part of a multilayer stack 101. Figure 1 The component carrier 100 includes a core structure 109 (e.g., a cured reinforcing resin, such as FR4). An upper stack structure is arranged on top of the core structure 109, the upper stack structure having a plurality of electrically insulating layer structures 102 and a plurality of electrically conductive layer structures 104 (schematically shown).

[0120] In another embodiment, the cavity 110 may extend from the surface of the core layer structure 109 (into the core layer structure), or the cavity 110 may extend through the core layer structure 109. In another embodiment, the second electrical insulating layer structure 108 is configured as the core layer, for example, the second electrical insulating layer structure 108 is configured as the core layer by using a fully cured (reinforced) resin material, such as FR4.

[0121] Below the core layer structure 109, a lower layer stack structure is arranged, which has multiple additional electrically insulating layer structures 102 and multiple additional electrically conductive layer structures 104 (shown schematically). On top of the upper layer stack structure, a... Figure 1 The stacked component configuration described herein. A layer 103 with through-hole connections is arranged below the lower layer stacked structure.

[0122] Figure 4A , Figure 4B and Figure 4C A microscopic image of a conductive layer structure 150 according to an exemplary embodiment of the present invention is shown.

[0123] Figure 4AOn top of the stack 101 and in the cavity 110, an electrically conductive layer structure 120 (first portion 121) can be seen. On top, additional material 170 in the form of solder (tin-containing) bumps can be seen, and therefore, the additional material 170 has a non-constant thickness.

[0124] Figure 4B A detailed view of the junction between the conductive layer structure 120 and the additional material 170 shows the covering conductive layer structure 150, which in this example comprises two layers: an intermediate layer 151 and a protective layer 152 (the protective layer 152 is too thin to be seen in this enlarged view, approximately 100 nm). The intermediate layer 151 comprises nickel, and the protective layer 152 comprises gold (e.g., ENIG). The protective layer 152 is exposed to the interior space of the cavity 110, and the underlying intermediate layer 151 is thicker than the protective layer 152. No additional layer is disposed between the intermediate layer 151 and the protective layer 152, nor between the conductive layer structure 120 of the first portion 121 and the intermediate layer 151. In this example, the intermediate layer 151 also covers the sidewalls of the conductive layer structure 120.

[0125] Figure 4C The intermediate layer 151 of the conductive layer structure 150 defines a foot structure 160 of less than 2 μm at the bottom wall 111 of the cavity 110 and at the junction of the first main surface 106 and the conductive layer structure 150. Here, the foot structure 160 is a nickel foot. This structure is a remnant of the manufacturing process and can enhance the adhesion between the conductive layer structure 150 and the first main surface 106.

[0126] Figure 6A , Figure 6B , Figure 6C and Figure 6D The process of manufacturing a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0127] Figure 6A A preform of a stack 101 is provided, the preform having a core layer structure 109 sandwiched between electrically conductive layers (e.g., copper). Additional layer stacks are arranged at the top and bottom, namely an upper layer stack having an electrically insulating layer structure 102 and an electrically conductive layer structure 104, and a lower layer stack having another electrically insulating layer structure 102 and another electrically conductive layer structure 104. The upper main surface of the outermost layer of the stack 101 (here, the first electrically insulating layer structure 102) defines a first main surface 106. An electrically conductive layer structure 120 is provided (e.g., by plating) on ​​the first main surface 106.

[0128] Figure 6BA release layer 180 is provided to partially cover the electrically conductive layer structure 120. The portion is a future first portion 121, while a future second portion 122 is not covered by the release layer 180.

[0129] Figure 6C A second electrically insulating layer structure 108 is formed on the first main surface 106 (e.g., by lamination). The release layer 180 is also covered by the second electrically insulating layer structure 108. A through-hole connection is then formed in the second electrically insulating layer structure 108. A portion 108b of the second electrically insulating layer structure 108 is separated from the remaining portion 108a of the second electrically insulating layer structure 108 (e.g., by laser cutting the second electrically insulating layer structure 108 along a lateral edge perpendicular to the release layer in a vertical direction). The portion 108b is located on the release layer 180 such that it can be easily removed after separation (e.g., by applying ultrasound or laser trimming). By removing the portion 108b of the second electrically insulating layer structure 108, a cavity 110 is formed. Subsequently, the release layer 180 is removed (peeled off).

[0130] Subsequently, a covering conductive layer structure 150 is formed on the exposed electrically conductive layer structure 120 (i.e., the first portion 121), that is, after forming the cavity 110, the second portion 122 is covered by the second electrically insulating layer structure 108 so that the covering conductive layer structure 150 cannot cover the second portion 122. This achieves... Figure 1 or Figure 3 Similar design.

[0131] Figure 6D An additional material 170 is applied to the conductive layer structure 150, and then the component 130 is placed in the cavity 110 on the additional material 170 for electrical connection. A third electrically insulating layer structure 140 is applied in the free space (gap) between the structures of the first portion 121 of the conductive layer structure 120 and on the exposed portion of the first main surface 106. The third electrically insulating layer structure 140 serves as an encapsulation material 141 and fills the entire cavity 110, thereby encapsulating the component 130 and the electrical connection.

[0132] An additional layer structure 190 is provided on the main surface of the stack 101. This additional layer structure 190 is the outermost layer (electrically conductive layer structure 104) of the stack 101, and is configured as at least one of a solder resist portion, a surface treatment portion, or an organic solder protection portion. The additional layer structure 190 may (at least partially) be covered by an additional cover (electrically conductive) layer structure 155. Although the cover electrically conductive layer structure 150 may also be a surface treatment portion, the materials of the additional cover layer structure 155 and the cover electrically conductive layer structure 150 may be different or the same. In this way, a highly reliable and mechanically strong dual connection of the embedded component is achieved.

[0133] Figure 7A and Figure 7B Edge portions of cavity 110 according to an exemplary embodiment of the present invention are shown. The electrically conductive layer structure 120 on the first main surface 106 includes an edge portion located through the sidewall 111 of cavity 110, such that a first sub-part 123 of the edge portion is exposed in cavity 110, and a second sub-part 124 of the edge portion is not exposed in cavity 110 and is embedded in the stack 101 (in the second electrically insulating layer structure 108). The edge portion is the region of the structure / trace of the electrically conductive layer structure 120 that includes the junction of the first portion 121 and the second portion 122. While the first portion 121 of the structure is exposed (first sub-part 123), the second portion 122 of the structure is not exposed (second sub-part 124). Therefore, the first sub-part 123 includes a covering of the electrically conductive layer structure 150.

[0134] Figure 7A The conductive layer structure 150 does not extend beyond the sidewall 112 (in the horizontal direction) of the cavity 110. Instead, the second electrically insulating layer structure 108 (sidewall 112) defines a clear division between the first sub-part 123 and the second sub-part 124. In an embodiment, the first sub-part 123 may be configured as a laser stop layer to prevent laser energy from damaging the dielectric layer located at the bottom of the cavity, while the second sub-part 124 may be an extension of the first sub-part 123. Thus, the two portions remaining at the edge can also leave an undercut between the sidewall and the bottom wall during etching, which, since it is too small to be filled, can then be sealed / sealed during encapsulation.

[0135] Figure 7BThe conductive layer structure 150 extends (horizontally) beyond the sidewall 112 of the cavity 110. Therefore, the conductive layer structure 150 is partially embedded in and covered by the second electrically insulating layer structure 108 of the stack 101. Thus, the junction between the covered portion 123 and the uncovered portion 124 is smooth and well protected by the electrically insulating material. In this embodiment, the sidewall 112 of the cavity 110 is defined by the second electrically insulating layer structure 108, the second portion 122 of the conductive layer structure (particularly the second sub-portion 124 of the edge portion), and the conductive layer structure 150 located on top of the second sub-portion 124. In this embodiment, the conductive layer structure 150 extends vertically along a portion of the sidewall 112. This design at least partially avoids damage to the sidewall from laser energy and / or excessive etching of the sidewall, which can lead to delamination at the edges of the sidewall and bottom wall.

[0136] List of reference numerals

[0137] 100 component carriers

[0138] 101 Stacked Components

[0139] 102 First Electrical Insulation Layer Structure

[0140] 103 Through-connection layer

[0141] 104 One or more additional electrically conductive layer structures

[0142] 106 First Primary Surface

[0143] 108 Second Electrical Insulation Layer Structure

[0144] 109 core structure

[0145] 110 cavity

[0146] The bottom (bottom wall) of cavity 111

[0147] 112 sidewalls

[0148] 120 Electrically Conductive Layer Structure

[0149] 121 Part One

[0150] 122 Part Two

[0151] 123 First Sub-part

[0152] 124 Second Sub-part

[0153] 130 parts

[0154] 131 Electrical connection part of component

[0155] 140 Third electrical insulation layer structure

[0156] 141 Packaging Material

[0157] 150 Covered Electrical Conductive Layer Structure

[0158] 151 Intermediate Layer, Nickel Layer

[0159] 152 protective layer, gold layer

[0160] 155. Additional covering structure

[0161] 160 foot structure, nickel foot

[0162] 170 Additional material, solder bump

[0163] 180 release layer

[0164] 190. Another layered structure.

Claims

1. A component carrier (100), the component carrier (100) comprising: The stack (101) includes at least one electrically conductive layer structure (120) and a plurality of electrically insulating layer structures; A cavity (110) is formed in the stack (101) and is defined by a bottom wall (111) and a side wall (112); The bottom wall (111) is partially defined by the first main surface (106) of the first electrical insulating layer structure (102) of the plurality of electrical insulating layer structures; The at least one electrically conductive layer structure (120) is disposed in or on the first main surface (106); Wherein, the at least one electrically conductive layer structure (120) includes: The first part (121), the first part (121) is exposed in the cavity (110), and The second part (122) is covered by the second electrical insulating layer structure (108) of the plurality of electrical insulating layer structures; and In addition to the structure including the second part (122), the first part (121) of the at least one electrically conductive layer structure (120) also includes a covering electrically conductive layer structure (150).

2. The component carrier (100) according to claim 1, in, The conductive layer structure (150) covers the main surface and lateral surface of the at least one conductive layer structure (120) of the first portion (121); and / or The electrically conductive layer structure (150) covers the structure of the first portion (121) that is not covered by the first main surface (106).

3. The component carrier (100) according to claim 1 or 2, in, The covering conductive layer structure (150) includes at least two layers (151, 152), and in particular, the covering conductive layer structure (150) includes exactly two layers.

4. The component carrier (100) according to any one of the preceding claims, in, The conductive layer structure (150) includes a seed layer and a plating layer.

5. The component carrier (100) according to any one of the preceding claims, in, The electrical conductive layer structure (150) includes an intermediate layer (151) and a protective layer (152). In particular, the intermediate layer (151) includes nickel, and in particular, the protective layer (152) includes gold.

6. The component carrier (100) according to claim 5, in, The protective layer (152) faces the interior space of the cavity (110), and in particular, the protective layer (152) is exposed to the interior space of the cavity (110); and / or Wherein, the intermediate layer (151) is thicker than the protective layer (152); and / or Wherein, no additional layer is arranged between the intermediate layer (151) and the protective layer (152); and / or In this case, no additional layer is arranged between the electrical conductive layer structure (120) of the first portion (121) of the at least one electrical conductive layer structure (120) and the intermediate layer (151).

7. The component carrier (100) according to any one of the preceding claims, in, The conductive layer structure (150) defines a foot structure (160) at the bottom wall (111) of the cavity (110). In particular, the conductive layer structure (150) defines a foot structure (160) at the bottom wall (111) of the cavity (110) and at the junction of the first main surface (106) and the conductive layer structure (150). In particular, the foot structure (160) is a nickel foot.

8. The component carrier (100) according to any one of the preceding claims, in, The bottom wall (111) of the cavity (110) is defined by the first portion (121) of the at least one electrically conductive layer structure (120) and the exposed portion of the first main surface (106).

9. The component carrier (100) according to any one of the preceding claims, in, The sidewall (112) of the cavity (110) is laterally defined by at least one of the layer structures (102, 104, 108) of the stack (101), preferably, the sidewall (112) of the cavity (110) is laterally defined by multiple layer structures (102, 104, 108) of the stack (101). In particular, In this embodiment, at least one additional electrically conductive layer structure (104) and / or the second electrically insulating layer structure (108) is in direct contact with the first main surface (106); and / or The sidewall (112) is at least partially defined by the second electrical insulating layer structure (108) of the plurality of electrical insulating layer structures.

10. The component carrier (100) according to any one of the preceding claims, in, Another electrical conductive layer structure (190) of the plurality of electrically conductive layer structures (104) is disposed on the surface of one of the plurality of electrically insulating layer structures (108). In particular, the other electrical conductive layer structure (190) of the plurality of electrically conductive layer structures (104) is disposed on the main surface of one of the plurality of electrically insulating layer structures (108). The other electrical conductive layer structure (190) of the plurality of electrically conductive layer structures (104) at least partially defines the sidewall (112) or is arranged below the cavity (110). The additional conductive layer structure (190) includes an additional covering conductive layer structure (155), which is different from the covering conductive layer structure (150) located on the first portion (121) of the at least one conductive layer structure (120). Specifically, the additional conductive layer structure (190) is the outermost conductive layer structure (104) of the stack (101), and the additional conductive layer structure (190) is the outermost conductive layer structure of the stack (101) located on the opening side of the cavity (110).

11. The component carrier (100) according to any one of the preceding claims, in, The at least one electrically conductive layer structure (120) located in or on the first main surface (106) includes an edge portion located through the sidewall (111) of the cavity (110) such that: a first sub-part (123) of the edge portion is exposed in the cavity (110), and a second sub-part (124) of the edge portion is not exposed in the cavity (110) and is embedded in the stack (101), in particular, the second sub-part (124) of the edge portion is embedded in the second electrically insulating layer structure (108).

12. The component carrier (100) according to claim 11, in, The first sub-part (123) includes the covered electrically conductive layer structure (150).

13. The component carrier (100) according to claim 11 or 12, in, The covering conductive structure (150) extends partially beyond the sidewall (112) of the cavity (110); and / or The covering electrical conductive structure (150) is partially embedded in at least one second electrical insulating layer structure (108) of the stack (101) and / or covered by at least one second electrical insulating layer structure (108) of the stack (101).

14. The component carrier (100) according to any one of the preceding claims, in, The electrically conductive layer structure (150) and / or the first electrically insulating layer structure (102) include a low-phosphorus material / surface; and / or The electrically conductive layer structure (150) includes ENIG or ENEPIG; and / or The electrically conductive layer structure (150) is substantially free of palladium.

15. The component carrier (100) according to any one of the preceding claims, wherein the component carrier (100) further comprises: Additional material (170) located on the upper surface of the covered conductive layer structure (150), In particular, The additional material (170) is disposed only on the upper surface; and / or Wherein, the lateral surfaces of the at least one electrically conductive layer structure (120) of the first portion (121) and the corresponding covering electrically conductive layer structure (150) do not contain the additional material (170); and / or Wherein, the additional material (170) is solder material, and in particular, the additional material (170) is a solder protrusion; and / or The additional material (170) includes phosphorus; and / or The additional material (170) has a non-constant thickness.

16. The component carrier (100) according to any one of the preceding claims, wherein the component carrier (100) further comprises: A third electrical insulating layer structure (140) is disposed in the cavity (110) on the at least one electrically conductive layer structure (120) of the first portion (121) and on the exposed portion of the first main surface (106). In particular, The third electrical insulating layer structure (140) includes components and / or structures different from those of another electrical insulating layer structure in the plurality of electrical insulating layer structures; and / or The third electrical insulation layer structure (140) is disposed only between the structures of the first part (121). Specifically, the third electrical insulation layer structure (140) is disposed on the exposed portion of the first main surface (106).

17. The component carrier (100) according to any one of the preceding claims, in, At least a portion of the first part (121) is defined as an electrical contact portion, and in particular, at least a portion of the first part (121) is defined as a pad.

18. The component carrier (100) according to any one of the preceding claims, wherein the component carrier (100) further comprises: Component (130), said component (130) being connected to said at least one electrically conductive layer structure (120), specifically, said component (130) being electrically connected to at least one electrical contact of the first portion (121), In particular, The component (130) is configured as a bridging element.

19. The component carrier (100) according to any one of the preceding claims, wherein the component carrier (100) further comprises: The encapsulation material (141) used to encapsulate the component (130), Specifically, the encapsulation material (141) is in contact with the third electrical insulating layer structure (140).

20. A method for manufacturing a component carrier (100), the method comprising: A stack (101) is provided, the stack (101) including at least one electrically conductive layer structure (120) and a plurality of electrically insulating layer structures; A cavity (110) is formed in the stacked member (101), the cavity (110) being bounded by a bottom wall (111) and a side wall (112). The bottom wall (111) is partially defined by the first main surface (106) of the first electrical insulating layer structure (102) of the plurality of electrical insulating layer structures, and Wherein, at least one electrically conductive layer structure (120) is disposed in / on the first main surface (106); A covering conductive layer structure (150) is provided on the at least one electrically conductive layer structure (120), such that the at least one electrically conductive layer structure (120) includes: A first portion (121) is exposed in the cavity (110), wherein, in addition to the structure including the second portion (122), the first portion (121) also includes the covering conductive layer structure (150). The second part (122) is covered by the second electrical insulation layer structure (108) of the plurality of electrical insulation layer structures.

21. The method according to claim 20, wherein, Forming the cavity (110) includes: The at least one electrically conductive layer structure (120) is partially covered by a release layer (180); At least a second electrical insulation layer structure (108) is provided on the release layer (180) and on the first main surface of the first electrical insulation layer structure (102); and At least a portion of the second electrical insulating layer structure (108) located on the release layer (180) is removed to form the cavity (110); Specifically, the release layer (180) is then further removed.

22. The method according to claim 20 or 21, further comprising: After the cavity (110) is formed, the covering conductive layer structure (150) is formed on the exposed conductive layer structure (120).

23. The method according to any one of claims 20 to 22, the method further comprising: A third electrically insulating layer structure (140) is provided in the free space between the structures of the first portion (121) of the at least one electrically conductive layer structure (120) and on the exposed portion of the first main surface (106).

24. The method according to any one of claims 20 to 23, the method further comprising: The component (130) is placed into the cavity (110) and onto the covering conductive layer structure (150), wherein, in particular, additional material (170) is placed between the component (130) and the covering conductive layer structure (150).

25. The method according to any one of claims 20 to 24, the method further comprising: The cavity (110) is filled with encapsulation material (141). Specifically, the cavity (110) is filled with an encapsulation material (141) to encapsulate the component (130) within the cavity (110).

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