A PCB layout method for a high-power-density mobile power supply with a wire

Abstract

The application relates to the technical field of electronic circuit layout, in particular to a self-wire high-power-density mobile power supply PCB layout method, which comprises the following steps: planning a four-layer PCB according to a power supply layer, a ground layer and a signal layer, and arranging battery groups, charging management chips, boost chips or bidirectional converters, detection units, active equalization driving units, self-wire interfaces and protection devices in partitions; compressing a large-current path from a battery end to a power conversion end and a self-wire interface end, so that power inductors, capacitors and switch nodes form small-area switch loops around the chips; avoiding sampling signals, control signals and interface identification signals from the strong noise area and transmitting the signals in continuous reference ground; arranging a via array on a heat source pad and cooperatively conducting heat with copper skins and filling spaces. The method reduces line loss and electromagnetic interference, and improves the heat diffusion and detection stability of the high-power-density mobile power supply.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit layout technology, and in particular to a PCB layout method for a high power density mobile power supply with built-in wiring. Background Technology

[0002] The field of electronic circuit layout technology involves the partitioning, routing, grounding, heat dissipation, and interface protection configuration of power electronic components on printed circuit boards. It is used to organize circuit units such as power conversion, signal acquisition, and protection control within a limited board area. Among them, the traditional mobile power bank PCB layout refers to arranging the battery connection terminal, charge and discharge management circuit, boost conversion circuit, interface output circuit, and protection circuit on the same circuit board, and completing power supply, detection, and output through copper foil traces, ground reference planes, and device pads.

[0003] Existing mobile power bank PCBs with built-in cables simultaneously carry battery current, boost switch current, and interface output current within a limited board space. The high current path is relatively long, and the sampling area is easily affected by backflow interference. The power inductor and switching node generate noise coupling. The signal lines and power lines near the built-in cable interface are not sufficiently spaced, the heat dissipation channel is discontinuous in areas with concentrated heat sources, and the potting compound filling space is limited, which increases line loss, aggravates electromagnetic interference, reduces sampling accuracy, and affects the stability of interface connection and heat dissipation capability. Summary of the Invention

[0004] To address the technical problems of long high-current paths, susceptibility to backflow interference in sampling areas, noise coupling at switching nodes, insufficient interface signal integrity, and discontinuous heat dissipation channels in areas with concentrated heat sources in the PCB design of self-contained power bank, this invention provides a PCB layout method for high-power-density self-contained power banks, comprising the following steps: planning a four-layer stack-up for the power bank PCB, dividing the layers into power layers, ground layers, and signal layers; configuring layers near high-current paths as low-impedance power return channels; configuring the ground layer as a continuous reference plane; and configuring the signal layer as a transmission area carrying BMS sampling signals, control signals, and interface identification signals; establishing a partitioned layout on the power bank PCB around the battery pack, charging management chip, boost chip or bidirectional converter, BMS detection unit, active balancing drive unit, self-contained interface, and protection devices, ensuring that battery status detection, charge / discharge power conversion, interface output, and protection triggering are located on the same continuous electrical link within the same board surface; and setting the power ground and analog ground as a single-point connection, and... The return paths of battery current, boost switch current, and integrated line output current are kept away from the analog sampling area. The charging management chip, boost chip or bidirectional converter, power inductor, energy storage capacitor, power switching device, and integrated line interface are placed compactly according to the current flow direction to shorten the trace distance from the battery end to the power conversion end and from the power conversion end to the integrated line interface end, so that the switching node, power inductor, and energy storage capacitor form a small area high-frequency switching loop around the corresponding chip. The copper foil traces carrying the charging and discharging current and the integrated line output current are set as wide traces and connected to the inner copper layer through multiple parallel vias. The traces of BMS sampling signal, control signal, and interface identification signal are arranged away from the power inductor and switching node, and ESD protection devices are arranged near the integrated line interface so that the electrostatic discharge path is first connected to the continuous reference plane. Heat dissipation pads, via arrays, and large-area copper foil are set in the heat source areas corresponding to the heat-generating chip, power inductor, power switching device, and integrated line interface, and space for heat dissipation potting compound is reserved around the heat source areas.

[0005] Furthermore, the four-layer board stack-up plan includes setting the power layer and the ground layer adjacent to each other, so that the high-current copper foil in the power layer forms a short return path through the ground layer; the BMS sampling signal, the control signal and the interface identification signal in the signal layer use the ground layer as a reference plane; the single-point connection position of the power ground and the analog ground is arranged at the common return node between the negative terminal of the battery pack and the power conversion return terminal, and the sampling reference point of the analog sampling area is led out from the common return node.

[0006] As a progressive solution, the BMS detection unit includes a voltage sampling interface, a temperature sampling interface, a current detection circuit, and an analog-to-digital converter (ADC). The sampling lines of the voltage sampling interface are led out in sequence according to the battery pack terminals and are spaced apart from the switching nodes of the power switching device before entering the ADC. The sampling lines of the temperature sampling interface are arranged near the heat source area and avoid the edge magnetic field area of ​​the power inductor. The detection terminal of the current detection circuit is connected to the main charging and discharging circuit and sends the detection signal to the ADC through the analog sampling area.

[0007] As a parallel solution, the traces from the power conversion terminal to the self-connected line interface are arranged in sections according to VBUS traces, high-current ground lines, and identification communication lines. The VBUS traces and the high-current ground lines are located in the board edge area near the self-connected line interface and are routed using short-path straight lines. The identification communication lines are located in the ground reference protection area between the VBUS traces and the power inductor, and are isolated from the VBUS traces by adjacent ground copper foils. Alternatively, the traces from the power conversion terminal to the self-connected line interface are arranged in parallel conductive paths according to high-current copper foils, multi-via parallel structures, and inner copper foils. The high-current copper foils extend from the power conversion terminal to the self-connected line interface, and the multi-via parallel structures are arranged between the high-current copper foils and the inner copper foils, so that the high-current copper foils, the multi-via parallel structures, and the inner copper foils jointly carry the self-connected line output current.

[0008] Furthermore, when the battery pack includes multiple cells connected in series or in parallel, an independent balancing power area is set on the mobile power supply PCB; the independent balancing power area includes an active balancing chip, a microcontroller, a voltage acquisition unit, a balancing switch, a balancing inductor, and a balancing energy storage capacitor; the active balancing chip, the balancing switch, the balancing inductor, and the balancing energy storage capacitor are compactly arranged around the energy transfer path; an interval wiring area is set between the independent balancing power area and the analog sampling area, and the cascaded communication traces are arranged along a continuous reference ground.

[0009] As a progressive scheme, the microcontroller receives the battery cell voltage from the voltage acquisition unit, the battery temperature from the temperature sampling interface, and the state of charge (SOC) obtained from the current detection circuit and the battery cell voltage; it normalizes the battery cell voltage, the battery temperature, and the SOC to obtain normalized voltage, normalized temperature, and normalized SOC values; it forms a fuzzy input set based on the normalized voltage, normalized temperature, normalized SOC, normalized voltage difference between adjacent cells, and normalized SOC difference; it matches the fuzzy input set with a preset fuzzy rule to obtain an equalization strength level, and converts the equalization strength level into an equalization current control quantity; the equalization current control quantity is used to drive the equalization switching device, enabling the equalization inductor and the equalization energy storage capacitor to transfer energy between the higher-voltage and lower-voltage cells.

[0010] As an additional limitation, when the state of charge (SOC) is in the low SOC or high SOC range, the microcontroller uses the normalized voltage value and the normalized voltage difference value as high-priority inputs; when the SOC is in the intermediate SOC range, the microcontroller uses the normalized SOC value and the normalized SOC difference value as high-priority inputs; when the battery cell voltage output by the voltage acquisition unit exceeds the overvoltage threshold or falls below the undervoltage threshold, or when the current output by the current detection circuit exceeds the overcurrent threshold, the microcontroller stops outputting the equalization current control quantity and outputs a cut-off or current-limiting control signal to the protection device; the overvoltage threshold, the undervoltage threshold, and the overcurrent threshold are provided by the battery protection parameter table, and when they equal the threshold boundaries, they are included in the trigger protection conditions.

[0011] Furthermore, the via array includes a first thermally conductive via group located below the heat dissipation pad and a second thermally conductive via group located around the heat source region; the first thermally conductive via group connects the heat dissipation pad to the inner copper layer; the second thermally conductive via group connects the inner copper layer to the outer heat dissipation copper layer; the heat dissipation potting compound fills the space along the gap between the heat-generating chip, the power inductor, the power switching device, and the battery connection area, so that the flow path of the potting compound covers the thermally conductive areas corresponding to the first thermally conductive via group and the second thermally conductive via group.

[0012] As a progressive solution, when determining the heat dissipation potting compound filling space, the heat source area, interface insulation protection area, and battery connection area are divided into potting coverage areas; a potting path, dispensing position, and dispensing time are configured for the potting coverage area, so that the mixed heat dissipation potting compound enters the heat dissipation potting compound filling space from the dispensing position; when the potting path passes near the self-connected interface, the dispensing position avoids the pad area of ​​the interface identification signal, and the heat dissipation potting compound filling space retains the discharge path from the ESD protection device to the continuous reference plane.

[0013] Compared with the prior art, the advantages and positive effects of the present invention are as follows: In this invention, by combining the four-layer board stack-up planning with single-point connections for power ground and analog ground, the high-current return path avoids the analog sampling area, reducing the impact of return coupling on voltage, current, temperature, and state of charge sampling. By compactly arranging power devices, inductors, capacitors, and integrated line interfaces according to the current flow direction, and using wide copper foil and multiple vias in parallel to carry the output current, the high-current path is shortened and high-frequency switching loops are suppressed. Through active equalization to isolate the power area from the sampling area, fuzzy input normalization, and protection threshold boundary assignment, equalization control and protection actions have clear triggering basis. Through the coordinated arrangement of heat dissipation pads, via arrays, copper foil, and potting space, a continuous heat conduction path is formed in the heat source area while also taking into account interface insulation protection. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the stacking and grounding relationship of a four-layer PCB for a power bank. Figure 2 A schematic diagram of the functional partitions and power path layout of a power bank PCB. Figure 3 A schematic diagram of the routing and ESD discharge path for the built-in interface area; Figure 4 A schematic diagram of the active balancing control chain and protection triggering relationship; Figure 5 This is a schematic diagram of the heat conduction path and the space filled by the heat dissipation potting compound in the heat source area. Detailed Implementation

[0015] The technical solutions described in this invention will be specifically described below with reference to the accompanying drawings. The following embodiments use a high-power-density mobile power bank PCB layout method with integrated wiring as the implementation object. The mobile power bank PCB is used to carry the battery pack, charging management chip, boost chip or bidirectional converter, BMS detection unit, active balancing drive unit, integrated wiring interface, and protection devices. In the following embodiments, terms such as power layer, ground layer, signal layer, low-impedance power return channel, continuous reference plane, analog sampling area, independent balancing power area, heat source area, and heat dissipation potting compound filling space are understood according to the technical solutions described in the application documents. The battery cell voltage, battery temperature, charge / discharge current, state of charge, voltage normalization value, temperature normalization value, state of charge normalization value, voltage difference normalization value, state of charge difference normalization value, fuzzy input set, balancing strength level, and balancing current control quantity involved in the embodiments are all data objects formed or used in the detection, control, and power conversion links of the mobile power bank PCB. The attached diagrams are only used to illustrate the layer relationships, partition relationships, signal paths, power paths, equalization control chains, and thermal management chains during the implementation process, and do not limit the specific shape, package type, or board size of the components.

[0016] Example 1 Please see Figure 1-5 This embodiment provides a PCB layout method for a high-power-density mobile power bank with integrated wiring. This method is applied to the PCB design process of a high-power fast-charging mobile power bank with integrated wiring. Through four-layer board stack-up planning, power and signal partitioning, ground reference planning, high-current path compression, interface protection, active equalization control support, and coordinated configuration of heat dissipation vias and potting space, a feasible electrical layout link is formed within the same mobile power bank PCB for battery status detection, charge / discharge power conversion, integrated wiring interface output, protection triggering, and heat dissipation. This method includes steps S1 to S7.

[0017] S1, plan the four-layer board stack-up for the power bank PCB. Please refer to [link / reference]. Figure 1 The power bank PCB is divided into power, ground, and signal layers. The power layer carries the power supply path from the battery to the power conversion terminal and from the power conversion terminal to the built-in line interface terminal. The ground layer forms a continuous reference plane, and the signal layer is used to arrange BMS sampling signals, control signals, and interface identification signals. During layer stack-up planning, layers near high-current paths are configured as low-impedance power return channels, allowing battery current, boost switch current, and built-in line output current to return along the short path between the power and ground layers. The ground layer remains continuous, avoiding any interruptions below the main traces of the BMS sampling and interface identification signals, ensuring that the sampling and identification traces in the signal layer have a consistent reference potential during transmission. After completing S1, the layer function allocation result is obtained, which serves as the basis for subsequent device partitioning, trace direction, and heat source area division.

[0018] S2, establish the functional partition layout on the power bank PCB. Please refer to... Figure 2 The battery pack, charging management chip, boost chip or bidirectional converter, BMS detection unit, active balancing drive unit, integrated line interface, and protection devices are arranged in zones according to current flow direction, signal sensitivity, and heat generation location. The battery pack connection is located on the input side of the main charging / discharging circuit; the charging management chip and boost chip or bidirectional converter are located in the power conversion area; the BMS detection unit is located in the analog sampling area; the active balancing drive unit is located in the independent balancing power area; the integrated line interface is located near the board edge; and the protection devices are located before the protected line enters the main control, BMS sampling, or interface identification circuit. Through the above zoning, the battery status detection path, charging / discharging power conversion path, interface output path, and protection trigger path maintain clear electrical boundaries within the board surface. The functional zoning results formed in S2 are called by S3 to S7 to constrain the grounding location, wiring path, balancing control chain, and heat dissipation area.

[0019] S3 sets the power ground and analog ground as a single-point connection. (See also...) Figure 1 and Figure 2 The power ground carries the return current of the battery current, boost switch current, and self-contained line output current, while the analog ground carries the reference return current of the voltage sampling interface, temperature sampling interface, current detection circuit, and analog-to-digital converter. The single-point connection is located at the common return node between the negative terminal of the battery pack and the power conversion return terminal. The sampling reference point for the analog sampling area is led out from this common return node. Since the power ground and analog ground are only electrically connected at the common return node, the battery current, boost switch current, and self-contained line output current will not form a circulating current path within the analog sampling area. After completing S3, the BMS detection unit can use the continuous reference plane and the common return node as sampling references, providing a clear electrical source for subsequent calculations of individual battery cell voltage, battery temperature, charge / discharge current, and state of charge.

[0020] S4 performs layout compression for high-current paths and high-frequency switching loops. (See also...) Figure 2 and Figure 3The charging management chip, boost chip or bidirectional converter, power inductor, energy storage capacitor, power switching device, and built-in line interface are compactly arranged according to the current flow direction from the battery end to the power conversion end and from the power conversion end to the built-in line interface end. The power inductor and energy storage capacitor are arranged around the corresponding chip, and the switching node is limited within the power conversion area, forming a small-area high-frequency switching loop between the power switching device, power inductor, and energy storage capacitor. The copper foil traces carrying the charging and discharging current and the built-in line output current are set as wide traces and connected to the inner copper layer through multiple parallel vias. The wide copper foil, multiple parallel vias, and inner copper layer together form a parallel conductive path. The power path layout result formed in S4 is used by S5 for interface area wiring constraints and by S7 for determining the heat source area and heat conduction path.

[0021] S5 provides interface output and signal isolation layout for the built-in line interface area. Please refer to [link / reference]. Figure 3 The built-in line interface is located near the edge of the power bank PCB. The VBUS traces, high-current ground lines, and identification communication lines within the interface area are zoned according to current rating and signal sensitivity. The VBUS traces and high-current ground lines are located near the edge of the built-in line interface and are routed in straight lines along the shortest path. The identification communication lines are located within the ground reference protection area between the VBUS traces and the power inductor. Ground copper is reserved adjacent to the identification communication lines to reduce crosstalk between them and the VBUS traces and high-frequency switching nodes. ESD protection devices are located near the built-in line interface. The electrostatic discharge path enters the ESD protection device from the interface end, first connecting to a continuous reference plane, and then isolating from the main control, BMS sampling, or fast charging protocol identification circuit. After S5 is completed, the output path, ground return path, identification communication path, and electrostatic discharge path of the built-in line interface all have defined routing boundaries.

[0022] S6, in scenarios involving multiple series or series-parallel connected battery cells, arranges an independent power balancing zone and establishes a power balancing control chain. Please refer to [link / reference]. Figure 4 When the battery pack comprises multiple cells connected in series or parallel, the power bank PCB features an independent balancing power area. This area includes an active balancing chip, microcontroller, voltage acquisition unit, balancing switch, balancing inductor, and balancing energy storage capacitor. These components are arranged around the energy transfer path, allowing energy transfer between higher-voltage and lower-voltage cells via a switching balancing path. An interval routing area separates the independent balancing power area from the analog sampling area. The sampling lines are kept away from the switching nodes of the balancing switch and the balancing inductor, and the cascaded communication traces are arranged along a continuous reference ground. This ensures that the balancing energy transfer path and the sampling signal path are isolated within the board, allowing the BMS detection unit to continue obtaining a sampling signal less affected by backflow interference during balancing operations.

[0023] In S6, the microcontroller receives the individual cell voltages from the voltage acquisition unit, the battery temperature from the temperature sampling interface, and the state of charge (SOC) formed by the current detection circuit and the individual cell voltages. The microcontroller normalizes the individual cell voltages, battery temperature, and SOC to obtain normalized voltage, temperature, and SOC values, respectively. Simultaneously, based on the voltage difference and SOC difference between adjacent cells or between an individual cell and the mean, it obtains normalized voltage difference and SOC difference values. These normalized values ​​together form a fuzzy input set. The microcontroller matches the fuzzy input set with preset fuzzy rules to obtain an equalization strength level, which is then converted into an equalization current control quantity. This equalization current control quantity is output to the equalization switching device, which changes its conduction state according to the control quantity, enabling the equalization inductor and equalization energy storage capacitor to transfer energy between cells with higher voltage and cells with lower voltage. The input sources, normalization processes, intermediate results, mapping results, and execution objects of this control chain are all supported by the sampling, control, and equalization power layout on the board.

[0024] In S6, when the state of charge (SOC) is in the low or high SOC range, the microcontroller uses the normalized voltage and voltage difference values ​​as high-priority inputs. When the SOC is in the intermediate range, the microcontroller uses the normalized SOC and SOC difference values ​​as high-priority inputs. The low, high, and intermediate SOC ranges are provided by the battery protection parameter table or BMS control parameter table, which is stored in a microcontroller-accessible memory area. If the battery cell voltage output by the voltage acquisition unit exceeds the overvoltage threshold or falls below the undervoltage threshold, or if the current output by the current detection circuit exceeds the overcurrent threshold, the microcontroller stops outputting the equalization current control quantity and outputs a cut-off or current-limiting control signal to the protection device. When the current equals the threshold boundary, it falls under the trigger protection condition, giving the protection trigger a defined boundary. After this judgment, the protection device changes the conduction state of the charging / discharging main circuit according to the cut-off or current-limiting control signal, forming a closed loop of detection input, state judgment, control command, switching action, and protection feedback.

[0025] S7 sets up the heat dissipation pads, via array, large copper area, and thermal potting compound to fill the space in the heat source area. Please refer to [link / reference]. Figure 2 and Figure 5The heat source area includes the areas corresponding to the heat-generating chip, power inductor, power switching device, and built-in interface. A heat dissipation pad is placed within the heat source area, with a first group of thermally conductive vias below the pad and a second group of thermally conductive vias surrounding the heat source area. The first group of thermally conductive vias connects the heat dissipation pad to the inner copper layer, and the second group connects the inner copper layer to the outer heat dissipation copper layer. The heat dissipation pad, the first group of thermally conductive vias, the inner copper layer, the second group of thermally conductive vias, and the outer heat dissipation copper layer form a continuous heat conduction path. The heat-dissipating potting compound fills the space along the gaps between the heat-generating chip, power inductor, power switching device, and battery connection areas, ensuring that the potting compound flow path covers the corresponding heat-conducting areas of the first and second groups of thermally conductive vias. After S7 is completed, the heat generated in the heat source area diffuses through the pads, vias, and copper layer, and continues to be transferred to the internal filling space of the housing through the contact area of ​​the potting material.

[0026] In S7, when determining the thermal potting compound filling space, the heat source area, interface insulation protection area, and battery connection area are divided into potting coverage areas. Each potting coverage area is configured with a potting path, dispensing position, and dispensing time, ensuring that the mixed thermal potting compound enters the thermal potting compound filling space from the dispensing position. When the potting path passes near the integrated interface, the dispensing position avoids the interface identification signal pad area and preserves the discharge path from the ESD protection device to the continuous reference plane. Therefore, the thermal potting compound filling space does not block the interface identification signal pad connection, nor does it interrupt the electrostatic discharge path. Observable verification states after potting include the formation of a continuous filling area around the heat source area, coverage of the corresponding area of ​​the thermal via group, the maintenance of distinguishable electrical connection boundaries in the interface identification signal pad area, and the maintenance of a continuous discharge path from the ESD protection device to the continuous reference plane.

[0027] Through steps S1 to S7, the mobile power supply PCB in this embodiment first establishes the basic carriers of power, ground, and signals through a four-layer board stack-up plan. Then, the functional partitions determine the location boundaries of the battery pack, power conversion, BMS detection, active equalization, built-in interface, and protection devices. Subsequently, through single-point grounding, high-current path compression, interface signal isolation, equalization control support, and thermal management path configuration, the power path, sampling path, control path, protection path, and heat dissipation path are interconnected. The verification method of this embodiment can be completed through layout inspection, electrical connection inspection, and layout relationship inspection. The inspection objects include the adjacency relationship between the power layer and the ground layer, the single-point connection relationship of the common return current node, the area of ​​the high-frequency switching loop, the spacing between the interface signal line and the power path, the isolation relationship between the equalization power area and the analog sampling area, the connection relationship between the thermal via group in the heat source area and the copper layer, and the boundary relationship between the potting space and the interface pad area.

[0028] Example 2 Please see Figure 1-5This embodiment provides a PCB layout method for a high-power-density mobile power supply with built-in lines. The difference between this embodiment and Embodiment 1 is that the routing from the power conversion end to the built-in line interface end is implemented with interface partitioning and isolation as the main constraint, focusing on limiting the relative positions and signal protection paths between VBUS traces, high-current ground lines and identification communication lines; the remaining four-layer board stack-up planning, functional partitioning, single-point grounding, active equalization control support and thermal management configuration can adopt the corresponding implementation methods in Embodiment 1.

[0029] After establishing the board layer functions, functional partitions, grounding relationships, and high-current main paths according to Example 1 in steps S1 to S4, step S5 divides the lines at the built-in line interface end into VBUS traces, high-current ground lines, and identification communication lines. Please refer to [link / reference]. Figure 3 The VBUS trace extends from the power conversion end to the self-contained line interface end. The high-current ground line returns to the corresponding return current area of ​​the continuous reference plane along the interface output return direction. The identification communication line is led out from the self-contained line interface end and enters the interface identification circuit. The VBUS trace and the high-current ground line are arranged near the board edge area of ​​the self-contained line interface, and both use short-path straight routing to reduce the turning path of the self-contained line output current near the interface. The identification communication line is arranged in the ground reference protection area, which is located between the VBUS trace and the power inductor. The ground copper adjacent to the identification communication line is connected to the continuous reference plane. With this arrangement, the adjacent path of the interface identification signal is limited by the ground copper before entering the interface identification circuit, and the switching noise generated by the power inductor and switching nodes does not run directly parallel to the long distance of the identification communication line.

[0030] In this embodiment, the ESD protection device is positioned between the integrated line interface and the interface identification circuit, with the ground terminal of the ESD protection device connected to a continuous reference plane. When an electrostatic discharge (ESD) event enters from the integrated line interface, it is first discharged to the continuous reference plane via the ESD protection device before reaching the electrical boundary before the main control, BMS sampling, or fast charging protocol identification circuit. If the interface identification signal pad area and the thermal potting compound filling space are adjacent on the board projection, the potting compound path's exit point avoids the interface identification signal pad area, ensuring the pad connection status of the identification communication line remains detectable. The intermediate state of this implementation includes three types of partitioning of the interface output line, the ground reference protection area of ​​the identification communication line, the discharge path of the ESD protection device, and the boundary of the potting compound path avoiding the pad area. The output result is a PCB layout state where the interface area forms a large current output, and identification communication and ESD discharge are mutually partitioned.

[0031] The verification method in this embodiment can be completed through interface area layout review. During the review, it is checked whether the VBUS traces and high-current ground lines form short paths near the self-contained line interface, whether the identification communication line is located within the ground reference protection area, whether the discharge path of the ESD protection device is first connected to the continuous reference plane, and whether the thermal potting compound filling space avoids the interface identification signal pad area. If all the above checks are satisfied, it indicates that there are distinguishable electrical boundaries between the high-current output path, signal transmission path, and electrostatic discharge path in the interface area, which can support the connection and identification process of the self-contained line interface.

[0032] Example 3 Please see Figure 1-5 This embodiment provides a PCB layout method for a high-power-density mobile power supply with built-in lines. The difference between this embodiment and Embodiment 1 is that the routing from the power conversion end to the built-in line interface end is implemented with parallel conductive paths as the main constraint, focusing on limiting the electrical connection relationship between high-current copper foil, multiple via parallel structure and inner copper layer; the remaining board layer planning, functional partitioning, signal isolation, active equalization control support and thermal management configuration can adopt the corresponding implementation method in Embodiment 1.

[0033] After establishing the power conversion area and the self-connected line interface area according to Embodiment 1 in steps S1 to S4, step S5 configures the output path from the power conversion terminal to the self-connected line interface terminal as a parallel conductive path. Please refer to [link to previous steps]. Figure 1 and Figure 3 The high-current copper foil extends from the power conversion end to the self-connected line interface end. A multi-via parallel structure is set between the high-current copper foil and the inner copper layer. The inner copper layer covers the projected area of ​​the high-current copper foil along the output current direction. After the self-connected line output current enters the high-current copper foil from the power conversion end, part of it is transmitted along the high-current copper foil, and the other part enters the inner copper layer through the multi-via parallel structure, and then returns to the interface end connection area through the parallel vias near the self-connected line interface end. Thus, the high-current copper foil, the multi-via parallel structure, and the inner copper layer jointly bear the self-connected line output current, forming a parallel conductive state from the power conversion end to the self-connected line interface end.

[0034] In this embodiment, the location of the parallel via structure is distinct from the heat dissipation via array in the heat source area. The parallel via structure is used for current carrying, while the heat dissipation via array is used for heat transfer; when they are adjacent on the board surface, their electrical uses are distinguished by the layout hierarchy and network connection relationship. The network connection objects of the high-current copper foil are the power conversion terminal and the built-in line interface terminal, and the network connection objects of the inner copper layer are consistent with the output path; the connection objects of the first and second thermally conductive via groups are the heat dissipation pads, the inner copper layer, and the outer heat dissipation copper layer. If the same inner copper layer participates in both electrical and thermal conduction, its network connection should be consistent with the output path, and an uncontrolled high-current return path should be avoided below the analog sampling area. The intermediate state of this embodiment includes a conductive network formed by the high-current copper foil, the parallel via structure, and the inner copper layer, and a thermally conductive network formed by the heat dissipation pads, the thermally conductive via group, and the heat dissipation copper layer. The output result is that the current carrying path and the thermal conduction path have distinguishable connection targets and transmission directions within the same board surface.

[0035] The verification method in this embodiment can be completed through electrical network inspection and layout cross-sectional relationship inspection. Electrical network inspection confirms that the high-current copper foil, the parallel via structure, and the inner copper layer are all connected to the output network from the power conversion terminal to the self-contained line interface terminal. Layout cross-sectional relationship inspection confirms that the parallel via structure and the inner copper layer form a vertical conductive relationship, and that no high-current return path is formed below the simulated sampling area that crosses the sampling reference path. If the inspection results show that the output network is continuous, the via parallel relationship is clear, and the sampling reference area is not crossed by a high-current return path, it indicates that this embodiment has formed a parallel conductive layout capable of carrying the self-contained line output current.

[0036] Example 4 Please see Figure 1 , Figure 2 , Figure 4 and Figure 5 This embodiment provides a PCB layout method for a high power density mobile power supply with built-in lines. The difference between this embodiment and Embodiment 1 is that the active equalization control support and protection trigger boundary are the main implementation focus. Specifically, it explains the closed-loop relationship from sampling input to equalization current control quantity and protection device action; the remaining board layer planning, power path, interface path and thermal management path can adopt the corresponding implementation method in Embodiment 1.

[0037] After establishing the sampling area, power conversion area, and interface area according to Example 1 in steps S1 to S5, the BMS detection unit acquires the battery cell voltage, battery temperature, and charge / discharge current in step S6. Please refer to [link to relevant documentation]. Figure 4The voltage acquisition unit receives voltage sampling signals from each battery cell, the temperature sampling interface receives temperature sampling signals from the heat source area or the area near the battery connection, and the current detection circuit receives current detection signals from the main charging and discharging circuit. After receiving the above sampling results, the microcontroller converts the battery cell voltage into a voltage normalized value, the battery temperature into a temperature normalized value, and the state of charge (SOC) into a SOC normalized value. It also obtains voltage difference normalized values ​​and SOC difference normalized values ​​based on the differences between adjacent cells or between a single cell and the mean. This normalization process unifies the expression scale of different physical quantities in the fuzzy input set, avoiding direct comparison of data from different units.

[0038] The microcontroller writes the normalized values ​​of voltage, temperature, state of charge (SCC), voltage difference, and SCC difference into a fuzzy input set. When matching the fuzzy input set with preset fuzzy rules, it first determines the fuzzy interval to which each normalized input belongs, and then obtains the equalization strength level according to the preset fuzzy rules. If multiple fuzzy rules are matched simultaneously, the equalization strength level with the higher priority is retained according to the rule priority recorded in the protection parameter table; if no valid rule is matched, the output stops the equalization process as the default output. After obtaining the equalization strength level, the microcontroller converts this level into an equalization current control quantity, which is sent as a drive signal to the equalization switching device. The equalization switching device changes its conduction state according to the equalization current control quantity, and the equalization inductor and equalization energy storage capacitor establish an energy transfer path between the higher-voltage and lower-voltage cells. After completing one equalization operation, the voltage acquisition unit re-acquires the individual battery cell voltages, re-forms the next round of normalized voltage and voltage difference values, and uses them as feedback inputs.

[0039] During the protection triggering process, the microcontroller compares the individual battery cell voltage with the overvoltage and undervoltage thresholds, and the charging / discharging current with the overcurrent threshold. These thresholds are provided by the battery protection parameter table; values ​​equal to the threshold boundaries trigger the protection condition. When the protection condition is met, the microcontroller stops outputting the equalization current control signal and outputs a cut-off or current-limiting control signal to the protection device. When the protection condition is not met, the microcontroller continues to output the equalization current control signal based on the fuzzy input set. Upon receiving the cut-off or current-limiting control signal, the protection device changes the conduction state of the charging / discharging main circuit, and the state of the main circuit is then fed back to the microcontroller by the current detection circuit. This process forms a physical technology chain encompassing power input, signal acquisition, state determination, control commands, switching actions, load response, and feedback protection.

[0040] The verification method in this embodiment can be completed through control signal link review and status readback review. Control signal link review is used to confirm the input-output relationship between the voltage acquisition unit, temperature sampling interface, current detection circuit, microcontroller, equalization switching device, and protection device; status readback review is used to confirm that the voltage acquisition unit can re-output the battery cell voltage after equalization action, and the current detection circuit can re-output the charging and discharging current after protection action. If there are clear receivers and subsequent uses among the sampling input, normalization processing, fuzzy rule matching, equalization current control output, protection device action, and feedback sampling, it indicates that the active equalization control support and protection trigger boundary of this embodiment form a closed loop.

[0041] The four-layer board stacking, functional partitioning, single-point grounding, high-current path arrangement, interface partitioning, active balancing control support, heat dissipation via array, and heat dissipation potting compound filling space described in the above embodiments are only used to explain the possible implementations of the present invention. The interface routing methods, parallel conductive paths, balancing control chains, and thermal management paths in different embodiments can be equivalently replaced, modified, combined, ordered, or have their field names changed, or their execution entities or carrier forms altered, without changing the technical solutions described in the present invention or the scope of the original disclosure. Equivalent implementations formed by those skilled in the art within the above scope should all fall within the protection scope of this patent; however, they must not be extended to independent protected subjects not recorded in the application documents, nor should the substantive correspondence of the technical objects be changed through changes in drawing numbers, reference numerals, or names.

Claims

1. A PCB layout method for a high-power-density mobile power supply with integrated wiring, characterized in that, Includes the following steps: The power bank PCB is designed with a four-layer stack-up, dividing the board into power layer, ground layer and signal layer. The layer close to the high current path is configured as a low impedance power return channel, the ground layer is configured as a continuous reference plane, and the signal layer is configured as the transmission area to carry BMS sampling signals, control signals and interface identification signals. On the PCB of the power bank, a partitioned layout is established around the battery pack, charging management chip, boost chip or bidirectional converter, BMS detection unit, active balancing drive unit, built-in line interface and protection device, so that the battery status detection, charging and discharging power conversion, interface output and protection trigger are located in the same board surface as a continuous electrical link. Set the power ground and analog ground to a single-point connection, and ensure that the return paths of battery current, boost switch current and self-contained line output current avoid the analog sampling area; The charging management chip, boost chip or bidirectional converter, power inductor, energy storage capacitor, power switching device and built-in line interface are placed compactly according to the current flow direction, shortening the routing distance from the battery end to the power conversion end and from the power conversion end to the built-in line interface end, so that the switching node, power inductor and energy storage capacitor form a small area high-frequency switching loop around the corresponding chip. The copper foil traces that carry the charging and discharging current and the self-generated line output current are set as wide traces and connected to the inner copper layer through multiple parallel vias. The traces of BMS sampling signals, control signals and interface identification signals are arranged away from power inductors and switching nodes, and ESD protection devices are arranged near the self-contained line interface so that the electrostatic discharge path is first connected to the continuous reference plane. Heat dissipation pads, via arrays, and large copper areas are set in the heat source areas corresponding to the heat-generating chips, power inductors, power switching devices, and built-in line interfaces, and space for heat dissipation potting compound is reserved around the heat source areas.

2. The PCB layout method for a high-power-density mobile power supply with integrated wiring as described in claim 1, characterized in that: The four-layer board stack-up plan includes setting the power layer and the ground layer adjacent to each other, so that the high-current copper foil in the power layer forms a short return path through the ground layer; The BMS sampling signal, the control signal, and the interface identification signal in the signal layer use the formation as a reference plane; The single-point connection between the power ground and the analog ground is located at the common return node between the negative terminal of the battery pack and the power conversion return terminal, and the sampling reference point of the analog sampling area is led out from the common return node.

3. The PCB layout method for a high-power-density mobile power supply with integrated wiring as described in claim 2, characterized in that: The BMS detection unit includes a voltage sampling interface, a temperature sampling interface, a current detection circuit, and an analog-to-digital converter; The sampling lines of the voltage sampling interface are led out in sequence according to the battery pack terminals, and are spaced apart from the switching nodes of the power switching device before entering the analog-to-digital converter; The sampling traces of the temperature sampling interface are arranged near the heat source area and avoid the edge magnetic field area of ​​the power inductor. The detection terminal of the current detection circuit is connected to the main charging and discharging circuit, and the detection signal is sent to the analog-to-digital converter through the analog sampling area.

4. The PCB layout method for a high-power-density mobile power supply with integrated wiring as described in claim 1, characterized in that: The wiring from the power conversion terminal to the self-contained line interface terminal is arranged in sections according to VBUS wiring, high current ground wire and identification communication line. The VBUS trace and the high-current ground trace are located near the board edge area of ​​the built-in line interface and are routed using short-path straight lines. The identification communication line is located within the ground reference protection area between the VBUS trace and the power inductor, and is isolated from the VBUS trace by adjacent ground copper.

5. The PCB layout method for a high-power-density mobile power supply with integrated wiring as described in claim 1, characterized in that: The traces from the power conversion terminal to the self-contained line interface terminal form a parallel conductive path using high-current copper foil, multiple via parallel structure and inner copper layer. The high-current copper foil extends from the power conversion end to the self-contained wire interface end; The multi-via parallel structure is disposed between the high-current copper foil and the inner copper layer, so that the high-current copper foil, the multi-via parallel structure, and the inner copper layer jointly carry the self-contained line output current.

6. The PCB layout method for a high-power-density mobile power supply with integrated wiring as described in claim 1, characterized in that: When the battery pack includes multiple cells connected in series or in parallel, an independent power balancing zone is set on the mobile power PCB. The independent equalization power zone includes an active equalization chip, a microcontroller, a voltage acquisition unit, equalization switching devices, an equalization inductor, and an equalization energy storage capacitor. The active balancing chip, the balancing switch device, the balancing inductor, and the balancing energy storage capacitor are arranged compactly around the energy transfer path; An interval wiring area is set between the independent equalization power area and the analog sampling area, and the cascaded communication traces are arranged along a continuous reference ground.

7. The PCB layout method for a high-power-density mobile power supply with integrated wiring as described in claim 6, characterized in that: The microcontroller receives the individual cell voltage from the voltage acquisition unit, the battery temperature from the temperature sampling interface, and the state of charge obtained from the current detection circuit and the individual cell voltage. The voltage of the individual battery cell, the battery temperature, and the state of charge are normalized to obtain normalized voltage values, normalized temperature values, and normalized state of charge values. A fuzzy input set is formed based on the normalized voltage value, the normalized temperature value, the normalized state of charge value, and the normalized voltage difference and state of charge difference values ​​between adjacent cells; The fuzzy input set is matched with a preset fuzzy rule to obtain the equalization intensity level, and the equalization intensity level is converted into an equalization current control quantity; The equalization current control quantity is used to drive the equalization switching device, so that the equalization inductor and the equalization energy storage capacitor transfer energy between the higher voltage cell and the lower voltage cell.

8. The PCB layout method for a high-power-density mobile power supply with integrated wiring as described in claim 7, characterized in that: When the state of charge is in the low state of charge range or the high state of charge range, the microcontroller uses the normalized voltage value and the normalized voltage difference value as high-priority inputs. When the state of charge is in the intermediate state of charge range, the microcontroller uses the normalized value of the state of charge and the normalized value of the state of charge difference as high-priority inputs. When the voltage of a single battery cell output by the voltage acquisition unit exceeds the overvoltage judgment threshold or falls below the undervoltage judgment threshold, or when the current output by the current detection circuit exceeds the overcurrent judgment threshold, the microcontroller stops outputting the equalization current control quantity and outputs a cut-off or current limiting control signal to the protection device. The overvoltage determination threshold, the undervoltage determination threshold, and the overcurrent determination threshold are provided by the battery protection parameter table, and when they are equal to the threshold boundary, they are included in the trigger protection condition.

9. The PCB layout method for a high-power-density mobile power supply with integrated wiring according to claim 1, characterized in that: The via array includes a first thermally conductive via group located below the heat dissipation pad and a second thermally conductive via group located around the heat source region. The first thermal via group connects the heat dissipation pad to the inner copper layer; The second thermal via group connects the inner copper layer to the outer heat dissipation copper layer; The heat-dissipating potting compound fills the space along the gap between the heat-generating chip, the power inductor, the power switching device, and the battery connection area, so that the flow path of the potting compound covers the heat-conducting areas corresponding to the first thermally conductive via group and the second thermally conductive via group.

10. The PCB layout method for a high-power-density mobile power supply with integrated wiring as described in claim 9, characterized in that: When determining the filling space of the heat dissipation potting compound, the heat source area, the interface insulation protection area and the battery connection area are divided into potting coverage areas; Configure the dispensing path, dispensing position, and dispensing time for the dispensing coverage area so that the mixed heat-dissipating potting compound enters the heat-dissipating potting compound filling space from the dispensing position; When the potting path passes near the self-connected interface, the dispensing position avoids the pad area of ​​the interface identification signal, and the heat dissipation potting compound fills the space to retain the discharge path of the ESD protection device to the continuous reference plane.

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