Method for manufacturing a plated structure with stub inhibition and printed circuit board

Abstract

The application discloses a kind of inhibiting stubs electroplating structure manufacturing method and printed circuit board, wherein the method comprises: manufacturing multilayer PCB substrate by pressing, the PCB substrate is mechanically drilled, and a plurality of through holes are obtained;By depositing flash plating, a metal layer is formed on the hole wall of the through hole, a layer of photosensitive adhesive film is made on the surface of the PCB substrate, and the position needing secondary electroplating is opened window by exposure process;Back drilling is carried out, the excess metal layer in the hole wall of the through hole is removed except the metal layer needing connection, and back drilling hole with stub is formed;Secondary electroplating is carried out on the back drilling hole, and the metal layer of secondary electroplating wraps the port edge of stub, to obtain the electroplating structure inhibiting stubs.The application can solve the problems that burr is difficult to eradicate in traditional back drilling process and stub (stub) tip effect is obvious.

Description

Technical Field

[0001] This invention relates to the field of high-frequency and high-speed printed circuit board precision manufacturing technology, and in particular to a method for manufacturing an electroplated structure to suppress residual chips and a printed circuit board. Background Technology

[0002] With the rapid iteration of products in fields such as 5G communication, high-speed servers, AI computing boards, and high-end industrial control, electronic products are showing a development trend of high frequency, high speed, high density, and low loss. As the core carrier for electrical interconnection and signal transmission, the processing accuracy of its via interconnect structure directly determines the signal integrity performance of the whole machine.

[0003] Currently, multilayer high-frequency and high-speed PCB products commonly employ metallized through-hole structures. The excess ends of these through-holes form suspended metal stubs. Under high-frequency signal transmission conditions, these suspended stubs are equivalent to parasitic transmission lines with one open end, easily causing adverse electrical effects such as impedance discontinuities, signal reflections, resonant crosstalk, and transmission delays. The industry commonly uses back-drilling to remove these excess stubs; however, existing back-drilling processes are limited by drill bit structure, drilling parameters, fiberglass substrate, copper ductility, and machine tool positioning accuracy. The break point of the back-drilled section is prone to producing annular copper burrs, copper chips, and other sharp-point defects.

[0004] Currently, the industry relies solely on post-processing methods such as chemical micro-etching and sandblasting to remove burrs, which offers minimal improvement: micro-burrs are small in size and hidden deep within holes, making complete removal difficult; residual metal burrs form irregular parasitic conductors, generating stray capacitance and parasitic inductance, inducing signal resonance, increasing insertion loss, and worsening return loss, resulting in waveform distortion and increased bit error rate. Simultaneously, burrs create an electron tip effect, causing copper ion ionization, leading to risks such as micro-short circuits, decreased insulation impedance, and reduced plate pressure resistance. At present, the industry only focuses on optimizing stub length and drilling precision, without addressing the burr generation mechanism and high-frequency coupling interference through specific electroplating process optimizations. There is a lack of electroplating processing solutions that suppress burrs at the source and optimize fracture structure. Summary of the Invention

[0005] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a method for manufacturing an electroplated structure and a printed circuit board for suppressing stubs, which can solve technical problems such as the difficulty in eliminating burrs in traditional back-drilling processes, the obvious tip effect of stubs, severe high-frequency interference, and poor product reliability.

[0006] A method for manufacturing an electroplated structure for suppressing residual piles according to a first aspect embodiment of the present invention includes: A multi-layer PCB substrate is manufactured by lamination, and then the PCB substrate is mechanically drilled to obtain multiple through holes. A metal layer is formed on the wall of the via by deposition flash plating, a photosensitive film is made on the surface of the PCB substrate, and the area that needs to be electroplated is exposed by exposure process. Back drilling is performed to remove the excess metal layer from the hole wall of the through hole, except for the metal layer that needs to be connected, to form a back drill hole with residual pile. A second electroplating process is performed on the back drilled hole, so that the metal layer of the second electroplating wraps around the edge of the residual pile, resulting in an electroplating structure that suppresses the residual pile.

[0007] In one embodiment, the method further includes: Resin is inserted into the back-drilled holes after secondary electroplating, and excess resin and the photosensitive film on the surface are removed to form buried vias. After capping and electroplating, a conductive layer is formed by etching, allowing for arbitrary layer addition and interconnection (HDI). Solder resist ink is then screen-printed on the surface of the PCB substrate to obtain the finished printed circuit board.

[0008] In one embodiment, the photosensitive film is a photosensitive organic resin film with a thickness of 25±5μm, or other thicknesses are acceptable.

[0009] In one embodiment, the metal layer is a copper layer with a thickness of 5 to 8 μm or other specifications.

[0010] In one embodiment, the area requiring secondary electroplating is exposed by an exposure process, including: By using an exposure process, the opening position of the through hole that requires secondary electroplating is expanded outward by 25μm or other specifications based on the pad size, thus creating a window for exposure.

[0011] In one embodiment, the back-drilled hole is subjected to secondary electroplating, so that the secondary electroplated metal layer covers the edge of the residual pile port, including: A second electroplating copper process is customized for the residual pile areas of through holes and back drill holes to control the electroplating deposition rate and ensure that the electroplated copper layer uniformly covers the residual pile. The irregular fracture surface of the back drill is filled and shaped with metal to transform the fracture surface into a smooth, circular encapsulated structure.

[0012] Secondly, this application also proposes an electroplating structure for suppressing residual piles, which is manufactured based on the method of any of the above embodiments; the electroplating structure for suppressing residual piles includes a PCB substrate and a back-drilled hole disposed on the PCB substrate, the inner wall of the back-drilled hole is covered with a metal layer, and the broken edge of the residual pile in the back-drilled hole is wrapped by the electroplated metal layer to form a smooth circular wrapping structure.

[0013] In one embodiment, the original metal layer covering the residual pile is a copper layer with a thickness of 5-8 μm or other specifications.

[0014] In one embodiment, the radius of the arc of the smooth circular wrapping structure is related to the thickness of the copper layer.

[0015] Thirdly, this application also proposes a printed circuit board including an electroplating structure for suppressing residual piles as described in any of the above embodiments.

[0016] The aforementioned method for manufacturing an electroplated structure and printed circuit board for suppressing residual studs includes the following steps: manufacturing a multilayer PCB substrate by lamination; mechanically drilling the PCB substrate to obtain multiple through holes; forming a metal layer on the hole walls by flash deposition; fabricating a photosensitive adhesive film on the surface of the PCB substrate; and exposing the areas requiring secondary electroplating through an exposure process; performing back drilling to remove excess metal layers from the hole walls of the through holes, except for the metal layer to be connected, to form back-drilled holes with residual studs; and performing secondary electroplating on the back-drilled holes. The secondary electroplating of the metal layer wraps around the edge of the stub's port, creating an electroplating structure that suppresses the stub's formation. This suppresses the generation of copper burrs at the back-drilled fracture site from the source. Combined with the secondary electroplating, the stub fracture is smoothly shaped, completely eliminating the tip effect of metal burrs. This avoids stray capacitance and parasitic inductance caused by burrs, significantly reducing insertion loss and return loss during high-frequency signal transmission, suppressing signal resonance and waveform distortion, and greatly improving the signal integrity of high-frequency, high-speed PCBs, meeting the high-frequency electrical performance requirements of AI computing boards and high-end server boards.

[0017] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present application. Attached Figure Description

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein: Figure 1 This is a schematic flowchart of the method for manufacturing an electroplated structure to suppress residual piles according to an embodiment of the present invention; Figure 2 This is a simplified process flow for the manufacturing method of the electroplated structure for suppressing residual piles according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the structural changes of a PCB substrate through mechanical drilling according to an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the structural changes of the present invention, including the formation of a metal layer on the hole wall by deposition flash plating, the fabrication of a photosensitive adhesive film on the surface of the PCB substrate, and back drilling processing. Figure 5 This is a schematic diagram illustrating the structural changes of the printed circuit board used for secondary electroplating and obtaining the finished product, according to an embodiment of the present invention.

[0019] Reference numerals: PCB substrate 100, multiple through holes 101, metal layer 102, photosensitive film 201, single-sided back drill hole 103, double-sided back drill hole 104, residual stud 105, secondary electroplated metal layer 106, smooth circular wrapping structure 107, resin 301, solder resist ink 401. Detailed Implementation

[0020] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0021] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0022] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0023] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0024] In the description of this invention, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0025] With the rapid iteration of products in fields such as 5G communication, high-speed servers, AI computing boards, and high-end industrial control, electronic products are showing a development trend of high frequency, high speed, high density, and low loss. As the core carrier for electrical interconnection and signal transmission, the processing accuracy of its via interconnect structure directly determines the signal integrity performance of the whole machine.

[0026] Currently, multilayer high-frequency and high-speed PCB products commonly employ metallized through-hole structures. The excess ends of these through-holes form suspended metal stubs. Under high-frequency signal transmission conditions, these suspended stubs are equivalent to parasitic transmission lines with one open end, easily causing adverse electrical effects such as impedance discontinuities, signal reflections, resonant crosstalk, and transmission delays. The industry commonly uses back-drilling to remove these excess stubs; however, existing back-drilling processes are limited by drill bit structure, drilling parameters, fiberglass substrate, copper ductility, and machine tool positioning accuracy. The break point of the back-drilled section is prone to producing annular copper burrs, copper chips, and other sharp-point defects.

[0027] Currently, the industry relies solely on post-processing methods such as chemical micro-etching and sandblasting to remove burrs, which offers minimal improvement: micro-burrs are small in size and hidden deep within holes, making complete removal difficult; residual metal burrs form irregular parasitic conductors, generating stray capacitance and parasitic inductance, inducing signal resonance, increasing insertion loss, and worsening return loss, resulting in waveform distortion and increased bit error rate. Simultaneously, burrs create an electron tip effect, causing copper ion ionization, leading to risks such as micro-short circuits, decreased insulation impedance, and reduced plate pressure resistance. At present, the industry only focuses on optimizing stub length and drilling precision, without addressing the burr generation mechanism and high-frequency coupling interference through specific electroplating process optimizations. There is a lack of electroplating processing solutions that suppress burrs at the source and optimize fracture structure.

[0028] Based on the aforementioned technical problems, this application proposes a method for manufacturing an electroplating structure and a printed circuit board to suppress stub burrs. It is understood that this application relates to the field of high-frequency, high-speed printed circuit board precision manufacturing technology, specifically to an electroplating structure and manufacturing method for suppressing stub burrs from back-drilling processes. This is applicable to the mass production of high-end high-frequency, high-speed printed circuit boards for 5G communication, high-speed servers, AI computing boards, etc., and is particularly suitable for precision PCB products with back-drilling structures, specifically addressing technical problems such as burrs at the break points and high-frequency signal interference in the back-drilling process. This invention addresses the technical pain points of traditional back-drilling processes, such as the difficulty in eliminating burrs, significant stub tip effects, severe high-frequency interference, and poor product reliability, by proposing an electroplating structure and manufacturing method for suppressing stub burrs from back-drilling processes.

[0029] Specifically, the core technical points of this application are as follows: 1. Through-hole pre-installed ultra-thin copper layer structure design: After machine drilling through holes, a combination of immersion copper plating and flash plating process is used to form an ultra-thin metallized copper layer of 5~8μm on the hole wall; by utilizing the low ductility and dense adhesion of the thin copper layer, the frictional resistance between the drill bit and the copper layer on the hole wall is greatly reduced during back drilling, and the generation of burrs and copper chips at the stub copper fracture position is suppressed from the source of the process, fundamentally improving the burr defects of back drilling stubs (residual piles).

[0030] 2. Board surface protection + precision window opening auxiliary structure: Before back drilling, a 25±5μm photosensitive organic resin protective film is prepared on the board surface. The required window is opened through the exposure process. The opening of the hole is based on the pad size and expanded outward by 25μm. This avoids the stepped copper caused by the electroplating structure of the outer pad. It is mainly used for the secondary electroplating of hole copper, and at the same time protects the thin copper surface from scratches caused by back drilling and other processes.

[0031] 3. Optimized secondary electroplating and shaping process after back drilling: After completing the back drilling with photosensitive organic resin film, a customized secondary electroplating copper process is carried out for the through holes and the stub area of ​​the back drill hole. The electroplating deposition rate is precisely controlled so that the electroplated copper layer uniformly covers the thin copper stub (residual stud). The irregular fracture of the back drill is filled and shaped with metal, and the uneven fracture is repaired into a smooth circular wrapping structure, completely eliminating the burrs on the metal tip.

[0032] 4. Optimized anti-burr process design: The process of thin copper pre-placement, photosensitive organic resin film protection, back drilling, and electroplating shaping is linked and matched, and the process parameters of each process are optimized to form a closed-loop anti-burr processing flow. There is no need to add an additional deburring post-process, which meets the product processing quality requirements.

[0033] The beneficial effects of this application are as follows: Excellent electrical performance: This invention suppresses the generation of copper burrs at the back-drilled fracture site from the source, and combines secondary electroplating of the hole copper to complete the smooth shaping of the stub fracture, completely eliminating the tip effect of metal burrs; it avoids stray capacitance and parasitic inductance generated by burrs, significantly reduces insertion loss and return loss in the high-frequency signal transmission process, suppresses signal resonance and waveform distortion, greatly improves the signal integrity of high-frequency and high-speed PCBs, and meets the high-frequency electrical performance requirements of AI computing boards and high-end server boards.

[0034] Improve product electrical performance reliability: Thoroughly remove residual burrs from back drills, eliminate the risk of micro-short circuits and copper ion ionization caused by burrs, stabilize interlayer insulation spacing, effectively improve product withstand voltage performance and insulation, reduce the probability of product failure during use, and enhance the long-term reliability of high-end PCBs.

[0035] Simplified production process: No need for strong corrosion post-deburring processes such as chemical micro-etching and sandblasting, streamlining the production process and shortening processing time.

[0036] The circuit capability is indicated; after the through-hole is applied, a thin copper plating process is used in combination with a secondary electroplating process to make the copper on the surface of the product thin and uniform, which is suitable for the high-end PCB manufacturing process requirements of dense fine lines.

[0037] High process versatility: No need to modify existing drilling, electroplating, and coating production equipment, high process compatibility, can be adapted to the production of various multilayer high-frequency and high-speed PCBs with back-drilling structure, and high process stability.

[0038] The following is in conjunction with the appendix Figure 1-5 This application describes in detail the manufacturing method of the electroplating structure for suppressing residual piles and the printed circuit board according to embodiments of this application. Reference Figure 1 This application proposes a method for manufacturing an electroplated structure to suppress residual piles, comprising steps 100 to 400, wherein: Step 100: A multi-layer PCB substrate is manufactured by lamination, and the PCB substrate is mechanically drilled to obtain multiple through holes.

[0039] Specifically, refer to Figure 2 A multi-layered PCB substrate is laminated together, and through holes that require back drilling are drilled using a mechanical machine.

[0040] For example, refer to Figure 3 A multi-layer PCB circuit board 100 is manufactured by lamination; the completed electronic circuit board is then machined to drill multiple through holes 101.

[0041] Step 200: A metal layer is formed on the wall of the via by deposition flash plating, a photosensitive film is made on the surface of the PCB substrate, and the area that needs to be electroplated is exposed by exposure process.

[0042] The metal layer can refer to a thin layer of copper.

[0043] Specifically, refer to Figure 2 The copper plating process forms a thin layer of copper on the wall of the through hole and a thin photosensitive film on the copper surface of the PCB substrate. The area to be exposed is then opened by exposure.

[0044] For example, refer to Figure 4 To enable functional interconnection of the inner conductive signal layer, a thin copper layer 102 is formed on the hole wall by deposition flash plating; a photosensitive organic resin film 201 is made on the board surface by lamination or screen printing, and the areas that need to be electroplated are exposed by exposure.

[0045] Step 300: Perform back drilling to remove excess metal layers from the hole wall of the through hole, except for the metal layer that needs to be connected, to form a back drill hole with residual pile.

[0046] Specifically, refer to Figure 2 Back drilling is performed to remove the excess metal layer from the hole wall of the through hole, except for the metal layer that needs to be connected, to form a back drill hole with a stub. This process is called back drilling to remove excess stubs.

[0047] Optionally, refer to Figure 4 According to the interconnection requirements of the conductive layer in the product design, the excess copper on the hole wall is removed by back drilling (the process of removing excess copper on the hole wall by secondary drilling on the through hole is commonly known as back drilling process), leaving only the part that needs to be connected between the metal layers, forming multiple single-sided back drilled holes 103 and double-sided back drilled holes such as 104 at different depths; the part that extends beyond the inner copper metal layer after back drilling is a stub 105.

[0048] Step 400: Perform secondary electroplating on the back drilled hole, so that the metal layer of the secondary electroplating wraps around the edge of the residual pile, thereby obtaining an electroplating structure that suppresses the residual pile.

[0049] Specifically, secondary electroplating is used to thicken the copper metal on the hole walls.

[0050] For example, refer to Figure 5 The secondary electroplating of a copper layer 106 meets the requirements for the thickness of the copper on the hole wall; the secondary electroplating process wraps the thin copper stub section of the hole wall with copper as shown in 107.

[0051] In one exemplary embodiment, the method further includes: Resin is inserted into the back-drilled hole after secondary electroplating to remove excess resin and photosensitive film from the surface of the PCB substrate, forming buried vias. After cap electroplating on the surface of the PCB substrate, a conductive layer is formed by etching for arbitrary layer addition and interconnection. Solder resist ink is screen-printed on the surface of the PCB substrate to obtain the finished printed circuit board.

[0052] Optionally, refer to Figure 5 Remove the photosensitive organic resin film and etch away the base copper; form the outer conductive circuit, that is, form the conductive circuit layer; seal the vias with resin 301; screen print the surface solder resist ink 401 to complete the PCB finished structure, that is, the finished printed circuit board.

[0053] The above-mentioned method for manufacturing electroplated structures to suppress residual stubs can achieve the following technical effects: 1. Excellent electrical performance: This invention suppresses the generation of copper burrs at the back-drilled fracture site from the source, and combines secondary electroplating of copper holes to complete the smooth shaping of the stub fracture, completely eliminating the tip effect of metal burrs; avoiding stray capacitance and parasitic inductance generated by burrs, significantly reducing insertion loss and return loss in the high-frequency signal transmission process, suppressing signal resonance and waveform distortion, greatly improving the signal integrity of high-frequency and high-speed PCBs, and meeting the high-frequency electrical performance requirements of AI computing boards and high-end server boards. 2. Improved product electrical performance reliability: Completely removes residual burrs from back-drilling, eliminates the hidden dangers of micro-short circuits and copper ionization caused by burrs, stabilizes the interlayer insulation spacing, effectively improves the product's withstand voltage performance and insulation, reduces the probability of product failure during use, and enhances the long-term reliability of high-end PCBs. 3. Simplified production process: No need to use strong corrosion post-deburring processes such as chemical micro-etching and sandblasting, simplifying the production process and shortening processing time. 4. Enhanced Circuit Capability: The through-hole process employs a thin copper plating process combined with secondary electroplating to achieve a thin and uniform copper surface, meeting the demands of high-end PCB manufacturing processes with dense, fine lines. 5. Strong Process Versatility: No modification to existing drilling, electroplating, or lamination equipment is required. High process compatibility allows for adaptation to various multilayer, high-frequency, and high-speed PCB production with back-drilling structures, ensuring high process stability.

[0054] In one exemplary embodiment, the photosensitive film is a photosensitive organic resin film with a thickness of 25±5μm.

[0055] In one exemplary embodiment, the metal layer is a copper layer with a thickness of 5 to 8 μm.

[0056] Specifically, by defining the physical properties of the stub's constituent materials—namely, a thin copper layer with low ductility—even if a small amount of burrs are generated, their volume and sharpness are far lower than those of conventional thick copper layers, providing a good base for perfect encapsulation during secondary electroplating.

[0057] In one exemplary embodiment, the area requiring secondary electroplating is exposed by an exposure process, including: By using an exposure process, the orifice of the through-hole that requires secondary electroplating is expanded outward by 25μm based on the pad size, thus creating a window for exposure.

[0058] In one exemplary embodiment, a second electroplating is performed on the back-drilled hole, such that the second electroplated metal layer covers the edge of the residual pile port, including: A second electroplating copper process is customized for the residual pile areas of through holes and back drill holes to control the electroplating deposition rate and ensure that the electroplated copper layer uniformly covers the residual pile. The irregular fracture surface of the back drill is filled and shaped with metal to transform the fracture surface into a smooth, circular encapsulated structure.

[0059] In an exemplary embodiment, this application also proposes an electroplating structure for suppressing residual piles, which is manufactured based on the method of any of the above embodiments; the electroplating structure for suppressing residual piles includes a PCB substrate and a back-drilled hole disposed on the PCB substrate, the inner wall of the back-drilled hole is covered with a metal layer, and the broken edge of the residual pile in the back-drilled hole is wrapped by the electroplated metal layer to form a smooth circular wrapping structure.

[0060] In one exemplary embodiment, the original metal layer covering the residual pile is a copper layer with a thickness of 5~8μm.

[0061] In one exemplary embodiment, the radius of the arc of the smooth circular wrapping structure is related to the thickness of the copper layer.

[0062] Specifically, the arc shape is determined by both the mask thickness and the electroplating deposition rate, resulting in a predictable and controllable geometry.

[0063] In one exemplary embodiment, this application also proposes a printed circuit board including an electroplating structure for suppressing residual piles as described in any of the above embodiments.

[0064] Specifically, this application applies the above-mentioned electroplating structure to specific PCB products (such as 5G communication boards and AI computing boards), giving the entire PCB board excellent high-frequency signal integrity and high reliability.

[0065] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments, and various changes can be made within the scope of knowledge possessed by those skilled in the art without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof can be combined with each other unless otherwise specified.

Claims

1. A method for manufacturing an electroplated structure to suppress residual piles, characterized in that, include: A multi-layer PCB substrate is manufactured by lamination, and the PCB substrate is mechanically drilled to obtain multiple through holes. A metal layer is formed on the hole wall of the via by deposition flash plating, a photosensitive film is made on the surface of the PCB substrate, and the area that needs to be electroplated is exposed by exposure process. Perform back drilling to remove excess metal layers from the hole wall of the through hole, except for the metal layer that needs to be connected, to form a back drill hole with residual pile. The back-drilled hole is subjected to secondary electroplating, and the metal layer of the secondary electroplating wraps around the edge of the residual pile, thereby obtaining the electroplating structure that suppresses the residual pile.

2. The method according to claim 1, characterized in that, The method further includes: Resin is inserted into the back-drilled hole after secondary electroplating to remove excess resin and photosensitive film from the surface of the PCB substrate, forming buried vias. After cap electroplating on the surface of the PCB substrate, a conductive layer is formed by etching for arbitrary layer addition and interconnection. Solder resist ink is screen-printed on the surface of the PCB substrate to obtain the finished printed circuit board.

3. The method according to claim 1, characterized in that, The photosensitive film is a photosensitive organic resin film with a thickness of 25±5μm.

4. The method according to claim 1, characterized in that, The metal layer is a copper layer with a thickness of 5 to 8 μm.

5. The method according to claim 1, characterized in that, The process of exposing the areas requiring secondary electroplating through an exposure process includes: By using an exposure process, the orifice of the through-hole that requires secondary electroplating is expanded outward by 25μm based on the pad size, thus creating a window for exposure.

6. The method according to claim 1, characterized in that, The process of performing secondary electroplating on the back-drilled hole, so that the secondary electroplated metal layer covers the edge of the residual pile port, includes: A secondary electroplating copper process is customized for the residual pile areas of the through holes and back drill holes to control the electroplating deposition rate and ensure that the electroplated copper layer uniformly covers the residual pile. The irregular fracture surface of the back drill is filled and shaped with metal to transform the fracture surface into a smooth, circular encapsulated structure.

7. An electroplating structure for suppressing residual piles, characterized in that, The structure is manufactured based on the method described in any one of claims 1 to 6; the electroplated structure for suppressing residual piles includes a PCB substrate and a back-drilled hole disposed on the PCB substrate, the inner wall of the back-drilled hole is covered with a metal layer, and the broken edge of the residual pile in the back-drilled hole is wrapped by the electroplated metal layer to form a smooth circular wrapping structure.

8. The electroplating structure for suppressing residual piles according to claim 7, characterized in that, The original metal layer covering the remaining pile was a copper layer with a thickness of 5 to 8 μm.

9. The electroplating structure for suppressing residual piles according to claim 7, characterized in that, The radius of the arc of the smooth circular wrapping structure is related to the thickness of the copper layer.

10. A printed circuit board, characterized in that, Including the electroplating structure for suppressing residual piles as described in any one of claims 7-9.

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