Planar polysilicon channel cell for evaluating 3D flash characteristics and method of fabrication

Abstract

The application discloses a planar polysilicon channel cell for evaluating 3D flash memory characteristics, which comprises a first oxide layer and a first polysilicon layer doped with a second conductive type formed on the top surface of a semiconductor substrate. A shallow trench isolation is sequentially formed through the first polysilicon layer, the first oxide layer and the semiconductor substrate. In each active region, a gate structure is formed on the top surface of the first polysilicon layer, and the gate structure comprises an ONO layer and a polysilicon gate sequentially stacked; a source region and a drain region are formed in the first polysilicon layer on both sides of the gate structure, and the source region and the drain region are respectively self-aligned with the side surface of the corresponding gate structure. The application further discloses a manufacturing method of the planar polysilicon channel cell for evaluating 3D flash memory characteristics. The application can be realized by using an STI process and a common logic process, so that the process is simple and can be used for evaluating 3D flash memory characteristics.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory. This invention also relates to a method for manufacturing a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory. Background Technology

[0002] 3D NAND flash typically uses a columnar structure of flash memory cells. The channel region of the flash memory cell is composed of polysilicon filling the columnar structure. The gate strips formed by each gate structure intersect with each columnar structure. The area where the gate strips and columnar structures intersect corresponds to the polysilicon and is the channel region. The source region of each flash memory cell on the same columnar structure is connected to the drain region of the adjacent flash memory cell. Finally, the drain region of the topmost flash memory cell is connected to the bit line, and the source region of the bottommost flash memory cell is connected to the source line.

[0003] Each gate structure typically employs a stacked structure of an ONO layer and a gate conductive material layer, such as a polysilicon gate or a tungsten gate. The ONO layer comprises a tunneling oxide layer, a silicon nitride storage layer, and a barrier oxide layer stacked sequentially. The silicon nitride storage layer can trap charges to achieve information storage.

[0004] In the development of 3D flash memory, it is necessary to first evaluate its characteristics. Current methods for evaluating 3D flash memory characteristics typically employ a simple planar flash cell structure to verify these characteristics, experiment with erase, read, and write functions, and explore the mechanisms underlying these functions to verify the feasibility of the 3D flash structure. However, existing planar flash cell structures require SOI substrates, resulting in high manufacturing costs. Summary of the Invention

[0005] The technical problem to be solved by this invention is to provide a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory, which can be implemented using STI and conventional logic processes, thus the process is simple and can be used for evaluating the characteristics of 3D flash memory. To this end, this invention also provides a method for manufacturing the planar polysilicon channel cell for evaluating the characteristics of 3D flash memory.

[0006] To address the aforementioned technical problems, the planar polysilicon channel cell for evaluating 3D flash memory characteristics provided by this invention includes: A semiconductor substrate doped with a second conductivity type, a first oxide layer formed on the top surface of the semiconductor substrate, and a first polycrystalline silicon layer doped with a second conductivity type formed on the top surface of the first oxide layer.

[0007] A shallow trench isolation is formed sequentially through the first polysilicon layer, the first oxide layer, and the semiconductor substrate. The region surrounded by the shallow trench isolation is designated as the active region, and the first polysilicon layer located in the active region is designated as the channel layer.

[0008] In each of the active regions, a gate structure is formed on the top surface of the first polysilicon layer. The gate structure includes an ONO layer and a polysilicon gate stacked sequentially. A source region and a drain region of a first conductivity type are formed in the first polysilicon layer on both sides of the gate structure. The source region and the drain region are self-aligned with the side of the corresponding gate structure.

[0009] A further improvement is that sidewalls are formed on both sides of the gate structure.

[0010] Metal silicides are formed on the top surface of the polysilicon gate, the top surface of the source region, and the top surface of the drain region.

[0011] The top of the source region, the drain region, and the polysilicon gate are respectively led out through corresponding contact holes, a first metal layer, a first through-hole, and a second metal layer.

[0012] A further improvement is that the semiconductor substrate is made of silicon.

[0013] A further improvement is that the ONO layer comprises a tunneling oxide layer, a silicon nitride storage layer, and a barrier oxide layer stacked sequentially.

[0014] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0015] To address the aforementioned technical problems, the present invention provides a method for manufacturing a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory, comprising the following steps: A first oxide layer is formed on the top surface of a semiconductor substrate doped with a second conductivity type, and a first polycrystalline silicon layer doped with a second conductivity type is formed on the top surface of the first oxide layer.

[0016] A shallow trench isolation is formed that passes sequentially through the first polysilicon layer, the first oxide layer, and the semiconductor substrate. The region surrounded by the shallow trench isolation is designated as the active region, and the first polysilicon layer located in the active region is designated as the channel layer.

[0017] An ONO layer and a second polycrystalline silicon layer are formed sequentially.

[0018] The second polysilicon layer and the ONO layer are sequentially patterned and etched. The patterned and etched second polysilicon layer forms a polysilicon gate, and the ONO layer and the polysilicon gate are stacked to form a gate structure.

[0019] Source and drain implantation of a first conductivity type with the side of the gate structure as the self-alignment condition is performed to form source and drain regions in the first polysilicon layer on both sides of the gate structure of each active region.

[0020] A further improvement is that, after completing the source-drain injection, the method further includes: Sidewalls are formed on both sides of the gate structure.

[0021] Metal silicides are formed on the top surface of the polysilicon gate, the top surface of the source region, and the top surface of the drain region.

[0022] An interlayer film, contact holes, a front metal layer, and vias are formed; the front metal layer includes a first metal layer and a second metal layer; the contact holes pass through the interlayer film at the bottom of the first metal layer; the vias include a first-layer via, which passes through the interlayer film between the second metal layer and the first metal layer to achieve connection between the first metal layer and the second metal layer; the top of the source region, the drain region, and the polysilicon gate are respectively led out through the corresponding contact holes, the first metal layer, the first vias, and the second metal layer.

[0023] A further improvement is that the semiconductor substrate is made of silicon.

[0024] A further improvement is that the ONO layer comprises a tunneling oxide layer, a silicon nitride storage layer, and a barrier oxide layer stacked sequentially.

[0025] A further improvement is that the steps for forming the first polysilicon layer doped with the second conductivity type include: The first polysilicon layer is deposited without doping, and the deposition thickness of the first polysilicon layer is greater than the target thickness.

[0026] The first polycrystalline silicon layer is doped by ion implantation of a second conductivity type.

[0027] The first CMP is performed to planarize and thin the first polysilicon layer.

[0028] The first polysilicon layer is fully etched to reduce its thickness to the target thickness.

[0029] A further improvement is that the steps for forming the shallow trench isolation include: A first hard mask layer is formed on the top surface of the first polycrystalline silicon layer.

[0030] Photolithography is used to define the formation area of ​​the shallow trench, and the area surrounded by the shallow trench is the active region.

[0031] The shallow trench is formed by etching the first hard mask layer, the first polysilicon layer, the first oxide layer and the semiconductor substrate in sequence.

[0032] A second oxide layer is filled, which completely fills the shallow trench and extends beyond the shallow trench.

[0033] A second CMP is performed to remove the second oxide layer on the top surface of the first hard mask layer outside the shallow trench and to lower the top surface of the second oxide layer in the shallow trench to be level with the top surface of the shallow trench.

[0034] Wet etching is performed to further lower the top surface of the second oxide layer to be level with the top surface of the first polysilicon layer.

[0035] The first hard mask layer is removed, and the shallow trench isolation is formed by a second oxide layer that fills the shallow trench and whose top surface is flush with the top surface of the first polysilicon layer outside the shallow trench.

[0036] A further improvement is that, after depositing the second polysilicon layer, the process further includes: A second hard mask layer is formed on the top surface of the second polysilicon layer.

[0037] A further improvement is that the patterned etching includes: Photolithography is used to define the formation region of the gate structure.

[0038] The second hard mask layer, the second polysilicon layer, and the ONO layer are etched sequentially.

[0039] A further improvement is that the polysilicon gate is subjected to rapid thermal oxidation before the source / drain implantation is performed.

[0040] A further improvement is that the material of the first hard mask layer includes silicon nitride.

[0041] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0042] Unlike existing planar polysilicon channel cells for evaluating 3D NAND flash memory characteristics, which require an SOI substrate, this invention directly forms a first oxide layer on a semiconductor substrate, and then forms a first polysilicon layer on the first oxide layer. Combined with shallow trench isolation, a channel layer composed of the first polysilicon layers in each active region is obtained. The gate structure is formed on the top surface of the first polysilicon layer and is composed of an ONO layer and a polysilicon gate superimposed. The source and drain regions are formed on both sides of the gate structure. In this invention, both the gate structure and the source and drain regions can be implemented using logic processes commonly used in the art. The resulting device unit is a planar polysilicon channel cell, which can be used to evaluate 3D NAND flash memory characteristics. Therefore, the device of this invention can be implemented using STI process and ordinary logic process, making the process simple and suitable for evaluating 3D NAND flash memory characteristics. Attached Figure Description

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory according to an embodiment of the present invention; Figures 2-10 This is a schematic diagram of the device structure in each step of the manufacturing method of a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory according to an embodiment of the present invention. Detailed Implementation

[0044] like Figure 1 The diagram shown is a schematic of a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory according to an embodiment of the present invention; the planar polysilicon channel cell for evaluating the characteristics of 3D flash memory according to an embodiment of the present invention includes: A semiconductor substrate 101 doped with a second conductivity type, a first oxide layer 102 formed on the top surface of the semiconductor substrate 101, and a first polysilicon layer 103 doped with a second conductivity type formed on the top surface of the first oxide layer 102.

[0045] A shallow trench isolation 104 sequentially passes through the first polysilicon layer 103, the first oxide layer 102, and the semiconductor substrate 101. The region surrounded by the shallow trench isolation 104 is designated as the active region, and the first polysilicon layer 103 located within the active region serves as the channel layer. Figure 1 As shown, in this embodiment of the invention, the first oxide layer 102 is equivalent to a buried layer located between the first polysilicon layer 103 and the semiconductor substrate 101. However, in this embodiment of the invention, an SOI substrate is not required. Instead, the first polysilicon layer 103 formed on top of the first oxide layer 102 is directly used as the channel layer, taking advantage of the characteristic that polysilicon can be directly grown from the first oxide layer 102. Therefore, this embodiment of the invention has the feature of simple process.

[0046] In each of the active regions, a gate structure is formed on the top surface of the first polysilicon layer 103. The gate structure includes an ONO layer 104 and a polysilicon gate 105 stacked sequentially. A source region 107a and a drain region 107b of a first conductivity type are formed in the first polysilicon layer 103 on both sides of the gate structure. The source region 107a and the drain region 107b are self-aligned with the side of the corresponding gate structure.

[0047] In this embodiment of the invention, sidewalls 106 are also formed on both sides of the gate structure.

[0048] Metal silicide 108 is formed on the top surface of the polysilicon gate 105, the top surface of the source region 107a and the drain region 107b.

[0049] The tops of the source region 107a, the drain region 107b, and the polysilicon gate 105 are respectively led out through corresponding contact holes 110, a first metal layer (not shown), a first via (not shown), and a second metal layer (not shown). The contact holes 110 pass through the interlayer film 109. In other embodiments, the front metal layer can also have more layers, which can be set according to actual needs. After adding metal layers, corresponding via layers need to be added to realize the connection between the metal layers.

[0050] In this embodiment of the invention, the semiconductor substrate 101 is made of silicon.

[0051] The ONO layer 104 includes a tunneling oxide layer 104a, a silicon nitride storage layer 104b, and a barrier oxide layer 104c stacked sequentially.

[0052] In this embodiment of the invention, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0053] As can be seen, in the embodiments of the present invention, the gate structure, the source region 107a, and the drain region 107b can all be implemented using logic (LG) processes commonly used in the art. It can also be seen that the gate structure is a planar gate, and the channel region is composed of the first polysilicon layer 103 covered by the gate structure. Therefore, the embodiments of the present invention implement planar polysilicon channel cells. Such planar polysilicon channel cells can well simulate the performance of 3D NAND flash memory cells because existing 3D NAND flash memory cells also use polysilicon channels. In existing 3D NAND flash memory, the polysilicon channels of each flash memory cell in the same NAND string are filled in the same columnar structure. However, in the embodiments of the present invention, it is not necessary to use polysilicon with a columnar structure; a planar polysilicon channel can be used to achieve simulation. Therefore, the process structure of the embodiments of the present invention is simple and can simultaneously achieve the function of evaluating the characteristics of 3D NAND flash memory.

[0054] Unlike existing planar polysilicon channel cells for evaluating 3D flash memory characteristics, which require an SOI substrate, this embodiment of the invention directly forms a first oxide layer 102 on a semiconductor substrate 101, and a first polysilicon layer 103 on the first oxide layer 102, combined with shallow trench isolation 104 to obtain a channel layer composed of the first polysilicon layers 103 in each active region. The gate structure is formed on the top surface of the first polysilicon layer 103 and is formed by stacking an ONO layer 104 and a polysilicon gate 105. The source / drain regions 107b are formed on both sides of the gate structure. In this embodiment of the invention, both the gate structure and the source / drain regions 107b can be implemented using logic processes commonly used in the art. The resulting device unit is a planar polysilicon channel cell, which can be used to evaluate 3D flash memory characteristics. Therefore, the device in this embodiment of the invention can be implemented using STI process and ordinary logic process, so the process is simple and can be used to evaluate the characteristics of 3D flash memory.

[0055] like Figures 2 to 10 The diagram shown is a schematic representation of the device structure in each step of the manufacturing method for evaluating the characteristics of planar polysilicon channel cells of 3D flash memory according to an embodiment of the present invention. The manufacturing method for evaluating the characteristics of planar polysilicon channel cells of 3D flash memory according to an embodiment of the present invention includes the following steps: like Figure 2 As shown, a first oxide layer 102 is formed on the top surface of a semiconductor substrate 101 doped with a second conductivity type, and a first polysilicon layer 103 doped with a second conductivity type is formed on the top surface of the first oxide layer 102.

[0056] In the method of this embodiment of the invention, the material of the semiconductor substrate 101 includes silicon.

[0057] The steps for forming the first polysilicon layer 103 doped with the second conductivity type include: like Figure 2 As shown, a doped deposition process is performed on the first polysilicon layer 103, and the deposition thickness of the first polysilicon layer 103 is greater than the target thickness.

[0058] The first polycrystalline silicon layer 103 is doped by ion implantation of a second conductivity type.

[0059] like Figure 3 As shown, the first CMP is performed to planarize and thin the first polysilicon layer 103.

[0060] like Figure 3 As shown, the first polysilicon layer 103 is fully etched to reduce the thickness of the first polysilicon layer 103 to the target thickness.

[0061] A shallow trench isolation 104 is formed that passes sequentially through the first polysilicon layer 103, the first oxide layer 102 and the semiconductor substrate 101. The region surrounded by the shallow trench isolation 104 is designated as the active region, and the first polysilicon layer 103 located in the active region is designated as the channel layer.

[0062] In the method of this embodiment of the invention, the steps of forming the shallow trench isolation 104 include: like Figure 3 As shown, a first hard mask layer 201 is formed on the top surface of the first polysilicon layer 103.

[0063] In the method of this embodiment of the invention, the material of the first hard mask layer 201 includes silicon nitride.

[0064] like Figure 4 As shown, photolithography is performed to define the formation area of ​​the shallow trench 202, and the area surrounded by the shallow trench 202 is the active region.

[0065] like Figure 4 As shown, the shallow trench 202 is formed by etching the first hard mask layer 201, the first polysilicon layer 103, the first oxide layer 102 and the semiconductor substrate 101 in sequence.

[0066] like Figure 5 As shown, the second oxide layer, namely the oxide layer of the shallow trench isolation 104, completely fills the shallow trench 202 and extends outside the shallow trench 202.

[0067] like Figure 6 As shown, a second CMP is performed to remove the second oxide layer on the top surface of the first hard mask layer 201 outside the shallow trench 202 and to lower the top surface of the second oxide layer in the shallow trench 202 to be level with the top surface of the shallow trench 202.

[0068] like Figure 7 As shown, wet etching is performed to further lower the top surface of the second oxide layer to be level with the top surface of the first polysilicon layer 103.

[0069] like Figure 7 As shown, after removing the first hard mask layer 201, the shallow trench isolation 104 is formed by a second oxide layer that fills the shallow trench 202 and whose top surface is flush with the top surface of the first polysilicon layer 103 outside the shallow trench 202.

[0070] like Figure 8 As shown, an ONO layer 104 and a second polysilicon layer, namely the polysilicon gate 105, are formed sequentially.

[0071] In the method of this embodiment of the invention, the ONO layer 104 includes a tunneling oxide layer 104a, a silicon nitride storage layer 104b, and a barrier oxide layer 104c stacked sequentially.

[0072] In the method of this embodiment of the invention, after depositing the second polycrystalline silicon layer, the method further includes: A second hard mask layer 203 is formed on the top surface of the second polysilicon layer. In some embodiments, the material of the second hard mask layer 203 includes an oxide layer.

[0073] The second polysilicon layer and the ONO layer 104 are sequentially patterned and etched. The patterned and etched second polysilicon layer forms a polysilicon gate 105. The ONO layer 104 and the polysilicon gate 105 are stacked to form a gate structure.

[0074] In the method of this embodiment of the invention, the patterned etching includes: Photolithography is used to define the formation region of the gate structure.

[0075] The second hard mask layer 203, the second polysilicon layer, and the ONO layer 104 are etched sequentially.

[0076] The process also includes rapid thermal oxidation of the polysilicon gate 105 before subsequent source / drain implantation.

[0077] Source and drain implantation of a first conductivity type with the side of the gate structure as the self-alignment condition is performed to form source region 107a and drain region 107b in the first polysilicon layer 103 on both sides of the gate structure of each active region.

[0078] In the method of this embodiment of the invention, after the source-drain injection is completed, the method further includes: Sidewalls 106 are formed on both sides of the gate structure.

[0079] Metal silicide 108 is formed on the top surface of the polysilicon gate 105, the top surface of the source region 107a and the drain region 107b.

[0080] An interlayer film 109, a contact hole 110, a front metal layer, and a via are formed. The front metal layer includes a first metal layer and a second metal layer. The contact hole 110 passes through the interlayer film 109 at the bottom of the first metal layer. The via includes a first-layer via that passes through the interlayer film 109 between the second metal layer and the first metal layer, thus connecting the first metal layer and the second metal layer. The tops of the source region 107a, the drain region 107b, and the polysilicon gate 105 are respectively led out through the corresponding contact hole 110, the first metal layer, the first-layer via, and the second metal layer. In other embodiments, the number of front metal layers can be set as needed.

[0081] In the method of this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0082] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A planar polysilicon channel cell for evaluating the characteristics of 3D flash memory, characterized in that, include: A semiconductor substrate doped with a second conductivity type, a first oxide layer formed on the top surface of the semiconductor substrate, and a first polycrystalline silicon layer doped with a second conductivity type formed on the top surface of the first oxide layer; A shallow trench isolation is formed sequentially through the first polysilicon layer, the first oxide layer, and the semiconductor substrate. The region surrounded by the shallow trench isolation is designated as the active region, and the first polysilicon layer located in the active region is designated as the channel layer. In each of the active regions, a gate structure is formed on the top surface of the first polysilicon layer, the gate structure comprising an ONO layer and a polysilicon gate stacked sequentially. A source region and a drain region of a first conductivity type are formed in the first polysilicon layer on both sides of the gate structure, and the source region and the drain region are self-aligned with the side of the corresponding gate structure.

2. The planar polysilicon channel cell for evaluating 3D flash memory characteristics as described in claim 1, characterized in that: Sidewalls are also formed on both sides of the gate structure; Metal silicides are formed on the top surface of the polysilicon gate, the top surface of the source region, and the top surface of the drain region; The top of the source region, the drain region, and the polysilicon gate are respectively led out through corresponding contact holes, a first metal layer, a first through-hole, and a second metal layer.

3. The planar polysilicon channel cell for evaluating 3D flash memory characteristics as described in claim 1, characterized in that: The semiconductor substrate is made of silicon.

4. The planar polysilicon channel cell for evaluating 3D flash memory characteristics as described in claim 1, characterized in that: The ONO layer comprises a tunneling oxide layer, a silicon nitride storage layer, and a barrier oxide layer stacked sequentially.

5. The planar polysilicon channel cell for evaluating 3D flash memory characteristics as described in any one of claims 1 to 4, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

6. A method for manufacturing a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory, characterized in that, Includes the following steps: A first oxide layer is formed on the top surface of a semiconductor substrate doped with a second conductivity type, and a first polycrystalline silicon layer doped with a second conductivity type is formed on the top surface of the first oxide layer. A shallow trench isolation is formed that passes sequentially through the first polysilicon layer, the first oxide layer and the semiconductor substrate. The region surrounded by the shallow trench isolation is designated as the active region, and the first polysilicon layer located in the active region is designated as the channel layer. An ONO layer and a second polycrystalline silicon layer are formed sequentially; The second polysilicon layer and the ONO layer are sequentially patterned and etched, and the patterned and etched second polysilicon layer forms a polysilicon gate. The ONO layer and the polysilicon gate are stacked to form a gate structure. Source and drain implantation of a first conductivity type with the side of the gate structure as the self-alignment condition is performed to form source and drain regions in the first polysilicon layer on both sides of the gate structure of each active region.

7. The method for manufacturing a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory as described in claim 6, characterized in that: After the source-drain injection is completed, the following is also included: Sidewalls are formed on both sides of the gate structure; Metal silicides are formed on the top surface of the polysilicon gate, the top surface of the source region, and the top surface of the drain region; An interlayer film, contact holes, a front metal layer, and vias are formed; the front metal layer includes a first metal layer and a second metal layer; the contact holes pass through the interlayer film at the bottom of the first metal layer; the vias include a first-layer via, which passes through the interlayer film between the second metal layer and the first metal layer to achieve connection between the first metal layer and the second metal layer; the top of the source region, the drain region, and the polysilicon gate are respectively led out through the corresponding contact holes, the first metal layer, the first vias, and the second metal layer.

8. The method for manufacturing a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory as described in claim 6, characterized in that: The semiconductor substrate is made of silicon.

9. The method for manufacturing a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory as described in claim 6, characterized in that: The ONO layer comprises a tunneling oxide layer, a silicon nitride storage layer, and a barrier oxide layer stacked sequentially.

10. The method for manufacturing a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory as described in claim 6, characterized in that, The steps for forming the first polysilicon layer doped with the second conductivity type include: Perform a doped deposition process on the first polysilicon layer and the deposition thickness of the first polysilicon layer is greater than the target thickness; The first polycrystalline silicon layer is doped with ion implantation of a second conductivity type; The first CMP is performed to planarize and thin the first polysilicon layer; The first polysilicon layer is fully etched to reduce its thickness to the target thickness.

11. The method for manufacturing a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory as described in claim 6, characterized in that, The steps for forming the shallow trench isolation include: A first hard mask layer is formed on the top surface of the first polycrystalline silicon layer; Photolithography is used to define the formation area of ​​the shallow trench, and the area surrounded by the shallow trench is the active region; The shallow trench is formed by sequentially etching the first hard mask layer, the first polysilicon layer, the first oxide layer, and the semiconductor substrate. A second oxide layer is filled, which completely fills the shallow trench and extends beyond the shallow trench; A second CMP is performed to remove the second oxide layer on the top surface of the first hard mask layer outside the shallow trench and to lower the top surface of the second oxide layer in the shallow trench to be level with the top surface of the shallow trench. Wet etching is performed to further lower the top surface of the second oxide layer to be flush with the top surface of the first polysilicon layer; The first hard mask layer is removed, and the shallow trench isolation is formed by a second oxide layer that fills the shallow trench and whose top surface is flush with the top surface of the first polysilicon layer outside the shallow trench.

12. The method for manufacturing a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory as described in claim 6, characterized in that: After depositing the second polysilicon layer, the process further includes: A second hard mask layer is formed on the top surface of the second polysilicon layer.

13. The method for manufacturing a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory as described in claim 12, characterized in that: The patterning etching includes: Photolithography is performed to define the formation region of the gate structure; The second hard mask layer, the second polysilicon layer, and the ONO layer are etched sequentially.

14. The method for manufacturing a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory as described in claim 13, characterized in that: The process also includes rapid thermal oxidation of the polysilicon gate before the source / drain implantation.

15. The method for manufacturing a planar polysilicon channel cell for evaluating the characteristics of 3D flash memory as described in claim 11, characterized in that: The material of the first hard mask layer includes silicon nitride.

16. The method for manufacturing a planar polysilicon channel cell for evaluating 3D flash memory characteristics as described in any one of claims 6 to 15, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

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