Sonos devices with improved pgm efficiency and methods of manufacturing the same

Abstract

The application provides a SONOS device with improved PGM efficiency and a manufacturing method thereof. A memory cell of the SONOS device has six transistors, i.e. four control gates and two selection gates. The four control gates share the two selection gates. The selection gates are arranged in the gap between the two control gates with small spacing. The spacing between the selection gates and the control gates is the side wall width of the control gates. The PGM efficiency of the SONOS device is further improved, the memory cell area is further reduced, the manufacturing process is simple and easy to control, and mass production is easy.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a SONOS device for improving PGM efficiency and its manufacturing method. Background Technology

[0002] As the market demands increasingly higher integration levels for Flash memory devices, the contradiction between the reliability of data storage and the operating speed, power consumption, and size of traditional Flash devices is becoming increasingly prominent. SONOS devices, characterized by small cell size, low operating voltage, and compatibility with CMOS processes, will drive the development of semiconductor memories towards miniaturization, high performance, large capacity, and low cost as continuous improvements in SONOS technology.

[0003] Traditional SONOS storage devices are typically 2T in size, such as... Figure 1 As shown, a memory cell contains two transistors (control gate CG and select gate SG, with each CG having its own dedicated SG). The polysilicon gates CG and SG are patterned directly using a photomask through exposure and etching. From the process window, the spacing between CG and SG is relatively large, and only one memory cell can be set in one active region, which is not conducive to further miniaturization.

[0004] SONOS memory devices use a silicon-Oxide-Nitride-Oxide-Silicon (SONOS) gate stack layer instead of the floating gate structure in traditional Flash memory devices. This is a charge-trap type of memory, and programming efficiency (PGM) is crucial in SONOS devices. Figure 2 As shown, the programming mechanism of 2T SONOS is FN (Fowler Nordheim) Tunneling. This operation requires a high electric field and the PGM efficiency time reaches the millisecond level, which is relatively slow. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a SONOS device with improved PGM efficiency and a method for manufacturing the same, so as to solve the problem that the PGM efficiency of existing SONOS devices needs to be further improved.

[0006] To achieve the above and other related objectives, this application provides a SONOS device for improving PGM efficiency. The SONOS device has six transistors in one memory cell, namely four control gates and two select gates. The four control gates share two select gates. The select gate is disposed in the gap between two closely spaced control gates. The distance between the select gate and the control gate is the sidewall width of the control gate.

[0007] Preferably, a single active region of the SONOS device is provided with multiple memory cells.

[0008] Preferably, the programming mechanism of the SONOS device is source-side hot electron injection.

[0009] This application also provides a method for manufacturing the above-mentioned SONOS device, comprising: Step 1: Provide a substrate, and sequentially form an ONO layer, a first gate material layer, and a mask layer on the substrate; Step 2: Etch the mask layer, the first gate material layer and the ONO layer in sequence to form the four control gates of the memory cell; Step 3: After forming sidewalls on both sides of the control gate, a second gate material layer is formed on the substrate; Step 4: Etch back the second gate material layer to expose the top of the control gate; Step 5: Remove the second gate material layer within the large gap between the control gates to form two selection gates for the storage cell; Step six: Form metal silicide on top of the control gate and the selection gate.

[0010] Preferably, the ONO layer comprises a tunneling oxide layer, a silicon nitride layer, and a barrier oxide layer stacked from bottom to top.

[0011] Preferably, the mask layer comprises a silicon oxide layer and a silicon nitride layer stacked from bottom to top.

[0012] Preferably, the step of forming the control gate includes: forming a photoresist layer with a control gate pattern on a mask layer by photolithography and etching processes; using the photoresist layer as a mask, sequentially etching the mask layer, the first gate material layer, and the ONO layer; and removing the photoresist layer by an ashing process.

[0013] Preferably, the etching of the ONO layer continues until the tunneling oxide layer is exposed.

[0014] Preferably, this etching is a blanket etching process.

[0015] Preferably, the second gate material layer within the large gap between the control gates is removed by photolithography and etching processes.

[0016] Preferably, the metal silicide material includes titanium disilicide or nickel monosilicide.

[0017] Preferably, after step six, the method further includes forming an interlayer dielectric layer on the substrate and forming contact holes in the interlayer dielectric layer.

[0018] As described above, the SONOS device and its manufacturing method for improving PGM efficiency provided in this application have the following beneficial effects: while further improving PGM efficiency, the storage cell area is further reduced, the manufacturing process is simple and easy to control, and it is easy to mass produce. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 The diagram shows a cross-sectional view of an existing SONOS device. Figure 2 This diagram illustrates the programming mechanism of existing SONOS devices. Figure 3 The diagram shown is a cross-sectional view of a SONOS device for improving PGM efficiency, as provided in an embodiment of this application. Figure 4 The diagram shows a schematic of the programming mechanism of a SONOS device for improving PGM efficiency as provided in an embodiment of this application. Figure 5 The flowchart shown is a method for manufacturing a SONOS device that improves PGM efficiency according to an embodiment of this application; Figure 6 The diagram shown is a cross-sectional view of the SONOS device formed after step one is completed in the manufacturing method of the SONOS device for improving PGM efficiency provided in the embodiments of this application. Figure 7 The diagram shown is a cross-sectional view of the SONOS device formed after step two in the manufacturing method of the SONOS device for improving PGM efficiency provided in the embodiments of this application. Figure 8 The diagram shown is a cross-sectional view of the SONOS device formed after step three in the manufacturing method of the SONOS device for improving PGM efficiency provided in the embodiments of this application. Figure 9 The diagram shown is a cross-sectional view of the SONOS device formed after step four in the manufacturing method of the SONOS device for improving PGM efficiency provided in this application embodiment. Figure 10 The diagram shown is a cross-sectional view of the SONOS device formed after step five in the manufacturing method of the SONOS device for improving PGM efficiency provided in the embodiments of this application. Figure 11The diagram shown is a cross-sectional view of the SONOS device formed after step six in the manufacturing method of the SONOS device for improving PGM efficiency provided in this application embodiment. Detailed Implementation

[0021] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0022] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0025] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0026] Please see Figure 3 The illustration shows a cross-sectional structural diagram of the SONOS device for improving PGM efficiency provided in the application embodiment.

[0027] like Figure 3As shown, a single memory cell in this SONOS device contains six transistors (four CGs and two SGs). The SGs are positioned within the gaps between two closely spaced CGs, and the four CGs share two SGs. After longitudinal arraying and multiplexing the SGs, a 1.25T structure is formed. The spacing between the SGs and CGs is equal to the sidewall width of the CGs. This significantly reduces the spacing, allowing multiple memory cells to be placed in a single active region, further reducing the area.

[0028] like Figure 4 As shown, the programming mechanism of this SONOS device is SSI (Source Side Injection). Electrons are accelerated into high-energy hot electrons by an electric field in the channel below the source (CG1 and SG), tunnel vertically through the ONO tunneling oxide layer below CG2, and are captured by the silicon nitride trapping layer, completing the charge writing. The PGM efficiency time is greatly reduced to the microsecond level, further improving the efficiency.

[0029] Please see Figure 5 The document illustrates a flowchart of a method for manufacturing a SONOS device that improves PGM efficiency, as provided in the embodiments of the application.

[0030] like Figure 5 As shown, the manufacturing method of the SONOS device with improved PGM efficiency includes the following steps: Step 1: Provide a substrate, and sequentially form an ONO layer, a first gate material layer, and a mask layer on the substrate; Step 2: Etch the mask layer, the first gate material layer and the ONO layer in sequence to form the four control gates of the memory cell; Step 3: After forming sidewalls on both sides of the control gate, a second gate material layer is formed on the substrate; Step 4: Etch back the second gate material layer to expose the top of the control gate; Step 5: Remove the second gate material layer within the large gap between the control gates to form two selection gates for the storage cell; Step six: Form metal silicide on top of the control gate and the selection gate.

[0031] In step one, as Figure 6As shown, the substrate 200 can be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, and can also be a multilayer structure, such as Si / SiGe. Those skilled in the art can select the constituent materials of the substrate according to the type of device structure formed on the substrate 200; therefore, the type of substrate 200 should not limit the scope of protection of this invention.

[0032] As an example, an ONO layer 201, a first gate material layer 202, and a mask layer 203 are sequentially formed on a substrate 200 by a deposition process.

[0033] For example, the ONO layer 201 includes a tunneling oxide layer, a silicon nitride layer and a barrier oxide layer stacked from bottom to top, the first gate material layer 202 is made of polysilicon, and the mask layer 203 includes a silicon oxide layer and a silicon nitride layer stacked from bottom to top.

[0034] In step two, as Figure 7 As shown, among the four control gates 205, the spacing between pairs of control gates 205 is small, and the spacing between two pairs of control gates 205 is large.

[0035] The steps for forming the control gate 205 include: forming a photoresist layer with a control gate 205 pattern on the mask layer 203 by photolithography and etching processes; using the photoresist layer as a mask, sequentially etching the mask layer 203, the first gate material layer 202 and the ONO layer 201; and removing the photoresist layer by ashing processes.

[0036] As an example, the etching of the ONO layer 201 ends when the tunneling oxide layer is exposed. The tunneling oxide layer located between the control gates 205 can serve as the gate oxide layer for the subsequently formed select gate. For simplicity, it is not shown in the illustration.

[0037] In step three, such as Figure 8 As shown, after sidewalls 206 are formed on both sides of the control gate 205, a second gate material layer 207 is formed on the substrate 200.

[0038] As an example, the steps of forming sidewall 206 include: forming a sidewall material layer on substrate 200 by a deposition process; and etching the sidewall material layer by a dry etching process to form sidewall 206. Exemplarily, the material of sidewall 206 includes silicon nitride.

[0039] As an example, a second gate material layer 207 is formed by a deposition process, and the material of the second gate material layer 207 includes polycrystalline silicon.

[0040] In step four, as Figure 9 As shown, the second gate material layer 207 is etched back to expose the top of the control gate 205. Exemplarily, this etch back is a blanket etch process.

[0041] In step five, as Figure 10 As shown, the second gate material layer 207 in the large gap between the control gates 205 is removed by photolithography and etching processes to form two select gates 208 of the storage cell. The select gates 208 and the control gates 205 share a sidewall 206.

[0042] For example, a photoresist layer with an opening pattern having a large gap between the control gates 205 is formed on the substrate 200. Using this photoresist layer as a mask, the exposed second gate material layer 207 is etched. After etching, the photoresist layer is removed. This etching is selective etching, which is selective to the second gate material layer 207 compared to the sidewalls 206 and the tunneling oxide layer. Therefore, this etching will not damage the substrate 200 and the control gates 205.

[0043] In step six, as Figure 11 As shown, a metal silicide 209 is formed on top of the control gate 205 and the select gate 208. Exemplarily, the material of the metal silicide 209 includes titanium disilicide, nickel monosilicide, etc.

[0044] After step six, the process also includes forming an interlayer dielectric layer on the substrate 200 and forming contact holes (CTs) in the interlayer dielectric layer, resulting in the following: Figure 3 The device structure shown.

[0045] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] In summary, the SONOS device and its manufacturing method for improving PGM efficiency provided in this application further enhance PGM efficiency while miniaturizing the storage cell area. The manufacturing process is simple, easy to control, and readily mass-produced. Therefore, this application effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0047] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A SONOS device for improving PGM efficiency, characterized in that, The SONOS device contains six transistors in one memory cell, namely four control gates and two select gates. The four control gates share two select gates. The select gate is disposed in the gap between two closely spaced control gates. The distance between the select gate and the control gate is the width of the sidewall of the control gate.

2. The SONOS device according to claim 1, characterized in that, The SONOS device has multiple memory cells set in one active region.

3. The SONOS device according to claim 1, characterized in that, The programming mechanism of the SONOS device is source-side hot electron injection.

4. A method for manufacturing a SONOS device according to any one of claims 1-3, characterized in that, The method includes: Step 1: Provide a substrate, and sequentially form an ONO layer, a first gate material layer, and a mask layer on the substrate; Step 2: Etch the mask layer, the first gate material layer, and the ONO layer sequentially to form the four control gates of the memory cell; Step 3: After forming sidewalls on both sides of the control gate, a second gate material layer is formed on the substrate; Step four: Etch back the second gate material layer to expose the top of the control gate; Step 5: Remove the second gate material layer within the large gap between the control gates to form two selection gates of the storage cell; Step six, forming metal silicide on top of the control gate and the selection gate.

5. The method according to claim 4, characterized in that, The ONO layer comprises, from bottom to top, a tunneling oxide layer, a silicon nitride layer, and a barrier oxide layer.

6. The method according to claim 4, characterized in that, The mask layer comprises a silicon oxide layer and a silicon nitride layer stacked from bottom to top.

7. The method according to claim 5, characterized in that, The steps for forming the control gate include: forming a photoresist layer with the control gate pattern on the mask layer by photolithography and etching processes; using the photoresist layer as a mask, sequentially etching the mask layer, the first gate material layer, and the ONO layer; and removing the photoresist layer by an ashing process.

8. The method according to claim 7, characterized in that, The etching of the ONO layer continues until the tunneling oxide layer is exposed.

9. The method according to claim 4, characterized in that, The etching process is a blanket etching process.

10. The method according to claim 4, characterized in that, The second gate material layer within the large gap between the control gates is removed by photolithography and etching processes.

11. The method according to claim 4, characterized in that, The materials of the metal silicide include titanium disilicide or nickel monosilicide.

12. The method according to claim 4, characterized in that, After step six is ​​completed, the method further includes forming an interlayer dielectric layer on the substrate and forming contact holes in the interlayer dielectric layer.

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