A planar nonvolatile memory device and a method of fabricating the same

Abstract

The present application relates to the technical field of semiconductor, in particular to a planar nonvolatile memory device and a preparation method thereof, and provides a planar nonvolatile memory device, and a device core comprises a metal ferroelectric body, a first electrode and a second electrode existing in multiple groups; the metal ferroelectric body is a heavy nitrogen-doped 3C-SiC single crystal material, after heavy doping, the crystal structure is distorted and is converted into R3m polar space group; the first electrode and the second electrode existing in pairs are spacedly distributed on the electrode mounting surface of the metal ferroelectric body and jointly constitute a transverse two-end ferroelectric tunnel junction structure; the present application provides a planar nonvolatile memory device based on 3C-SiC metal ferroelectric body and a preparation method thereof, and the device has the advantages of non-volatility, high read-write speed, low power consumption, high stability, wide working temperature range (at least can resist high temperature up to 600 DEG C) and the like.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a planar non-volatile memory device and its fabrication method. Background Technology

[0002] Ferroelectric tunneling junctions (FTJs) are novel non-volatile memory devices that utilize ferroelectric polarization reversal to control the tunneling barrier height. They offer advantages such as fast write / erase speeds, low power consumption, and simple structure, and are considered one of the core technologies for extreme environment storage. With the rapid development of extreme scenarios such as aerospace, deep-earth oil and gas exploration, nuclear power plant monitoring, and high-temperature industrial control, electronic systems are placing stringent requirements on the temperature resistance, radiation resistance, and long-term reliability of non-volatile memory. However, existing memory technologies currently exhibit significant limitations in terms of operating temperature and long-term reliability.

[0003] In terms of operating temperature, traditional silicon-based memories typically operate below 150°C, where charge retention characteristics degrade drastically. Magnetic memories and resistive random access memories also face performance degradation and reliability issues above 200°C, failing to meet the long-term stable operation requirements of extreme environments above 600°C. To adapt to higher-temperature applications, the industry has attempted to construct memory devices by depositing heterogeneous ferroelectric thin films on wide-bandgap silicon carbide substrates. However, this approach has consistently failed to overcome the inherent bottleneck of heterogeneous integration: significant lattice mismatch and thermal expansion coefficient mismatch exist between the ferroelectric thin film and the silicon carbide substrate, resulting in numerous dislocations and defects at the interface, leading to increased leakage current, degraded data retention characteristics, and further performance degradation due to interdiffusion of interfacial elements at high temperatures.

[0004] In terms of reliability, all current commercial and R&D ferroelectric memory devices adopt a stacked architecture of insulating ferroelectric thin films, using polycrystalline thin films such as lead zirconate titanate (PZT), hafnium oxide (HfO2)-based, and aluminum scandium nitride (AlScN) as the active storage layer. This type of thin film structure has inherent defects that are difficult to overcome at both the material intrinsics and device architecture levels: First, polycrystalline thin films have dense grain boundary defects, resulting in large leakage current, significant polarization fatigue, and a continuously narrowing storage window after long-term cycling; Second, the insulating ferroelectric layer has a strong depolarization field effect, and the thinner the film, the worse the polarization stability, which restricts the device from being miniaturized to higher densities; Third, there is a band barrier between the ferroelectric layer and the metal electrode, and carrier injection easily leads to the accumulation of interface defects, further degrading the device's retention characteristics and lifespan.

[0005] Metallic ferroelectrics are a new type of functional material that simultaneously possesses reversible spontaneous ferroelectric polarization and metallic conductivity. From a fundamental perspective, they can completely overcome the architectural bottlenecks of traditional insulating ferroelectric thin films to improve the reliability of memory devices. Their basic principles and advantages include: 1) Intrinsic metallic conductivity can effectively shield depolarization fields, allowing ultrathin devices to maintain stable polarization and support high-density integration; 2) Low-resistance ohmic contacts can be formed between the ferroelectric layer and the electrodes, significantly weakening the interface barrier and carrier injection effect, thus significantly improving fatigue life and long-term stability; 3) The synergistic effect of free electrons and ferroelectric domains can accelerate domain flipping dynamics, potentially enabling sub-nanosecond ultra-high-speed read / write operations. However, currently reported metallic ferroelectric materials are all oxide systems, such as those doped with strontium titanate or rare-earth nickelates. These materials have poor crystal structure stability, are prone to phase decomposition and performance failure above 300℃, and have extremely poor compatibility with silicon-based and silicon carbide-based semiconductor processes, making it impossible to prepare large-size, high-quality single crystals. They remain at the laboratory thin film sample stage, making it difficult to achieve engineering applications in extreme environments. Summary of the Invention

[0006] This invention provides a planar non-volatile memory device and its fabrication method, which can provide a non-volatile memory device in which the metal ferroelectric material is a large-size single crystal material that is resistant to high temperature and has strong compatibility with silicon-based and silicon carbide-based semiconductor processes.

[0007] In a first aspect, the present invention provides a planar non-volatile memory device, the core of which includes a metal ferroelectric body and a first electrode and a second electrode in multiple pairs; The metallic ferroelectric material is a diazo-doped 3C-SiC single crystal material. After heavy doping, its crystal structure is distorted and transformed into the R3m polar space group. The paired first and second electrodes are spaced apart on the electrode mounting surface of the metallic ferroelectric body, together forming a transverse ferroelectric tunnel junction structure.

[0008] Optionally, the nitrogen doping concentration of the ferroelectric functional matrix is ​​5.0 × 10⁻⁶. 19 ~5.0×10 21 atoms·cm -3 .

[0009] Optionally, the electrode mounting surface of the ferroelectric functional substrate is the (111) crystal plane of a diazo-doped 3C-SiC single crystal material.

[0010] Optionally, the thickness of both the first electrode and the second electrode is 30~200nm, and the distance between the first electrode and the second electrode is 0.5μm~50μm.

[0011] Optionally, both the first electrode and the second electrode form Schottky contacts with the metallic ferroelectric material.

[0012] Optionally, the first electrode and the second electrode are single-layer or multi-layer structures, and the material used to prepare each layer is selected from gold, platinum, aluminum, and titanium-tungsten alloy.

[0013] Optionally, the first electrode and / or the second electrode are Ti / Au stacked structures, wherein the Ti layer is adhered to the surface of the metal ferroelectric material and has a thickness of 5~10nm, and the Au main electrode layer is disposed on the Ti layer and has a thickness of 40~100nm; the first electrode unit is circular or square and the unit feature size is 0.5μm~50μm.

[0014] Secondly, the present invention provides a method for fabricating a planar non-volatile memory device, used to fabricate any of the planar non-volatile memory devices described above, the fabrication method comprising the following steps: S1 Diazo-doped 3C-SiC bulk single crystal growth: 3C-SiC single crystal ingots were obtained by high-temperature solution growth; S2 wafer fabrication: The single crystal ingot is cut along the target crystal direction and mechanically thinned to obtain a single crystal wafer of a set thickness. Then, the surface is chemically and mechanically polished to make the root mean square roughness of the surface ≤0.2nm. S3 electrode patterning: Photoresist is spin-coated onto the polished single crystal surface, and the patterns of the first and second electrodes are defined by photolithography. S4 Electrode Deposition and Stripping: Metal electrodes are deposited using thermal evaporation or magnetron sputtering processes, and then stripped to obtain spaced first and second electrodes, thus completing the fabrication of planar structure devices.

[0015] Optionally, in step S4, after the metal electrode deposition is completed, a low-temperature annealing treatment of 100~200℃ is performed to optimize the metal-semiconductor contact interface characteristics.

[0016] Compared with the prior art, the present invention has at least the following beneficial effects: (1) Ultra-high thermal stability, filling the gap in extreme high temperature storage The core functional material of this invention is a heavily doped 3C-SiC bulk single crystal, whose R3m ferroelectric phase can be stable up to at least 599℃, far exceeding that of traditional ferroelectric memory materials (PZT up to about 350℃) and existing ferroelectric metal systems (WTe2 about 67℃, LiOsO3 about -133℃). It is currently the ferroelectric metal memory material system with the best thermal stability. The device can operate stably for a long time in extreme environments above 500℃, perfectly adapting to high-temperature and high-radiation scenarios such as aerospace, deep earth exploration, and nuclear industry monitoring, filling the technological gap in the field of high-temperature non-volatile memory.

[0017] (2) Intrinsic bulk phase characteristics, without inherent defects of thin film devices This invention is the first to use bulk single crystal as the ferroelectric functional layer, completely avoiding the inherent defects of thin film systems: no substrate clamping effect, no epitaxial strain, no interface dead layer, ferroelectric properties are intrinsic bulk phase properties of the material, and polarization reversal is more stable; there are no problems of resistive state drift and retention force decay caused by thin film interface defects, and long-term reliability is significantly improved; at the same time, it breaks through the size limitation of two-dimensional ferroelectric metals, and can realize 6-inch wafer-level large-scale preparation, which greatly reduces the threshold for industrialization.

[0018] (3) Metallic conductivity characteristics, balancing low power consumption and large readout current The ferroelectric functional layer of this invention has metallic conductivity and a room temperature resistivity as low as 0.52 mΩ·cm. The readout current is much greater than that of traditional insulated ferroelectric tunnel junctions, effectively solving the pain points of weak readout signal and low signal-to-noise ratio of traditional ferroelectric tunnel junctions (FTJs). At the same time, the erase and write operations rely on electric field-driven polarization reversal, eliminating the melting-crystallization process of phase change storage and the conductive wire melting process of resistive switching storage. The Joule heat loss is extremely low, achieving a balance between low power consumption and high readout sensitivity.

[0019] (4) Strong radiation resistance and high reliability, suitable for extreme working conditions The 3C-SiC matrix itself has excellent radiation resistance and chemical stability, making it more suitable for extreme environments with strong radiation and strong corrosion compared to silicon-based storage and oxide ferroelectric storage. The polarization reversal originates from the reversible displacement of the crystal lattice and sublattice, and there are no failure mechanisms such as the breakage of conductive filaments or material phase transformation fatigue, resulting in better cycle life. The material does not contain toxic elements such as lead, making it more environmentally friendly than traditional PZT ferroelectric materials.

[0020] (5) Strong process compatibility and low manufacturing cost The device of this invention has a planar lateral structure, requiring only surface electrode technology and eliminating the need for complex thin-film epitaxy, high aspect ratio etching and stacking processes. The 6-inch wafer size is fully compatible with existing SiC power device production lines, eliminating the need to build new production lines. The manufacturing cost and process difficulty are far lower than those of three-dimensional stacked memory and vertical structure ferroelectric tunnel junction (FTJ), providing a solid foundation for large-scale mass production. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a storage device provided in an embodiment of the present invention; In the picture: 1-First electrode; 2-Second electrode; 3-Schottky contact layer; 4-Metallic ferroelectric material; Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0024] In the description of the embodiments of the present invention, unless otherwise expressly specified and limited, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; unless otherwise specified or stated, the term "multiple" refers to two or more; the terms "connected," "fixed," etc., should be interpreted broadly. For example, "connected" can be a fixed connection, a detachable connection, an integral connection, or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0025] In this specification, it should be understood that the directional terms such as "upper" and "lower" used in the description of the embodiments of the present invention are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of the present invention. Furthermore, in the context, it should also be understood that when it is mentioned that one element is connected "upper" or "lower" to another element, it can be directly connected to the other element "upper" or "lower," or indirectly connected to the other element "upper" or "lower" through an intermediate element.

[0026] Please refer to Figure 1 The present invention provides a planar non-volatile memory device, the core of which includes a metal ferroelectric body, a first electrode and a second electrode with multiple pairs; The metallic ferroelectric material is a diazo-doped 3C-SiC single crystal material. After heavy doping, its crystal structure is distorted and transformed into the R3m polar space group. The paired first and second electrodes are spaced apart on the electrode mounting surface of the metallic ferroelectric body, together forming a transverse ferroelectric tunnel junction structure.

[0027] In this invention, diazo doping induces lattice distortion along the

[111] crystal direction, transforming it into a polar crystal structure of the R3m space group, which simultaneously possesses metallic conductivity and spontaneous polarization characteristics that can be electrically controlled and flipped, and simultaneously assumes the dual role of ferroelectric functional layer and lateral conductive channel.

[0028] The coercivity voltage of the memory device provided by this invention is 1.0~5.0V, and the high-to-low impedance switching ratio is ≥15 under a 4V operating bias, reaching 20 under optimal conditions; the impedance hold time is ≥10 seconds. 4 It exhibits no significant resistance drift or fatigue under bipolar pulse cycling, demonstrating excellent nonvolatility and cycle stability.

[0029] In this embodiment, the polarization direction of the ferroelectric functional substrate is controlled by an external electric field, causing the ferroelectric polarization below the electrode and in the channel region to undergo a 180° reversible flip. The polarization charge changes the Schottky barrier height at the interface between the metal electrode and 3C-SiC, thereby switching the overall resistance of the device between a high-resistance state and a low-resistance state. After the external voltage is removed, the ferroelectric polarization can be stably maintained, and the corresponding resistance state is retained, achieving non-volatile storage. The erase and write operations can be repeatedly completed by bipolar voltage pulses.

[0030] The specific working principle includes: 1. Underlying physical foundation The functional matrix is ​​diazo-doped 3C-SiC (R3m polar phase), which belongs to n-type degenerate semiconductor (with metallic conductivity). Its crystal has spontaneous polarization along the

[111] crystal direction, and the polarization direction can be reversed by an external electric field by 180°.

[0031] When the Au metal electrode comes into contact with the 3C-SiC substrate, a Schottky barrier is formed due to the difference in work function. The two electrodes correspond to two Schottky contacts, and the 3C-SiC body in the middle is a conductive channel. The overall resistance of the device is determined by the Schottky barriers at the two interfaces and the channel body resistance.

[0032] The bound charges of ferropolarization are superimposed on the metal-semiconductor interface, directly changing the height of the Schottky barrier—this is the core reason for resistive switching.

[0033] 2. Two stable resistive states (corresponding to "0" and "1") Different spontaneous polarization directions result in different interface barrier heights, corresponding to two stable resistance states: High resistance state (HRS, corresponding to data "0"): The spontaneous polarization direction is away from the electrode (the negative polarization end faces the metal interface), which will intensify the band bending on the semiconductor side and increase the height of the Schottky barrier; the difficulty for electrons to cross the barrier increases, and the overall resistance of the device is higher.

[0034] Low resistance state (LRS, corresponding to data "1"): The spontaneous polarization direction points towards the electrode (positive polarization terminal faces the metal interface), which will offset part of the band bending and reduce the height of the Schottky barrier; electrons are easier to transport, and the overall resistance of the device is lower.

[0035] 3. Erasing / writing operation: Voltage-driven polarization reversal When a bipolar pulse or DC voltage exceeding the coercive voltage (1.0~5.0V) is applied between the two electrodes, the external electric field will drive the ferropolarization below the electrodes and in the channel region to flip 180°, and the Schottky barrier at the interface will rise or fall accordingly. The device switches between a high-resistivity state and a low-resistivity state to complete the writing or erasing of data.

[0036] Voltage polarity determines the polarization reversal direction, corresponding to "writing 0" or "writing 1"; after the voltage amplitude exceeds the coercive voltage, the more complete the polarization reversal, the greater the resistance difference (switching ratio).

[0037] 4. Read operation: Non-destructive read Apply a read bias voltage much lower than the coercive voltage (e.g., 0.5V): This voltage is insufficient to trigger polarization reversal; it is only used to test the magnitude of the current passing through the device. By detecting the level of the current, it is possible to determine whether the current is in a high-resistance state or a low-resistance state, thus completing the data reading without altering the stored data, which is a non-destructive reading process.

[0038] 5. The principle of non-volatility Ferropolarization is an intrinsic stable state of the crystal structure. After the external electric field is removed, the polarization direction will not spontaneously reverse, and the corresponding interface barrier height and device resistance state will also remain stable for a long time. Therefore, the data will not be lost after power is turned off, and it has non-volatile storage characteristics.

[0039] In some embodiments of the present invention, the nitrogen doping concentration of the ferroelectric functional matrix is ​​5.0 × 10⁻⁶. 19 ~5.0×10 21 atoms·cm -3 .

[0040] In this embodiment, the nitrogen doping concentration needs to be controlled at 5.0 × 10⁻⁶. 19 ~5.0×10 21 atoms·cm -3 In this way, the material possesses both metallic conductivity and electrically tunable spontaneous polarization characteristics, thus simultaneously serving as both a ferroelectric functional layer and a conductive channel.

[0041] In this embodiment, the nitrogen doping concentration is preferably 1.0 × 10⁻⁶. 20 ~5.0×10 20 atoms·cm -3 Within this range, the R3m phase exhibits the best thermodynamic stability, with the ferroelectric switching characteristics and metallic conductivity being optimally matched. The corresponding room temperature resistivity is 0.3~1.0 mΩ·cm, the carrier concentration is highly matched with the nitrogen doping concentration, the nitrogen atom ionization rate is ≥90%, the Fermi level enters the conduction band, and it exhibits typical degenerate semiconductor metallic conductivity characteristics.

[0042] In this invention, the ferroelectric phase can exist stably in a wide temperature range below 600°C, which is much higher than the phase transition temperature of traditional oxide ferroelectric materials and existing ferroelectric metal systems, enabling the device to operate normally in extreme high-temperature environments.

[0043] In some embodiments of the present invention, the electrode mounting surface of the ferroelectric functional substrate is the (111) crystal plane of a diazo-doped 3C-SiC single crystal material.

[0044] In some embodiments of the present invention, the thickness of the first electrode and the second electrode is 30~200nm, and the distance between the first electrode and the second electrode is 0.5μm~50μm.

[0045] In this embodiment, within the above parameter range, the ferroelectric functional matrix exhibits excellent performance uniformity and mass production adaptability.

[0046] In some embodiments of the present invention, both the first electrode and the second electrode form a Schottky contact with the metal ferroelectric material.

[0047] In some embodiments of the present invention, the first electrode and the second electrode are single-layer or multi-layer structures, and the material for each layer is selected from gold, platinum, aluminum, and titanium-tungsten alloy.

[0048] In some embodiments of the present invention, the first electrode and / or the second electrode is a Ti / Au stacked structure, wherein the Ti layer is adhered to the surface of the metal ferroelectric material and has a thickness of 5~10nm, and the Au main electrode layer is disposed on the Ti layer and has a thickness of 40~100nm; the first electrode and the second electrode unit are circular or square and the unit feature size is 0.5μm~50μm.

[0049] In this embodiment, the feature dimension is the diameter or side length.

[0050] The present invention also provides a method for fabricating a planar non-volatile memory device, for fabricating any of the planar non-volatile memory devices described above, the method comprising the following steps: S1 Diazo-doped 3C-SiC bulk single crystal growth: 3C-SiC single crystal ingots were obtained by high-temperature solution growth; S2 wafer fabrication: The single crystal ingot is cut along the target crystal direction and mechanically thinned to obtain a single crystal wafer of a set thickness. Then, the surface is chemically and mechanically polished to make the root mean square roughness of the surface ≤0.2nm. S3 electrode patterning: Photoresist is spin-coated onto the polished single crystal surface, and the patterns of the first and second electrodes are defined by photolithography. S4 Electrode Deposition and Stripping: Metal electrodes are deposited using thermal evaporation or magnetron sputtering processes, and then stripped to obtain spaced first and second electrodes, thus completing the fabrication of planar structure devices.

[0051] In some embodiments of the present invention, in step S4, after the metal electrode deposition is completed, a low-temperature annealing treatment of 100~200°C is performed to optimize the metal-semiconductor contact interface characteristics.

[0052] Example 1: Fabrication and Testing of Optimal Performance Ferroelectric Tunnel Junction Storage Device This embodiment fabricates a diazo-doped 3C-SiC lateral ferroelectric tunnel junction device based on the optimal doping concentration. The specific steps are as follows: Step 1: Diazo-doped 3C-SiC bulk single crystal growth A 6-inch-scale heavily doped 3C-SiC single crystal ingot was grown using a high-temperature solution method; nitrogen doping was achieved by introducing nitrogen gas into the growth atmosphere, with a nitrogen doping concentration of 2.7 × 10⁻⁶. 20 atoms·cm -3 .

[0053] Step 2: Wafer Fabrication The single crystal ingot was cut into 350 μm thick (111) faceted wafers, and the cutting damage layer was removed by mechanical grinding; then chemical mechanical polishing was performed, and the root mean square roughness of the wafer surface was finally 0.15 nm.

[0054] Step 3: Electrode Patterning and Deposition Positive photoresist was spin-coated onto the polished (111) crystal wafer surface, and the electrode patterns at both ends were defined by ultraviolet lithography with an electrode spacing of 10 μm. A 5 nm Ti adhesion layer and a 50 nm Au main electrode layer were deposited sequentially using a thermal evaporation process. The wafer was then placed in an acetone solution and ultrasonically peeled off to obtain patterned metal electrodes at both ends, thus completing the device fabrication.

[0055] Device performance testing: Resistive switching hysteresis characteristics: When the bias voltage is increased to above 2.0V, the IV curve shows a clear bipolar hysteresis loop. The hysteresis window gradually widens as the bias voltage increases, which is consistent with the barrier control law of gradual flipping of ferroelectric domains. The high and low resistance switching ratio is about 20 under a 4V bias voltage.

[0056] Cyclic stability: The IV hysteresis curves of three consecutive voltage scans highly overlapped, with no obvious drift or polarity asymmetry, ruling out exogenous resistance switching mechanisms such as ion migration and conductive filaments, confirming that it is a stable resistance switching driven by intrinsic ferroelectric polarization.

[0057] Non-volatile: Bipolar voltage pulse cycle testing can repeatedly achieve high and low impedance state switching, and the impedance state retention time exceeds 10 after voltage removal. 4s has good non-volatile storage characteristics.

[0058] High-temperature stability: When tested at a high temperature of 600℃, the device can still stably achieve resistive switching with no significant decrease in the switching ratio, which confirms its excellent high-temperature performance.

[0059] Test results show that the vertical device retains all the advantages of high temperature and high reliability of this material system, while having further advantages in polarization driving efficiency, performance uniformity and integration, verifying the feasibility and application value of the dual-structure scheme.

[0060] Example 2 Example 2 is basically the same as Example 1, except that the nitrogen doping concentration is 6.3 × 10⁻⁶. 19 atoms·cm -3 .

[0061] Device performance testing: Resistive switching hysteresis characteristics: When the bias voltage is increased to above 3.0V, the IV curve shows a clear bipolar hysteresis loop. The hysteresis window gradually widens as the bias voltage increases, which is consistent with the barrier control law of gradual flipping of ferroelectric domains. The high and low resistance switching ratio is about 15 under a 4V bias voltage.

[0062] Cyclic stability: The IV hysteresis curves of three consecutive voltage scans highly overlapped, with no obvious drift or polarity asymmetry, ruling out exogenous resistance switching mechanisms such as ion migration and conductive filaments, confirming that it is a stable resistance switching driven by intrinsic ferroelectric polarization.

[0063] Non-volatile: Bipolar voltage pulse cycle testing can repeatedly achieve high and low impedance state switching, and the impedance state retention time exceeds 10 after voltage removal. 4 s has good non-volatile storage characteristics.

[0064] High-temperature stability: When tested at a high temperature of 600℃, the device can still stably achieve resistive switching with no significant decrease in the switching ratio, which confirms its excellent high-temperature performance.

[0065] Example 3 Example 3 is basically the same as Example 1, except that the nitrogen doping concentration is 3.7 × 10⁻⁶. 21 atoms·cm -3 .

[0066] Device performance testing: Resistive switching hysteresis characteristics: When the bias voltage is increased to above 3.0V, the IV curve shows a clear bipolar hysteresis loop. The hysteresis window gradually widens as the bias voltage increases, which is consistent with the barrier control law of gradual flipping of ferroelectric domains. The high and low resistance switching ratio is about 12 under a 4V bias voltage.

[0067] Cyclic stability: The IV hysteresis curves of three consecutive voltage scans highly overlapped, with no obvious drift or polarity asymmetry, ruling out exogenous resistance switching mechanisms such as ion migration and conductive filaments, confirming that it is a stable resistance switching driven by intrinsic ferroelectric polarization.

[0068] Non-volatile: Bipolar voltage pulse cycle testing can repeatedly achieve high and low impedance state switching, and the impedance state retention time exceeds 10 after voltage removal. 4 s has good non-volatile storage characteristics.

[0069] High-temperature stability: When tested at a high temperature of 600℃, the device can still stably achieve resistive switching with no significant decrease in the switching ratio, which confirms its excellent high-temperature performance.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A planar non-volatile storage device, characterized in that, The core of the device includes a metallic ferroelectric material, a first electrode and a second electrode with multiple pairs; The metallic ferroelectric material is a diazo-doped 3C-SiC single crystal material. After heavy doping, its crystal structure is distorted and transformed into the R3m polar space group. The paired first and second electrodes are spaced apart on the electrode mounting surface of the metallic ferroelectric body, together forming a transverse ferroelectric tunnel junction structure.

2. The storage device according to claim 1, characterized in that, The nitrogen doping concentration of the ferroelectric functional matrix is ​​5.0 × 10⁻⁶. 19 ~5.0×10 21 atoms·cm -3 .

3. The storage device according to claim 1, characterized in that, The electrode mounting surface of the ferroelectric functional substrate is the (111) crystal plane of diazo-doped 3C-SiC single crystal material.

4. The storage device according to claim 1, characterized in that, The thickness of both the first and second electrodes is 30~200nm, and the distance between the first and second electrodes is 0.5μm~50μm.

5. The storage device according to claim 1, characterized in that, Both the first electrode and the second electrode form Schottky contacts with the metallic ferroelectric material.

6. The storage device according to claim 1, characterized in that, The first electrode and the second electrode are single-layer or multi-layer structures, and the material used to prepare each layer is selected from gold, platinum, aluminum, and titanium-tungsten alloy.

7. The storage device according to claim 1, characterized in that, The first electrode and / or the second electrode are Ti / Au stacked structures, wherein the Ti layer is adhered to the surface of the metal ferroelectric material and has a thickness of 5~10nm, and the Au main electrode layer is disposed on the Ti layer and has a thickness of 40~100nm; the first electrode unit is circular or square and the unit feature size is 0.5μm~50μm.

8. A method for fabricating a planar non-volatile storage device, characterized in that, The method for fabricating the planar non-volatile storage device according to any one of claims 1-7 includes the following steps: S1 Diazo-doped 3C-SiC bulk single crystal growth: 3C-SiC single crystal ingots were obtained by high-temperature solution growth; S2 wafer fabrication: The single crystal ingot is cut along the target crystal direction and mechanically thinned to obtain a single crystal wafer of a set thickness. Then, the surface is chemically and mechanically polished to make the root mean square roughness of the surface ≤0.2nm. S3 electrode patterning: Photoresist is spin-coated onto the polished single crystal surface, and the patterns of the first and second electrodes are defined by photolithography. S4 Electrode Deposition and Stripping: Metal electrodes are deposited using thermal evaporation or magnetron sputtering processes, and then stripped to obtain spaced first and second electrodes, thus completing the fabrication of planar structure devices.

9. The preparation method according to claim 8, characterized in that, In step S4, after the metal electrode deposition is completed, a low-temperature annealing treatment of 100~200℃ is performed to optimize the metal-semiconductor contact interface characteristics.

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