Ferroelectric memory layout structure and wiring method
Patent Information
- Application Number
- CN202610837930.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-10
- Publication Date
- 2026-10-13
AI Technical Summary
其常规布局具有版图设计相对简单的优点，但也存在以下不足：第一，面积利用率不高，难以实现更高的存储密度；第二，深沟槽等层次在版图中排布规律性弱，工艺上容易受到负载效应的影响，导致器件性能波动；第三，由于板线与位线在空间上存在交叉，位线需要多次跳线，在板线上方的金属层中完成布线，增加了互连复杂度
本发明通过使有源区相对字线倾斜设置，可以打破常规布局中位线与板线必然交叉的限制，使得两者可以沿同一方向延伸，从而避免位线跳线。同时，倾斜有源区可使存储单元排布更为紧凑，提升存储密度，且深沟槽等层次随有源区方向形成周期性排布，改善工艺均匀性。
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Figure CN122909847A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a ferroelectric memory layout structure and wiring method. Background Technology
[0002] In 28nm and below process nodes, the integration of traditional floating gate, silicon-oxide-nitride-oxide-silicon and other memory structures with logic processes is becoming increasingly difficult. The industry is gradually turning to new memory technologies such as magnetoresistive random access memory, resistive random access memory, phase change memory, and ferroelectric memory.
[0003] For a common layout of a transistor and a capacitor-type ferroelectric memory, such as Figure 1 As shown. Its conventional layout has the advantage of relatively simple layout design, but it also has the following disadvantages: First, the area utilization rate is not high, making it difficult to achieve higher storage density; Second, the arrangement of layers such as deep trenches in the layout is not regular, and the process is easily affected by the load effect, resulting in device performance fluctuations; Third, since the board lines and bit lines intersect in space, the bit lines need to be jumpered multiple times and the wiring is completed in the metal layer above the board lines, which increases the interconnection complexity. Summary of the Invention
[0004] In a first aspect, the present invention provides a layout structure for a ferroelectric memory, comprising: An active region, wherein the active region is arranged at an angle in the layout; Multiple word lines extend along a first direction and cross the active region, forming the gate of a transistor at the overlap. Multiple bit lines are located in the first metal layer and extend along a second direction, which is perpendicular to the first direction. Multiple board lines are located on the metal layer above the ferroelectric capacitor, used to connect the upper electrode of the ferroelectric capacitor, and are set parallel to the word lines; The bit lines are routed within the first metal layer, eliminating the need for jumpers to cross the board lines.
[0005] In one possible implementation, the extension direction of the active region is tilted at a non-orthogonal and non-parallel angle to the first direction.
[0006] In one possible implementation, multiple active regions are arranged parallel to each other and at equal intervals to form an oblique periodic array.
[0007] In one possible implementation, the structure further includes a deep trench located at one end of the active region for forming a ferroelectric capacitor.
[0008] In one possible implementation, the arrangement direction of the deep trenches is consistent with or matches the extension direction of the active region, so that the multiple deep trenches are arranged periodically in the layout.
[0009] In one possible implementation, the structure further includes a contact hole, the contact hole comprising at least: Active region contact holes, located in the source or drain region of the transistor, are used to connect the active region to the bit line of the first metal layer; A gate contact hole, located on the word line, is used to connect the word line to the upper metal layer.
[0010] In one possible implementation, the contact hole further includes a capacitor contact hole located at the upper electrode lead of the ferroelectric capacitor for connecting the plate wire.
[0011] In one possible implementation, the ferroelectric memory has a 1T1C type structure, with each memory cell including one transistor and one ferroelectric capacitor.
[0012] Secondly, this application provides a wiring method for a ferroelectric memory layout structure, including: Provides an active area that is set at an angle; A word line is formed that extends along a first direction and crosses the active region, and a transistor gate is formed at the intersection. Bit lines extending in the second direction are formed in the first metal layer; Forming a plate line that is consistent with the extension direction of the character line; The bit lines complete all connections within the first metal layer, without any jumper operations crossing the board lines.
[0013] Thirdly, this application provides a ferroelectric memory, including the ferroelectric memory layout structure as described in any one of claims 1 to 8.
[0014] Due to the adoption of the above technical solutions, this application has the following beneficial effects: This invention, by tilting the active area relative to the word lines, breaks the constraint that bit lines and board lines inevitably intersect in conventional layouts, allowing them to extend in the same direction and thus avoiding bit line jumpers. Simultaneously, the tilted active area enables a more compact arrangement of memory cells, increasing storage density, and the deep trenches and other layers are arranged periodically along the direction of the active area, improving process uniformity. Attached Figure Description
[0015] To more clearly illustrate the technical solution of the present invention and facilitate a further understanding of its technical effects, features, and objectives, the present invention will be described in detail below with reference to the accompanying drawings. The drawings constitute an essential part of the specification and are used together with Embodiment 1 of the present invention to illustrate the technical solution of the present invention, but do not constitute a limitation on the present invention.
[0016] The same reference numerals in the attached diagrams represent the same parts, specifically: Figure 1 This is a typical layout of a transistor and a capacitor-type ferroelectric memory.
[0017] Figure 2 This is a top view of the ferroelectric memory layout provided in the first embodiment of the present invention.
[0018] Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure.
[0019] Figure 4 This is a schematic flowchart of the wiring method of the present invention.
[0020] in: 10. Active area; 20. Word line; 30. Deep trench; 41. Active area contact hole; 42. Capacitor contact hole; 50. Bit line. Detailed Implementation
[0021] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Of course, the specific embodiments described below are merely illustrative of the technical solutions of the present invention, and not intended to limit the invention. Furthermore, the parts described in the embodiments or drawings are merely illustrative examples of relevant parts of the present invention, and not the entirety of the invention.
[0022] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0024] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other. Example 1
[0025] like Figure 2 As shown, this embodiment provides a compact layout structure of a transistor and a capacitive ferroelectric memory with an inclined active region. The active region 10 is inclined in the layout, and its extension direction forms an angle of approximately 45 degrees with the first direction of extension of the word line 20 (the horizontal direction shown in the figure). This angle is neither orthogonal nor parallel, thereby shortening the projected length of a single memory cell in the vertical direction and effectively reducing the cell area.
[0026] Multiple word lines 20 are arranged parallel to each other along a first direction and cross the active region 10. The area where the word lines 20 and the active region 10 overlap forms the gate of the transistor, and the active regions on both sides of the overlap serve as the source and drain regions, respectively. A deep trench 30 is provided at one end of the active region 10 to form a ferroelectric capacitor. A lower electrode, a ferroelectric dielectric layer, and a top electrode are deposited sequentially within the deep trench 30 to form the capacitor body. The arrangement direction of the deep trenches 30 is consistent with the extension direction of the active region 10. Therefore, multiple deep trenches 30 form a regular and periodic pattern in the layout following the active region, significantly reducing the interference of the load effect.
[0027] The contact holes include an active region contact hole 41 and a capacitor contact hole 42. The active region contact hole 41 is located above the drain region of the transistor, connecting the drain region to the bit line 50 in the first metal layer. The capacitor contact hole 42 is located at the upper electrode lead-out end of the deep trench 30, connecting the upper electrode of the capacitor to the board line. In this embodiment, the board line is disposed on the metal layer above the ferroelectric capacitor, but its extension direction is consistent with that of the word line 20, both being the first direction (horizontal direction in the figure). Due to the inclined setting of the active region, the bit line 50 can avoid the deep trench 30 and be routed within the first metal layer, while the board line is routed on the metal layer above the capacitor. Therefore, the bit line 50 does not need to jump upwards to a higher metal layer to cross the board line, and the routing of the entire array can be completed within the first metal layer.
[0028] Figure 3 It shows along Figure 2The cross-sectional structure is as follows: The active region 10 is formed in the semiconductor substrate, the deep trench 30 extends downward from the substrate surface, the word line 20 is located above the substrate and is isolated from the active region through the gate dielectric layer, the active region contact hole 41 is filled with conductive material to connect the drain region and the bit line 50 of the first metal layer, and the capacitor contact hole 42 connects the upper electrode lead-out area at the top of the deep trench 30 to the plate line. Example 2
[0029] The main difference between this embodiment and the first embodiment lies in the tilt angle of the active region 10. The angle between the extension direction of the active region 10 and the first direction of the word line 20 is 30 degrees. Depending on the specific design rules and photolithography capabilities, the tilt angle can be flexibly selected within the range of 15 degrees to 75 degrees to achieve a balance between area reduction, current drive, and manufacturability. The layout and connection relationships of other layers are the same as in the first embodiment and will not be described again. Example 3
[0030] This embodiment provides a variation of the array arrangement. In the layout, multiple tilted active regions 10 are arranged parallel to each other and at equal intervals to form a first subarray. Adjacent to the first subarray, a second subarray is arranged in a mirror image of the first subarray, with the two subarrays facing each other. In this way, adjacent subarrays can share the contact area of word lines 20 or the lead-out position of board lines, further compressing the peripheral circuit area and increasing the overall storage density. The deep trenches 30 are arranged mirror-symmetrically with the active regions 10, also maintaining a regular periodicity. Example 4
[0031] The difference between this embodiment and the first embodiment is that the board line and the bit line 50 are disposed on the same metal layer, that is, both are located on the first metal layer. Parallel and spaced lines are etched into the first metal layer using a patterning process, serving as the bit line 50 and the board line, respectively. Because the active region 10 is tilted, the contact positions of the bit line and the board line are naturally offset in the second direction, preventing short circuits. This same-layer wiring scheme saves one layer of metal and reduces manufacturing costs. Example 5
[0032] This embodiment provides a ferroelectric memory, which includes the layout structure described in any of the foregoing embodiments. This ferroelectric memory can be used as a standalone memory chip or embedded in a logic chip or system-on-a-chip. Example 6
[0033] like Figure 4 As shown, this embodiment provides a wiring method for a ferroelectric memory layout structure, including: Step S1: Provide an active area that is tilted; Step S2: Form a word line that extends along the first direction and crosses the active region, and form a transistor gate at the intersection of the active region and the word line; Step S3: A deep trench is formed at one end of the active region to form a ferroelectric capacitor; Step S4: Form contact holes such as active area contact holes and capacitor contact holes; Step S5: Form a bit line extending along the second direction in the first metal layer; Step S6: Form a plate line that is consistent with the extension direction of the bit line and is located in the metal layer above the ferroelectric capacitor; In this case, the bit lines complete all connections within the first metal layer, without performing jumper operations that cross board lines.
[0034] In summary, the ferroelectric memory layout structure and method provided by this invention, by adopting a tilted active region design, achieves higher storage density while making the layered arrangement of deep trenches and other layers more regular, significantly improving the process load effect; and by using the tilted active region, it avoids bit line jumper wiring and simplifies the interconnect structure.
[0035] The above descriptions are merely some embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural changes made based on the concept of the present invention and the description and drawings, or the use of different tilt angles, different wiring layer combinations, different array mirroring methods, etc., are all included within the scope of protection of the present invention. It should be noted that the above embodiments are only for more clearly illustrating the technical solution of the present invention. Those skilled in the art will understand that the implementation of the present invention is not limited to the above content. Any obvious changes, substitutions or replacements made based on the above content do not exceed the scope of the technical solution of the present invention. Other implementations will also fall within the scope of the present invention without departing from the concept of the present invention.
Claims
1. A layout structure for a ferroelectric memory, characterized in that, include: An active region, wherein the active region is arranged at an angle in the layout; Multiple word lines extend along a first direction and cross the active region, forming the gate of a transistor at the overlap. Multiple bit lines are located in the first metal layer and extend along a second direction, which is perpendicular to the first direction. Multiple board lines are located on the metal layer above the ferroelectric capacitor, used to connect the upper electrode of the ferroelectric capacitor, and are set parallel to the word lines; The bit lines are routed within the first metal layer, eliminating the need for jumpers to cross the board lines.
2. The ferroelectric memory layout structure as described in claim 1, characterized in that, The extension direction of the active region is at an angle that is neither orthogonal nor parallel to the first direction.
3. The ferroelectric memory layout structure as described in claim 1, characterized in that, Multiple active regions are arranged parallel to each other and at equal intervals to form an oblique periodic array.
4. The ferroelectric memory layout structure as described in claim 1, characterized in that, The structure also includes a deep trench located at one end of the active region, which is used to form a ferroelectric capacitor.
5. The ferroelectric memory layout structure as described in claim 4, characterized in that, The arrangement direction of the deep trenches is consistent with or matches the extension direction of the active region, so that multiple deep trenches are arranged periodically in the layout.
6. The ferroelectric memory layout structure as described in claim 1, characterized in that, The structure further includes a contact hole, the contact hole comprising at least: Active region contact holes, located in the source or drain region of the transistor, are used to connect the active region to the bit line of the first metal layer; A gate contact hole, located on the word line, is used to connect the word line to the upper metal layer.
7. The ferroelectric memory layout structure as described in claim 6, characterized in that, The contact hole also includes a capacitor contact hole, located at the upper electrode lead-out end of the ferroelectric capacitor, for connecting the plate wire.
8. The ferroelectric memory layout structure as described in claim 4, characterized in that, The ferroelectric memory has a 1T1C type structure, and each memory cell includes one transistor and one ferroelectric capacitor.
9. A wiring method for a ferroelectric memory layout structure, characterized in that, include: Provides an active area that is set at an angle; A word line is formed that extends along a first direction and crosses the active region, and a transistor gate is formed at the intersection. Bit lines extending in the second direction are formed in the first metal layer; Forming a plate line that is consistent with the extension direction of the character line; The bit lines complete all connections within the first metal layer, without any jumper operations crossing the board lines.
10. A ferroelectric memory, characterized in that, The layout structure of the ferroelectric memory is included as described in any one of claims 1 to 8.