Resistive random access memory and method of manufacturing the same

Abstract

The application provides a resistive random access memory and a manufacturing method thereof. The resistive random access memory comprises a semiconductor substrate, an active region arranged in the semiconductor substrate, the active region being in an H-shaped structure and comprising longitudinal active regions and a transverse active region connecting the longitudinal active regions, a word line arranged across the longitudinal active regions, a source line arranged in the transverse active region to realize source line connection and wiring, a first metal layer arranged above the semiconductor substrate, and a resistive random access memory element arranged on the first metal layer. The application realizes source line wiring through the transverse active region, omits source line contact, compresses the word line spacing, and improves the storage density. Meanwhile, the resistive random access memory element is moved downward to the first metal layer, so that all connections can be realized by only two metal layers in the storage area, the process is simplified, and the cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a resistive random access memory and its manufacturing method. Background Technology

[0002] In the field of embedded storage, as semiconductor manufacturing processes advance to advanced technology nodes such as 28nm, 22nm, and 14nm, the integration of traditional memory structures such as floating gate and silicon-oxygen-silicon nitride-oxygen-silicon (SONOS) with logic processes becomes increasingly difficult, and their performance is increasingly unable to meet the growing demands of chips. Therefore, the industry is gradually turning to explore new memory technologies such as magnetic random access memory (MRAM), resistive random access memory (RRAM), phase-change memory (PCM), and ferroelectric random access memory (FeRAM). Among these, resistive random access memory (RRAM) has attracted significant attention due to its substantial advantages, including fast read / write speeds, low power consumption, low manufacturing costs, and high storage density.

[0003] In existing resistive random-access memory (RRAM) architectures, conventional single-transistor single-resistive-transfer (1T1R) architectures typically require at least three metal layers to implement circuit connections. Specifically, in conjunction with... Figure 1 The schematic diagram of a conventional 1T1R resistive switching memory shown is as follows: Figure 2 As shown in the schematic diagram of a conventional resistive random access memory (RRAM), in a conventional structure, the source line (SL) is usually implemented on the first metal layer (M1); the resistive random access memory element (RRAM resistor) is built on the second metal layer (M2); and the bit line (BL) is implemented on the third metal layer (M3) and connected to the top electrode of the resistive random access memory element through a via.

[0004] However, the conventional resistive random access memory (RRAM) structure described above has the following significant drawbacks:

[0005] First, the back-end interconnection process is complex and costly. For example... Figure 2 As shown in the cross-sectional diagram, this conventional structure requires at least three metal layers (M1, M2, M3) and multiple vias (Via1, Via2) to complete the electrical connection of a complete memory cell. This results in cumbersome back-end interconnect (BEOL) process steps and greatly increases manufacturing costs.

[0006] Secondly, storage density is limited, making further miniaturization difficult. For example... Figure 1 and Figure 2As shown, in order to connect the source terminal located in the active region (ACT) of the semiconductor substrate to the first metal layer (M1) to realize the source line (SL) routing, additional source line contacts (i.e., CT in the figure) must be placed between the two word lines (WL). These contacts themselves occupy a certain amount of physical space, and are limited by the design rules of the contact manufacturing process (such as the safety spacing requirements between the contacts and word lines), which prevents the spacing between word lines from being further compressed. This dependence on source line contacts severely restricts the further improvement of the storage density of resistive random access memory.

[0007] Therefore, how to optimize the structure of resistive random access memory, eliminate source line contacts to compress word line spacing, and reduce the number of required metal layers has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0008] The technical problem to be solved by the present invention is that: existing resistive random access memory usually requires at least three metal layers to realize circuit connection, and the source needs to be led out to the metal layer through contacts for source line routing. This results in the contacts occupying a large chip area, and the word line spacing cannot be further reduced, which seriously restricts the improvement of storage density, while increasing the complexity of back-end interconnection process and manufacturing cost.

[0009] To address the aforementioned technical problems, the present invention provides a resistive random access memory, comprising:

[0010] Semiconductor substrate;

[0011] An active region is disposed in the semiconductor substrate. The active region has an H-shaped structure and includes a vertical active region and a lateral active region connecting the vertical active region.

[0012] The character line is set across the longitudinal active area;

[0013] The source line is located in the transverse active area to enable source line connection and routing;

[0014] A first metal layer is disposed above the semiconductor substrate;

[0015] A resistive switching memory element is disposed on the first metal layer.

[0016] Preferably, the source line includes a silicide layer located on the surface of the lateral active region and a doped region located inside the lateral active region.

[0017] Preferably, the silicide layer is a self-aligned silicide layer.

[0018] Preferably, the resistive switching memory further includes a second metal layer disposed above the resistive switching memory element.

[0019] Preferably, the resistive switching memory further includes bit lines disposed in the second metal layer and electrically connected to the top electrode of the resistive switching memory element.

[0020] Preferably, the resistive switching memory element includes a bottom electrode, a resistive switching dielectric layer, and a top electrode stacked sequentially.

[0021] The present invention also provides a method for manufacturing a resistive random access memory (RRAM), for manufacturing the RRAM as described above, comprising:

[0022] Step 1: Provide a semiconductor substrate;

[0023] Step 2: Form an H-shaped active region in the semiconductor substrate, the active region including a vertical active region and a lateral active region connecting the vertical active region;

[0024] Step 3: Form word lines across the longitudinal active region on the semiconductor substrate;

[0025] Step 4: Form a source line in the transverse active region;

[0026] Step 5: Form a first metal layer on the semiconductor substrate;

[0027] Step 6: Form a resistive switching memory element on the first metal layer.

[0028] Preferably, in step four, forming the source line includes: forming a silicide layer on the surface of the lateral active region and forming a doped region inside the lateral active region.

[0029] Preferably, in step four, the silicide layer is formed using a self-aligned silicide process.

[0030] Preferably, in step six, after forming the resistive switching memory element, the method further includes: forming a second metal layer above the resistive switching memory element, and forming bit lines in the second metal layer.

[0031] As described above, the resistive random access memory and its manufacturing method of the present invention have the following beneficial effects:

[0032] This invention designs an H-shaped active region and directly connects and routes source lines using the lateral active region, eliminating the contacts connecting the source ends of word lines and the first metal layer used for source line routing in traditional architectures. This design not only frees up the wiring space of the first metal layer, allowing resistive random access memory (RRAM) elements to be directly built on the first metal layer, thus reducing the number of metal layers required for the entire memory area to two, significantly simplifying the back-end interconnect process and reducing manufacturing costs; at the same time, by completely eliminating the source line contacts, the physical space occupied by the contacts themselves and their safety spacing is eliminated, allowing the spacing between word lines to be further compressed, thereby significantly improving the storage density of the resistive random access memory. Attached Figure Description

[0033] Figure 1 The diagram shown is a planar schematic of a conventional resistive random access memory (RRAM) in the prior art.

[0034] Figure 2 The diagram shown is a cross-sectional schematic of a conventional resistive random access memory (RRAM) in the prior art.

[0035] Figure 3 The diagram shows a process flow diagram of the manufacturing method of the resistive switching memory of the present invention.

[0036] Figure 4 The diagram shown is a plan view of the resistive switching memory of the present invention.

[0037] Figure 5 The diagram shown is a cross-sectional schematic of the resistive switching memory of the present invention. Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] Please refer to Figure 4 and Figure 5 , Figure 4 This is a planar schematic diagram of the resistive random access memory provided in an embodiment of the present invention. Figure 5 This is a cross-sectional schematic diagram of a resistive random access memory provided in an embodiment of the present invention.

[0040] This invention discloses a novel resistive random access memory (RRAM) architecture and its manufacturing method. By optimizing the active region layout and interconnect structure, the number of metal layers required for the memory region is effectively reduced, and the device size is minimized, thereby increasing memory density and reducing manufacturing costs. Embodiments of this invention can be applied to various integrated circuits, including but not limited to microprocessors, microcontrollers, digital signal processors, application-specific integrated circuits (ASICs), and other system-on-a-chip (SoCs) requiring embedded non-volatile memory.

[0041] The resistive random access memory includes a semiconductor substrate 101.

[0042] In some embodiments, such as Figure 5 As shown in the cross-sectional schematic diagram, the semiconductor substrate 101 may include a bulk semiconductor substrate or a silicon-on-insulator substrate. The bulk semiconductor substrate may be made of single-crystal silicon. In other alternatives, the semiconductor substrate 101 may also include other basic semiconductor materials, such as germanium; or compound semiconductor materials, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; or alloy semiconductor materials, such as silicon germanium, gallium arsenide phosphide, gallium aluminum arsenide, indium aluminum arsenide, indium gallium arsenide, or indium gallium arsenide phosphide.

[0043] The semiconductor substrate 101 can be doped with different types of materials according to design requirements, such as implanting P-type or N-type dopants to form P-type or N-type well regions. P-type dopants may include boron, boron difluoride, or indium, and N-type dopants may include phosphorus or arsenic. The semiconductor substrate 101 may also include various isolation features, such as... Figure 5 The shallow trench isolation structure 102 shown is used to define and electrically isolate an active region. Forming the shallow trench isolation structure 102 typically involves etching trenches in a semiconductor substrate 101, followed by filling the trenches with an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or doped silicate glass, using a chemical vapor deposition (CVD) process, high-density plasma chemical vapor deposition (HDPD) process, or spin-coating process. After filling, a chemical mechanical polishing (CMP) process is typically performed to planarize the surface and remove excess insulating material.

[0044] The active region is disposed in the semiconductor substrate 101. The active region has an H-shaped structure and includes a vertical active region and a horizontal active region connecting the vertical active region.

[0045] In some embodiments, combined with Figure 4 As can be seen from the planar layout, the active region is the area in the semiconductor substrate 101 not covered by the shallow trench isolation structure 102, and is used to form active devices. From Figure 4As can be clearly seen, the H-shaped structure design breaks the layout limitations of traditional strip-shaped active regions. Specifically, the vertical active region can be used to form the channel region of the transistor and part of the source-drain region, while the lateral active region physically connects adjacent vertical active regions. This lateral active region provides a continuous semiconductor substrate for the subsequent lateral routing of source lines, avoiding the problem in traditional architectures where the source needs to be led out to the upper metal layer for routing via vertical contacts. Compared with conventional designs, this embodiment eliminates the source contact, effectively saving the chip area occupied by the contact itself and the safety clearance required around it, allowing the spacing between word lines 104 to be further compressed, achieving higher storage density. In addition, the active region can be configured as a planar transistor structure or a three-dimensional multi-gate transistor structure. In the architecture of a three-dimensional field-effect transistor, the active region can be represented as a semiconductor wafer protruding upward from the semiconductor substrate 101, while the lateral active region can be represented as a lateral epitaxial structure or a lateral wafer connection portion connecting different semiconductor wafers.

[0046] The character line 104 is set across the vertical active area.

[0047] In some embodiments, such as Figure 4 and Figure 5 As shown, word line 104 serves as the gate structure for a selection transistor, controlling its on / off state. Word line 104 may include a gate dielectric layer and a gate conductive layer above it. The gate dielectric layer may be a silicon oxide layer formed by thermal oxidation or a high-dielectric-constant material layer formed by atomic layer deposition. The high-dielectric-constant material may include hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, tantalum oxide, yttrium oxide, barium strontium titanate, or combinations thereof. The gate conductive layer may be made of doped polycrystalline silicon. In advanced process nodes, the gate conductive layer typically employs a metal gate structure, which may include a work function adjustment layer and a main conductive layer. The work function adjustment layer is used to adjust the threshold voltage of the transistor. P-type work function materials may include titanium nitride, tantalum nitride, or tungsten carbonitride, while N-type work function materials may include aluminum titanium, aluminum titanium carbide, or aluminum tantalum. The main conductive layer is used to reduce the overall resistance of word line 104, and its material may include tungsten, cobalt, ruthenium, aluminum, or copper. The sidewalls of word line 104 are typically also provided with gate sidewalls, which may include single or multiple layers of insulating material, such as silicon oxide, silicon nitride, silicon carbonitride, or silicon carbonitride oxycarbonate. The gate sidewalls are used to protect the gate structure in subsequent ion implantation processes and to assist in the formation of a lightly doped drain structure.

[0048] The source line is located in the horizontal active area to enable source line connection and routing.

[0049] In some embodiments, the source line includes a silicide layer 110 located on the surface of the lateral active region and a doped region 103 located inside the lateral active region.

[0050] In some embodiments, the silicide layer 110 is a self-aligned silicide layer.

[0051] In some embodiments, such as Figure 5 As shown in the cross-sectional structure, the doped region 103 is located inside the semiconductor lattice of the lateral active region, and its doping type is opposite to that of the semiconductor substrate 101 or the background doping type of the well region. For example, in a P-type well region, the doped region 103 is an N-type heavily doped region implanted with phosphorus or arsenic. The doped region 103 not only serves as the source of the transistor, but also forms a bottom conductive path with a certain conductivity due to its continuous extension along the lateral active region. To further reduce the resistance of this bottom conductive path, a silicide layer 110 is formed on the surface of the lateral active region. The self-aligned silicide layer can effectively reduce the sheet resistance and contact resistance of the source line, improve the transmission speed of electrical signals, and reduce signal delay. The material of the silicide layer 110 may include titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, or a nickel-platinum alloy. The connection and routing of the source line are achieved through the parallel conduction of the doped region 103 inside the lateral active region and the silicide layer 110 on the surface. This design eliminates the need for contacts at the source ends of word lines 104 and the first metal layer 106 for source line routing in traditional structures, greatly simplifying the interconnect structure and reducing manufacturing complexity.

[0052] The first metal layer 106 is disposed above the semiconductor substrate 101.

[0053] In some embodiments, such as Figure 4 and Figure 5 As shown, the first metal layer 106 is part of the back-end interconnect structure and is typically embedded in the interlayer dielectric layer. Figure 5 In this configuration, the first metal layer 106 is connected to the drain region of the longitudinal active region via an outer contact 105. The interlayer dielectric layer may include a low dielectric constant material, an extremely low dielectric constant material, or conventional silicon oxide material to reduce parasitic capacitance between adjacent metal lines. The first metal layer 106 can be formed using a single damascene process or a double damascene process. The material of the first metal layer 106 may include copper, aluminum, tungsten, cobalt, ruthenium, or alloys thereof. A barrier layer and a seed layer are typically included when forming the first metal layer 106. The barrier layer is used to prevent metal atoms from diffusing into the surrounding dielectric layer, and its material may include tantalum, tantalum nitride, titanium, or titanium nitride. Since the source lines are routed through the lateral active region of the underlying layer, a significant amount of wiring resources in the first metal layer 106 are freed up. These freed-up wiring spaces directly serve as the support platform and bottom connection node for the upper resistive switching memory element 107.

[0054] The resistive switching memory element 107 is disposed on the first metal layer 106.

[0055] In some embodiments, the resistive switching memory element 107 includes a bottom electrode, a resistive switching dielectric layer, and a top electrode stacked sequentially.

[0056] In some embodiments, such as Figure 5 As shown, the bottom electrode is in direct contact with the first metal layer 106 and forms an electrical connection. The bottom and top electrodes need to possess good conductivity and chemical stability; their materials can include titanium nitride, tantalum nitride, platinum, gold, ruthenium, iridium, tungsten, or combinations thereof. The resistive switching dielectric layer is the core functional layer for realizing the resistive switching effect; its resistance state can reversibly switch between a low-resistance state and a high-resistance state under the influence of an external electric field. The material of the resistive switching dielectric layer can include transition metal oxides, such as hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, zirconium oxide, tungsten oxide, or nickel oxide. The resistive switching mechanism of the resistive switching dielectric layer is usually related to the generation and recombination of oxygen vacancies. Under the programming voltage, oxygen vacancies accumulate in the resistive switching dielectric layer to form conductive filaments, causing the device to exhibit a low-resistance state; under the erase voltage, the conductive filaments break, and the device returns to a high-resistance state. Moving the resistive switching memory element 107 down and building it directly on the first metal layer 106 makes full use of the vertical space, shortens the conductive path between the memory element and the underlying control transistor, helps to reduce parasitic resistance and parasitic capacitance, and improves read and write speed.

[0057] In some embodiments, the resistive switching memory further includes a second metal layer 109 disposed above the resistive switching memory element 107.

[0058] In some embodiments, the resistive random access memory further includes a bit line 109 disposed in a second metal layer 109 and electrically connected to the top electrode of the resistive random access memory element 107.

[0059] In some embodiments, from Figure 4 floor plan and Figure 5 As can be clearly seen in the cross-sectional view, the second metal layer 109 is also embedded in the intermetallic dielectric layer. Its material and formation process can be similar to that of the first metal layer 106, for example, using a copper damask process. The bit line 109 serves as the main channel for data transmission, responsible for applying voltage to the resistive switching memory element 107 or reading current signals during read / write operations. The bit line 109 typically extends in a direction perpendicular to the word line 104. The bit line 109 can be electrically connected to the top electrode of the resistive switching memory element 107 through a vertical conductive via 108. The material of the conductive via 108 can include tungsten, copper, or cobalt.

[0060] With the above structural design, the entire memory area only requires two metal layers to achieve all the necessary electrical connections. Compared to the traditional architecture that requires at least three metal layers, this design significantly reduces the number of photomasks used, simplifies the back-end interconnect process, lowers manufacturing costs, reduces yield risks associated with multi-layer metal interconnects, and improves the overall reliability of the device.

[0061] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the manufacturing process of a resistive random access memory (RRAM) provided in an embodiment of the present invention. Figure 3 As shown, the manufacturing method of resistive random access memory includes the following steps:

[0062] Step 1: Provide a semiconductor substrate 101.

[0063] In some embodiments, the step of providing the semiconductor substrate 101 may further include performing a series of pretreatment processes on the semiconductor substrate 101. Semiconductor manufacturing equipment may include a cleaning machine and an oxidation furnace. Typically, standard cleaning processes are used to remove organic matter, particles, and metallic impurities from the surface of the semiconductor substrate 101. Subsequently, a thin sacrificial oxide layer can be grown on the surface of the semiconductor substrate 101 through a thermal oxidation process and then removed to achieve the removal of surface defects.

[0064] Step 2: An H-shaped active region is formed in the semiconductor substrate 101. The active region includes a vertical active region and a lateral active region connecting the vertical active region.

[0065] In some embodiments, the formation of the H-shaped active region relies primarily on advanced photolithography and etching techniques. Specifically, a photoresist layer is uniformly coated on the surface of a semiconductor substrate 101, and the photoresist is exposed using a mask with an H-shaped pattern. After exposure, the photoresist undergoes development to form a photoresist mask pattern corresponding to the H-shaped active region. Then, using the photoresist as a mask, the semiconductor substrate 101 or the hard mask layer above it is etched to remove excess semiconductor or mask material, thereby preserving the H-shaped active region. During the etching process, the verticality and dimensional accuracy of the etching profile can be ensured by adjusting the ratio of etching gas, RF power, and chamber pressure. Next, silicon oxide insulating material is filled into the trenches using a high-density plasma chemical vapor deposition process; finally, excess insulating material and the hard mask layer are removed using a chemical mechanical polishing process to achieve surface planarization, thereby defining the inclined active region boundary in the semiconductor substrate. This special H-shaped pattern design allows for the direct use of the semiconductor substrate to achieve lateral interconnection of source lines without adding additional metal layers. For three-dimensional transistor architectures, forming H-type active regions may also involve epitaxial growth processes, such as selectively epitaxially growing semiconductor materials between adjacent semiconductor wafers to form a lateral bridging structure connecting the vertical semiconductor wafers.

[0066] Step 3: Form word lines 104 that span the vertical active region on the semiconductor substrate 101.

[0067] In some embodiments, the first step of forming the select transistor includes defining a pattern of the well region using a photolithography process and implanting corresponding impurity ions into the semiconductor substrate using an ion implanter to form a P-type well region or an N-type well region. After implantation, a high-temperature annealing process is performed to repair lattice damage and activate the implanted impurities. The semiconductor manufacturing equipment may include a photolithography machine, a cleaning machine, an ion implanter, and a rapid thermal annealing device. Next, the step of forming the word line 104 includes sequentially depositing a gate dielectric material layer and a gate conductive material layer on the semiconductor substrate 101. The deposition equipment may include an atomic layer deposition device, a chemical vapor deposition device, or a physical vapor deposition device. Subsequently, the gate dielectric material layer and the gate conductive material layer are patterned using photolithography and etching processes to form a strip-shaped word line 104 structure spanning the vertical active region. In embodiments employing a post-gate replacement process, a pseudo-gate structure composed of polysilicon is first formed. After completing the formation of the source / drain regions and the deposition and planarization of the interlayer dielectric layer, the polysilicon pseudo-gate is removed to form a gate trench. Then, a high-dielectric-constant gate dielectric layer, a work function metal layer, and a fill metal layer are sequentially deposited in the gate trench. Finally, excess metal material is removed by chemical mechanical polishing to form the actual metal word line 104. After the word line 104 is formed, sidewall structures are typically formed on both sides of the word line 104. The sidewall formation method involves conformally depositing one or more layers of insulating material across the entire device surface, for example, depositing a silicon nitride layer using a low-pressure chemical vapor deposition process, followed by an anisotropic etching-back process to remove the insulating material on the horizontal surface, leaving only the insulating material on the sidewalls of the word line 104 to form the sidewalls. The sidewalls are used to protect the word line 104 in subsequent ion implantation processes and to achieve self-alignment of the lightly doped drain structure and the heavily doped source / drain region.

[0068] Step 4: Form source lines in the transverse active region.

[0069] In some embodiments, step four, forming a source line includes forming a silicide layer 110 on the surface of the lateral active region and forming a doped region 103 inside the lateral active region.

[0070] In some embodiments, in step four, a silicide layer 110 is formed using a self-aligned silicide process.

[0071] In some embodiments, the doped region 103 can be formed by implanting a high dose of N-type or P-type impurity ions into the lateral active region using an ion implantation device, with the word line 104 and sidewalls as masks. The implantation process can be performed in multiple steps, including halo implantation to suppress short-channel effects, lightly doped drain implantation to reduce the peak drain field, and main source / drain implantation to form low-resistance contacts. After implantation, a rapid thermal annealing or laser annealing process is performed to allow impurity atoms to enter and activate the lattice points, while repairing lattice damage caused by implantation, thereby forming a continuous conductive doped region 103 within the lateral active region.

[0072] Self-aligned silicide processes typically involve the following detailed steps: First, a pre-cleaning process is performed, such as using a dilute hydrofluoric acid solution to remove the native oxide layer on the surface of the lateral active region, ensuring a clean semiconductor surface. Then, a refractory metal thin film, such as titanium, cobalt, nickel, or alloys thereof, is deposited uniformly on the surface of the semiconductor substrate 101 using physical vapor deposition. Next, a first rapid thermal annealing process is performed, at a specific temperature, causing the metal thin film to undergo a solid-state chemical reaction with the silicon on the surface of the lateral active region, generating a metal-rich silicide phase. Since the metal thin film does not react with the insulating material on the sidewalls or isolation structures, this process exhibits self-alignment characteristics. Subsequently, a selective wet etching process, such as using a mixture of ammonia, hydrogen peroxide, and deionized water, is used to remove the unreacted metal thin film. Finally, a second rapid thermal annealing process is performed, at an even higher temperature, to transform the metal-rich silicide phase into a low-resistivity stable silicide layer 110. In this way, source lines are formed directly within the lateral active region without the need for additional contacts to connect to the upper metal layer, effectively reducing word line spacing.

[0073] Step 5: Form a first metal layer 106 on the semiconductor substrate 101.

[0074] In some embodiments, before forming the first metal layer 106, a contact interlayer dielectric layer is deposited on the semiconductor substrate 101, and the contact interlayer dielectric layer is chemically and mechanically polished to achieve surface planarization. The material of the contact interlayer dielectric layer may include phosphosilicate glass, borosilicate glass, or undoped silicate glass. Subsequently, contact holes are formed in the contact interlayer dielectric layer by photolithography and etching processes, and conductive materials, such as tungsten or cobalt, are filled in the contact holes to form contacts 105 connecting the underlying device and the upper metal layer. It should be noted that since the source line has already been routed through the lateral active region of the underlying layer, it is not necessary to form contacts connecting the source line to the first metal layer 106 here. Next, a first intermetallic dielectric layer is deposited above the contact interlayer dielectric layer. The first metal layer 106 is formed in the first intermetallic dielectric layer by damascus etching or patterned etching processes. Taking the copper double damask process as an example, trenches and vias are first etched in the dielectric layer. Then, a tantalum or tantalum nitride barrier layer and a copper seed layer are deposited using physical vapor deposition. Next, copper metal is filled using electroplating. Finally, excess copper and barrier layer material outside the trenches are removed using chemical mechanical polishing. Since the source lines are already routed in the active region, a large amount of wiring space in the first metal layer 106 is freed up, allowing for more flexible circuit layout.

[0075] Step 6: Form a resistive switching memory element 107 on the first metal layer 106.

[0076] In some embodiments, after forming the resistive switching memory element 107 in step six, a second metal layer 109 is formed over the resistive switching memory element 107, and a bit line 109 is formed in the second metal layer 109.

[0077] In some embodiments, forming the resistive switching memory element 107 includes sequentially depositing a bottom electrode material layer, a resistive switching dielectric material layer, and a top electrode material layer on the surface of a first metal layer 106 and a planarized dielectric layer. The deposition process can employ atomic layer deposition, chemical vapor deposition, or physical vapor deposition to ensure the uniformity and density of the thickness of each film layer. Subsequently, photoresist is coated or a hard mask layer is deposited over the top electrode material layer, and the pattern of the resistive switching memory element 107 is defined by photolithography. Using the photoresist or hard mask layer as a mask, a dry etching process such as reactive ion etching is employed to sequentially etch through the top electrode material layer, the resistive switching dielectric material layer, and the bottom electrode material layer, patterning them into individual resistive switching memory cells. After etching, a protective dielectric layer, such as silicon nitride, is typically deposited to encapsulate the resistive switching memory element 107 and prevent it from being corroded by moisture or oxygen in subsequent processes. The process for forming the second metal layer 109 and the bit line 109 can continue to employ a dual damascene process.

[0078] Specifically, a second intermetallic dielectric layer is deposited above the resistive switching memory element 107. Through-holes and trenches are etched into the second intermetallic dielectric layer using photolithography and etching processes, with the through-holes exposing the top electrode of the resistive switching memory element 107. Then, a barrier layer and a seed layer are sequentially deposited, followed by electroplating to fill with a conductive material, such as copper or cobalt. Finally, chemical mechanical polishing is performed to form a second metal layer 109 and bit lines 109 located therein. The bit lines 109 are reliably electrically connected to the top electrode of the resistive switching memory element 107 through through-holes 108. This manufacturing method allows the entire memory device to be manufactured using only two metal layers, simplifying the process, shortening the production cycle, and improving production efficiency.

[0079] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0080] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A resistive random access memory, characterized in that, include: Semiconductor substrate; An active region is disposed in the semiconductor substrate. The active region has an H-shaped structure and includes a vertical active region and a lateral active region connecting the vertical active region. The character line is set across the longitudinal active area; The source line is located in the transverse active area to enable source line connection and routing; A first metal layer is disposed above the semiconductor substrate; A resistive switching memory element is disposed on the first metal layer.

2. The resistive random access memory according to claim 1, characterized in that: The source line includes a silicide layer located on the surface of the lateral active region and a doped region located inside the lateral active region.

3. The resistive random access memory according to claim 2, characterized in that: The silicide layer is a self-aligned silicide layer.

4. The resistive random access memory according to claim 1, characterized in that: The resistive switching memory further includes a second metal layer disposed above the resistive switching memory element.

5. The resistive random access memory according to claim 4, characterized in that: The resistive switching memory further includes bit lines disposed in the second metal layer and electrically connected to the top electrode of the resistive switching memory element.

6. The resistive random access memory according to claim 1, characterized in that: The resistive switching memory element includes a bottom electrode, a resistive switching dielectric layer, and a top electrode stacked sequentially.

7. A method for manufacturing a resistive random access memory (RRAM), characterized in that, include: Step 1: Provide a semiconductor substrate; Step 2: Form an H-shaped active region in the semiconductor substrate, the active region including a vertical active region and a lateral active region connecting the vertical active region; Step 3: Form word lines across the longitudinal active region on the semiconductor substrate; Step 4: Form a source line in the transverse active region; Step 5: Form a first metal layer on the semiconductor substrate; Step 6: Form a resistive switching memory element on the first metal layer.

8. The method for manufacturing a resistive random access memory according to claim 7, characterized in that: In step four, forming the source line includes: forming a silicide layer on the surface of the lateral active region and forming a doped region inside the lateral active region.

9. The method for manufacturing a resistive random access memory according to claim 8, characterized in that: In step four, the silicide layer is formed using a self-aligned silicide process.

10. The method for manufacturing a resistive random access memory according to claim 7, characterized in that: In step six, after forming the resistive switching memory element, the method further includes: forming a second metal layer above the resistive switching memory element, and forming bit lines in the second metal layer.

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