A silicon carbide semiconductor device having a multi-layer buffer and a shallow junction termination and a manufacturing process thereof

Abstract

The present application relates to the technical field of semiconductor devices, in particular to a silicon carbide semiconductor device with multi-layer buffer and shallow junction terminal and a manufacturing process thereof. The device comprises a substrate, an N-type composite buffer layer arranged on the substrate and decreasing in concentration layer by layer, a drift region, an active region and a composite terminal structure. The active region is located on a top first surface of the drift region, and an integrated composite terminal structure is arranged on a sunken step surface surrounding the active region, which is lower than the first surface by a height Δh. Through the sunken structure, the distance D term is strictly less than the distance D active from the bottom of the P-type injection region of the active region to the top of the buffer layer, forming an out-of-plane field stop coupling structure. The present application uses the difference in spatial distance to make the depletion layer touch the buffer layer in advance, generates a field stop effect to protect the terminal edge, ensures super-high-speed soft recovery, improves voltage-withstanding reliability, has low process thermal budget, and has high performance and high practicality.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a silicon carbide semiconductor device with multilayer buffers and shallow junction terminals and its manufacturing process. Background Technology

[0002] Silicon carbide (SiC) is an ideal material for manufacturing next-generation high-power, high-frequency semiconductor devices due to its inherent superior properties, such as large bandgap, high critical breakdown electric field, and high thermal conductivity. Among them, the SiC junction barrier Schottky (JBS) diode combines the extremely low forward voltage drop and ultrafast switching speed of a Schottky diode (SBD) with the low reverse leakage current of a PiN diode, making it extremely promising for applications in photovoltaic inverters, new energy vehicles, and high-frequency switching power supplies.

[0003] In the design of SiC JBS diodes, to achieve higher frequency switching characteristics and extremely low reverse recovery charge (Qrr), an N-type buffer layer is typically introduced at the bottom of the drift region to modulate the longitudinal electric field, smooth the carrier extraction process, achieve "soft recovery" characteristics, and prevent dynamic avalanche. On the other hand, to alleviate the electric field concentration effect at the device edge and achieve high breakdown voltage, a junction termination extension region (JTE) or field limiting ring (FLR) is usually set around the active region. Due to the extremely low diffusion coefficient of impurity atoms in SiC material, traditional deep junction JTE structures require extremely high ion implantation energy and extremely long ultra-high temperature annealing (typically >1700℃), which not only leads to extremely high process thermal budgets but also causes severe degradation of the device surface morphology (such as step clustering effect).

[0004] To reduce thermal budgets and simplify manufacturing processes, the industry has begun to explore shallow junction extension (S-JTE). However, existing device designs often fall into a design limitation of horizontal and vertical separation: treating the bottom buffer layer design and the surface termination structure as two independent modules. In actual high-voltage, high-frequency dynamic blocking processes, this completely planar isolated design exposes serious structural defects.

[0005] Specifically, when using a conventional coplanar structure, the uniformly distributed high-concentration buffer layer at the bottom pushes the depletion layer upwards under reverse bias. For surface shallow junction terminations (S-JTEs), which already have weak resistance to electric field distortion, this downward pushing effect leads to severe lateral and longitudinal three-dimensional accumulation of the surface electric field at the boundary between the active and termination regions (Crowding effect). This makes the shallow junction termination highly susceptible to premature edge breakdown before reaching the theoretical design voltage.

[0006] Therefore, how to overcome the damage to the edge of the shallow junction termination caused by the upward electric field of the buffer layer under the planar architecture, and achieve three-dimensional deep coordination between the lateral termination and the vertical buffer layer in terms of spatial electric field distribution, while ensuring the ultra-high speed soft recovery characteristics of SiC JBS devices and utilizing the shallow junction termination process with low thermal budget, is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] The purpose of this invention is to provide a silicon carbide semiconductor device with multilayer buffers and shallow junction terminals and its manufacturing process, so as to solve the technical problem mentioned in the background art that the electric field pushed on the bottom buffer layer can easily cause edge electric field distortion and premature breakdown of the surface shallow junction terminals under the existing planar architecture.

[0008] To achieve the above objectives, the present invention provides a silicon carbide semiconductor device with multilayer buffer and shallow junction termination, comprising an N+ type SiC substrate, an N-type composite buffer layer disposed on the substrate, an N-type drift region disposed on the buffer layer, and an active region and an integrated composite termination structure surrounding the active region; wherein: The active region is located on the top first surface of the N-type drift region; The integrated composite terminal structure is set on the sunken step surface surrounding the active area, and the sunken step surface is lower than the first surface by a step height Δh; The integrated composite termination structure includes a shallow junction terminal extension region (S-JTE) and a field limiting ring. The junction depth of the S-JTE is 0.1μm-0.4μm. The N-type composite buffer layer consists of at least two N-type SiC epitaxial layers with concentrations decreasing from bottom to top. The first vertical distance from the bottom of the shallow knot terminal extension region to the top of the N-type composite buffer layer is D. term The second vertical distance from the bottom of the P-type ion implantation region to the top of the N-type composite buffer layer within the active region is D. active Due to the existence of the step height Δh, D term Strictly less than D active Together, they constitute a non-surface field cutoff coupling structure.

[0009] Preferably, the step height Δh ranges from 0.5 μm to 1.5 μm.

[0010] Preferably, the total thickness of the N-type composite buffer layer is 1.2 μm to 6 μm; in the reverse blocking state, the bottom depletion layer of the terminal region is configured to contact the N-type composite buffer layer before the bottom depletion layer of the active region.

[0011] Preferably, the active region includes alternating Schottky contact regions and P-type ion implantation regions, forming a junction barrier Schottky (JBS) structure.

[0012] The present invention also provides a manufacturing process for the above-mentioned silicon carbide semiconductor device, comprising the following steps: S1. An N-type composite buffer layer and an N-type drift region are epitaxially grown sequentially on an N+ type SiC substrate; S2. Local dry etching is performed on the surface of the N-type drift region using a mask to form a sunken step surface in the terminal region that is lower than the first surface of the active region by Δh. S3. Perform the first ion implantation on the surface of the sunken step to form a shallow junction terminal extension region and field confinement ring with a junction depth of 0.1μm-0.4μm; S4. Perform a second ion implantation on the first surface to form a P-type ion implantation region with an active area. S5. Perform a high-temperature annealing process to simultaneously activate the implanted ions in the terminal region and the active region.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: In this silicon carbide semiconductor device and its manufacturing process featuring multilayer buffers and shallow junction terminations, the present invention abandons the conventional coplanar design inertia and introduces a sunken step structure. Due to the presence of the step height Δh, the fragile shallow junction termination is physically and geometrically closer to the bottom multilayer composite buffer layer (i.e., D). term <D active When the device is subjected to reverse high voltage, the depletion layer at the termination edge can preferentially and early contact the top layer of the composite buffer layer. At this time, the high-concentration region at the top layer of the composite buffer layer is transformed into an early field cutoff region specifically designed for the termination, which clamps the peak electric field at the termination edge and pushes it into a safe region inside the device. This eliminates the damage to the surface shallow junction caused by the upward push of the bottom buffer electric field, and significantly improves the device's resistance to dynamic avalanche and breakdown voltage.

[0014] Secondly, the bottom layer of this invention retains a multi-layer buffer design with gradually decreasing concentration, located directly below the active region (at a considerable distance, D). term (The buffer layer is relatively large), which acts as an electron deceleration slope, smoothly extracting charge carriers and ensuring that the device has excellent ultra-high-speed soft recovery characteristics and extremely low reverse recovery charge (Qrr). At the same time, thanks to the electric field clamping effect of the aforementioned edge step, the device maintains soft recovery without edge leakage or premature breakdown, successfully breaking the traditional limitations between on-state voltage drop, reverse recovery characteristics and breakdown voltage.

[0015] Meanwhile, the junction depth of the terminal structure in this invention is only 0.1μm-0.4μm (ultra-shallow junction), which significantly reduces the energy requirements for ion implantation and the thermal budget (annealing time and temperature) required for subsequent activation. This low thermal budget process not only effectively avoids the step-like clustering effect on the SiC surface but also protects the thin, multi-layered composite buffer layer at the bottom at the thermodynamic process level, preventing the diffusion of step impurity concentration due to high temperatures. Furthermore, the fabrication of the step structure only requires an additional step of conventional micron-level dry etching, making it fully compatible with existing SiC wafer manufacturing lines, with high yield and strong feasibility for large-scale mass production. Attached Figure Description

[0016] Figure 1 This is an overall flowchart of Embodiment 2 of the present invention. Detailed Implementation

[0017] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1: A 1200V SiC JBS diode with multilayer buffer and sunken shallow junction termination.

[0019] This embodiment provides a semiconductor device based on 4H-SiC material, optimized for 1200V high-frequency applications. The device, from bottom to top, includes: N+ type SiC substrate: using offset <0001> The N+ type 4H-SiC substrate with a crystal orientation tilt of 4 degrees and a thickness of about 350 μm has a doping concentration that is typically greater than 1E19 cm^-3 to ensure extremely low substrate resistance.

[0020] N-type composite buffer layer: Epitaxially grown on the substrate. In this embodiment, the composite buffer layer has a three-layer stepped structure with a total thickness T. buffer It is 2.5 μm. Specifically, from bottom to top, it includes: First buffer layer: 0.5 μm thick, doping concentration 1E18 cm^-3. Its extremely high concentration is used to block minority carriers from being injected into the substrate and to act as a barrier layer against epitaxial defects.

[0021] Second buffer layer: 1.0 μm thick, doping concentration 5E17 cm^-3.

[0022] Third buffer layer: 1.0 μm thick, doping concentration 1E17 cm^-3.

[0023] The above-mentioned three-layer concentration decreasing layer by layer can, in the later stage of reverse recovery of the device, act as a longitudinal deceleration slope for carrier extraction by gradually widening the space charge region, thereby effectively suppressing current surges (decrease di / dt) and achieving smooth ultrafast soft recovery characteristics.

[0024] N-type drift region: continuously epitaxially grown on the composite buffer layer, with a thickness of 10 μm and a doping concentration of 8E15 cm^-3. This drift region is horizontally divided into a central region (corresponding to the top first surface) and a peripheral terminal region surrounding the central region.

[0025] Mesa (Sunken Step Structure): In the terminal region, the surface of the drift area is locally etched downwards, forming a sunken step surface that is lower than the first surface of the central region. In this embodiment, the step height Δh is set to 0.8 μm. Preferably, the angle between the etched sidewall and the bottom surface of the step is controlled between 45° and 80° to avoid electric field spikes (crowding effect) caused by right-angle steps.

[0026] Active region (JBS structure): Located on the first surface of the unetched central region, it includes alternating Schottky contact regions and P-type ion implantation regions. The P-type ion implantation regions are arranged in a periodic stripe or hexagonal honeycomb array with a junction depth of 0.6 μm and a surface doping concentration of 1E19 cm^-3.

[0027] Integrated composite termination structure: This structure is integrally disposed on the surface of the recessed step. It includes a shallow junction termination extension region (S-JTE) adjacent to the sidewall of the step and at least three guard field restraint rings (FLRs) extending outwards. The implantation junction depth of the S-JTE and FLRs is extremely shallow, only 0.2 μm, with a doping concentration gradient ranging from 1E17 cm⁻³ to 5E17 cm⁻³.

[0028] In conventional coplanar devices, the edge electric field is prone to three-dimensional divergence, both downwards and laterally. However, in this embodiment: The first vertical distance D from the bottom of the active P-junction to the top of the third buffer layer active =10μm-0.6μm=9.4μm.

[0029] The second vertical distance D from the bottom of the S-JTE terminal to the top of the third buffer layer term =10μm-0.8μm-0.2μm=9.0μm.

[0030] Due to the existence of Δh, D term <D active When the device is reverse biased and the voltage gradually increases to the rated voltage (1200V), the depletion layer simultaneously extends downwards. Due to D termEven shorter, the depletion layer front in the terminal region will touch the third buffer layer with a higher doping concentration about 0.4 μm earlier.

[0031] Once touched, the donor charges in the third buffer layer will immediately neutralize the terminal electric field, triggering an early field cutoff effect. This is equivalent to building an invisible electric field barrier directly below the fragile shallow junction, forcibly shifting the peak electric field that would normally accumulate at the edge of the step towards the bulk silicon at the center of the device, thus perfectly solving the problem of edge avalanche breakdown that is very prone to occur at shallow junction terminals.

[0032] Example 2: Manufacturing process for SiC semiconductor devices with the above structure.

[0033] This embodiment provides a low-thermal-budget manufacturing process that matches Embodiment 1 and has extremely high production line compatibility. Figure 1 As shown, the specific steps are as follows: S1. Continuous epitaxial growth: On an N+ type SiC substrate, a chemical vapor deposition (CVD) device is used to continuously epitaxially grow the first buffer layer, the second buffer layer, the third buffer layer and the N-type drift region in one go by precisely controlling the flow ratio of silicon source, carbon source and nitrogen doping source, ensuring the lattice integrity of each layer interface.

[0034] S2. Inductively Coupled Plasma (ICP) Etching of the Recessed Step: A silicon dioxide hard mask is deposited on the surface of the drift region and a photolithographic pattern is formed to expose the peripheral terminal area. An ICP dry etching process based on an SF6 / O2 mixed gas is used to precisely etch down to 0.8 μm, forming a recessed step surface with a sidewall tilt angle of approximately 60°. The hard mask is removed after etching.

[0035] S3, Shallow Junction Low-Energy Implantation in Terminal Region: An oxide mask is deposited again on the wafer surface. Multi-stage low-energy implantation of aluminum (Al) ions is performed on the surface of the sunken step (energy controlled at 30keV-150keV, temperature at 500℃ to reduce lattice damage) to form S-JTE and FLR with a junction depth of 0.2μm.

[0036] S4. High-energy implantation of deep junction in active region: Using a new photolithography mask, high-energy implantation of aluminum ions (up to 350keV) is performed on the unetched central first surface to form a P-type implantation region with a junction depth of 0.6μm.

[0037] S5. Carbon Film Co-annealing with Low Thermal Budget: To prevent silicon atom sublimation (step-like clustering effect) in the ultra-shallow junction at high temperatures, photoresist is spin-coated onto the wafer surface and pyrolyzed and carbonized at 800°C to form a dense carbon protective film. This is followed by rapid high-temperature annealing at 1650°C in an argon (Ar) atmosphere. Due to the 0.2μm ultra-shallow junction design at the terminal, the thermodynamic time required for ion activation is significantly reduced. This low thermal budget process, while activating surface ions, greatly suppresses the thermal diffusion and mutual dissolution of doped atoms within the bottom three-layer composite buffer layer, perfectly preserving its step-like concentration gradient morphology. After annealing, oxygen plasma ashing is used to remove the carbon protective film.

[0038] S6. Metallization and Passivation: Titanium (Ti) and nickel (Ni) are sputtered and deposited on the front side, and ohmic contacts are formed in the P-type region by rapid thermal annealing at 900℃; then titanium (Ti) is sputtered as Schottky barrier metal. Finally, polyimide (PI) is deposited as a surface passivation layer, and a Ni / Ag metal stack is evaporated on the back side to form a cathode.

[0039] Example 3: Parameter extension for UHV applications of 3300V and above.

[0040] For high-voltage power transmission and distribution and rail transit applications of 3300V or higher, the electric field energy inside the device increases exponentially. This embodiment performs in-depth optimization of the non-plane coupling parameters: The thickness of the drift region was increased to 30 μm, and the doping concentration was reduced to 3E15 cm^-3.

[0041] To absorb the enormous turn-off peak energy under ultra-high voltage, the total thickness T of the composite buffer layer is increased. buffer The concentration was increased to 5.0 μm and further subdivided into 4-5 layers of extremely slowly varying concentration gradients.

[0042] To match the thickened buffer layer and ensure that the early field cutoff effect remains strong, the step height Δh was simultaneously increased to 1.5 μm.

[0043] Under the extremely high dv / dt impact generated by the instantaneous reverse bias of ultra-high voltage, the extremely thick buffer layer at the bottom absorbs the impact energy with an extremely wide space charge region (suppressing dynamic avalanche), while its top layer provides a strong field cutoff capability to support the shallow junction terminal that sinks 1.5μm, thus ensuring extremely high withstand voltage while maintaining excellent dynamic soft recovery characteristics.

[0044] To verify the technical effect of the sunken step combined with the multi-layer buffer non-plane coupling structure of this invention, the inventors conducted TCAD simulation and chip fabrication physical testing based on a 1200V / 20A benchmark design (using a dual-pulse test platform, bus voltage 800V, forward current 20A, di / dt=150A / μs). The test results are shown in Table 1 below.

[0045] Sample grouping and design Example 1 Sample (Invention): Step height 0.8μm + terminal junction depth 0.2μm + total thickness of buffer layer 2.5μm (using low thermal budget rapid annealing).

[0046] Comparative Example 1 (Conventional coplanar shallow junction): No step (0μm, coplanar) + terminal junction depth 0.2μm + total thickness of buffer layer 2.5μm (low thermal budget rapid annealing).

[0047] Comparative Example 2 (Conventional Coplanar Deep Junction): No step (0μm, coplanar) + terminal junction depth 1.5μm + total thickness of buffer layer 2.5μm (using 1750℃ long-time high-temperature annealing to ensure deep junction activation).

[0048] Comparative Example 3 (insufficient step depth): Step height 0.1μm + terminal junction depth 0.2μm + total thickness of buffer layer 2.5μm (low thermal budget rapid annealing).

[0049] Comparative Example 4 (step depth transition): step height 3.0μm + terminal junction depth 0.2μm + total thickness of buffer layer 2.5μm (low thermal budget rapid annealing).

[0050] Table 1: Experimental Data Results ; As shown in the table above, Comparative Example 1 clearly demonstrates that if a coplanar combination is used according to the conventional thinking of existing technology, the bottom buffer electric field will directly destroy the surface shallow junction, leading to premature breakdown at 950V. Comparative Example 2 demonstrates that using a deep junction to solve the breakdown voltage problem inevitably destroys the bottom buffer layer during high-temperature annealing, resulting in the loss of soft recovery characteristics (S drops sharply to 0.35). By cleverly introducing a 0.8μm step in the embodiment, the buffer layer is preserved from high-temperature damage, and the breakdown voltage problem of the shallow junction is solved by utilizing the non-planar structure.

[0051] Secondly, Comparative Example 3 shows that if the step is too shallow (0.1 μm), it cannot induce a significant early field cutoff effect; Comparative Example 4 shows that if the step is too deep (3.0 μm), it will severely compress the depletion region development space of the terminal, leading to high leakage current and increased dynamic loss.

[0052] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A silicon carbide semiconductor device with multilayer buffers and shallow junction terminations, characterized in that, The invention comprises an N+ type SiC substrate, an N-type composite buffer layer disposed on the N+ type SiC substrate, an N-type drift region disposed on the N-type composite buffer layer, an active region, and an integrated composite termination structure surrounding the active region; characterized in that: The active region is disposed on the unetched top first surface of the N-type drift region; The integrated composite terminal structure is disposed on a sunken step surface surrounding the active area, and the sunken step surface is lower than the top first surface by a step height Δh. The integrated composite terminal structure includes at least a shallow junction terminal extension region (S-JTE), wherein the junction depth of the shallow junction terminal extension region is 0.1 μm to 0.4 μm; The N-type composite buffer layer is composed of at least two N-type SiC epitaxial layers with doping concentration decreasing from bottom to top. The vertical distance from the bottom of the shallow knot terminal extension area to the top of the N-type composite buffer layer is defined as the first vertical distance D. term The vertical distance from the bottom of the P-type ion implantation region within the active region to the top of the N-type composite buffer layer is defined as the second vertical distance D. active ; Due to the existence of the step height Δh, the first vertical distance D term Less than the second vertical distance D active The integrated composite terminal structure and the N-type composite buffer layer are configured together as an anisotropic field cutoff coupling structure.

2. The silicon carbide semiconductor device with multilayer buffer and shallow junction termination according to claim 1, characterized in that, The step height Δh ranges from 0.5μm to 1.5μm; the angle between the step sidewall connecting the top first surface and the sunken step surface and the horizontal plane is from 45 degrees to 80 degrees.

3. The silicon carbide semiconductor device with multilayer buffer and shallow junction termination according to claim 1, characterized in that, The total thickness of the N-type composite buffer layer ranges from 1.2 μm to 5.0 μm; when the silicon carbide semiconductor device is in reverse blocking state, due to the first vertical distance D term Less than the second vertical distance D active The terminal depletion layer located below the surface of the sunken step touches the top layer of the N-type composite buffer layer before the active depletion layer below the active region.

4. The silicon carbide semiconductor device with multilayer buffer and shallow junction termination according to claim 1, characterized in that, The active region includes alternating Schottky contact regions and P-type ion implantation regions, forming a junction barrier Schottky structure; the junction depth of the P-type ion implantation region is greater than the junction depth of the shallow junction terminal extension region.

5. The silicon carbide semiconductor device with multilayer buffer and shallow junction termination according to claim 1, characterized in that, The integrated composite terminal structure also includes at least three field-limiting rings extending outward, the junction depth of which is the same as the junction depth of the shallow junction terminal extension region; and the shallow junction terminal extension region and the field-limiting rings have a doping concentration gradient distribution.

6. A manufacturing process for a silicon carbide semiconductor device having multilayer buffers and shallow junction terminations as described in any one of claims 1 to 5, characterized in that, Includes the following steps: S1. Provide an N+ type SiC substrate, continuously epitaxially grow multiple N-type composite buffer layers with progressively decreasing doping concentration on the substrate, and epitaxially grow an N-type drift region on the N-type composite buffer layer. S2. Define a terminal region on the surface of the N-type drift region and perform local downward etching to form a sunken step surface with a height Δh lower than the first surface of the active region. S3. Perform the first ion implantation on the surface of the sunken step to form a shallow junction terminal extension region with a junction depth of 0.1 μm to 0.4 μm; S4. Perform a second ion implantation on the first surface of the active region that has not been etched to form a P-type ion implantation region of the active region. S5. Perform a high-temperature annealing process to simultaneously activate the injected ions in the active region and the integrated composite terminal structure.

7. The silicon carbide semiconductor device with multilayer buffer and shallow junction termination according to claim 6, characterized in that, In step S2, an inductively coupled plasma dry etching process is used, and the downward etching depth, i.e., the step height Δh, is controlled between 0.5 μm and 1.5 μm; in step S3, the energy of the first ion implantation is lower than the energy of the second ion implantation in step S4.

8. The silicon carbide semiconductor device with multilayer buffer and shallow junction termination according to claim 6, characterized in that, S5 specifically includes: spin-coating photoresist on the surface of a silicon carbide semiconductor device and pyrolyzing it to form a dense carbon protective film; then performing rapid high-temperature annealing at 1600°C to 1700°C in an inert gas atmosphere to activate surface ions while suppressing thermal diffusion and mutual dissolution of doped atoms inside the bottom N-type composite buffer layer; and removing the carbon protective film by an ashing process after annealing.

Images