A method for controlling the turn-off time of a bipolar transistor

Abstract

The present application belongs to the technical field of silicon manufacturing process, and particularly relates to a control method for turn-off time of a bipolar transistor. The method comprises the following steps: obtaining a wafer to be processed, forming a protective layer on a P-type doped region and an N-type doped region, and removing a heavy metal coating layer outside the two regions by using a chemical etching process; removing an organic insulating medium layer by using plasma physical bombardment and performing physical cleaning; removing an oxide layer by using a first etching and rinsing with an acidic solution; diffusing the heavy metal to form a uniform doped layer by using a step annealing process; removing an annealing oxide layer by using a second etching and rinsing with an acidic solution; and finally continuously depositing an electrode metal. The method effectively improves the turn-off characteristics of the bipolar transistor and solves the problem of product parameter degradation caused by heavy metal doping.

Description

Technical Field

[0001] This invention belongs to the field of silicon manufacturing process technology, specifically relating to a method for controlling the turn-off time of a bipolar transistor. Background Technology

[0002] The theoretical research on transistor turn-off time control in silicon manufacturing processes has long been a focus of the scientific community. However, a mature and practical technical method for controlling the turn-off time of bipolar transistors has not yet been formed.

[0003] Traditional bipolar transistor (BPT) manufacturing processes typically employ a single heavy metal ion to control the BPT's turn-off time. The process involves four stages: first, evaporating a layer of heavy metal ions onto the back of the wafer; second, redistributing these ions through high-temperature annealing; third, chemically etching the precipitated heavy metal ions onto the wafer's back; and fourth, forming the back electrode through back-side thinning and metallization. However, this method is highly dependent on process control, especially for BPTs requiring precise turn-off time control. Accurate control of the heavy metal ion thickness, annealing temperature, and time is crucial. Furthermore, the diffusion of heavy metal ions over a large area degrades parameters such as the forward current transfer ratio and saturation voltage drop, directly impacting product performance. Summary of the Invention

[0004] The purpose of this invention is to provide a method for controlling the turn-off time of a bipolar transistor, so as to solve the technical problem that the existing technology cannot accurately control the turn-off time and the diffusion area of ​​heavy metal ions of bipolar transistors, which leads to the degradation of parameters such as the forward current transfer ratio and saturation voltage drop of bipolar transistors. To achieve the above objectives, the present invention employs the following technical solution: This application discloses a method for controlling the turn-off time of a bipolar transistor, including: S1: Obtain the wafer to be processed, form a protective layer on the P-type doped region and N-type doped region on the surface of the wafer to be processed, and use a chemical etching process to remove the heavy metal coating layer outside the P-type doped region and N-type doped region. S2: After removing the organic insulating dielectric layer outside the P-type doped region and N-type doped region by plasma physical bombardment process, the wafer surface is physically cleaned to remove surface residues. S3: Use an acidic solution to perform the first etching rinse on the cleaned wafer surface to remove the oxide layer on the wafer surface; S4: A stepped annealing process is used to diffuse the heavy metal coating layer on the surface of the P-type doped region and the N-type doped region into the silicon body to form a uniformly doped heavy metal diffusion layer. S5: The wafer surface is subjected to a second etching and rinsing using an acidic solution to remove the oxide layer formed by the stepped annealing process and environmental oxidation; S6: Electrode metal is continuously deposited on the surfaces of the P-type doped region and the N-type doped region to form a metal electrode.

[0005] Optionally, the protective layer in S1 is a photoresist layer, and photoresist-coated regions are formed on the surfaces of the P-type doped regions and N-type doped regions by photolithography, while the remaining regions are non-photoresist-coated regions; the chemical etching process is performed using a mixed solution of nitric acid and hydrochloric acid.

[0006] Optionally, in S2, the plasma physical bombardment process is carried out in an oxygen atmosphere, the applied power of the plasma physical bombardment process is 350W~500W, and the processing time is 20 minutes to 40 minutes.

[0007] Optionally, the physical cleaning of the wafer surface to remove surface residues specifically involves using manual wiping or wiping equipment to perform surface treatment on the wafer surface.

[0008] Optionally, the acidic solution in S3 is an HF acid solution, with the ratio of HF acid to water being 50:1 to 200:1. The corrosion rinsing is carried out at a normal temperature of 25℃±5℃ for a duration of less than 1 minute.

[0009] Optionally, the stepped annealing process in S4 includes several annealing stages performed sequentially, with the annealing temperature increasing sequentially and the annealing time decreasing sequentially or set independently in each annealing stage.

[0010] Optionally, the annealing temperatures for each annealing stage are, in sequence: 700℃±50℃, 800℃±50℃, 900℃±50℃ and 950℃±50℃, and the annealing times for each annealing stage are, in sequence: 20 minutes to 60 minutes, 20 minutes to 40 minutes, 10 minutes to 40 minutes and 10 minutes to 20 minutes.

[0011] Optionally, the acidic solution in S5 is an HF acid solution, with the ratio of HF acid to water being 10:1 to 100:1. The corrosion rinsing is carried out at a normal temperature of 25℃±5℃ for a duration of no more than 2 minutes.

[0012] Optionally, the electrode metal is one of Al, Al / Cu, CrNiAg, TiNiAu, or CrNiAu, and the deposition thickness of the metal electrode is 3μm to 5μm, which is deposited using an evaporation device or a sputtering device.

[0013] Optionally, the wafer to be processed has the following conditions: An epitaxial layer is grown on a silicon substrate, and a P-type doped region with a depth of 3μm to 5μm and an N-type doped region with a depth of 2μm to 4μm are formed on the epitaxial layer. The P-type and N-type doped regions are surrounded by silicon dioxide steps with a height of 1.0 nm to 1.5 μm; The surfaces of the P-type doped region and the N-type doped region have been treated with an oxide layer. A heavy metal coating layer has been formed on the surface of the P-type doped region and the N-type doped region. The heavy metal coating layer is a single metal structure or multiple metal structures, and the overall coating thickness is 100μm~500μm.

[0014] Compared with the prior art, the present invention has the following beneficial effects: This invention, through the selective masking of the protective layer and the combination of chemical etching, can precisely remove the heavy metal coating layer outside the P-type and N-type doped regions. This avoids the introduction of unnecessary recombination centers by heavy metal ions in non-working areas, which could lead to increased leakage current, and lays the foundation for subsequent controlled doping only in the working areas. Subsequently, through continuous plasma bombardment and physical cleaning, the organic insulating dielectric layer and stubborn particles are effectively removed, preventing residual impurities from becoming uncontrollable impurity sources or causing surface defects during high-temperature annealing, thus ensuring the interface cleanliness of subsequent diffusion processes. Based on this, an acidic solution is used for the first etching rinse, simultaneously removing the oxide layer introduced by plasma etching and the native oxide layer. This eliminates the blocking effect of the oxide layer on the diffusion of heavy metal ions, ensuring that the stepped annealing process allows the heavy metal coating layer to diffuse precisely and uniformly into the silicon body of the designated doped regions, forming a heavy metal diffusion layer with ideal depth and concentration distribution. The diffusion layer introduces deep recombination centers that effectively shorten minority carrier lifetime, thereby directly accelerating the turn-off speed of bipolar transistors from the device physics level. The second etching and rinsing removes the high-temperature oxide layer formed by stepped annealing and the subsequent natural oxide layer, avoiding the impact of oxide layer residue on the subsequent electrode contact resistance. This ensures that high-quality ohmic contacts are formed between the deposited metal electrodes and the P-type and N-type doped regions, ensuring that the external circuit can quickly extract the remaining carriers, so that the improvement in turn-off performance can be effectively reflected at the device level. Each step is implemented sequentially in the order of S1 to S6. The processing results of each step provide the necessary process window for the next step, forming a complete chain from selective removal, interface purification, controllable diffusion to electrode forming. Together, they achieve the technical effect of effectively improving the turn-off time of bipolar transistors while keeping other electrical parameters of the transistor from degrading significantly, providing a reliable process path for the engineering mass production of silicon wafers.

[0015] Furthermore, by employing photolithography to precisely form photoresist protective layers on the surfaces of P-type and N-type doped regions, the excellent masking properties of photoresist can be utilized to construct clearly defined photoresist-bearing areas on the P-type and N-type doped regions. This ensures that the etching process is strictly confined to the non-photoresist-bearing areas, thereby guaranteeing the precise alignment of the removal position of the large-area heavy metal coating with the device's working area. This avoids the unintended etching of heavy metals in the working area due to masking deviations, which could affect the uniformity of subsequent doping. Simultaneously, a mixed solution of nitric acid and hydrochloric acid is used to etch the non-photoresist-bearing areas. Utilizing the highly efficient chemical dissolution capability of this mixed solution for heavy metal materials, excess heavy metal coatings can be rapidly removed over a large area. Moreover, this etching process has a very high selectivity for the photoresist layer and the underlying organic insulating material, effectively removing heavy metal materials without damaging the organic insulating medium. This ensures the integrity of the heavy metal coating on the surfaces of the P-type and N-type doped regions and preserves the intact underlying structure for subsequent plasma bombardment processes, improving the stability and repeatability of the overall manufacturing process from a process integration perspective. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of the wafer to be processed in this invention; Figure 2 This is a schematic diagram of the processed structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the deposited metal structure according to an embodiment of the present invention.

[0018] Wherein: 1-Silica step; 2-Heavy metal coating layer; 3-N-type doped region; 4-P-type doped region; 5-Heavy metal diffusion layer; 6-Metal electrode; 7-Epipolar layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0022] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0023] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0024] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0025] The present invention will now be described in further detail with reference to the accompanying drawings: This invention discloses a method for controlling the turn-off time of a bipolar transistor, comprising: S1: Obtain the wafer to be processed, form a protective layer on the P-type doped region 4 and N-type doped region 3 on the surface of the wafer to be processed, and use a chemical etching process to remove the heavy metal coating layer 2 in the area outside the P-type doped region 4 and N-type doped region 3. S2: After removing the organic insulating dielectric layer in areas other than P-type doped region 4 and N-type doped region 3 by plasma physical bombardment process, the wafer surface is physically cleaned to remove surface residues. S3: Use an acidic solution to perform the first etching rinse on the cleaned wafer surface to remove the oxide layer on the wafer surface; S4: A stepped annealing process is used to diffuse the heavy metal coating layer 2 on the surface of the P-type doped region 4 and the N-type doped region 3 into the silicon body to form a uniformly doped heavy metal diffusion layer 5. S5: The wafer surface is subjected to a second etching and rinsing using an acidic solution to remove the oxide layer formed by the stepped annealing process and environmental oxidation; S6: Electrode metal is continuously deposited on the surfaces of P-type doped region 4 and N-type doped region 3 to form metal electrode 6.

[0026] This method precisely controls the turn-off time of a bipolar transistor (BPT) without altering its device structure or performance, resolving the conflict between BPT turn-off time control and parameter control such as forward current transfer ratio and saturation voltage drop. The technical method of this invention is highly operable, effectively improving the process control of BPT turn-off time without damaging the original product structure. This approach can be effectively applied to the engineering manufacturing process of silicon wafers.

[0027] In some embodiments, the protective layer in S1 is a photoresist layer, and photoresist-coated regions are formed on the surfaces of the P-type doped regions and N-type doped regions by photolithography, while the remaining regions are non-photoresist-coated regions; the chemical etching process is performed using a mixed solution of nitric acid and hydrochloric acid. Photolithography is used to precisely form resist-coated areas on the surfaces of the P-type and N-type doped regions, while the remaining areas form resist-free areas. The excellent masking properties of photoresist allow for precise spatial definition of the areas to be retained and removed from the heavy metal coating, avoiding positioning errors caused by mechanical stripping or non-selective etching. Furthermore, a mixed solution of nitric acid and hydrochloric acid is used to etch the resist-free areas. This mixed solution has a highly selective chemical stripping capability for heavy metals, enabling rapid and thorough removal of large areas of heavy metal coating outside the P-type and N-type doped regions. Simultaneously, this etching process does not erode the target heavy metal coating under the photoresist protective layer, nor does it damage the organic insulating materials and step structures on the wafer surface. Thus, while achieving precise removal of large areas of heavy metal layer, the integrity of the heavy metal coating on the doped region surface and the morphology of the surrounding structure are effectively protected. This provides a precise boundary and clean interface process basis for subsequent stepped annealing processes to controllably dope only the target area, avoiding device leakage and parameter degradation problems caused by heavy metal residue or mis-etching. In some embodiments, in step S2, the plasma physical bombardment process is performed in an oxygen atmosphere. The applied power of the plasma physical bombardment process is 350W~500W, and the processing time is 20 to 40 minutes. By setting the power of 350W~500W and the processing time of 20~40 minutes in an oxygen atmosphere, this plasma bombardment process can efficiently ashing and thoroughly remove the organic insulating medium outside the P-type doped region and N-type doped region while avoiding thermal damage or lattice defects on the wafer surface. Moreover, within this parameter window, the sputtering and etching effect of plasma on the heavy metal coating layer is extremely low, which can ensure that the heavy metal coating layer in the target area is not lost due to physical bombardment. Thus, while obtaining a clean surface, sufficient and complete heavy metal diffusion sources are preserved for the subsequent stepped annealing process.

[0028] In some embodiments, the physical cleaning of the wafer surface to remove surface residues specifically involves manual wiping or surface treatment using a wiping device. Immediately following plasma bombardment, manual or equipment-based physical wiping directly and thoroughly removes stubborn particulate matter and carbide residues generated by the plasma reaction from the wafer surface, overcoming the limitations of simple chemical cleaning or plasma treatment in removing hard residues. Furthermore, this operation must be performed continuously after plasma treatment, effectively preventing the problem of residues hardening or re-adhering and becoming impossible to remove if the wafer is left for too long after spin-drying. This provides the wafer surface with extremely high physical cleanliness before subsequent pickling and annealing processes, ensuring consistent results in subsequent etching, rinsing, and heavy metal diffusion processes, and preventing electrical performance degradation caused by uneven diffusion or localized contamination due to surface impurities.

[0029] In some embodiments, the acidic solution in S3 is an HF acid solution, with an HF acid to water ratio of 50:1 to 200:1. The etching and rinsing are performed at room temperature (25℃±5℃) for less than one minute. This method utilizes the highly efficient dissolving properties of HF acid in silicon dioxide to simultaneously remove the oxide layer formed by plasma etching under an oxygen atmosphere and the oxide layer formed by the natural oxidation of silicon in air, restoring the intrinsic cleanliness of the wafer surface. Simultaneously, the dilution ratio and extremely short processing time ensure that the etching effect is limited to the surface oxide layer, without excessively eroding the silicon substrate, stepped structures, or heavy metal coatings. This effectively removes the oxide barrier layer and provides low-resistance interface conditions for the smooth diffusion of heavy metal ions into the silicon mass during subsequent stepped annealing processes, ensuring diffusion uniformity and doping efficiency.

[0030] In some embodiments, the stepped annealing process in S4 includes several annealing stages performed sequentially, wherein the annealing temperature of each annealing stage increases sequentially, and the annealing time decreases sequentially or is set independently.

[0031] In some embodiments, the annealing temperatures of each annealing stage are, in sequence: 700℃±50℃, 800℃±50℃, 900℃±50℃ and 950℃±50℃, and the annealing times corresponding to each annealing stage are, in sequence: 20 minutes to 60 minutes, 20 minutes to 40 minutes, 10 minutes to 40 minutes and 10 minutes to 20 minutes. A multi-stage stepped annealing process is employed, with temperatures increasing sequentially and time decreasing sequentially or set independently. This allows the heavy metal coating to undergo a complete process from initial diffusion on the surface to penetration into the bulk and finally uniform distribution during the gradual temperature increase. This effectively avoids the problem of heavy metal ion aggregation on the surface or abrupt changes in the diffusion front caused by excessive thermal shock during single high-temperature annealing. The annealing temperatures are sequentially set to 700℃±50℃, 800℃±50℃, 900℃±50℃, and 950℃±50℃, with gradient decreases or independent durations of 20-60 minutes, 20-40 minutes, 10-40 minutes, and 10-20 minutes, ensuring... The process ensures sufficient pre-diffusion and stress release of heavy metal ions at low temperatures, completes the main doping process at medium temperatures, and achieves uniform doping concentration and final state distribution at high temperatures. Ultimately, a heavy metal diffusion layer with an ideal gradient distribution of doping concentration is formed in the silicon body of the P-type and N-type doped regions. The concentration distribution of recombination centers introduced by this diffusion layer is uniform and controllable, effectively shortening the minority carrier lifetime and thus accelerating the turn-off speed. At the same time, the gradual heating annealing method reduces the accumulation of thermal stress inside the wafer, avoids thermal damage or deformation of the structure outside the P-type and N-type doped regions, and ensures the integrity of the overall device structure and the stability of its electrical performance.

[0032] In some embodiments, the acidic solution in S5 is an HF acid solution, with an HF acid to water ratio of 10:1 to 100:1. The etching and rinsing are performed at room temperature (25℃±5℃) for a duration of less than 2 minutes. This concentration is higher than that of the first etching and rinsing, effectively removing the dense oxide layer formed by the high-temperature environment during the stepped annealing process, as well as the oxide layer formed by the natural oxidation of silicon in air after annealing. Simultaneously, the appropriate dilution ratio and controllable 2-minute duration ensure sufficient but not excessive etching, preventing corrosion of the silicon substrate, diffused heavy metal layers, or stepped structures. While removing the oxide barrier layer, it maintains high cleanliness and flatness of the P-type and N-type doped surfaces, providing excellent interface conditions for subsequent continuous deposition of metal electrodes. This ensures a low-resistance ohmic contact between the metal electrode and the silicon body, thereby guaranteeing the effective realization of the improved turn-off performance at the device electrical level.

[0033] In some embodiments, the electrode metal is one of Al, Al / Cu, CrNiAg, TiNiAu, or CrNiAu, and the deposition thickness of the metal electrode 6 is 3μm to 5μm, which is deposited using an evaporation device or a sputtering device. These materials all exhibit excellent compatibility with silicon-based semiconductor processes, enabling the formation of low-resistance ohmic contacts with P-type and N-type doped regions. Among them, the Al / Cu alloy possesses excellent anti-electromigration capabilities due to the pinning effect of copper atoms, while multilayer structures such as CrNiAg and CrNiAu combine good adhesion and solderability, meeting the electrode reliability requirements of various application scenarios. Controlling the deposition thickness to 3μm~5μm ensures that the electrode layer has sufficient conductive cross-sectional area to reduce series resistance, while avoiding the stress increase and patterning difficulties caused by excessively thick deposition. At the same time, uniform deposition of this thickness can be achieved using either evaporation or sputtering equipment. Both methods can form dense and continuous metal films under high-cleanliness interfaces, ensuring a strong bond and excellent electrical contact between the metal electrode and the silicon body. This ensures that the turn-off speed improvement introduced by the heavy metal diffusion layer can be effectively transferred to the external circuit through the electrode, achieving stable optimization of the overall device performance.

[0034] In some embodiments, the wafer to be processed has the following conditions: An epitaxial layer 7 is grown on a silicon substrate, and a P-type doped region 4 with a depth of 3μm to 5μm and an N-type doped region 3 with a depth of 2μm to 4μm are formed on the epitaxial layer 7. The P-type doped region 4 and the N-type doped region 3 are surrounded by silicon dioxide steps 11 with a height of 1.0 nm to 1.5 μm; The surfaces of the P-type doped region 4 and the N-type doped region 3 have been treated with an oxide layer. A heavy metal coating layer 2 has been formed on the surfaces of the P-type doped region 4 and the N-type doped region 3. The heavy metal coating layer 2 is a single metal structure or a multi-metal structure, with an overall coating thickness of 100 μm to 500 μm. An epitaxial layer is grown on a silicon substrate, and a P-type doped region with a depth of 3 μm to 5 μm and an N-type doped region with a depth of 2 μm to 4 μm are formed on it. This provides precise vertical structural dimensions for the base and emitter / collector regions of the bipolar transistor, ensuring that the device possesses basic switching functions and withstand voltage characteristics. The P-type and N-type doped regions are surrounded by silicon dioxide steps with a height of 1.0 nm to 1.5 μm. These steps act as a natural physical barrier and mask-like auxiliary structure during subsequent chemical etching and plasma bombardment, effectively limiting the removal range and diffusion area of ​​the heavy metal coating layer and preventing contamination and leakage in non-target areas. The pre-treatment of the oxide layer on the surfaces of the two doped regions ensures the subsequent coating of heavy metals. The layer forms a direct and uniform contact interface with the silicon surface, avoiding the hindering effect of the interface oxide layer on the diffusion of heavy metal ions, and improving diffusion efficiency and uniformity. The heavy metal coating layer covering the surface of the doped region is a single metal structure or multiple metal structures, with an overall thickness of 100μm~500μm. This thickness range provides sufficient diffusion sources to ensure the formation of a heavy metal diffusion layer with sufficient recombination center concentration after annealing, while avoiding excessive stress and subsequent selective removal difficulties caused by excessive coating thickness. At the same time, the choice of multiple metal structures provides a flexible material combination scheme for controlling minority carrier lifetime. Together, they lay a reliable structural and material foundation for achieving uniform and controllable heavy metal doping in the subsequent stepped annealing process.

[0035]

Example 1

[0036] With the above structure in place, the embodiments of the present invention adopt the following technical solutions: A method for controlling the turn-off time of a bipolar transistor includes the following steps: Step 1: Using photolithography in silicon manufacturing process, a region with adhesive is formed on the surface of P-type doped region 4 and N-type doped region 3, and a region without adhesive is formed outside P-type doped region 4 and N-type doped region 3. Step 2: Utilizing the masking effect of photoresist etching, a mixed solution of nitric acid and hydrochloric acid is used to perform large-area chemical stripping etching on the heavy metal coating layer 2 outside the P-type doped region 4 and N-type doped region 3. This etching process has high selectivity and can effectively remove heavy metal materials without causing loss of organic insulating materials. In an oxygen atmosphere, plasma is used to perform large-area physical stripping of the organic insulating medium outside the P-type doped region 4 and N-type doped region 3. During the removal process, the heavy metal coating layer 2 on the surface of the P-type doped region 4 and N-type doped region 3 will not be lost. Step 3: Use manual wiping or wiping equipment to perform surface treatment on the wafer surface to effectively remove organic insulating material residues with strong adhesion. Step 4: Use a mixed solution of HF acid and water to etch the natural oxide layer on the wafer surface to remove the thin oxide layer formed by plasma; Step 5: Using a stepped annealing process and controlling the annealing time and temperature, the heavy metal coating layer 2 forms a uniformly doped heavy metal diffusion layer 5 in the P-type doped region 4 and the N-type doped region 3, and reaches a certain depth. Step 6: Use HF acid solution to perform light etching and rinsing on the wafer surface to remove the thermal oxide layer formed during the stepped annealing process and the oxide layer formed by the oxidation reaction of silicon in air. Step 7: After obtaining a P-type and N-type silicon interface with high cleanliness and high flatness, the electrode metal deposition process is carried out continuously. The electrode metal can be selected from metal materials such as Al, Al / Cu, CrNiAg, TiNiAu and CrNiAu.

[0037]

Example 2

[0038] In step 1, photolithography, a technique used in silicon manufacturing, is employed to form resist-coated regions on the surfaces of P-type doped regions 4 and N-type doped regions 3, while areas without resist are formed outside these regions. Utilizing the masking effect of the photoresist, a mixed solution of nitric acid and hydrochloric acid is used to perform large-area chemical stripping etching on the heavy metal coating layer 2 outside the P-type doped regions 4 and N-type doped regions 3. The HNO3:HCl solution ratio can be 3:1 to 10:1, and the solution temperature can be controlled, with the acid solution temperature set at 100℃±10℃. The processing time can range from 20 minutes to 1 hour, aiming to completely remove the heavy metal coating layer 2 over a large area outside the P-type doped regions 4 and N-type doped regions 3. This step is primarily used for large-scale stripping of the heavy metal coating layer 2, as it undergoes a chemical reaction under high temperature and strong acid conditions, leading to its removal. This corrosion process is highly selective and can effectively remove heavy metal materials without causing loss of organic insulating materials. In an oxygen atmosphere, plasma is used to physically remove the organic insulating medium outside the P-type doped region 4 and N-type doped region 3 over a large area. During the removal process, the heavy metal coating layer 2 on the surface of the P-type doped region 4 and N-type doped region 3 will not be lost.

[0039] Step 2 involves using plasma in an oxygen atmosphere to physically remove a large area of ​​organic insulating material outside the P-type doped region 4 and the N-type doped region 3. The plasma power applied is between 350W and 500W, and the processing time can be 20 to 40 minutes, with the principle of completely removing the large area of ​​organic insulating material outside the P-type doped region 4 and the N-type doped region 3. This stripping process effectively removes the organic insulating material without causing the loss of the heavy metal coating layer 2 on the surface of the P-type doped region 4 and the N-type doped region 3.

[0040] Step 3 involves manually wiping the wafer or using a wiping device to clean the surface of the wafer in the slot area, removing stubborn particles and carbides. This step needs to be performed continuously after Step 3 to effectively remove residual impurities from the wafer surface. If the wafer is left for too long after spin-drying, residual impurities on the surface cannot be effectively removed.

[0041] Step 4: Use HF acid solution to perform a light etching and rinsing on the wafer surface to remove two types of oxide layers: one is the oxide layer formed by plasma etching under an oxygen atmosphere; the other is the oxide layer formed by the oxidation reaction of silicon in air. The HF acid to water solution ratio is 50:1~200:1, at room temperature 25℃±5℃, for no more than 1 minute.

[0042] Step 5: A stepped annealing process is used to diffuse the heavy metal coating layer 2, achieving uniform distribution and a certain depth. The stepped annealing temperatures are 700℃±50℃, 800℃±50℃, 900℃±50℃, and 950℃±50℃, respectively, and the annealing times are 20-60 minutes, 20-40 minutes, 10-40 minutes, and 10-20 minutes, respectively. The principle is to ensure that the heavy metal coating layer 2 completely diffuses into the silicon mass within the P-type doped region 4 and the N-type doped region 3, forming a uniformly doped heavy metal diffusion layer 5. This annealing process effectively achieves uniform doping of heavy metal ions without causing structural loss outside the P-type doped region 4 and the N-type doped region 3.

[0043] Step 6: Use HF acid solution to perform a light etching and rinsing on the wafer surface to remove two types of oxide layers: one is the oxide layer formed by step annealing; the other is the oxide layer formed by the oxidation reaction of silicon in air. The HF acid to water solution ratio is 10:1 to 100:1, at room temperature (25℃±5℃), for no more than 2 minutes.

[0044] Step 7: After obtaining a P-type and N-type silicon interface with high cleanliness and high flatness, continuously perform electrode metal deposition process. The electrode metal can be selected from metal materials such as Al, Al / Cu, CrNiAg, TiNiAu and CrNiAu. The deposition metal thickness can be 3μm~5μm. Either evaporation equipment or sputtering equipment can be used. The setting parameters are subject to the specific equipment settings.

[0045] The above combined processing methods must be implemented in the order of combination; if the order is reversed, the expected results will not be achieved.

[0046] In an embodiment of the present invention, a method for controlling the turn-off time of a bipolar transistor uses the above-mentioned complete process flow, which effectively improves the turn-off characteristics of the bipolar transistor compared with the traditional bipolar transistor fabrication process, and solves the problem of product parameter degradation caused by heavy metal doping. This method can be effectively applied to the engineering manufacturing process of silicon wafers.

[0047] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for controlling the turn-off time of a bipolar transistor, characterized in that, include: S1: Obtain the wafer to be processed, form a protective layer on the P-type doped region (4) and N-type doped region (3) on the surface of the wafer to be processed, and use a chemical etching process to remove the heavy metal coating layer (2) outside the P-type doped region (4) and N-type doped region (3). S2: After removing the organic insulating dielectric layer outside the P-type doped region (4) and N-type doped region (3) by plasma physical bombardment process, the wafer surface is physically cleaned to remove surface residues; S3: Use an acidic solution to perform the first etching rinse on the cleaned wafer surface to remove the oxide layer on the wafer surface; S4: Using a stepped annealing process, the heavy metal coating layer (2) on the surface of the P-type doped region (4) and the N-type doped region (3) diffuses into the silicon body to form a uniformly doped heavy metal diffusion layer (5). S5: The wafer surface is subjected to a second etching and rinsing using an acidic solution to remove the oxide layer formed by the stepped annealing process and environmental oxidation; S6: Electrode metal is continuously deposited on the surfaces of the P-type doped region (4) and the N-type doped region (3) to form a metal electrode (6).

2. The method for controlling the turn-off time of a bipolar transistor according to claim 1, characterized in that, The protective layer in S1 is a photoresist layer. Photolithography is used to form photoresist-coated regions on the surfaces of the P-type and N-type doped regions, while the remaining regions are non-photoresist-coated regions. The chemical etching process uses a mixed solution of nitric acid and hydrochloric acid for etching.

3. The method for controlling the turn-off time of a bipolar transistor according to claim 1, characterized in that, In S2, the plasma physical bombardment process is carried out in an oxygen atmosphere, the applied power of the plasma physical bombardment process is 350W~500W, and the processing time is 20 minutes to 40 minutes.

4. The method for controlling the turn-off time of a bipolar transistor according to claim 1, characterized in that, The physical cleaning of the wafer surface to remove surface residues specifically involves using manual wiping or wiping equipment to perform surface treatment on the wafer surface.

5. The method for controlling the turn-off time of a bipolar transistor according to claim 1, characterized in that, The acidic solution in S3 is an HF acid solution, with a HF acid to water ratio of 50:1 to 200:

1. The corrosion rinsing is carried out at room temperature (25℃±5℃) for less than 1 minute.

6. The method for controlling the turn-off time of a bipolar transistor according to claim 1, characterized in that, The stepped annealing process in S4 includes several annealing stages performed sequentially, with the annealing temperature increasing sequentially and the annealing time decreasing sequentially or set independently in each stage.

7. The method for controlling the turn-off time of a bipolar transistor according to claim 6, characterized in that, The annealing temperatures for each annealing stage are as follows: 700℃±50℃, 800℃±50℃, 900℃±50℃ and 950℃±50℃, and the annealing times for each annealing stage are as follows: 20 minutes to 60 minutes, 20 minutes to 40 minutes, 10 minutes to 40 minutes and 10 minutes to 20 minutes.

8. The method for controlling the turn-off time of a bipolar transistor according to claim 1, characterized in that, The acidic solution in S5 is an HF acid solution, with the ratio of HF acid to water being 10:1 to 100:

1. The corrosion rinsing is carried out at room temperature (25℃±5℃) for a duration of no more than 2 minutes.

9. The method for controlling the turn-off time of a bipolar transistor according to claim 1, characterized in that, The electrode metal is one of Al, Al / Cu, CrNiAg, TiNiAu or CrNiAu, and the deposition thickness of the metal electrode (6) is 3μm~5μm, which is deposited using an evaporation device or a sputtering device.

10. The method for controlling the turn-off time of a bipolar transistor according to claim 1, characterized in that, The wafer to be processed meets the following conditions: An epitaxial layer (7) is grown on a silicon substrate, and a P-type doped region (4) with a depth of 3μm~5μm and an N-type doped region (3) with a depth of 2μm~4μm are formed on the epitaxial layer (7). The P-type doped region (4) and the N-type doped region (3) are surrounded by silicon dioxide steps (1) with a height of 1.0 nm to 1.5 μm; The surfaces of the P-type doped region (4) and the N-type doped region (3) have been treated with an oxide layer. The P-type doped region (4) and N-type doped region (3) have a heavy metal coating layer (2) formed on their surfaces. The heavy metal coating layer (2) is a single metal structure or multiple metal structures, and the overall coating thickness is 100μm~500μm.

Images