Semiconductor device and method of manufacturing the same
Patent Information
- Application Number
- CN202610837863.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-06-12
- Filing Date
- 2026-06-11
- Publication Date
- 2026-10-13
Smart Images
Figure CN122909862A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology
[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are generally manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.
[0003] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size (which allows more components to be integrated into a given area). However, as the minimum feature size decreases, additional problems arise that need to be addressed. Summary of the Invention
[0004] According to one embodiment of the present disclosure, a method of manufacturing a semiconductor device includes: forming a fin structure having a top surface; depositing a sacrificial material over the fin structure; etching a first selected portion and a second selected portion of the sacrificial material to form a sacrificial segment, wherein the top surface of the fin structure below the first selected portion is etched to a first recessed surface, and the top surface of the fin structure below the second selected portion is etched to a second recessed surface; forming spacers around the fin structure and above the first and second recessed surfaces; and replacing the sacrificial segment with a replacement structure having a first sidewall and a second sidewall, wherein each sidewall extends upward from the top surface of the fin structure, wherein a first angle defined between the first sidewall and the first recessed surface is 90 to 95 degrees, and wherein a second angle defined between the second sidewall and the second recessed surface is 90 to 95 degrees.
[0005] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: depositing a first sacrificial layer above the uppermost surface of a semiconductor material; depositing a second sacrificial layer on the first sacrificial layer; etching the first sacrificial layer and the second sacrificial layer to form a sacrificial segment; forming spacers around the sacrificial segment; forming features aligned with the spacers; forming an interlayer material above the features; removing the second sacrificial layer of the sacrificial segment; and removing the first sacrificial layer of the sacrificial segment by performing a removal process, wherein the uppermost surface of the semiconductor material has a depression of less than 0.5 nanometers in the removal process.
[0006] According to one embodiment of this disclosure, a semiconductor device includes: a fin structure terminating at an uppermost surface having a first edge region and a central region therebetween; and a gate structure contacting the uppermost surface at the central region; wherein the central region of the uppermost surface has a maximum height difference of 0.5 nanometers. Attached Figure Description
[0007] When accompanied by Figure 1 When reading this document, the various aspects of the disclosure can be best understood from the following detailed description. It should be noted that, according to standard industrial practice, the various features are not drawn to scale. In fact, for clarity of expression, the dimensions of the various features may be arbitrarily increased or decreased.
[0008] Figures 1 to 5 These are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments;
[0009] Figure 6 According to some embodiments Figure 5 A cross-sectional side view of the semiconductor device structure taken by line AA;
[0010] Figures 7 to 14 Manufacturing according to some embodiments Figure 5 A cross-sectional side view of each stage of the semiconductor device structure, taken by line AA.
[0011] Figure 15 Manufacturing according to some embodiments Figure 5 The line BB cut Figure 14 A cross-sectional side view of a stage in the structure of a semiconductor device;
[0012] Figures 16 to 18 Manufacturing according to some embodiments Figure 5 A cross-sectional side view of each stage of the semiconductor device structure, taken by line AA.
[0013] Figure 19 According to some embodiments Figure 18 A portion of the focused view;
[0014] Figure 20 Manufacturing according to some embodiments Figure 5 A cross-sectional side view of each stage of the semiconductor device structure, taken by line AA.
[0015] Figure 21 According to some embodiments Figure 20 A perspective view of the device;
[0016] Figure 22 According to some embodiments Figure 20 A portion of the focused view.
[0017] [Symbol Explanation]
[0018] 100: Semiconductor device structure
[0019] 101: Substrate
[0020] 103: First Sacrifice Layer
[0021] 104: Semiconductor layer
[0022] 105: Second Sacrificial Layer
[0023] 106: First semiconductor layer
[0024] 107: Sacrificial Materials
[0025] 108: Second semiconductor layer
[0026] 110: Oxide layer
[0027] 111: Nitride layer
[0028] 112: Fin structure
[0029] 113: Top surface
[0030] 113' : Maximum concave surface
[0031] 113": The uppermost surface of the depression
[0032] 114: Trench
[0033] 115: Sidewall
[0034] 116: Substrate portion
[0035] 118: Insulating materials
[0036] 119: Upper edge
[0037] 120: Isolation Features
[0038] 130: Sacrificial gate electrode line
[0039] 131: Side surface
[0040] 135: Gate cavity
[0041] 140: Spacer
[0042] 150: Source / Drain cavity
[0043] 155: Insulation material
[0044] 160: Internal spacers
[0045] 165: Semiconductor Materials
[0046] 170: Source / Drain Characteristics
[0047] 175: Contact Etching Termination Layer
[0048] 180: Interlayer dielectric layer
[0049] 190: Replace gate
[0050] 191: Sidewall
[0051] 202: First mask layer
[0052] 204: Second mask layer
[0053] 206: Third masking layer
[0054] 208: Fourth masking layer
[0055] 210: Fifth masking layer
[0056] 212: Sixth mask layer
[0057] 214: Opening
[0058] AA: Line
[0059] A1: Angle
[0060] A2: Angle
[0061] A8: Angle
[0062] A9: Angle
[0063] BB: Line
[0064] CC: Line
[0065] D1: Depth
[0066] D2: Distance
[0067] D9: Depth
[0068] H1: Height
[0069] H2: Height
[0070] H103: Thickness
[0071] H105: Thickness
[0072] H202: Thickness
[0073] H2O4: Thickness
[0074] H206: Thickness
[0075] H208: Thickness
[0076] H210: Thickness
[0077] X: Direction
[0078] Y : direction
[0079] Z: Direction Detailed Implementation
[0080] The following disclosure provides numerous different embodiments or examples for implementing various features of the subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.
[0081] Furthermore, for ease of description, spatial relative terms such as “above,” “overlapping,” “on top,” “upper part,” “top,” “below,” “under,” “below,” “under,” “lower part,” “bottom,” “side,” and similar terms may be used herein to describe the relationship of an element or feature to another element or feature as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein will be interpreted accordingly.
[0082] In some embodiments herein, a “material structure” is a structure comprising at least 50% by weight of the identified material, such as at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of the identified material; and a structure formed from the “material” comprises at least 50% by weight of the identified material, such as at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of the identified material. For example, in some embodiments, each of the tungsten structure and the structure formed from tungsten is a structure comprising at least 50% by weight, at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of tungsten.
[0083] For the sake of brevity, this document may not describe typical technologies associated with semiconductor device manufacturing in detail. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionality not described in detail herein. Specifically, the various processes in semiconductor device manufacturing are well-known, and therefore, for the sake of brevity, many typical processes will only be briefly mentioned or omitted entirely without providing well-known process details. Those skilled in the art will readily understand upon fully reading the disclosure that the structures disclosed herein can be used in various technologies and incorporated into various semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include a varying number of components, and a single component shown in a drawing may represent multiple components.
[0084] This document presents embodiments of semiconductor devices and methods for manufacturing such devices. The methods described herein can be easily integrated into current process flows.
[0085] Embodiments herein provide a method for forming a transistor device with fewer recesses having a top semiconductor surface. For example, embodiments herein reduce etching of the top surface of a fin structure or a nanostructure. During sacrificial gate patterning, the outer regions of the top surface may suffer undesired etching. During sacrificial gate removal, the central region of the top surface between the outer regions may suffer undesired etching. Embodiments herein reduce or eliminate etching of the top surface by reducing the aspect ratio during the etching process.
[0086] Therefore, the embodiments herein provide a film scheme for virtual gate patterning and optimization for yield improvement. Specifically, conventional processes that allow undesirable recesses on the surface of the top semiconductor layer may suffer from tapered channel edges, resulting in small source / drain channels, and the recessed center portion results in a rounded metal gate, increased resistance, and reduced DC.
[0087] In some embodiments, the film-based etching process provides a small aspect ratio (17:1 to 12:1) to reduce damage to the top of the sheet. Furthermore, interlayer oxide removal (IORM) involves chemical etching to reduce silicon channel recesses to less than 0.5 nm. The resulting two shape modifications effectively enhance electrical properties.
[0088] While embodiments of this disclosure have been discussed in relation to nanostructured channel FETs (such as horizontal gate all-around (HGAA) FETs), some embodiments of this disclosure can be used in other processes and / or other devices, such as fin field-effect transistors, planar field-effect transistors, nanosheet field-effect transistors, vertical gate all-around (VGAA) field-effect transistors, vertical field-effect transistors, forked field-effect transistors, complementary field-effect transistors, metal-oxide-semiconductor field-effect transistors, advanced devices, industrial semi-finished products, or other devices or products. Those skilled in the art will readily understand that other modifications are contemplated within the scope of this disclosure. In cases where a gate all-around (GAA) transistor structure is employed, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the production of patterns with, for example, a smaller pitch than that otherwise achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.
[0089] Compared to existing processes, the embodiments herein provide a semiconductor manufacturing method with higher yield. Embodiments of this disclosure provide a method for forming a semiconductor device structure. One method may include patterning a sacrificial material comprising a sacrificial gate or electrode layer and a sacrificial gate dielectric layer or etch stop layer to form a sacrificial gate line or segment. The sacrificial gate layer may have a vertical thickness of about 35 nm to about 40 nm above the uppermost surface of the fin structure. The patterning process may use a mask structure comprising a primary mask layer, such as an oxide layer, having a vertical thickness of about 60 nm to about 65 nm above the uppermost surface of the fin structure. When various layers are etched to form the sacrificial gate line, the thickness of the sacrificial gate layer and the primary mask layer may, together with the thickness of other layers above the fin structure, provide an aspect ratio from 17:1 to 12:1. Due to the reduced aspect ratio, during the removal of a portion of the sacrificial material, the material of the fin structure beneath the removed portion of the sacrificial material is minimized. For example, during the etching of the sacrificial gate material, the uppermost surface of the fin structure is vertically recessed by less than 0.5 nm to define the sacrificial gate line.
[0090] Furthermore, one approach may include a gate replacement process in which the sacrificial electrode layer of the sacrificial gate line is removed. Then, during the removal process, the sacrificial gate dielectric layer (such as an interlayer oxide) is removed, minimizing etching of the uppermost surface of the underlying layer (such as the uppermost surface of a fin structure). For example, during the removal of the interlayer oxide, the uppermost surface of the fin structure may have a vertical recess of less than 0.5 nm.
[0091] The embodiments disclosed herein offer advantages over the prior art. Although it should be understood that other embodiments may offer different advantages, not all advantages need to be discussed herein, and not all embodiments require a particular advantage.
[0092] Figures 1 to 21 An exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of this disclosure is shown. It should be understood that for additional embodiments of this method, additional operations may be provided before, during, and after the illustrated process, and some of the operations described below may be replaced or eliminated. The order of operations / processes is not limiting and may be interchangeable.
[0093] Figures 1 to 5 This is a perspective view of various stages in manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1As shown, the semiconductor device structure 100 includes a stack of semiconductor layers 104 formed over the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (lnSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaAsBP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one embodiment, the insulating layer is an oxygen-containing layer.
[0094] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants with p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).
[0095] The stack of semiconductor layers 104 comprises alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel FETs. In some embodiments, the stack of semiconductor layers 104 comprises a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the stack of semiconductor layers 104 comprises alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si and the second semiconductor layer 108 may be made of SiGe. In some instances, the first semiconductor layer 106 may be made of SiGe and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.
[0096] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. By way of example, the epitaxial growth of the stacked layers of semiconductor layer 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.
[0097] The first semiconductor layer 106 or a portion thereof may form nanostructure channels of the semiconductor device structure 100 in a later manufacturing stage. The second semiconductor layer 108, which may be referred to as the interposer 108, is inserted between the first semiconductor layers 106.
[0098] The term nanostructure is used herein to refer to any portion of material having a nanoscale, or even microscale, size and an elongated shape, regardless of the cross-sectional shape of this portion. Thus, this term refers to elongated portions of material with circular or substantially circular cross-sections, as well as beam-shaped or strip-shaped portions of material (including, for example, cylindrical or substantially rectangular cross-sections). Nanostructured channels of semiconductor device structure 100 may be surrounded by gate electrodes. Semiconductor device structure 100 may include nanostructured transistors. Nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MCB) transistors, or any transistor having a gate electrode surrounding the channel. The following further discusses the use of a first semiconductor layer 106 to define one or more channels of semiconductor device structure 100.
[0099] Each first semiconductor layer 106 may have a thickness of about 5 nm to about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness between about 2 nm and about 50 nm. Figure 1 As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately. This is for illustrative purposes and is not intended to limit the scope of the claims. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the stack of semiconductor layers 104, and the number of layers depends on the predetermined number of channels in the semiconductor device structure 100. Figure 1As shown, an oxide layer 110 is formed on the topmost first semiconductor layer 106, and a nitride layer 111 is formed on the oxide layer 110. The oxide layer 110 may be silicon oxide and may have different etch selectivity compared to the nitride layer 111. The nitride layer 111 may include any suitable nitride material, such as silicon nitride. In some embodiments, the oxide layer 110 and the nitride layer 111 may be a mask structure.
[0100] exist Figure 2 In this embodiment, fin structures 112 are formed by stacking semiconductor layers 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a substrate portion 116 formed from the substrate 101. The fin structures 112 can be formed by patterning hard mask layers (such as oxide layer 110 and nitride layer 111) using multiple patterning operations (including photolithography and etching processes). Etching processes can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. Photolithography processes can include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to the pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element can be performed using an electron beam (e-beam) lithography process. An etching process forms trenches 114 in unprotected areas. These trenches penetrate the hard mask layer, pass through the stack of semiconductor layers 104, and enter the substrate 101, leaving a plurality of extending fin structures 112. The trenches 114 extend in the X direction. Dry etching (e.g., RIE), wet etching, and / or combinations thereof can be used to etch the trenches 114. The fin structures 112 extend in the X direction and are spaced apart from each other in the Y direction by the trenches 114. As shown, each fin structure 112 has an opposing sidewall 115 adjacent to the trench 114.
[0101] exist Figure 3In the process, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation, such as chemical mechanical polishing (CMP) and / or etching back, is performed to expose the top of the fin structure 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride, silicon carbonitride, fluorine-doped silicate glass (FSG), a low dielectric constant dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).
[0102] exist Figure 4 In this configuration, insulating material 118 is recessed to form isolation feature 120. The recesses in insulating material 118 expose portions of fin structures 112, such as stacks of semiconductor layers 104. The recesses in insulating material 118 expose trenches 114 between adjacent fin structures 112. Isolation feature 120 can be formed using suitable processes, such as dry etching, wet etching, or combinations thereof. The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 that contacts the substrate portion 116 formed from substrate 101. In some embodiments, isolation feature 120 is a shallow trench isolation (STI) feature. In some embodiments, oxide layer 110 and nitride layer 111 are also removed during the recessing of insulating material 118. As shown, each fin structure 112 has an uppermost surface 113.
[0103] exist Figure 5 In this structure, sacrificial material 107 is formed on the exposed surfaces of the semiconductor device structure 100, including the uppermost surface 113 of the structure 100. As shown, sacrificial material 107 may include a first sacrificial layer 103 and a second sacrificial layer 105. As shown, the first sacrificial layer 103 is formed on the exposed surfaces of the semiconductor device structure 100, including the uppermost surface 113, and the second sacrificial layer 105 is formed on the first sacrificial layer 103.
[0104] In some embodiments, the first sacrificial layer 103 comprises a dielectric material, such as an oxide, for example silicon oxide. The first sacrificial layer 103 may be referred to as an interface oxide or interface layer.
[0105] The first sacrificial layer 103 can be formed by any suitable process, such as CVD or PECVD. In some embodiments, the first sacrificial layer 103 is a conformal layer formed by a conformal process, such as atomic layer deposition (ALD).
[0106] In some embodiments, the second sacrificial layer 105 comprises a semiconductor material, such as polysilicon. The second sacrificial layer 105 can be formed by any suitable process, such as CVD, PECVD, ALD, or PVD. The second sacrificial layer 105 can be deposited first to embed the fin structure 112, followed by a planarization process, such as a CMP process.
[0107] In some embodiments, the first sacrificial layer 103 may be referred to as a sacrificial dielectric layer or a sacrificial gate dielectric layer, and the second sacrificial layer 105 may be referred to as a sacrificial gate layer or a sacrificial electrode layer.
[0108] Figure 6 According to some embodiments Figure 5 A cross-sectional side view of the semiconductor device structure 100 taken by line AA. Figures 7 to 13 Manufacturing according to some embodiments Figure 5 A cross-sectional side view of each stage of the semiconductor device structure 100, taken by line AA.
[0109] like Figure 7 As shown, a plurality of masking layers are formed on the second sacrificial layer 105. In some embodiments, the plurality of masking layers include a first masking layer 202 (or lower masking layer 202) disposed on the second sacrificial layer 105, a second masking layer 204 (or main masking layer 204) disposed on the first masking layer 202, a third masking layer 206 (or upper masking layer 206) disposed on the second masking layer 204, a fourth masking layer 208 disposed on the third masking layer 206, a fifth masking layer 210 disposed on the fourth masking layer 208, and a sixth masking layer 212 disposed on the fifth masking layer 210.
[0110] In some embodiments, the first masking layer 202 may be a SiN layer, the second masking layer 204 may be an oxide layer, such as a silicon oxide layer, and the third masking layer 206 may include the same material as the first masking layer 202.
[0111] In some embodiments, the fourth masking layer 208, the fifth masking layer 210, and the sixth masking layer 212 form a photoresist structure. For example, the photoresist structure may be a three-layer photoresist. The fourth masking layer 208 may be the bottom layer, the fifth masking layer 210 may be the middle layer, and the sixth masking layer 212 may be a photoresist layer. The fourth masking layer 208 and the fifth masking layer 210 are made of different materials, such that the optical properties and / or etch properties of the fourth masking layer 208 and the fifth masking layer 210 are different from each other. In some embodiments, the fourth masking layer 208 may be a carbon layer, and the fifth masking layer 210 may be a silicon-rich layer designed to provide etch selectivity between the fifth masking layer 210 and the fourth masking layer 208. The sixth masking layer 212 may be a chemically amplified photoresist layer, and may be a positive or negative photoresist. The sixth masking layer 212 may comprise polymers such as phenolic resins, poly(norbornene)-co-maleic anhydride (COMA) polymers, poly(4-hydroxystyrene) (PHS) polymers, phenolic (Bakelite) polymers, polyethylene (PE) polymers, polypropylene (PP) polymers, polycarbonate polymers, polyester polymers, or acrylate-based polymers such as poly(methyl methacrylate) (PMMA) polymers or poly(methacrylic acid) (PMAA) polymers. The sixth masking layer 212 may be formed by spin coating. The sixth masking layer 212 may be patterned to have openings 214 formed therein.
[0112] like Figure 7 As shown, each of layers 103 to 210 has a thickness in the Z direction, i.e., a vertical thickness, above the uppermost surface 113. For example, the first sacrificial layer 103 has a thickness of about 3 nm to about 5 nm H103; the second sacrificial layer 105 has a thickness of about 35 nm to about 40 nm H105; the first masking layer 202 has a thickness of about 20 nm to about 30 nm H202; the second masking layer 204 has a thickness of about 60 nm to about 65 nm H204; the third masking layer 206 has a thickness of about 20 nm to about 30 nm H206; the fourth masking layer 208 has a thickness of about 40 nm to about 50 nm H208; and the fifth masking layer 210 has a thickness of about 20 nm to about 30 nm H210.
[0113] Therefore, prior to the sequential etching process, the structure of layers 103 to 210 above the stack of semiconductor layer 104 can have a reduced total vertical thickness, such as from about 198 nm to about 250 nm, compared to a typical process. More specifically, the second sacrificial layer 105 can have a reduced thickness compared to a typical process, and the second masking layer 204 can have a reduced thickness compared to a typical process. Furthermore, in each sequential etching process, the remaining layers of layers 103 to 210 can have a reduced total vertical thickness compared to a typical process.
[0114] Because the total vertical thickness of layers 103 to 210 is reduced, the etching process is performed with a reduced aspect ratio compared to typical processing. For example, the aspect ratio can be 17:1 to 12:1 during any continuous etching process.
[0115] like Figure 8 As shown, opening 214 extends through the fifth masking layer 210. In some embodiments, a first etching process is performed to remove a portion of the fifth masking layer 210. The first etching process can be any suitable process. In some embodiments, a plasma etching process is performed to extend opening 214 through the fifth masking layer 210. The plasma etching process can use carbon-based etchants, such as CHF3, CH3F, CF4, and / or C4F6, and a carrier gas or passivation gas (such as N2 and / or He) can flow with the etchant. The plasma power of the plasma etching process can be from about 500 W to about 2000 W, and the process pressure can be from about 10 mT to about 50 mT.
[0116] like Figure 9 As shown, opening 214 extends through the fourth masking layer 208. In some embodiments, a second etching process is performed to remove a portion of the fourth masking layer 208. The second etching process can be any suitable process. In some embodiments, a plasma etching process is performed to extend opening 214 through the fourth masking layer 208. The plasma etching process may use an oxy-based etchant, such as SO2 and / or O2, and may flow with the etchant to assist the plasma etching process. The plasma power of the second etching process may be greater than the plasma power of the first etching process. In some embodiments, the plasma power of the second etching process is from about 1000 W to about 4000 W. The process pressure of the second etching process may be less than the process pressure of the first etching process. In some embodiments, the process pressure of the second etching process is from about 1 mT to about 20 mT.
[0117] like Figure 10As shown, opening 214 extends through the third masking layer 206. In some embodiments, a third etching process is performed to remove a portion of the third masking layer 206. The third etching process can be any suitable process. In some embodiments, a plasma etching process is performed to extend opening 214 through the third masking layer 206. The plasma etching process can use the same etchant and other gases as the first etching process, except for N2 gas. In some embodiments, additional etchants, such as HBr and / or O2, can be used in the third etching process. The plasma power of the third etching process can be less than that of the second etching process. In some embodiments, the plasma power of the third etching process is from about 500 W to about 2000 W. The process pressure of the third etching process can be substantially the same as that of the second etching process.
[0118] like Figure 11 As shown, opening 214 extends through the second masking layer 204. In some embodiments, a fourth etching process is performed to remove a portion of the second masking layer 204. The fourth etching process can be any suitable process. In some embodiments, a plasma etching process is performed to extend opening 214 through the second masking layer 204. The plasma etching process can use carbon-based etchants, such as CHF3, CH3F, CF4, and / or C4F6. A carrier gas or passivating gas (such as Ar and / or O2) can flow with the etchant. The plasma power of the fourth etching process can be less than that of the first etching process. In some embodiments, the plasma power of the fourth etching process is from about 10 W to about 100 W. The process pressure of the fourth etching process can be substantially the same as that of the third etching process. In some embodiments, the flow rate of the etchant and / or other gases in the fourth etching process can be relatively slow.
[0119] like Figure 12 As shown, opening 214 extends through the first masking layer 202 to expose a portion of the second sacrificial layer 105. In some embodiments, a fifth etching process is performed to remove a portion of the first masking layer 202. The fifth etching process can be any suitable process. In some embodiments, the fifth etching process is similar to the third etching process, except that Ar is used instead of HBr and He.
[0120] like Figure 13 As shown, opening 214 extends through the second sacrificial layer 105 and the first sacrificial layer 103 to form parallel sacrificial gate electrode lines 130. The sacrificial gate electrode lines 130 extend in the Y direction and are spaced apart from each other in the X direction.
[0121] As described above, the second masking layer 204 has a reduced thickness H204 and the second sacrificial layer 105 has a reduced thickness H105, thus reducing the aspect ratio of the opening 214 compared to a typical process. This reduced aspect ratio of the opening 214 helps reduce wafer top loss. For example, the amount of semiconductor material removed from the underlying structure (i.e., fin structure 112) during the etching processes of sacrificial layers 105 and 103 is reduced or minimized. In some embodiments, the uppermost surface 113 is not recessed during the etching processes of sacrificial layers 105 and 103. In some embodiments, the uppermost surface 113 is recessed by no more than 0.5 nanometers during the etching processes of sacrificial layers 105 and 103.
[0122] In some embodiments, multiple processes may be performed to remove portions of the second sacrificial layer 105 and the first sacrificial layer 103. These multiple processes may include a main etching process, a breakthrough process, and / or a soft-landing process. The main etching process may be a plasma etching process and may utilize etchants and other gases such as Cl2, HBr, CH2F2, CHF3, CH3F, O2, and / or Ar. The process pressure of the main etching process may be from about 40 mT to about 800 mT, and the plasma power of the main etching process may be from about 200 W to about 1500 W. The breakthrough process may be performed after the main etching process. In some embodiments, the breakthrough process is a plasma etching process and may utilize etchants and other gases such as CF4, C4F6, CHClF2, and / or Ar. The process pressure of the breakthrough process may be from about 1 mT to about 100 mT, and the plasma power of the breakthrough process may be from about 50 W to about 1000 W. In some embodiments, an ashing process may be performed between the main etching process and the breakthrough process. The ashing process can be a plasma process and can utilize gases such as CO2, CH4, SO2, and / or Ar. The process pressure of the ashing process can be from about 1 mT to about 100 mT, and the plasma power of the ashing process can be from about 500 W to about 4000 W.
[0123] Following the breakthrough process, a soft landing process can be performed. The soft landing process can be a plasma etching process, utilizing etchants and gases such as Cl2, HBr, CH2F2, CF4, C4F6, CHClF2, HF, O2, and / or Ar. In some embodiments, the soft landing process has a plasma power of approximately 100 W to approximately 500 W. The plasma power can be generated by a first radio frequency (RF) power source, and the plasma power can be pulsed. In some embodiments, the soft landing process has a bias power of approximately 600 W to approximately 1200 W. The bias power can be generated by a second RF power source different from the first RF power source. Both the plasma power and the bias power can be pulsed.
[0124] For example, the plasma power Ws and bias power Wb1 may have the same pulse pattern. In some embodiments, the time period T is from about 5 ms to about 15 ms, such as about 10 ms. Within the time period T, the pulse pattern has an activation period and an off period. In some embodiments, the activation period is from about 80% to about 90% of the time period T, and the off period is from about 10% to about 20% of the time period T. The off period may be after the activation period. During the activation period, the plasma power Ws has a duty cycle of from about 1% to about 6% (such as about 3%). In other words, the plasma power is pulsed multiple times during the activation period. During the off period, the plasma power Ws is turned off. During the activation period, the bias power Wb1 has a duty cycle of from about 1% to about 8% (such as about 4%). In other words, the bias power is pulsed multiple times during the activation period. During the off period, the bias power Wb1 is turned off. During the soft landing process, the pulse pattern in the time period T may be repeated multiple times. In some embodiments, the soft landing process has a duration of from about 10 seconds to about 60 seconds.
[0125] In some embodiments, an optional passivation process may be performed after the soft landing process, and an optional second soft landing process may be performed after the passivation process. The passivation process protects the vertical surface of the second sacrificial layer 105. In some embodiments, the passivation process is a plasma treatment process using nitrogen-containing plasma. The plasma power of the passivation process may be from about 500 W to about 4000 W, and may have a duty cycle of from about 3% to about 20%. The process pressure of the passivation process may be from about 50 mT to about 300 mT. The optional second soft landing process may be the same as the soft landing process described above.
[0126] Next, an optional rinsing process can be performed. The rinsing process can be a plasma etching process to remove byproducts from the surface of the semiconductor device structure 100. The rinsing process can utilize etchants such as CF4 and / or C4F6, and can have a plasma power of about 50 W to about 1000 W. The process pressure of the rinsing process can be about 1 mT to about 100 mT.
[0127] Following the rinsing process, an additional etching process may be performed. This additional process may be a plasma etching process, utilizing etchants and gases such as Cl2, HBr, CH2F2, CF4, C4F6, CHClF2, HF, O2, and / or Ar. The process pressure of the additional etching process may be from about 40 mT to about 800 mT. The plasma power of the additional process may be from about 300 W to about 1000 W. In some embodiments, a second bias power supply may be used to provide a second bias power during the additional process. For example, the additional process may include a first bias power of about 400 W to about 1200 W and a second bias power of about 10 W to about 200 W. The duty cycle of the plasma power, the first bias power, and the second bias power may be from about 3% to about 20%.
[0128] The plasma power and two bias voltages of the additional etching process can be pulsed. In some embodiments, the plasma power Ws and the first bias voltage Wb1 of the over-etching process have the same pulse pattern, while the second bias voltage Wb2 of the over-etching process has a different pulse pattern compared to the equality of the plasma power Ws and the first bias voltage Wb1. In some embodiments, the duty cycle of the plasma power Ws and the first bias voltage Wb1 is 20%, while the duty cycle of the second bias voltage is 10%. In some embodiments, the second bias voltage Wb2 is turned on after the first bias voltage Wb1 is turned off.
[0129] Following an additional etching process, the second sacrificial layer 105 and the first sacrificial layer 103 form two or more sacrificial gate electrode lines 130, such as Figure 13 As shown. The third, fourth, fifth, and sixth masking layers 206, 208, 210, and 212 can be removed during or before the patterning of the second sacrificial layer 105 and / or the first sacrificial layer 103. The first and second masking layers 202 and 204 can remain on the sacrificial gate electrode layer 130, as shown. Figure 13 As shown.
[0130] In some embodiments, the opening 214 has a smaller aspect ratio due to the smaller relative thickness H204 of the second masking layer 204 and the smaller relative thickness H105 of the second sacrificial layer 105. Because of the smaller aspect ratio, damage to the uppermost surface 113 of the lower layer is minimized.
[0131] Figure 14 yes Figure 13 A view of the structure, wherein the first masking layer 202 and the second masking layer 204 are not shown, and only the two sacrificial gate lines 130 are shown.
[0132] like Figure 14 As shown, due to the low aspect ratio during the etching process, when the sacrificial gate is patterned, the etching of the topmost surface 113 formed by the topmost first semiconductor layer 106 or nanosheet 106 is reduced, i.e. the loss at the top of the sheet is reduced. Figure 14 The maximum recessed surface 113' is shown. In some embodiments, the uppermost surface 113 may remain horizontally flat. The recess of the uppermost surface 113 may be limited to a depth D1 of no more than 0.5 nanometers, such as no more than 0.4 nanometers, no more than 0.3 nanometers, no more than 0.2 nanometers, or no more than 0.1 nanometers. The amount of recess in the uppermost surface 113 is generated by the processing used herein and may not be achievable using other processing steps. For example, when patterning a sacrificial gate, the aspect ratio may be from 17:1 to 12:1.
[0133] As shown, an angle A1 is formed between the sidewall or side surface 131 of the sacrificial gate line 130 and the uppermost surface 113. In some embodiments, the angle A1 is about 90 degrees to about 105 degrees, such as about 90 degrees to about 95 degrees, or about 91 degrees to about 94 degrees. The angle A1 is generated by the processing used herein and may not be achievable using other processing steps. For example, when patterning the sacrificial gate, the aspect ratio may be from 17:1 to 12:1, resulting in minimizing the recess from the initial uppermost surface 113 to the recessed upper surface 113'.
[0134] Figures 6 to 14 It is along Figure 5 The X-section is the section cut by line AA in the middle. Figure 15 It is along Figure 5 The Y-section cut by line BB in the middle shows the relationship with Figure 14 The same processing stage. Figure 15 A portion of the fin structure 112 located below the opening 214 is shown, in which the sacrificial gate material has been removed.
[0135] like Figure 15 As shown, the etching process for removing the sacrificial gate material causes the upper edge 119 (corner in the cross-sectional view) where the sidewall 115 intersects with the uppermost surface 113 to be rounded. As shown, the uppermost nanostructure 106 has a height H1 at a central location between the sidewalls 115 of the fin structure. Further, the sidewalls 115 of the uppermost nanostructure 106 extend upwards from the lower interposer 108 to a location where the rounding begins at height H2. In some embodiments, height H2 is about 1 nanometer to about 1.5 nanometers lower than height H1. Moreover, the upper surface 113 begins to round at a distance D2 from the adjacent sidewall 115. In some embodiments, distance D2 is about 1.5 nanometers to about 2 nanometers. As further shown, an angle A2 is formed between the plane defined by the upper surface 113 and the tangent of the rounded curve. In some embodiments, angle A2 is about 135 degrees to about 140 degrees.
[0136] Now for reference Figure 16 This shows the semiconductor device structure 100 after subsequent processing. Figure 16 It is similar to Figures 6 to 14 X-section cross-sectional view.
[0137] like Figure 16 As shown, the process includes forming a spacer 140 over the sacrificial gate line 130. For example, a dielectric spacer material (such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof, such as SiOC or SiOCN) may be deposited on... Figure 14 and Figure 15The spacer material can be deposited using processes such as subatmospheric CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes. The spacer material can be formed above the sacrificial gate line and above the fin structure. As shown, the spacer material 140 is formed as a sidewall spacer on the side surface 131 of the sacrificial gate line 130.
[0138] Further, the process may include etching the source / drain cavity 150 into the fin structure 112. As shown in the figure, Figure 16 The portion of the single fin structure 112 located below the sacrificial gate line 130 and spacer 140 shown remains unetched and defines the channel region. In some embodiments, the source / drain cavity 150 may extend into the substrate 101.
[0139] like Figure 16 As further shown, in the process for etching the source / drain cavity 150, the sides of the interposer 108 are not covered. The process may further include laterally recessing the interposer 108 to form a lateral recess, and then forming an internal spacer 160 in the lateral recess. In some embodiments, the internal spacer 160 may be silicon-based. Further, the internal spacer 160 may be formed of a nitride. For example, the internal spacer 160 may be SiN, SiCN, SiON, SiOCN, or another suitable material.
[0140] Now for reference Figure 17 This shows the result after subsequent processing. Figure 16 The semiconductor device structure 100 is shown. As illustrated, an optional isolation material 155 may be formed in the source / drain cavity 150. The isolation material 155 may be silicon-based. For example, the isolation material may be SiO, SiN, SiCN, SiON, SiOCN, or another suitable material.
[0141] exist Figure 17 In this embodiment, semiconductor material 165 may be formed on the uncovered surface of nanostructure 106. In some embodiments, semiconductor material 165 is epitaxial and may be doped.
[0142] As shown, the source / drain feature 170 is epitaxially grown from the semiconductor material of nanostructure 106 or semiconductor material 165. The source / drain feature 170 can be grown vertically and horizontally to form facets that correspond to the crystalline planes of the material used for the first semiconductor layer 106. In this disclosure, the source and drain regions are used interchangeably and have substantially the same structure. Furthermore, the source / drain regions can individually or collectively represent the source or drain depending on the context. The source / drain feature 170 can be made from one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or Si, SiGe, and Ge for p-channel FETs. For p-channel FETs, p-type dopants such as boron (B) can also be included in the source / drain feature 170. The source / drain feature 170 can be formed by epitaxial growth methods using CVD, ALD, or MBE.
[0143] As further shown, a contact etch stop layer (CESL) 175 may be conformally formed on the exposed surface of the semiconductor device structure 100. CESL 175 covers the sidewall spacers 140 and the source / drain features 170. CESL 175 may comprise an oxygen- or nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or similar combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. An interlayer dielectric (ILD) layer 180 may then be formed on the CESL 175 above the semiconductor device structure 100. The material of the ILD layer 180 may comprise compounds (including Si, O, C, and / or H), such as silicon oxide, silicon oxycarbonide, or silicon oxycarbide. Organic materials such as polymers may also be used for the ILD layer 180. The ILD layer 180 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of the ILD layer 180, the semiconductor device structure 100 may be subjected to a heat treatment to anneal the ILD layer 180.
[0144] like Figure 17 As shown, the process may include removing the sacrificial gate line 130 to form the gate cavity 135. The sacrificial gate line 130 may be removed by an anisotropic dry etching process. For example, the etching process may include using a dry etching process that selectively etches the sacrificial gate line 130 without etching the interlayer dielectric material 180 or the sidewall spacers 140 using a reactive gas. The sacrificial gate dielectric layer 103 may be used as an etch stop layer when etching the sacrificial gate electrode material of the sacrificial gate line 130.
[0145] exist Figure 18In this process, the sacrificial gate dielectric layer 103 is removed. For example, for the sacrificial gate dielectric layer 103 used as a silicon oxide interface layer, an interlayer oxide removal process is performed. The interlayer oxide removal process is designed and controlled to minimize or eliminate any depressions on the uppermost surface 113 of the uppermost nanostructure 106.
[0146] In some embodiments, the process for removing the interface layer 103 is dry etching, which uses an etching gas, such as HF, NH3, or another suitable etching gas; a selective passivation gas, such as N2, O2, CO2, or another suitable passivation gas; and a dilution gas, such as He, Ar, N2, or another suitable dilution gas. Dry etching can be performed at a power of 10 W to 2000 W, a pressure of 10 mTorr to 500 mTorr, and a gas flow rate of 20 sccm to 2000 sccm.
[0147] Figure 19 yes Figure 18 A cross-sectional view of a portion of the structure of the semiconductor device 100, focusing on the uppermost surface 113 of the uppermost nanostructure 106, and showing the maximum amount of recesses on the uppermost surface 113. Specifically, Figure 19 The uppermost surface 113 can be recessed to a maximum extent to the recessed uppermost surface 113". As shown, the recessed uppermost surface 113" can reach a depth D9 below the uppermost surface 113. In the embodiments herein, the maximum depth D9 can be 0.4 nanometers. For example, the uppermost surface 113 can be recessed by 0.1 nanometers to 0.4 nanometers. The amount by which the uppermost surface 113 is recessed to the recessed uppermost surface 113" is generated by the processing used herein and may not be achievable using other processing steps. For example, the chemical properties and process parameters of the etching process minimize the recess of the uppermost surface 113.
[0148] Depth D9 can be referred to as the maximum height difference of the uppermost recessed surface 113", that is, the maximum difference in the Z direction between two points on the uppermost recessed surface 113". The highest point includes the unetched point of the sacrificial gate dielectric layer 103 covered by the sidewall spacer 140 to remove the etch process, and the lowest point includes the point on the uppermost recessed surface 113" closest to the substrate 101.
[0149] Figures 20 to 21 The drawing is shown after subsequent processing. Figure 18 The semiconductor device structure 100. Figure 20 It is similar to Figure 18 The cross-sectional view, and Figure 21 yes Figure 20 A perspective view of a portion of a semiconductor device 100, wherein the CC line indicates... Figure 20 Cross-sectional view.
[0150] Cross-reference Figures 20 to 21 Intermediate layer 108 can be removed during sheet peeling processes.
[0151] As further shown, a replacement gate structure 190 is formed in the gate cavity 135. For example, a gate dielectric layer and a gate electrode material are formed in the gate cavity 135. The gate dielectric layer may be conformally deposited in the gate cavity 135, including around the nanostructure 106. In some embodiments, an interface layer (IL) (not shown) is formed between the gate dielectric layer and the exposed surface of the first semiconductor layer 106.
[0152] The gate dielectric layer may comprise one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-dielectric-constant dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-dielectric-constant dielectric materials include hafnium dioxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium zirconium oxide, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-dielectric-constant dielectric materials, and / or combinations thereof. Methods for forming the gate dielectric layer may include chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, molecular-beam deposition (MBD), and the like.
[0153] Gate electrode material is deposited over the gate dielectric layer and fills the remainder of cavity 135. The gate electrode material may include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, titanium aluminum, titanium aluminum nitride, tantalum carbonitride, tantalum carbide, tantalum silicon nitride, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode material may be formed by chemical vapor deposition, atomic layer deposition, electroplating, or other suitable deposition techniques. The gate electrode material may also be deposited over the upper surface of ILD layer 180. The gate dielectric layer and gate electrode layer formed over ILD layer 180 are then removed by, for example, CMP until the top surface of ILD layer 180 is uncovered.
[0154] Figure 22 yes Figure 20 A cross-sectional view of a portion of the structure of the semiconductor device 100, focusing on the uppermost surface 113 of the uppermost nanostructure 106, and illustrating the maximum amount of depressions on the uppermost surface 113. Similar to... Figure 19 , Figure 22The recessed uppermost surface 113 is indicated to reach a depth D9 below the initial uppermost surface 113. In embodiments herein, the maximum depth D9 may be 0.4 nanometers. For example, the initial uppermost surface 113 may be recessed by 0.1 nanometers to 0.4 nanometers. The amount of recess in the uppermost surface 113 is generated by the process used herein and may not be achievable using other processing steps. For example, the chemical properties and process parameters of the etching process minimize the recess in the uppermost surface 113 while removing the interface layer 103.
[0155] Below the sidewall spacers 140, the uppermost surface 113 below the gate structure 190 may have a recessed uppermost surface 113'. (Refer to the above...) Figure 14 As described above, due to the low aspect ratio during the etching process, the etching distance from the initial uppermost surface 113 to the recessed surface 113' is reduced when the sacrificial gate is patterned. The recessed surface 113' may not exceed a depth D1 from the initial surface 113. The depth D1 may not exceed 0.5 nanometers, such as not exceeding 0.4 nanometers, 0.3 nanometers, 0.2 nanometers, or 0.1 nanometers. The amount of recess on the uppermost surface 113 is generated by the process used herein and may not be achievable using other processing steps. For example, when the sacrificial gate is patterned, the aspect ratio may be 17:1 to 12:1, thus minimizing the recess from the initial uppermost surface 113 to the recessed upper surface 113'.
[0156] As shown, the replacement gate 190 has a sidewall 191. An angle A9 is defined between the sidewall 191 and the recessed surface 113'. In some embodiments, the angle A9 is about 90 degrees to about 105 degrees, such as about 90 degrees to about 95 degrees, or about 91 degrees to about 94 degrees. The angle A9 is generated by the processing used herein and may not be achievable using other processing steps. For example, when patterning the sacrificial gate, the aspect ratio may be from 17:1 to 12:1, thus minimizing the recess from the initial uppermost surface 113 to the upper recessed surface 113'.
[0157] As shown in the figure, an angle A8 is defined from the recessed surface 113' to the recessed surface 113" (as shown, away from the opening of the gate structure 190). In some embodiments, angle A8 is 160 to 180 degrees, such as 165 to 178 degrees, for example 167 to 175 degrees. Angle A8 is generated by the process used herein and may not be achievable using other processing steps. For example, the aspect ratio may be 17:1 to 12:1 while patterning the sacrificial gate to minimize the recess from the initial uppermost surface 113 to the recessed upper surface 113', and the chemical properties and process parameters of the etching process may minimize the recess from the uppermost surface 113 to the recessed upper surface 113" while removing the interface layer 103.
[0158] It should be noted that the aspect ratio during the processing described herein may decrease as the upper masking layer is removed, and may increase as the opening or cavity is etched deeper. Therefore, any etching process described herein may have an initial aspect ratio less than 17:1, less than 16:1, less than 15:1, less than 14:1, or less than 13:1 and greater than 12:1, i.e., the aspect ratio at the start of etching. Furthermore, any etching process described herein may have a final aspect ratio less than 17:1, less than 16:1, less than 15:1, less than 14:1, or less than 13:1 and greater than 12:1, i.e., the aspect ratio at the end of etching.
[0159] In one embodiment, a method for forming a semiconductor device structure includes: forming a fin structure having a top surface; depositing a sacrificial material over the fin structure; etching a first selected portion and a second selected portion of the sacrificial material to form a sacrificial segment, wherein the top surface of the fin structure below the first selected portion is etched to a first recessed surface, and the top surface of the fin structure below the second selected portion is etched to a second recessed surface; forming spacers around the fin structure and above the first and second recessed surfaces; and replacing the sacrificial segment with a replacement structure having a first sidewall and a second sidewall, wherein each sidewall extends upward from the top surface of the fin structure, wherein a first angle defined between the first sidewall and the first recessed surface is 90 to 95 degrees, and wherein a second angle defined between the second sidewall and the second recessed surface is 90 to 95 degrees.
[0160] In some embodiments of this method, each of the first angle and the second angle is 91 to 94 degrees.
[0161] In some embodiments of this method, the uncovered portions of the fin structure are located adjacent to the spacer, and the method further includes removing these uncovered portions of the fin structure to form recesses; and forming source / drain features in these recesses.
[0162] In some embodiments of this method, the fin structure includes nanosheet layers separated by an interlayer; the uncovered portions of the fin structure include portions of the nanosheet layers and the interlayer; and the method further includes etching the interlayer to form lateral recesses, and forming internal spacers in the lateral recesses before forming the source / drain features in the recesses.
[0163] In some embodiments of this method, after the sacrificial material is deposited over the fin structure, the sacrificial material has a thickness of about 38 nanometers to about 45 nanometers over the uppermost surface; the method further includes depositing a primary masking layer over the sacrificial material, wherein the primary masking layer has a thickness of about 60 nanometers to about 65 nanometers; and the method further includes removing portions of the primary masking layer before etching the first and second selected portions of the sacrificial material, wherein the etching of the first and second selected portions of the sacrificial material is performed with an aspect ratio of less than 17:1.
[0164] In some embodiments of this method, depositing the sacrificial material over the fin structure includes depositing a first sacrificial layer around the fin structure; and depositing a second sacrificial layer on the first sacrificial layer, wherein the second sacrificial layer has a thickness of about 35 nm to about 40 nm.
[0165] In some embodiments of this method, the second sacrificial layer comprises silicon.
[0166] In some embodiments, the method further includes depositing a lower masking layer on the sacrificial material, wherein the primary masking layer is deposited on the lower masking layer; depositing an upper masking layer on the primary masking layer; forming a resist structure on the upper masking layer; performing a resist etching process to remove a portion of the resist structure; performing an upper etching process to remove a portion of the upper masking layer; and performing a lower etching process to remove a portion of the lower masking layer.
[0167] In some embodiments of this method, the resist etching process, the upper etching process, the main etching process, and the lower etching process are different processes.
[0168] In some embodiments, the method further includes removing the sacrificial segment by performing a removal process in which the uppermost surface of the fin structure located below the sacrificial segment is recessed by less than 0.5 nanometers.
[0169] In some embodiments of this method, the replacement structure is located above the central region of the uppermost surface, which is located between the edge regions of the uppermost surface, and the central region is less than about 0.5 nanometers lower than the edge regions.
[0170] In some embodiments of this method, the replacement structure is located above the central region of the uppermost surface, and the third angle defined between the central region of the uppermost surface and the first recessed surface is 165 to 178 degrees.
[0171] In another embodiment, a method for forming a semiconductor device structure includes: depositing a first sacrificial layer over the uppermost surface of a semiconductor material; depositing a second sacrificial layer on the first sacrificial layer; etching the first and second sacrificial layers to form a sacrificial segment; forming spacers around the sacrificial segment; forming features aligned with the spacers; forming an interlayer material over the features; removing the second sacrificial layer of the sacrificial segment; removing the first sacrificial layer of the sacrificial segment by performing a removal process in which the uppermost surface of the semiconductor material is recessed by less than 0.5 nanometers; and forming a replacement structure over the uppermost surface.
[0172] In some embodiments of this method, the first sacrificial layer comprises silicon oxide and has a thickness of about 3 nanometers to about 5 nanometers when deposited.
[0173] In some embodiments of this method, the removal process includes plasma etching.
[0174] In some embodiments of this method, the second sacrificial layer has a thickness of about 35 nanometers to about 40 nanometers, and etching the first sacrificial layer and the second sacrificial layer to form the sacrificial segment includes depositing a primary masking layer over the second sacrificial layer, wherein the primary masking layer has a thickness of about 60 nanometers to about 65 nanometers; performing a primary etching process to remove a portion of the primary masking layer; and performing multiple processes to remove portions of the second sacrificial layer and the first sacrificial layer to form the sacrificial segment, wherein these multiple processes are performed at aspect ratios of 12:1 to 17:1.
[0175] In another embodiment, a semiconductor structure includes: a fin structure terminating at an uppermost surface having a first edge region, a second edge region, and a central region therebetween; a first spacer contacting the uppermost surface at the first edge region; a second spacer contacting the uppermost surface at the second edge region; and a gate structure contacting the uppermost surface at the central region; wherein the central region of the uppermost surface has a maximum height difference of 0.5 nanometers.
[0176] In some embodiments of this semiconductor structure, the gate structure has a first sidewall extending upward away from the uppermost surface, and wherein a first angle defined between the first sidewall and the first edge region is about 91 degrees to about 94 degrees.
[0177] In some embodiments of this semiconductor structure, the second angle from this first edge region to this central region, away from the opening of this gate structure, is about 167 degrees to about 175 degrees.
[0178] In some embodiments of this semiconductor structure, the uppermost surface is formed of an uppermost nanosheet, and the fin structure includes at least one lower nanosheet located below the uppermost nanosheet.
[0179] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, It includes: Forming a fin structure with an uppermost surface; Sacrificial material is deposited on top of the fin structure; A first selected portion and a second selected portion of the sacrificial material are etched to form a sacrificial section, wherein the uppermost surface of the fin structure under the first selected portion is etched to a first recessed surface, and the uppermost surface of the fin structure under the second selected portion is etched to a second recessed surface. A spacer is formed around the fin structure and above the first recessed surface and the second recessed surface; and The sacrificial section is replaced by a replacement structure having a first sidewall and a second sidewall, wherein each sidewall extends upward from the uppermost surface of the fin structure, wherein a first angle is defined between the first sidewall and the first recessed surface of 90 to 95 degrees, and wherein a second angle is defined between the second sidewall and the second recessed surface of 90 to 95 degrees.
2. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The uncovered portion of the fin structure is located adjacent to the spacer, and the method further includes: Remove the uncovered portions of the fin structure to form multiple recesses; and Source / drain characteristics are formed in these recesses.
3. The method for manufacturing a semiconductor device as described in claim 2, characterized in that, in: The fin structure comprises nanosheets separated by an intermediate layer; The uncovered portions of the fin structure include portions of the nanosheets and the intermediate layers; and The method further includes etching the interposers to form a plurality of lateral recesses, and forming internal spacers in the lateral recesses before forming the source / drain features in the recesses.
4. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, in: After the sacrificial material is deposited on the fin structure, the sacrificial material has a thickness of 38 nanometers to 45 nanometers above the uppermost surface; The method further includes depositing a primary masking layer over the sacrificial material, wherein the primary masking layer has a thickness of 60 nanometers to 65 nanometers; and The method further includes removing a portion of the main masking layer before etching the first selected portion and the second selected portion of the sacrificial material; The first and second selected portions of the sacrificial material are etched with an aspect ratio of less than 17:
1.
5. The method for manufacturing a semiconductor device as claimed in claim 4, characterized in that, The sacrificial material deposited above the fin structure comprises: A first sacrificial layer is deposited around the fin structure; and A second sacrificial layer is deposited on the first sacrificial layer, wherein the second sacrificial layer has a thickness of 35 nm to 40 nm.
6. The method for manufacturing a semiconductor device as claimed in claim 4, characterized in that, It further includes: A lower masking layer is deposited on the sacrificial material, wherein the main masking layer is deposited on the lower masking layer; A top masking layer is deposited on the main masking layer; A resist structure is formed on the upper shielding layer; A resist etching process is performed to remove a portion of the resist structure; Perform an upper etching process to remove a portion of the upper masking layer; and Perform a lower etching process to remove part of the lower masking layer.
7. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The replacement structure is located above a central region of the uppermost surface, and a third angle between the central region of the uppermost surface and the first recessed surface is 165 to 178 degrees.
8. A method for manufacturing a semiconductor device, characterized in that, The method includes: A first sacrificial layer is deposited above the uppermost surface of a semiconductor material; A second sacrificial layer is deposited on the first sacrificial layer; The first sacrificial layer and the second sacrificial layer are etched to form a sacrificial section; A spacer is formed around the sacrifice section; Forming features aligned with the spacer; Interlayer material is formed above these features; Remove the second sacrificial layer from the sacrificial section; and The first sacrificial layer of the sacrificial segment is removed by a removal process in which the uppermost surface depression of the semiconductor material is less than 0.5 nanometers.
9. A semiconductor device, characterized in that, It includes: A fin structure terminating on an uppermost surface having a first edge region and a central region; and A gate structure that contacts the uppermost surface in the central region; wherein the central region of the uppermost surface has a maximum height difference of 0.5 nanometers.
10. The semiconductor device as claimed in claim 9, characterized in that, The uppermost surface is formed by an uppermost nanostructure, and the fin structure includes at least one lower nanostructure located below the uppermost nanostructure.