Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and a semiconductor device. The manufacturing method comprises: forming a stack on a substrate, the stack comprising alternatingly stacked sacrificial layers and semiconductor layers; patterning the stack to form fins extending along a first direction; forming a sacrificial gate on the stack extending along a second direction intersecting the first direction so as to intersect the fins; forming source / drain layers on opposite sides of the sacrificial gate in the first direction, the source / drain layers being respectively in contact with the sacrificial layers and the semiconductor layers in the fins; removing the sacrificial gate and selectively etching the sacrificial layers in the stack to release gate spaces; forming inner spacers on the sidewalls of the source / drain layers through the gate spaces; and forming a gate stack in the gate spaces.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] With the continuous development of integrated circuit manufacturing process nodes and key technologies, NS-GAA FET (Nano-SheetGate-All-Around Field-Effect Transistor) will replace the existing Fin FET (Fin Field-Effect Transistor) technology at 3nm and below. Furthermore, because Innerspacer technology plays a crucial role in improving device AC performance, controlling leakage current, and controlling channel length, it is considered one of the key processes distinguishing NS-GAA FET from Fin FET technology.

[0003] However, the process methods for implementing the inner wall in the relevant examples are quite difficult and still have certain limitations. Summary of the Invention

[0004] In view of the above problems, this application provides a method for manufacturing a semiconductor device and a semiconductor device.

[0005] According to a first aspect of the present application, a method for manufacturing a semiconductor device is provided, comprising: forming a stack on a substrate, the stack including alternately stacked sacrificial layers and semiconductor layers; patterning the stack to form fins extending along a first direction; forming a sacrificial gate on the stack extending along a second direction intersecting the first direction and thus intersecting the fins; forming source / drain layers on opposite sides of the sacrificial gate in the first direction, the source / drain layers being respectively connected to the sacrificial layer and the semiconductor layer in the fins; removing the sacrificial gate and selectively etching the sacrificial layer in the stack to release a gate space; forming inner sidewalls on the sidewalls of the source / drain layers through the gate space; and forming a gate stack within the gate space.

[0006] According to an embodiment of this application, forming an inner sidewall on the sidewall of the source / drain layer through the gate space includes: forming a dielectric layer in the gate space using an atomic layer deposition process; and etching the dielectric layer using an anisotropic etching process to retain the portion in contact with the sidewall of the source / drain layer as the inner sidewall.

[0007] According to an embodiment of this application, the manufacturing method further includes: performing multiple cycles of atomic layer deposition and anisotropic etching processes within the gate space to form an inner sidewall.

[0008] According to an embodiment of this application, the manufacturing method further includes: forming a gate sidewall on the sidewall of the sacrificial gate, wherein the inner sidewall has a different etching selectivity relative to the gate sidewall.

[0009] According to an embodiment of this application, the above manufacturing method further includes: using a sacrificial gate and a gate sidewall as a mask to pattern the fin, so that the sacrificial layer and the semiconductor layer in the patterned fin each have a side surface exposed in a first direction, wherein a source / drain layer is epitaxially grown on the side surface exposed in the first direction of the sacrificial layer and the semiconductor layer.

[0010] According to an embodiment of this application, the manufacturing method further includes: forming a capping layer on the side surface of the sacrificial layer and the semiconductor layer exposed in a first direction, wherein a source / drain layer is epitaxially grown after the capping layer is formed.

[0011] According to an embodiment of this application, the above manufacturing method further includes: forming an etch protection layer on a semiconductor layer via a gate space, wherein a dielectric layer is formed after the etch protection layer is formed; and removing the etch protection layer after the inner sidewall is formed.

[0012] According to an embodiment of this application, the manufacturing method further includes: doping a substrate to form a doped layer, and forming a stack on the doped layer.

[0013] According to a second aspect of the embodiments of this application, a semiconductor device is provided. The device includes a substrate, a plurality of semiconductor layers, source / drain layers, a gate stack, and inner sidewalls. The plurality of semiconductor layers are located on the substrate and stacked at intervals from each other in a vertical direction. The source / drain layers are located on opposite sides of the plurality of semiconductor layers in a first direction. The gate stack at least partially surrounds the periphery of the plurality of semiconductor layers in a second direction, intersecting the first direction. The inner sidewalls are located between the source / drain layers and the gate stack. The portions of the source / drain layers on the sidewalls of the semiconductor layers and the portions on the inner sidewalls have a continuous crystal structure.

[0014] According to an embodiment of this application, the inner wall has an inner wall that is recessed toward the source / drain layer in a first direction.

[0015] According to embodiments of this application, a method for manufacturing a semiconductor device is provided. This method employs a post-sidewall process, where source / drain layers are formed and channels are released first, and inner sidewalls are formed on the sidewalls of the source / drain layers within the released gate space. Compared to the pre-sidewall process in related examples (i.e., forming inner sidewalls before forming the source / drain layers), this method avoids the technical difficulties of etching processes before and after inner sidewall deposition, the impact of etching processes on the crystal quality of the source / drain layers, and the difficulty of epitaxy of the source / drain layers. It at least partially solves the limitations of existing manufacturing processes and expands the applicable scenarios for inner sidewall technology. Attached Figure Description

[0016] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, which will be explained below in conjunction with the drawings:

[0017] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application is shown schematically.

[0018] Figure 2 A perspective view of a semiconductor device according to an embodiment of this application is shown schematically;

[0019] Figures 3A to 9B Cross-sectional views along various axial directions are schematically shown for some stages in a method for manufacturing a semiconductor device according to embodiments of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0021] The endpoints and any values ​​of the ranges disclosed in this application are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this application.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0023] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0024] In the description of this application, it should be understood that the terms "longitudinal", "length", "circumferential", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the subsystem or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0025] Similarly, to simplify this application and aid in understanding one or more of the various disclosed aspects, in the above description of exemplary embodiments of this application, various features of this application are sometimes grouped together into a single embodiment, figure, or description thereof. The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0026] As integrated circuit manufacturing processes continue to advance towards smaller dimensions, the structural innovation of transistors, as one of the core units of integrated circuits, has become a significant driving force for the development of the semiconductor industry. NS-GAA FETs have become the mainstream technology to replace FinFETs at 3nm and below. Furthermore, the inner sidewalls in NS-GAA FETs are considered one of the key processes that distinguishes them from FinFETs. Located between the source / drain layer and the gate, the inner sidewalls reduce parasitic capacitance between the gate and the source / drain layer, optimizing the device's response characteristics and thus improving its AC performance. Additionally, the inner sidewalls prevent direct contact between the gate and the source / drain layer, thereby reducing leakage current, enhancing the gate's control over the channel, and reducing process deviations by controlling the channel length.

[0027] However, the mainstream process sequence for achieving inner sidewalls is to form them before growing the source / drain layers. This sequence is not only difficult to manufacture but also affects device performance, thus limiting the application of inner sidewalls. For example, the etching of the sacrificial layer before inner sidewall deposition requires high selectivity between the sacrificial layer and the semiconductor layer, making it difficult to control the etching morphology. It is also susceptible to the effects of active region pattern loading, resulting in variations in inner sidewall thickness at different locations and causing deviations in device electrical characteristics. In addition, the etching process after inner sidewall deposition requires long-term physical etching with strong verticality to ensure the steepness of the sidewalls. This process can easily damage the channel material in the epitaxial region, thereby degrading the crystal quality of subsequent epitaxial source / drain layers. Furthermore, the inner sidewall etching process removes part of the sacrificial layer from the sidewalls, leading to discontinuities in the nucleation interface of subsequent epitaxial source / drain layers. This increases the process difficulty of epitaxial source / drain layers and increases dislocation defects after epitaxial source / drain layers, making it difficult to provide effective stress to the channel, resulting in device performance degradation.

[0028] In view of this, the embodiments of this application provide a method for manufacturing a semiconductor device, which can at least partially solve the limitations of existing manufacturing processes and increase the applicable scenarios of the inner sidewall technology.

[0029] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application is shown.

[0030] like Figure 1 As shown, the manufacturing method of this embodiment may include operations S110 to S170.

[0031] In operation S110, a stack is formed on the substrate, the stack comprising alternating sacrificial layers and semiconductor layers.

[0032] In operation S120, the stack is patterned to form fins extending along a first direction.

[0033] In operation S130, a sacrificial gate is formed on the stack extending along a second direction intersecting the first direction, thereby intersecting the fin.

[0034] In operation S140, source / drain layers are formed on opposite sides of the sacrificial gate in the first direction, and the source / drain layers are respectively connected to the sacrificial layer and the semiconductor layer in the fin.

[0035] In operation S150, the sacrificial gate is removed and the sacrificial layer in the stack is selectively etched to free up gate space.

[0036] In operation S160, an inner sidewall is formed on the sidewall of the source / drain layer through the gate space.

[0037] In operation S170, a gate stack is formed within the gate space.

[0038] According to an embodiment of this application, the manufacturing method in this embodiment adopts a post-inner-sidewall process, that is, the source / drain layer is formed and the channel is released first, and the inner sidewall is formed on the sidewall of the source / drain layer in the released gate space. Compared with the pre-inner-sidewall process in related examples (i.e., the inner sidewall is formed before the source / drain layer is formed), it avoids the technical difficulties of the etching process before and after the inner sidewall deposition, the impact of the etching process on the crystal quality of the source / drain layer, and the difficulty of epitaxy of the source / drain layer. It at least partially solves the limitations of the existing manufacturing process and increases the applicable scenarios of the inner sidewall technology.

[0039] To better understand the semiconductor device manufacturing method of this application, the following is combined with... Figure 2 , Figures 3A to 9B The manufacturing method of the embodiments of this application will be described below.

[0040] Figure 2 A perspective view of a semiconductor device according to an embodiment of this application is shown schematically. Figures 3A to 9B Cross-sectional views along various axes are schematically shown for some stages of a method for manufacturing a semiconductor device according to embodiments of this application. It should be noted that in the various figures shown in this application, when the numbers in the titles of multiple figures are the same, the manufacturing processes corresponding to those multiple figures are the same. When the numbers in the titles of multiple figures are the same but the letters are different, the manufacturing processes corresponding to those multiple figures are the same, but the axes corresponding to those multiple figures are different. For example, Figure 5A and Figure 5B These are cross-sectional views of two axes, representing the same manufacturing process.

[0041] Specifically, Figure 2 The perspective view of the semiconductor device is shown only schematically and is intended to illustrate the location of the cross-sectional views involved in other figures, and is not intended to illustrate a specific three-dimensional structure of the semiconductor device according to embodiments of this application. The structure of the semiconductor device according to embodiments of this application can be understood from the following cross-sectional views. Figures 3A to 9B Cross-sectional views of a semiconductor device according to embodiments of this application are shown at some stages along the X-X' axis and / or the Y-Y' axis; Figures 3A to 9A Cross-sectional views of a semiconductor device according to embodiments of this application are shown at some stages along the Y-Y' axis. Figures 3B to 9B Cross-sectional views of a semiconductor device according to an embodiment of this application are shown at some stages along the X-X' axis. Figure 6C and Figure 8C The accompanying figure shows a cross-sectional view of a semiconductor device according to another embodiment of this application at some stages along the Y-Y' axis, with the tilde "~" in the figure representing the space released during the etching process.

[0042] More specifically, Figure 2 The diagram illustrates the main components of a semiconductor device, such as shallow trench isolation (STI), nanosheets (NS), innerspacers, source / drain layers (S / D), and gate stacks, and their positional relationships. Of course, the number of nanosheets (NS) is not limited to this. On both sides of the nanosheets (NS) in a first direction, there are source / drain layers (S / D) that are in contact with the channel portion (i.e., the nanosheets (NS)). The gate stack (Gate) may extend along a second direction intersecting (e.g., perpendicular to) the first direction to at least partially surround the outer periphery of the channel portion (i.e., the nanosheets (NS)). The innerspacer (Innerwall) may be located between the gate stack (Gate) and the source / drain layers (S / D). The nanosheets (NS) may be formed on top of the underlying silicon (sub-Si), and the underlying silicon (sub-Si) may be surrounded by the shallow trench isolation (STI).

[0043] According to an embodiment of this application, the Y-Y' axis can extend along a first direction and is located in the middle of the nanosheet NS in a second direction; the X-X' axis can extend along a second direction and is located in the middle of the source / drain layer S / D in the first direction.

[0044] refer to Figure 3A and Figure 3B It can form a stack on the substrate.

[0045] A substrate 101 may be provided. The substrate 101 may be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The bulk semiconductor substrate may include Si, and the SOI substrate may include silicon-on-insulator (SOI), etc. In the following embodiments, a bulk silicon substrate is used as an example. In some embodiments, the substrate 101 may be doped using ion implantation to form a doped layer 102 in the substrate 101, and a stack may be formed on the substrate 101. For example, the doping concentration of the doped layer 102 may be 5 × 10⁻⁶. 18 cm －3 ~1×10 20 cm －3 The doped layer 102 can form a ground plane (GP) doping layer to suppress leakage in the sub-Si. The doped layer 102 can be omitted, especially in the case of a semiconductor-on-insulator substrate. In the embodiment, the substrate 101 can be pretreated sequentially by well lithography, ion implantation, annealing, and cleaning.

[0046] A stacked layer can be formed on substrate 101 using an epitaxial growth process. The stacked layer may include alternating sacrificial layers 103 and semiconductor layers 104. Semiconductor layer 104 may include a semiconductor material suitable for serving as a channel, and sacrificial layer 103 may include a material with etching selectivity relative to semiconductor layer 104. For example, sacrificial layer 103 may include SiGe, and semiconductor layer 104 may include Si, etc. The thickness of semiconductor layer 104 in the vertical direction can be 3 nm to 7 nm. The thickness of sacrificial layer 103 in the vertical direction can be 7 nm to 13 nm, etc. Semiconductor layer 104 may be undoped or lightly doped, for example, with a doping concentration of 1 × 10⁻⁶. 15 cm －3 The doping type of semiconductor layer 104 can be set according to the type of semiconductor device. It can be the opposite of the conductivity type of the semiconductor device. For example, it can be N-type doped for P-type devices or P-type doped for N-type devices.

[0047] refer to Figure 4A and Figure 4B The layers can be patterned to form fins extending along a first direction, and sacrificial gates can be formed on the fins.

[0048] The fin pattern can be defined using a sidewall pattern transfer (SIT) process. For example, a mandrel can be formed on the stack and patterned using photolithography to obtain a linear pattern extending along a first direction (Y-Y' axis). The mandrel can be made of polycrystalline silicon or amorphous silicon, etc. Sidewalls are formed on the sidewalls of the mandrel, and the patterned mandrel is removed after the sidewalls are formed, leaving the sidewalls on the stack. The sidewalls can be used as etching masks, and an anisotropic etching process, such as reactive ion etching (RIE) in the vertical direction, can be used to etch the stack structure (sacrificial layer 103 and semiconductor layer 104) to form fins on the substrate 101 and etched regions distributed on both sides of the fins in a second direction. This etching can penetrate into the substrate 101.

[0049] Within the etched area, a first dielectric layer 106 is deposited, and the first dielectric layer 106 is etched back to be below or flush with the upper surface of the substrate 101, thereby forming shallow trench isolation (STI). In some embodiments, a second dielectric layer 105 may be deposited on the sidewalls of the substrate 101 before the first dielectric layer 106 is deposited. The first dielectric layer 106 may include silicon oxide, etc., and the second dielectric layer 105 may include silicon nitride, etc.

[0050] A sacrificial gate spanning the fin can be formed on the first dielectric layer 106 using processes such as thermal oxidation, chemical vapor deposition, or sputtering. The sacrificial gate may include a vertically stacked gate oxide layer 107, a silicon layer 108, and a hard mask layer 109. For example, the gate oxide layer 107 may include silicon oxide, the silicon layer 108 may include amorphous silicon or polycrystalline silicon, and the hard mask layer 109 may include nitrides, oxides, carbides, or organic materials.

[0051] refer to Figure 5A and Figure 5B A gate sidewall 110 can be formed on the sidewall of the sacrificial gate using a sidewall forming process. For example, the gate sidewall 110 may include nitrides, etc. The thickness of the gate sidewall 110 in the first direction can be 3nm to 9nm, etc. In an embodiment, the sacrificial gate and the gate sidewall can be used as a mask to pattern the fin, so that the sacrificial layer 103 and the semiconductor layer 104 in the patterned fin each have a side surface exposed in the first direction.

[0052] refer to Figure 6A and Figure 6B This can form a source / drain layer.

[0053] Source / drain materials can be epitaxially grown on the side surfaces exposed in the first direction of the sacrificial layer 103 and the semiconductor layer 104, thereby forming a source / drain layer 111 in contact with the sacrificial layer 103 and the semiconductor layer 104. In this embodiment, the source / drain layer 111 can be heavily doped (e.g., by in-situ doping) to reduce the series resistance, and the doping concentration can be 1 × 10⁻⁶. 21 cm －3 ~1×10 22 cm －3 The source / drain layer 111 can be activated, for example, by using a rapid thermal annealing process below 900°C to activate impurities in the source / drain layer 111, thereby forming an activated source / drain layer 111.

[0054] like Figure 6A As shown, source / drain layers 111 can be epitaxially grown on continuous crystal surfaces (the side surfaces exposed in the first direction of sacrificial layer 103 and semiconductor layer 104). However, in the inner sidewall pre-process, the sidewalls of sacrificial layer 103 are replaced by the sidewalls of the inner sidewalls, thus source / drain layers can only be epitaxially grown on discrete crystal surfaces (the side surfaces exposed in the first direction of semiconductor layers 104 spaced apart in the vertical direction) (the sidewalls of the inner sidewalls of the dielectric material cannot serve as seeds for crystal growth). Sources / drains grown from the discrete crystal surfaces merge, leading to defects such as stacking faults. These defects degrade device performance, particularly making it difficult to achieve high effective stress. In contrast, according to embodiments of this application, since source / drain layers can be grown on continuous crystal interfaces, the source / drain layers can have improved crystal quality, particularly reducing defects such as stacking faults caused by merging. According to some embodiments, the portion of the source / drain layer 111 on the sidewall of the semiconductor layer 104 and the portion on the inner sidewall 114 may have a continuous crystal structure.

[0055] In some embodiments, such as Figure 6C As shown, before epitaxially growing the source / drain layer 111, a capping layer 111A can be grown on the sidewalls (and surface of the substrate 101) of the sacrificial layer 103 and the semiconductor layer 104, and the source / drain layer 111 is epitaxially grown on the capping layer. The capping layer 111A is used as an etch stop layer to protect the source / drain layer 111 in the subsequent etch process to release the gate space. The capping layer 111A may include a material with etch selectivity relative to the sacrificial layer 103 (SiGe in this example), such as silicon. The thickness of the capping layer 111A in the first direction can be 1 nm to 3 nm, etc. For ease of description, the following description still uses an embodiment without a capping layer as an example. In a specific embodiment, during the epitaxial growth of the source / drain material, due to the anisotropy of the crystal growth rate, the source / drain layer 111 can exhibit a polygonal epitaxial morphology, such as... Figure 6B As shown in the image.

[0056] In some embodiments, the semiconductor device is a P-type field-effect transistor, and the source / drain layer 111 may include SiGe to apply stress to the channel (e.g., semiconductor layer 104 of Si). In cases where the sacrificial layer 103 also includes SiGe, a capping layer 111A of, for example, Si may be formed first to prevent the source / drain layer 111 from being undesirably etched during the etching process that releases the gate space.

[0057] refer to Figure 7A and Figure 7B It can remove the sacrificial gate and selectively etch the sacrificial layer in the stack to free up gate space.

[0058] A third dielectric layer 113 is formed on substrate 101 and planarized, for example, by chemical mechanical polishing (CMP). Planarization removes the hard mask layer 109 in the sacrificial gate and exposes the silicon layer 108. The silicon layer 108 and the gate oxide layer 107 are then etched using a selective etching process to expose the sacrificial layer 103 and the sidewalls of the semiconductor layer 104 in the second direction. In some embodiments, an etch stop layer 112 may be deposited before depositing the third dielectric layer 113 to prevent over-etching of the source / drain layer 111 during subsequent etching of the contact holes. The sacrificial layer 103 is etched using a selective etching process via the exposed sidewalls, thereby freeing up space inside the gate sidewall 110. Since the freed space is subsequently used to form the gate stack, it is therefore referred to below as the gate space.

[0059] refer to Figure 8A and Figure 8B Due to the release of the gate space, the sidewalls of the source / drain layer 111 (which were originally connected to the sacrificial layer 103) can be exposed within the gate space. Inner sidewalls can be formed on the sidewalls of the source / drain layer through the gate space. For example, an atomic layer deposition process can be used to form a dielectric layer within the gate space, and an anisotropic etching technique can be used to etch the dielectric layer, retaining the portion connected to the sidewalls of the source / drain layer as the inner sidewall 114.

[0060] In some embodiments, a dielectric layer can be deposited to substantially fill the released gate space, and the dielectric layer filling the gate space can be anisotropically etched to form an inner sidewall 114. In some other embodiments, multiple cycles of atomic layer deposition and anisotropic etching processes can be performed within the gate space to form the inner sidewall 114. Each atomic layer deposition process can deposit a thin layer, for example, in a substantially conformal manner. Due to this formation method, the inner sidewall 114 can have an inner sidewall recessed toward the source / drain layer 111 in a first direction. The thickness of the inner sidewall 114 in the first direction can be 2 nm to 8 nm, etc. The inner sidewall 114 can include a material with etch selectivity relative to the gate sidewall 110, including oxides such as silicon oxide or nitrides such as silicon nitride. According to embodiments of this application, the multi-cycle deposition and etching process can reduce structural defects that are prone to occur in a single deposition process, increase the deposition quality of the inner sidewall, and thereby improve the performance of the inner sidewall in controlling leakage current and parasitic capacitance.

[0061] In some embodiments, such as Figure 8C As shown, an etch protection layer 104A can be formed on the semiconductor layer 104 via the gate space to reduce damage to the semiconductor layer 104 caused by the etching process of the inner sidewall 114. The thickness of the etch protection layer 104A can be 4 angstroms to 10 angstroms, etc. The inner sidewall 114 can be a material with etching selectivity relative to the etch protection layer 104A. For example, an oxide etch protection layer 104A can be formed by thermal oxidation. In some embodiments, the etch protection layer can also be formed on the sidewall of the source / drain layer 111 ( Figure 8C (Not shown in the diagram). A dielectric layer may be formed after the etching protective layer 104A is formed, and the etching protective layer 104A may be removed after the inner sidewall 114 is formed. For ease of description, the following description will still take an embodiment without an etching protective layer as an example.

[0062] refer to Figure 9A and Figure 9B It can form a gate stack within the gate space.

[0063] A gate stack can be formed around the semiconductor layer 104 on the inner sidewall of the gate space. The gate stack may include a gate dielectric layer 115 and a gate conductor. The gate dielectric layer 115 may include a high-k dielectric material, where K represents the dielectric constant. The high-k dielectric material may include HfO2, HfSiOx, HfON, HfSiON, or HfAlO. x HfLaO x Al2O3, ZrO2, ZrSiO x It can be one or a combination of Ta2O5 or La2O3. The thickness of the gate dielectric layer 115 can be 8 angstroms to 20 angstroms. The gate conductor may include a work function layer 116 and a conductor layer 117.

[0064] Dielectric material can be deposited further on the third dielectric layer 113, and the deposited dielectric material, together with the previous third dielectric layer 113, can still be shown as the third dielectric layer 113. Various interconnect structures, such as contact plugs 118, can be fabricated in the third dielectric layer 113. Thus, as follows, Figure 2 The semiconductor device shown.

[0065] Return to reference Figure 2 , Figure 9A and Figure 9B The semiconductor device in this embodiment may include a substrate 101, a semiconductor layer 104, a source / drain layer 111, a gate stack, and an inner sidewall 114.

[0066] The substrate 101 can be a bulk semiconductor substrate or a semiconductor-on-insulator substrate. The bulk semiconductor substrate can include Si, and the semiconductor-on-insulator substrate can include silicon-on-insulator (SOI). A doped layer 102 can also be formed in the substrate 101 by ion implantation. The doped layer 102 can be GP doped to suppress leakage in the sub-Si.

[0067] Semiconductor layer 104 may be located on substrate 101. The number of semiconductor layers 104 can be arbitrary and is not limited herein. For example, there may be multiple semiconductor layers 104. Multiple semiconductor layers 104 may be stacked at intervals from each other in the vertical direction. For example, multiple semiconductor layers 104 may be nanosheets extending along a first direction and parallel to each other. The first direction corresponds to... Figure 2 and Figure 9A In the Y-Y' axis, the second direction corresponds to Figure 2 and Figure 9B In the X-X' axis, the second direction may intersect (e.g., be perpendicular to) the first direction. The semiconductor layer 104 may be undoped or lightly doped. The doping type of the semiconductor layer 104 can be set according to the type of semiconductor device, and may be opposite to the conductivity type of the semiconductor device; for example, it may be N-type doped for a P-type device or P-type doped for an N-type device.

[0068] Source / drain layers 111 may be located on opposite sides of the plurality of semiconductor layers 104 in a first direction. A gate stack at least partially surrounds the outer periphery of the plurality of semiconductor layers 104 in a second direction. The gate stack may include a gate dielectric layer 115 and a gate conductor. The gate dielectric layer 115 may include a high-k dielectric material, where K represents the dielectric constant. High-k dielectric materials include HfO2 and HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO xThe work function layer 116 may be a combination of one or more of Ta₂O₅ or La₂O₃. The gate conductor may include a work function layer 116 located on the gate dielectric layer 115 and a conductor layer 117 on the work function layer 116. The work function layer 116 may include a work function material compatible with the semiconductor device. For example, in the case of an N-type field-effect transistor in this embodiment, the work function layer 116 may be an N-type work function layer; in the case of a P-type field-effect transistor in this embodiment, the work function layer 116 may be a P-type work function layer. The work function material may include titanium nitride, etc. The conductor layer 117 may include a metal such as tungsten, etc.

[0069] The inner sidewall 114 may be located between the source / drain layer 111 and the gate stack. The inner sidewall 114 may comprise an oxide such as silicon oxide, or a nitride such as silicon nitride. The portion of the source / drain layer 111 on the sidewall of the semiconductor layer 104 has a continuous crystal structure with the portion on the inner sidewall 114. The inner sidewall 114 can form physical isolation between the gate stack and the source / drain layer 111, reducing parasitic capacitance between the gate and source, and between the gate and drain, thereby improving the switching speed of the device and reducing dynamic power consumption.

[0070] In some embodiments, the inner wall may also have an inner wall recessed toward the source / drain layer in a first direction.

[0071] In some embodiments, the semiconductor device in this embodiment may further include a third dielectric layer 113 and a contact plug 118 that penetrates the third dielectric layer and electrically connects the source / drain layer 111 and the gate stack.

[0072] According to the embodiments of this application, the inner sidewall post-processing in the above manufacturing method avoids the technical difficulties of etching before and after inner sidewall deposition, the impact of etching on the crystal quality of the source / drain layer, and the difficulty of epitaxy of the source / drain layer. It at least partially solves the limitations of existing manufacturing processes, increases the applicable scenarios of inner sidewall technology, and thus reduces the parasitic capacitance between the gate and the source / drain layer in the manufactured semiconductor device, optimizes the response characteristics of the device, and improves the AC performance of the device. In addition, the inner sidewall also avoids direct contact between the gate and the source / drain layer, thereby reducing leakage current, enhancing the gate's control over the channel, and reducing process deviation by controlling the channel length.

[0073] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application. Embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Those skilled in the art can make various substitutions and modifications without departing from the scope of this application, and these substitutions and modifications should all fall within the scope of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A stack is formed on a substrate, the stack comprising alternating sacrificial layers and semiconductor layers; The stack is patterned to form fins extending along a first direction; A sacrificial gate is formed on the stack, extending along a second direction intersecting the first direction and thus intersecting the fin; Source / drain layers are formed on opposite sides of the sacrificial gate in the first direction, and the source / drain layers are respectively connected to the sacrificial layer and the semiconductor layer in the fin; Remove the sacrificial gate and selectively etch the sacrificial layer in the stack to free up gate space; An inner sidewall is formed on the sidewall of the source / drain layer through the gate space; A gate stack is formed within the gate space.

2. The manufacturing method according to claim 1, characterized in that, The process of forming an inner sidewall on the sidewall of the source / drain layer through the gate space includes: A dielectric layer is formed within the gate space using atomic layer deposition (ALD) technology. The dielectric layer is etched using anisotropic etching technology to retain the portion that is in contact with the sidewall of the source / drain layer as the inner sidewall.

3. The manufacturing method according to claim 2, characterized in that, The manufacturing method further includes: The inner sidewall is formed by performing multiple cycles of the atomic layer deposition process and the anisotropic etching process within the gate space.

4. The manufacturing method according to any one of claims 1 to 3, characterized in that, The manufacturing method further includes: A gate sidewall is formed on the sidewall of the sacrificial gate, and the inner sidewall has a different etching selectivity relative to the gate sidewall.

5. The manufacturing method according to claim 4, characterized in that, The manufacturing method further includes: Using the sacrificial gate and the gate sidewall as a mask, the fin is patterned so that the sacrificial layer and the semiconductor layer in the patterned fin each have a side surface exposed in the first direction. The source / drain layer is epitaxially grown on the side surfaces exposed in the first direction of the sacrificial layer and the semiconductor layer.

6. The manufacturing method according to claim 5, characterized in that, The manufacturing method further includes: A capping layer is formed on the side surfaces of the sacrificial layer and the semiconductor layer exposed in the first direction, wherein the source / drain layer is epitaxially grown after the capping layer is formed.

7. The manufacturing method according to claim 2, characterized in that, The manufacturing method further includes: An etching protection layer is formed on the semiconductor layer via the gate space, wherein the dielectric layer is formed after the etching protection layer is formed; After the inner sidewall is formed, the etched protective layer is removed.

8. The manufacturing method according to claim 1, characterized in that, The manufacturing method further includes: The substrate is doped to form a doped layer, and the stack is formed on the doped layer.

9. A semiconductor device, characterized in that, include: Substrate; Multiple semiconductor layers are stacked on the substrate at vertical intervals; Source / drain layers located on opposite sides of the plurality of semiconductor layers in a first direction; A gate stack that at least partially surrounds the outer periphery of the plurality of semiconductor layers in a second direction, the second direction intersecting the first direction; as well as The inner wall between the source / drain layer and the gate stack, The source / drain layer has a continuous crystal structure in the portion on the sidewall of the semiconductor layer and the portion on the inner sidewall.

10. The semiconductor device according to claim 9, characterized in that, The inner wall has an inner wall that is recessed toward the source / drain layer in the first direction.

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