Deep trench field effect transistor with double-gate structure and method of manufacturing the same

Abstract

The application provides a deep trench field effect transistor with upper and lower gate structures and a preparation method thereof. The deep trench field effect transistor is provided with a lower gate conductive part in the trench of the deep trench, the lower part and the side part of the lower gate conductive part are separated from the semiconductor layer by a relatively thick insulating layer, the upper end of the lower gate conductive part is lower than the first surface of the semiconductor layer, an upper gate conductive part surrounding the upper part of the lower gate conductive part is formed at the upper part of the trench, and the upper gate conductive part is insulated from the semiconductor layer and the lower gate conductive part by a relatively thin gate medium layer. The first surface side of the semiconductor layer is formed with a body region and a source region, and a source contact structure, a gate contact structure, a source metal and a gate metal are arranged. By arranging the upper gate and the lower gate in the depth direction of the same trench, the channel control, the drift region electric field modulation, and the on-resistance and voltage resistance performance can be considered while the compact unit size is maintained.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device design and manufacturing technology, and specifically relates to a deep trench field-effect transistor with a double gate structure and its fabrication method. Background Technology

[0002] Power transistors are used to control the operation of power electronic devices and provide power output to loads, and are widely used in various power control and high-frequency high-power circuits. As the performance requirements of power electronic systems increase, power semiconductor field-effect transistors typically need to operate under high voltage and high current conditions.

[0003] Power devices typically operate under high voltage and high current conditions, generally characterized by high withstand voltage, large operating current, and high self-dissipation power. Therefore, their usage differs somewhat from that of general low-power devices. To ensure the optimal functioning of switching devices, power semiconductor field-effect transistors (FETs) must meet two basic requirements: 1) When the device is in the on-state, it must possess very low on-resistance to minimize its own power loss; 2) When the device is in the off-state, it must possess sufficiently high reverse breakdown voltage.

[0004] Existing power transistors generally employ superjunction transistor structures. However, the fabrication process of superjunction transistors is complex. Due to the influence of processes such as annealing, the interdiffusion of ions within the superjunction can easily lead to a significant deviation between the actual doping concentration and the actual value. Furthermore, the breakdown voltage of superjunction transistors is highly sensitive to the ion doping concentration, thus greatly increasing the difficulty of fabrication, especially for devices with high doping concentration and low junction width. Moreover, superjunction power transistors are generally used in high-voltage or medium-high-voltage circuits. Because the width of superjunction power transistors is limited, it is difficult to implement conventional superjunction power transistors for circuits with voltages less than 180V.

[0005] Furthermore, as the size of semiconductor device units continues to shrink, the available space between deep trench electrodes becomes increasingly limited. Trench devices with side oxide structures face higher process complexity in terms of the formation of gate and source contact structures, ultimately leading to increased device manufacturing difficulty and cost.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a deep trench field-effect transistor with a dual-gate structure and a method for fabricating the same. A lower gate conductive portion and an upper gate conductive portion located at the top of the trench are disposed along the depth direction within the same trench. The lower gate conductive portion is isolated from the lower semiconductor layer of the trench by a thicker first insulating layer, while the upper gate conductive portion is isolated from the upper semiconductor layer of the trench by a thinner gate dielectric layer, and is mutually insulated from the lower gate conductive portion by the gate dielectric layer. This allows for the partitioning of the channel control region and the deep trench region within the same deep trench.

[0008] To achieve the above and other related objectives, the present invention provides a method for fabricating a deep trench field-effect transistor with a dual-gate structure. The method includes: providing a semiconductor substrate, the semiconductor substrate including a semiconductor layer located on a first surface side; forming a trench from the first surface into the semiconductor layer; forming an insulating layer at the bottom and sidewalls of the trench, and forming a first conductive material within the trench, and etching back to make the upper end of the first conductive material lower than the first surface to form a lower gate conductive portion and a top gate receiving region formed on the lower gate conductive portion, the lower gate conductive portion being insulated from the semiconductor layer through the insulating layer; removing the insulating layers on both sides of the upper portion of the lower gate conductive portion to form a side gate receiving region, and forming a top gate receiving region on the side gate receiving region. A gate dielectric layer is formed on the exposed lower gate conductive portion and the surface of the semiconductor layer; a second conductive material is deposited and etched back to the first surface to form a top gate conductive portion and a side gate conductive portion in the top gate receiving region and the side gate receiving region, respectively. The top gate conductive portion and the side gate conductive portion form an upper gate conductive portion. The upper gate conductive portion is insulated from the semiconductor layer and the lower gate conductive portion through the gate dielectric layer; a body region and a source region located in the body region are formed on the first surface side; an interlayer dielectric layer, a source contact structure, a gate contact structure, a source metal, and a gate metal are formed. The source metal is electrically connected to the source region and the body region through the source contact structure, and the gate metal is electrically connected to the upper gate conductive portion and the lower gate conductive portion through the gate contact structure.

[0009] Optionally, the semiconductor layer is an epitaxial layer with a thickness of 1 μm to 10 μm and a resistivity of 0.1 Ω·cm to 1 Ω·cm; the trench has a depth of 1.2 μm to 6 μm and a width of 0.2 μm to 2 μm.

[0010] Optionally, the thickness of the insulating layer is 0.1 μm to 1 μm, and after the lower gate conductive portion is etched back onto the first conductive material, its upper end is located 0.05 μm to 0.3 μm below the first surface. The first conductive material includes doped polycrystalline silicon.

[0011] Optionally, the gate dielectric layer is formed by a thermal oxidation process, and the thickness of the gate dielectric layer is 200 Å to 1200 Å.

[0012] Optionally, the bottom ends of the side gate conductive portions are all located above the bottom end of the upper gate conductive portion, such that the depth of the lower gate conductive portion extending into the semiconductor layer is greater than the depth of the two side gate conductive portions extending into the semiconductor layer.

[0013] Optionally, forming the body region includes implanting boron from the first surface at a dose of 5 × 10⁻⁶. 12 cm -2 ~2×10 13 cm -2 The injected energy is 60keV to 200keV, and the heat treatment is carried out at 950℃ to 1200℃ for 30 seconds to 30 minutes, so that the body region extends to the channel control region corresponding to the side gate conductive part.

[0014] Optionally, the deep trench field-effect transistor includes a source contact region and a gate contact region, and arsenic is implanted only in the source contact region on the first surface side to form the source region, wherein the arsenic implantation dose is 1×10⁻⁶. 15 cm -2 ~1×10 16 cm -2 The injected energy is 60keV to 120keV, and the heat treatment is carried out at 950℃ to 1000℃ for 30 seconds to 30 minutes; the gate contact area does not form the source region.

[0015] Optionally, the thickness of the interlayer dielectric layer is 0.4 μm to 2 μm; a source contact structure is formed in the source contact region, passing through the interlayer dielectric layer and extending at least to the body region, the source contact structure connecting both the source region and the body region; a gate contact structure is disposed in the gate contact region and contacts the upper gate conductive portion, and the gate contact structure extends downward to the lower gate conductive portion, so that the gate metal connects the upper gate conductive portion and the lower gate conductive portion to the same gate potential through the gate contact structure; a metal layer with a thickness of 0.5 μm to 4 μm is deposited on the interlayer dielectric layer and the source metal and gate metal are patterned to form the source metal and gate metal.

[0016] Optionally, the gate metal is connected to the upper gate conductive portion and the lower gate conductive portion along the trench width direction, and the source metal is connected to the source region and the body region along the trench width direction; the source metal and the gate metal extend along the trench width direction and are spaced apart from each other, so that the source metal and the gate metal are mutually insulated on the device surface and are led out respectively.

[0017] The present invention also provides a deep trench field-effect transistor with a dual-gate structure, comprising: a semiconductor substrate having a semiconductor layer and a first surface; a trench extending from the first surface into the semiconductor layer; an insulating layer located at the bottom and sidewalls of the trench; a lower gate conductive portion located within the trench and extending along the depth direction of the trench, the lower portion of the lower gate conductive portion being insulated from the semiconductor layer through the insulating layer, the upper portion of the lower gate conductive portion being removed to form a top-side gate receiving region, and the insulating layers on both sides of the upper portion of the lower gate conductive portion being removed to form side-side gate receiving regions; and a gate dielectric layer formed on the substrate. The top-side gate accommodating region and the side-side gate accommodating region expose the lower gate conductive portion and the surface of the semiconductor layer; the upper gate conductive portion is located in the top-side gate accommodating region and the side-side gate accommodating region, and the upper gate conductive portion is insulated from the semiconductor layer and the lower gate conductive portion through the gate dielectric layer; the body region is located on the first surface side and adjacent to the upper part of the trench; the source region is located in the body region; the interlayer dielectric layer, the source contact structure, the gate contact structure, the source metal and the gate metal, the source metal being electrically connected to the source region and the body region through the source contact structure, and the gate metal being electrically connected to the upper gate conductive portion and the lower gate conductive portion.

[0018] Optionally, the bottom ends of the side gate conductive portions are all located above the bottom end of the upper gate conductive portion, such that the depth of the lower gate conductive portion extending into the semiconductor layer is greater than the depth of the two side gate conductive portions extending into the semiconductor layer; the insulating layer is located between the lower gate conductive portion and the lower sidewall and bottom of the trench, and the thickness of the insulating layer is greater than the thickness of the gate dielectric layer.

[0019] Optionally, the gate metal is electrically connected to both the upper gate conductive portion and the lower gate conductive portion through a gate contact structure, so that the upper gate conductive portion and the lower gate conductive portion are at the same gate potential; wherein, the upper gate conductive portion forms a channel control gate, and the lower gate conductive portion forms a field modulation conductive portion extending to the drift region through the insulating layer.

[0020] Optionally, the source contact structure is located between adjacent trenches and extends from the first surface toward the body region, the source contact structure extends through the source region into the body region, so that the source metal is electrically connected to both the source region and the body region simultaneously.

[0021] Optionally, the source metal and the gate metal extend along the width direction of the trench and are spaced apart from each other, so that the source metal and the gate metal are insulated from each other on the device surface and are led out respectively.

[0022] Optionally, the semiconductor layer and the source region are N-type, and the body region is P-type; the thickness of the semiconductor layer is 1 μm to 10 μm, and the resistivity is 0.1 Ω·cm to 1 Ω·cm; the thickness of the top gate conductive portion is 0.05 μm to 0.3 μm; the depth of the trench is 1.2 μm to 6 μm, and the width is 0.2 μm to 2 μm; the thickness of the insulating layer is 0.1 μm to 1 μm; the thickness of the gate dielectric layer is 200 Å to 1200 Å; the thickness of the interlayer dielectric layer is 0.4 μm to 2 μm; and the thickness of the source metal and the gate metal is 0.5 μm to 4 μm.

[0023] As described above, the deep trench field-effect transistor with a dual-gate structure and its fabrication method of the present invention have the following beneficial effects:

[0024] This invention forms an upper gate conductive portion and a lower gate conductive portion along the depth direction within the same trench. The upper gate conductive portion is located at the top of the trench, and the lower gate conductive portion extends into the depth of the trench. This utilizes the same trench space to form a composite gate structure with upper and lower partitions, which is beneficial for achieving channel control and deep trench electric field regulation within a relatively compact unit size. When conducting, the lower gate conductive portion can promote carrier accumulation in its adjacent drift region through capacitive coupling. When turning off, the lower gate conductive portion and the thicker insulating layer can change the equipotential line and depletion region distribution in the lower part of the trench, reducing the local electric field peak and improving the breakdown voltage.

[0025] The present invention employs a thinner gate dielectric layer in the upper part of the trench to ensure channel control capability, and a thicker insulating layer in the lower part of the trench to reduce deep gate coupling and bear electric field modulation. Different insulating layer thicknesses can be configured in different depth regions to structurally balance the upper gate control capability and the lower withstand voltage requirements.

[0026] In this invention, the first conductive material is etched back to 0.05μm to 0.3μm below the wafer surface before forming the upper gate conductive portion. This allows for the construction of a two-stage gate structure in the same trench without increasing the number of trenches. The gate contact area and the source contact area are arranged separately along the trench extension direction, which is beneficial for the gate and source to be led out separately.

[0027] The source contact structure of this invention simultaneously contacts the source region and the body region, which can reliably short-circuit the body region and the source region, helping to suppress parasitic bipolar transistor triggering and improve the stability of the device under high current and avalanche operating conditions. Attached Figure Description

[0028] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0029] Figure 1 The diagram shows the surface layout of a deep trench field-effect transistor with a dual-gate structure in this embodiment.

[0030] Figures 2-13 The diagram shown is a cross-sectional view of a deep trench field-effect transistor with a dual-gate structure as described in this embodiment. Figures 2-13 Include Figure 1 Schematic diagrams of the cross-sectional structure at A-A' and at B-B'.

[0031] Component designation explanation

[0032] 102 trench 103 Insulation layer 104 Lower gate conductive part 105 Side gate storage area 106 Side gate conductive part 107 Body area 108 Source region 109 Interlayer dielectric layer 110 Source contact structure 111 Gate contact structure 112 Source Metal 113 gate metal 114 Gate dielectric layer 115 Top grid storage area 116 Top gate conductive part Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0035] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0036] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0037] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0038] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0039] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0040] For conventional deep trench gate devices, if a thin gate oxide layer is used for most of the trench sidewall depth, the gate electrode is prone to large capacitive coupling with the drift region. At the same time, the electric field distribution at the bottom of the trench and the lower part of the sidewall is not easy to adjust independently. If the coupling is reduced by adding a thick oxide structure, the effective gate control area at the top of the trench will be compressed.

[0041] like Figures 1-13 As shown, where, Figure 1 The diagram shows the surface layout of a deep trench field-effect transistor with a dual-gate structure in this embodiment. Figures 2-13 All include Figure 1 The cross-sectional structural diagrams at A-A' and B-B' illustrate a method for fabricating a deep trench field-effect transistor with a dual-gate structure. The method includes the following steps:

[0042] like Figure 2 As shown, step 1) is performed first to provide a semiconductor substrate, the semiconductor substrate including a semiconductor layer 101 located on the first surface side;

[0043] In this embodiment, the semiconductor layer 101 can be an N-type epitaxial layer formed on an N-type semiconductor substrate, and the semiconductor substrate can have a higher doping concentration than the epitaxial layer.

[0044] Specifically, a first conductivity type semiconductor layer 101 can be formed on a semiconductor substrate. Preferably, the first conductivity type semiconductor layer 101 can be formed by epitaxial growth, and its thickness is 1 μm to 10 μm, with a resistivity of 0.1 Ω·cm to 1 Ω·cm. This semiconductor layer 101 can serve as the main drift region of the device.

[0045] like Figure 3 As shown, then step 2) is performed to form a trench 102 from the first surface into the interior of the semiconductor layer 101.

[0046] In some embodiments, such as Figure 3As shown, step 2) may include: forming a patterned mask on the surface of the first conductivity type semiconductor layer 101, and forming a plurality of trenches 102 by dry etching or a combination of dry and wet etching. The trenches 102 extend from the first surface into the interior of the semiconductor layer 101, preferably with a depth of 1.2 μm to 6 μm and a width of 0.2 μm to 2 μm. In some embodiments, the plurality of trenches 102 may extend parallel to each other to form periodic strip units.

[0047] like Figures 4-5 As shown, then step 3) is performed, an insulating layer 103 is formed at the bottom and sidewalls of the trench 102, and a first conductive material is formed in the trench 102. The material is then etched back so that the upper end of the first conductive material is lower than the first surface to form a lower gate conductive portion 104. A top gate receiving area 115 is formed on the lower gate conductive portion 104. The lower gate conductive portion 104 is insulated from the semiconductor layer 101 through the insulating layer 103.

[0048] In some embodiments, after the first conductive material is etched back, its upper end is located 0.05 μm to 0.3 μm below the first surface, and the first conductive material includes doped polycrystalline silicon.

[0049] like Figure 4 As shown, an insulating layer 103 is formed on the sidewalls and bottom of the trench 102. The insulating layer 103 may include silicon oxide and may be formed by thermal oxidation, chemical vapor deposition, or a combination of both. The thickness of the insulating layer 103 is preferably 0.1 μm to 1 μm, which is significantly greater than the subsequently formed gate dielectric layer 114, in order to achieve electric field modulation and capacitance control in the depth of the trench 102.

[0050] like Figure 5 As shown, after forming the insulating layer 103, a first conductive material is deposited, filling the space enclosed by the insulating layer 103 in the trench 102. Subsequently, the first conductive material above the surface of the semiconductor layer 101 is removed by an etch-back process. Then, a portion of the first conductive material in the trench is further etched away, causing the upper end of the first conductive material to be lower than the first surface, forming a lower gate conductive portion 104, and a top gate receiving region 115 is formed on the lower gate conductive portion 104. The first conductive material is preferably in-situ doped or post-doped polysilicon. The lower gate conductive portion 104 extends along the depth direction of the trench 102 to the lower part of the trench 102, and its bottom and lower sidewalls are isolated from the semiconductor layer 101 by the insulating layer 103.

[0051] like Figures 6-7 As shown, in step 4), the insulating layers 103 on both sides of the upper part of the lower gate conductive portion 104 are removed to form a side gate receiving region 105, and a gate dielectric layer 114 is formed on the surface of the lower gate conductive portion 104 exposed in the side gate receiving region 105 and the semiconductor layer 101.

[0052] like Figures 6-7 As shown, the insulating layer 103 located on the upper part of the trench 102, near the opposite sidewalls of the trench 102, is selectively removed or etched back to expose the lower gate conductive portion 104 and the semiconductor layer 101 on the upper part of the trench 102, thereby forming side gate receiving regions 105 on the left and right sides of the lower gate conductive portion 104, respectively. Subsequently, a gate dielectric layer 114 is grown or deposited on the exposed side semiconductor layers 101 and the lower gate conductive portion 104, the thickness of the gate dielectric layer 114 being 200 Å to 1200 Å.

[0053] like Figure 8 As shown, step 5) is then performed to deposit a second conductive material and etch it back to the first surface to form a top gate conductive portion 116 and a side gate conductive portion 106 in the top gate receiving region 115 and the side gate receiving region 105, respectively. The top gate conductive portion 116 and the side gate conductive portion 106 form an upper gate conductive portion, which is insulated from the semiconductor layer 101 and the lower gate conductive portion 104 through the gate dielectric layer 114.

[0054] like Figure 8 As shown, a second conductive material is deposited on the device surface to fill the two side gate receptacle regions 105 located on the left and right sides of the top gate receptacle region 115 and the lower gate conductive portion 104. The second conductive material is then etched back or planarized onto the surface of the wafer semiconductor layer 101 to form a top gate conductive portion 116 and a side gate conductive portion 106 in the top gate receptacle region 115 and the side gate receptacle region 105, respectively. The side gate conductive portions 106 face the opposite sidewalls of the trench 102 across the gate dielectric layer 114, and the bottom ends of the side gate conductive portions 106 are all located above the bottom ends of the lower gate conductive portions 104, such that the depth of the lower gate conductive portion 104 extending into the semiconductor layer 101 is greater than the depth of the two side gate conductive portions 106 extending into the semiconductor layer 101. The second conductive material can be, for example, doped polysilicon.

[0055] like Figure 9 As shown, step 6) is performed to form a body region 107 and a source region 108 located in the body region 107 on the first surface side.

[0056] like Figure 9 As shown, step 6-1) is performed to implant boron ions from the first surface of the device, with an implantation dose of 5 × 10⁻⁶. 12 cm -2 ~2×10 13 cm -2The injection energy is 60keV to 200keV, and thermal diffusion is performed at 950°C to 1200°C for 30 seconds to 30 minutes to transform the N-type semiconductor layer 101 on the first surface side into a P-type body region 107. The body region 107 extends along the upper sidewall of the trench 102, and its junction with the lower N-type drift region is preferably located within the effective gate control depth range of the two side gate conductive portions 106, that is, the bottom end of the side gate receiving region 105 extends below the bottom of the body region.

[0057] like Figure 10 As shown, in step 6-2), arsenic ion implantation is performed in the source contact region, i.e., the region corresponding to section A-A' in the figure, using a mask to form an N-type source region 108. The arsenic implantation dose is 1 × 10⁻⁶. 15 cm -2 ~1×10 16 cm -2 The injected energy is 60keV to 120keV, and the heat treatment is carried out at 950℃ to 1000℃ for 30 seconds to 30 minutes. The gate contact area, that is, the area corresponding to the cross section B-B' shown in the figure, can be blocked by a mask to prevent the formation of the N-type source region 108.

[0058] like Figures 11-13 As shown, step 7 is performed last to form an interlayer dielectric layer 109, a source contact structure 110, a gate contact structure 111, a source metal 112, and a gate metal 113. The source metal 112 is electrically connected to the source region 108 and the body region 107 through the source contact structure 110, and the gate metal 113 is electrically connected to the upper gate conductive portion and the lower gate conductive portion 104 through the gate contact structure.

[0059] like Figure 11 As shown, in step 7-1), an interlayer dielectric layer 109 is deposited on the first surface of the device. The interlayer dielectric layer 109 may include silicon oxide, borosilicate glass, phosphosilicate glass, silicon nitride, or a stack thereof, and its thickness is preferably 0.4 μm to 2 μm. The interlayer dielectric layer 109 is used to isolate the subsequent metal from the unselected semiconductor and polysilicon regions.

[0060] like Figure 12As shown, in step 7-2), the interlayer dielectric layer 109 is etched in the source contact region and further etched into the body region 107 to form the source contact structure 110. The source contact structure 110 can pass through the source region 108 and simultaneously expose the source region 108 and the body region 107. In the gate contact region, at least one gate contact structure 111 is formed for each trench. The gate contact structure is disposed in the gate contact region and contacts the upper gate conductive portion, and the gate contact structure extends downward to the lower gate conductive portion 104, so that the gate metal connects the upper gate conductive portion and the lower gate conductive portion 104 to the same gate potential through the gate contact structure. The gate contact structure only needs to pass through a thin top gate conductive portion and gate dielectric layer to realize the lead-out of the upper gate conductive portion and the lower gate conductive portion 104, which greatly reduces the depth and width of the gate contact structure, thereby greatly reducing the process difficulty and manufacturing cost. Therefore, the two side gate conductive portions 106 are connected together through the top gate conductive portion 116. The gate contact structure does not need to form additional contact structures on both sides. The entire upper gate conductive portion can be electrically led out through the top gate conductive portion 116.

[0061] In one embodiment, the gate metal 113 is connected to the upper gate conductive portion and the lower gate conductive portion along the trench width direction, and the source metal 112 is connected to the source region 108 and the body region 107 along the trench width direction; the source metal 112 and the gate metal 113 extend along the trench width direction and are spaced apart from each other, so that the source metal 112 and the gate metal 113 are insulated from each other on the device surface and are led out respectively.

[0062] like Figure 13 As shown, in step 7-3), a metal layer is deposited on the device surface and within each contact hole. The thickness of the metal layer is preferably 0.5 μm to 4 μm. A source metal 112 and a gate metal 113, which are mutually insulated, are formed through photolithography and etching. The source metal 112 contacts both the N-type source region 108 and the P-type body region 107 via the source contact structure 110. The gate metal 113 connects the upper gate conductive portion and the lower gate conductive portion 104 in the gate contact region through the gate contact structure 111. When a complete vertical power device needs to be formed, a drain metal can be further formed on the back side of the semiconductor substrate for electrical connection with the semiconductor substrate.

[0063] like Figure 13As shown, this embodiment also provides a deep trench field-effect transistor with a dual-gate structure, comprising: a semiconductor substrate having a semiconductor layer 101 and a first surface; a trench 102 extending from the first surface into the semiconductor layer 101; an insulating layer 103 located at the bottom and sidewalls of the trench 102; a lower gate conductive portion 104 located within the trench 102 and extending along the depth direction of the trench 102, the lower portion of the lower gate conductive portion 104 being insulated from the semiconductor layer 101 by the insulating layer 103, the upper portion of the lower gate conductive portion 104 being removed to form a top-side gate receiving region 105, and the insulating layers 103 on both sides of the upper portion of the lower gate conductive portion 104 being removed to form side gate receiving regions 105; and a gate dielectric layer 114 formed on the top-side gate receiving region. The lower gate conductive portion 104 and the surface of the semiconductor layer 101 are exposed in the nano-region 105 and the side gate receiving region 105; the upper gate conductive portion is located in the top side gate receiving region 105 and the side gate receiving region 105, and the upper gate conductive portion is insulated from the semiconductor layer 101 and the lower gate conductive portion 104 through the gate dielectric layer 114; the body region 107 is located on the first surface side and adjacent to the upper part of the trench 102; the source region 108 is located in the body region 107; the interlayer dielectric layer 109, the source contact structure 110, the gate contact structure 111, the source metal 112 and the gate metal 113, the source metal 112 is electrically connected to the source region 108 and the body region 107 through the source contact structure 110, and the gate metal 112 is electrically connected to the upper gate conductive portion and the lower gate conductive portion 104.

[0064] In one embodiment, the bottom ends of the side gate conductive portions 106 are all located above the bottom end of the upper gate conductive portion, such that the depth of the lower gate conductive portion 104 extending into the semiconductor layer 101 is greater than the depth of the two side gate conductive portions 106 extending into the semiconductor layer 101; the insulating layer 103 is located between the lower gate conductive portion 104 and the lower sidewall and bottom of the trench 102, and the thickness of the insulating layer 103 is greater than the thickness of the gate dielectric layer 114.

[0065] When the device is turned on, the upper gate conductive portion 106 controls the surface potential of the adjacent body region 107 above the trench 102 through the gate dielectric layer 114, thereby forming a gate-controlled conductive channel between the source region 108 and the semiconductor layer 101; the lower gate conductive portion 104 extends to a deeper position in the trench 102, and can affect the potential distribution in the deep part of the trench 102 through the insulating coupling between it and the semiconductor layer 101.

[0066] When the device is turned off and withstands the drain voltage, the lower gate conductive portion 104 in the depth of the trench 102 and the thicker insulating layer 103 together form an electric field conditioning structure that is different from the upper thin gate dielectric region. This allows the electric field distribution in the depth of the trench 102 to have a geometric adjustment space independent of the upper channel gate region, which is beneficial to take into account the turn-off withstand voltage requirements of the device.

[0067] In one embodiment, the gate metal is electrically connected to both the upper gate conductive portion and the lower gate conductive portion 104 through a gate contact structure, so that the upper gate conductive portion and the lower gate conductive portion 104 are at the same gate potential; wherein, the upper gate conductive portion forms a channel control gate, and the lower gate conductive portion 104 forms a field modulation conductive portion extending to the drift region through the insulating layer 103.

[0068] In one embodiment, the source contact structure 110 is located between adjacent trenches 102 and extends from the first surface toward the body region. The source contact structure 110 extends through the source region 108 into the body region 107, so that the source metal 112 is electrically connected to both the source region 108 and the body region 107.

[0069] In one embodiment, the source metal 112 and the gate metal 113 extend along the width direction of the trench 102 and are spaced apart from each other, so that the source metal 112 and the gate metal 113 are insulated from each other on the device surface and are led out respectively.

[0070] In one embodiment, the semiconductor layer 101 and the source region 108 are N-type, and the body region 107 is P-type; the semiconductor layer 101 has a thickness of 1 μm to 10 μm and a resistivity of 0.1 Ω·cm to 1 Ω·cm; the top gate conductive portion 116 has a thickness of 0.05 μm to 0.3 μm; the trench 102 has a depth of 1.2 μm to 6 μm and a width of 0.2 μm to 2 μm; the insulating layer 103 has a thickness of 0.1 μm to 1 μm; the gate dielectric layer 114 has a thickness of 200 Å to 1200 Å; the interlayer dielectric layer 109 has a thickness of 0.4 μm to 2 μm; and the source metal 112 and the gate metal 113 have a thickness of 0.5 μm to 4 μm.

[0071] The working principle of the deep trench field-effect transistor with a dual-gate structure in this embodiment is as follows:

[0072] 1) On-state. When a driving voltage higher than the threshold voltage is applied to the gate electrode relative to the source electrode, the upper gate conductive portion modulates the surface potential of its adjacent P-type body region 107 through the gate dielectric layer 114, forming an inversion channel on the left and right sidewalls of the trench, leading from the N-type source region 108 to the lower N-type semiconductor layer 101. The two sidewall channels are connected in parallel, allowing electrons to enter the drift region from the source region 108 through the left and right channels respectively, and then flow longitudinally to the drain terminal corresponding to the semiconductor substrate. Therefore, a larger equivalent channel width can be obtained and the on-resistance of the channel portion can be reduced under the same cell pitch.

[0073] 2) Drift Region Resistance Modulation. In the preferred common-gate connection, the lower gate conductor 104 and the upper gate conductor are at the same gate potential. The lower gate conductor 104 extends into the depth of the trench through a thicker insulating layer 103. Its positive gate bias can cause majority carrier accumulation in the adjacent N-type drift region, increasing the electron concentration near the trench and further reducing the equivalent resistance of the drift region. Since the insulating layer 103 is significantly thicker than the gate dielectric layer 114, the capacitive coupling of the lower gate conductor 104 to the drift region is weaker than the coupling of the upper gate conductor to the channel. Therefore, deep field modulation can be provided while avoiding the extension of the thin gate dielectric to the entire deep trench.

[0074] 3) Turn-off and withstand voltage states. When the gate electrode voltage drops to a level that cannot maintain the inversion channel, the channels on both sides of the upper gate conductor are closed, cutting off the electron path between the source and drain. When the drain voltage increases, the PN junction between the P-type body region 107 and the N-type drift region is reverse biased, and the depletion region extends into the drift region. The lower gate conductor 104 and its surrounding thicker insulating layer 103 alter the equipotential distribution at the bottom of the trench, preventing the electric field from concentrating at the bottom of a single trench or in the thin gate oxide region. Instead, the electric field is distributed more evenly along the trench depth and between adjacent cells, thereby helping to reduce the peak electric field and increase the reverse breakdown voltage.

[0075] 4) Gate charge and switching characteristics. The left and right side gate conductive portions 106 are located only in the channel control region at the top of the trench, while a thicker insulating layer 103 is used between the lower gate conductive portion 104 and the drift region. Compared with a structure that extends a thin gate oxide layer and the same gate electrode into the depth of the trench, this partitioned structure can reduce the impact of deep capacitive coupling on the gate drive and allows channel control and breakdown voltage modulation to be handled by different geometric regions. In common-gate connection, only one gate drive terminal is needed to synchronously control the left and right side gates and the lower gate conductive portion 104.

[0076] 5) Source-body short-circuit and reverse operation. The source contact structure 110 simultaneously contacts the N-type source region 108 and the P-type body region 107, keeping the P-type body region 107 at the source potential. This structure reduces the likelihood of parasitic bipolar transistors being triggered and provides a lower impedance lead path for the body region 107 for reverse conduction of the body diode and avalanche current, thereby improving the stability of the device during power switching.

[0077] As described above, the deep trench field-effect transistor with a dual-gate structure and its fabrication method of the present invention have the following beneficial effects:

[0078] This invention forms an upper gate conductive portion and a lower gate conductive portion along the depth direction within the same trench. The upper gate conductive portion is located at the top of the trench, and the lower gate conductive portion extends into the depth of the trench. This utilizes the same trench space to form a composite gate structure with upper and lower partitions, which is beneficial for achieving channel control and deep trench electric field regulation within a relatively compact unit size. When conducting, the lower gate conductive portion can promote carrier accumulation in its adjacent drift region through capacitive coupling. When turning off, the lower gate conductive portion and the thicker insulating layer can change the equipotential line and depletion region distribution in the lower part of the trench, reducing the local electric field peak and improving the breakdown voltage.

[0079] The present invention employs a thinner gate dielectric layer in the upper part of the trench to ensure channel control capability, and a thicker insulating layer in the lower part of the trench to reduce deep gate coupling and bear electric field modulation. Different insulating layer thicknesses can be configured in different depth regions to structurally balance the upper gate control capability and the lower withstand voltage requirements.

[0080] In this invention, the first conductive material is etched back to 0.05μm to 0.3μm below the wafer surface before forming the upper gate conductive portion. This allows for the construction of a two-stage gate structure in the same trench without increasing the number of trenches. The gate contact area and the source contact area are arranged separately along the trench extension direction, which is beneficial for the gate and source to be led out separately.

[0081] The source contact structure of this invention simultaneously contacts the source region and the body region, which can reliably short-circuit the body region and the source region, helping to suppress parasitic bipolar transistor triggering and improve the stability of the device under high current and avalanche operating conditions.

[0082] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a deep trench field-effect transistor with a dual-gate structure, characterized in that, The preparation method includes: A semiconductor substrate is provided, the semiconductor substrate including a semiconductor layer located on a first surface side; A trench is formed from the first surface into the interior of the semiconductor layer; An insulating layer is formed at the bottom and sidewalls of the trench, and a first conductive material is formed in the trench. The material is then etched back so that the upper end of the first conductive material is lower than the first surface to form a lower gate conductive portion and a top gate receiving area is formed on the lower gate conductive portion. The lower gate conductive portion is insulated from the semiconductor layer through the insulating layer. The insulating layers on both sides of the upper part of the lower gate conductive portion are removed to form a side gate receiving region, and a gate dielectric layer is formed on the exposed lower gate conductive portion and the surface of the semiconductor layer in the side gate receiving region. A second conductive material is deposited and etched back onto the first surface to form a top gate conductive portion and a side gate conductive portion in the top gate receiving region and the side gate receiving region, respectively. The top gate conductive portion and the side gate conductive portion form an upper gate conductive portion. The upper gate conductive portion is insulated from the semiconductor layer and the lower gate conductive portion through a gate dielectric layer. A body region and a source region located in the body region are formed on the first surface side; An interlayer dielectric layer, a source contact structure, a gate contact structure, a source metal, and a gate metal are formed. The source metal is electrically connected to the source region and the body region through the source contact structure, and the gate metal is electrically connected to the upper gate conductive portion and the lower gate conductive portion through the gate contact structure.

2. The method for fabricating a deep trench field-effect transistor with a dual-gate structure according to claim 1, characterized in that: The semiconductor layer is an epitaxial layer with a thickness of 1 μm to 10 μm and a resistivity of 0.1 Ω·cm to 1 Ω·cm; the trench has a depth of 1.2 μm to 6 μm and a width of 0.2 μm to 2 μm.

3. The method for fabricating a deep trench field-effect transistor with a dual-gate structure according to claim 1, characterized in that: The thickness of the insulating layer is 0.1 μm to 1 μm. After the lower gate conductive part is etched back onto the first conductive material, its upper end is located 0.05 μm to 0.3 μm below the first surface. The first conductive material includes doped polycrystalline silicon.

4. The method for fabricating a deep trench field-effect transistor with a dual-gate structure according to claim 1, characterized in that: The gate dielectric layer is formed by a thermal oxidation process, and the thickness of the gate dielectric layer is 200 Å to 1200 Å.

5. The method for fabricating a deep trench field-effect transistor with a dual-gate structure according to claim 1, characterized in that: The bottom ends of the lower gate conductive portion and the side gate conductive portions are all located above the bottom end of the upper gate conductive portion, so that the depth of the lower gate conductive portion extending into the semiconductor layer is greater than the depth of the two side gate conductive portions extending into the semiconductor layer.

6. The method for fabricating a deep trench field-effect transistor with a dual-gate structure according to claim 1, characterized in that: Forming the body region includes implanting boron from the first surface at a dose of 5 × 10⁻⁶. 12 cm -2 ~2×10 13 cm -2 The injected energy is 60keV to 200keV, and the heat treatment is carried out at 950℃ to 1200℃ for 30 seconds to 30 minutes, so that the body region extends to the channel control region corresponding to the side gate conductive part.

7. The method for fabricating a deep trench field-effect transistor with a dual-gate structure according to claim 1, characterized in that: The deep trench field-effect transistor includes a source contact region and a gate contact region. Arsenic is implanted only in the source contact region on the first surface side to form the source region, wherein the arsenic implantation dose is 1 × 10⁻⁶. 15 cm -2 ~1×10 16 cm -2 The injected energy is 60keV to 120keV, and the heat treatment is carried out at 950℃ to 1000℃ for 30 seconds to 30 minutes; the gate contact area does not form the source region.

8. The method for fabricating a deep trench field-effect transistor with a dual-gate structure according to claim 7, characterized in that: The thickness of the interlayer dielectric layer is 0.4 μm to 2 μm; a source contact structure is formed in the source contact region, passing through the interlayer dielectric layer and extending at least to the body region, the source contact structure connecting the source region and the body region; a gate contact structure is disposed in the gate contact region and contacts the upper gate conductive portion, and the gate contact structure extends downward to the lower gate conductive portion, so that the gate metal connects the upper gate conductive portion and the lower gate conductive portion to the same gate potential through the gate contact structure; a metal layer with a thickness of 0.5 μm to 4 μm is deposited on the interlayer dielectric layer and the source metal and gate metal are patterned to form the source metal and gate metal.

9. The method for fabricating a deep trench field-effect transistor with a dual-gate structure according to claim 1, characterized in that: The gate metal is connected to the upper gate conductive portion and the lower gate conductive portion along the width direction of the trench, and the source metal is connected to the source region and the body region along the width direction of the trench; the source metal and the gate metal extend along the width direction of the trench and are spaced apart from each other, so that the source metal and the gate metal are mutually insulated on the device surface and are led out respectively.

10. A deep trench field-effect transistor with a dual-gate structure, characterized in that, include: A semiconductor substrate having a semiconductor layer and a first surface; The trench extends from the first surface into the interior of the semiconductor layer; An insulating layer is located at the bottom and sidewalls of the trench; A lower gate conductive portion is located within the trench and extends along the depth direction of the trench. The lower part of the lower gate conductive portion is insulated from the semiconductor layer through the insulating layer. The upper part of the lower gate conductive portion is removed to form a top side gate receiving region. The insulating layers on both sides of the upper part of the lower gate conductive portion are removed to form side gate receiving regions. A gate dielectric layer is formed on the surface of the lower gate conductive portion exposed in the top gate receiving region and the side gate receiving region, and on the surface of the semiconductor layer. The upper gate conductive portion is located in the top gate receiving region and the side gate receiving region, and the upper gate conductive portion is insulated from the semiconductor layer and the lower gate conductive portion through the gate dielectric layer; The body region is located on the side of the first surface and adjacent to the upper part of the trench; The source region is located within the body region; The system comprises an interlayer dielectric layer, a source contact structure, a gate contact structure, a source metal, and a gate metal. The source metal is electrically connected to the source region and the body region via the source contact structure, and the gate metal is electrically connected to the upper gate conductive portion and the lower gate conductive portion.

11. The deep trench field-effect transistor with a dual-gate structure according to claim 10, characterized in that: The bottom ends of the side gate conductive portions are all located above the bottom end of the upper gate conductive portion, such that the depth of the lower gate conductive portion extending into the semiconductor layer is greater than the depth of the two side gate conductive portions extending into the semiconductor layer; the insulating layer is located between the lower gate conductive portion and the lower sidewall and bottom of the trench, and the thickness of the insulating layer is greater than the thickness of the gate dielectric layer.

12. The deep trench field-effect transistor with a dual-gate structure according to claim 10, characterized in that: The gate metal is electrically connected to both the upper gate conductive portion and the lower gate conductive portion through a gate contact structure, so that the upper gate conductive portion and the lower gate conductive portion are at the same gate potential; wherein, the upper gate conductive portion forms a channel control gate, and the lower gate conductive portion forms a field modulation conductive portion extending to the drift region through the insulating layer.

13. The deep trench field-effect transistor with a dual-gate structure according to claim 10, characterized in that: The source contact structure is located between adjacent trenches and extends from the first surface toward the body region. The source contact structure extends through the source region into the body region, so that the source metal is electrically connected to both the source region and the body region simultaneously.

14. The deep trench field-effect transistor with a dual-gate structure according to claim 10, characterized in that: The source metal and the gate metal extend along the width direction of the trench and are spaced apart from each other, so that the source metal and the gate metal are insulated from each other on the device surface and are led out respectively.

15. The deep trench field-effect transistor with a dual-gate structure according to claim 10, characterized in that: The semiconductor layer and the source region are N-type, and the body region is P-type; the thickness of the semiconductor layer is 1 μm to 10 μm, and the resistivity is 0.1 Ω·cm to 1 Ω·cm; the thickness of the top gate conductive portion is 0.05 μm to 0.3 μm; the depth of the trench is 1.2 μm to 6 μm, and the width is 0.2 μm to 2 μm; the thickness of the insulating layer is 0.1 μm to 1 μm; the thickness of the gate dielectric layer is 200 Å to 1200 Å; the thickness of the interlayer dielectric layer is 0.4 μm to 2 μm; and the thickness of the source metal and the gate metal is 0.5 μm to 4 μm.

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