Enhanced hemt devices with regrown structures and dielectric spacers and methods of making the same

Abstract

The application discloses an enhanced HEMT device with a regrowth structure and a dielectric sidewall and a preparation method thereof. The device comprises a substrate layer, a buffer layer, a high resistance layer, a channel layer and a barrier layer; a p-GaN cap layer, a first regrowth mask dielectric sidewall and a first regrowth layer are arranged on the barrier layer, and the first regrowth layer is located outside the dielectric sidewall; a second regrowth layer is arranged on the first regrowth layer, and the doping concentration of the second regrowth layer is higher than that of the first regrowth layer; a gate regrowth layer and a gate electrode are sequentially arranged on the p-GaN cap layer; and a source electrode and a drain electrode are arranged on the second regrowth layer, respectively. Through the design of the multiple regrowth structure and the doping concentration gradient, the device can improve the channel two-dimensional electron gas concentration and realize low resistance ohmic contact, thereby effectively reducing the specific on-resistance of the device; meanwhile, the dielectric sidewall process is used to reduce the requirement for photolithography overlay accuracy, the gate half-floating field plate is combined to optimize the electric field distribution, and the yield, stability and off-state breakdown characteristics of the device are effectively improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor device technology, and in particular relates to enhancement-mode HEMT devices with regenerated structures and dielectric sidewalls and their fabrication methods. Background Technology

[0002] GaN-based HEMT devices have become the preferred solution for high-frequency, high-power applications due to their wide bandgap, high electron drift velocity, and high two-dimensional electron gas density. In the field of high-power switching, achieving extremely low specific on-resistance and power consumption while maintaining high voltage withstand capability is currently a research focus for integrated power devices. The design trade-off between high voltage withstand capability and low loss in traditional lateral HEMT structures limits the continuous improvement of their overall performance.

[0003] GaN-based HEMTs (High Electron Mobility Transistors) have become the mainstream device type in high-frequency switching and high-power-density applications due to their material and structural advantages, such as wide bandgap, high critical breakdown field strength, high electron saturation drift velocity, and high concentration of two-dimensional electron gas at the AlGaN / GaN heterojunction interface. Especially in low-voltage, high-current power conversion systems, GaN-based HEMTs are gradually replacing traditional Si-based power devices because they combine high switching speed and low conduction loss.

[0004] However, in the pursuit of higher integration and better overall performance, GaN-based HEMTs still face several technical bottlenecks that urgently need to be overcome.

[0005] First, there is the trade-off between on-resistance and threshold voltage. To achieve enhancement-mode (normally off) operation and ensure a positive shift in the threshold voltage, the thickness of the AlGaN barrier layer and the aluminum composition typically need to be selected within a narrow range. This directly limits the areal density of the two-dimensional electron gas at the heterojunction interface, resulting in a high channel sheet resistance and making it difficult to further reduce the device's on-resistance. How to effectively reduce on-resistance while maintaining a high threshold voltage is a classic challenge in enhancement-mode GaN-based HEMT design.

[0006] Secondly, there is the issue of increased contact resistance due to proportionally reduced feature size. With the development of low-voltage, high-density integration processes, the gate-drain distance of devices is continuously decreasing, significantly increasing the proportion of ohmic contact resistance between the source and drain in the on-resistance. This is especially true at submicron and even nanometer-scale gate lengths, where contact resistance has become one of the dominant factors restricting further improvements in device performance. Traditional ohmic contact optimization methods are no longer sufficient to meet the stringent contact resistance requirements of low-voltage, high-performance devices.

[0007] Third, advanced lithography processes are increasingly reliant on manufacturing precision. With the continuous miniaturization of device feature sizes, the relative positions of key structures such as the source, drain, and gate need to be defined through multiple lithography steps, placing extremely high demands on the overlay precision of the lithography machine. Any minute alignment deviation can lead to significant dispersion in the electrical characteristics of the device, severely restricting the manufacturing consistency and mass production yield of devices in high-frequency, large-scale integrated circuits.

[0008] To address the aforementioned issues, existing research has attempted to improve ohmic contacts or increase channel carrier concentration through regeneration techniques. However, current solutions typically only address a single problem and optimize a single-layer structure, lacking a systematic consideration of device on-resistance, gate control capability, breakdown characteristics, and process compatibility. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide an enhanced HEMT device with a regenerated structure and dielectric sidewalls and a method for fabricating the same, addressing the problems of difficulty in balancing on-resistance and threshold voltage, significant increase in ohmic contact resistance with size reduction, and narrow high-precision photolithography process window in existing enhanced HEMTs.

[0010] To address the aforementioned technical problems, this application provides the following technical solution: In a first aspect, this application provides an enhanced HEMT device having a regenerated structure and dielectric sidewalls, comprising: A substrate layer, wherein a buffer layer, a high-resistivity layer, a channel layer and a barrier layer are sequentially stacked on the substrate layer; A first regeneration layer, a p-GaN cap layer, and a first regeneration mask dielectric sidewall are disposed on the upper surface of the barrier layer, wherein the first regeneration mask dielectric sidewall is located on the outer sidewall of the p-GaN cap layer, and the first regeneration layer is located on the outer sidewall of the first regeneration mask dielectric sidewall. A second regeneration layer is disposed on the first regeneration layer, wherein the second regeneration layer covers a portion of the first regeneration layer; A gate regeneration layer and a gate are sequentially stacked on the p-GaN cap layer; The source electrode is disposed on one side of the p-GaN cap layer, wherein the source electrode is located on the upper surface of the second regenerated layer; The drain is located on the other side of the p-GaN cap layer, while the source is located on the upper surface of the second regenerated layer.

[0011] Furthermore, the enhanced HEMT device also includes: a composite dielectric structure and a gate semi-floating field plate; The composite medium structure includes: a second regeneration mask layer, a first passivation layer and a second passivation layer stacked sequentially; The second regeneration mask layer covers at least a portion of the upper surface of the first regeneration mask dielectric sidewall, a portion of the upper surface of the first regeneration layer, the sidewall of the gate regeneration layer, and a portion of the gate sidewall; The first passivation layer at least covers the second regeneration mask layer, a portion of the second regeneration layer, and a portion of the gate sidewall; A gate semi-floating field plate is disposed on the upper surface of the first passivation layer on the drain side; the second passivation layer is stacked on the first passivation layer and the gate semi-floating field plate, and covers the top of the source, drain and gate.

[0012] Furthermore, the enhanced HEMT device also includes: an isolation structure; The isolation structure sequentially penetrates the second regenerated layer, the first regenerated layer, the barrier layer, and the channel layer, and the isolation structure partially penetrates the GaN high-resistivity layer.

[0013] Furthermore, the material of the first regenerated layer is doped AlGaN, and the thickness ranges from 3nm to 50nm; The material of the second regrowth layer is doped AlGaN, and the thickness ranges from 3nm to 50nm. The doping concentration of the second regrowth layer is greater than that of the first regrowth layer.

[0014] Furthermore, the material of the gate regeneration layer is doped AlGaN, and the thickness ranges from 3nm to 50nm.

[0015] Furthermore, the material of the gate semi-floating field plate is TiN, and the thickness is between 20nm and 300nm.

[0016] Secondly, this application also provides a method for fabricating an enhanced HEMT device with a regenerated structure and dielectric sidewalls, comprising: S10, Provide a substrate layer; S20. A buffer layer, a high-resistivity layer, a channel layer, a barrier layer, and a p-GaN layer are grown and formed sequentially from bottom to top on the substrate. S30. Deposit a TiN metal layer on the upper surface of the p-GaN layer, and deposit a first protective dielectric layer on the upper surface of the TiN layer; S40. A gate region is formed on the upper surface of the first protective dielectric layer, and the first protective dielectric layer, the TiN metal layer, and the p-GaN layer outside the gate region are etched away, with the etching depth reaching the upper surface of the barrier layer, thereby forming a p-GaN cap layer. S50. A first regeneration mask layer is grown on the top of the device using a low-pressure chemical vapor deposition method, and the first regeneration mask layer is etched without a mask using inductively coupled plasma etching to form the first regeneration mask dielectric sidewall, as well as the source / drain regeneration region and the gate regeneration region. S60. Within the preset regrowth region, doped AlGaN is epitaxially grown on both sides of the p-GaN cap layer and the first regrowth mask dielectric sidewall to form the first regrowth layer and the gate regrowth layer, respectively. S70. A second regeneration mask layer is grown on the top of the device using low-pressure chemical vapor deposition. The second regeneration mask layer above the preset second regeneration layer area is etched away. Finally, a second regeneration layer is epitaxially grown on the first regeneration layer. S80. Place the device in a high-temperature environment of 700℃-900℃ for 5-15 minutes for activation. S90. N ions are implanted downwards into the high-resistivity layer from the second regenerated layer on both sides of the device to form an isolation structure on both sides of the device. S100. A first passivation layer is grown on the top of the device using plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition. The first passivation layer is patterned and etched. A gate window is opened in a preset gate region to form a gate and a gate semi-floating field plate. S110. A second passivation layer is grown on the top of the device using plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition. The dielectric in the preset source and drain regions is etched away until the upper surface of the second regenerated layer is formed, creating source and drain etch regions. Ohmic metal is then deposited to form the source and drain.

[0017] Furthermore, the preparation process of the first regenerated layer and the second regenerated layer includes: Either molecular beam epitaxy or metal-organic chemical vapor deposition.

[0018] Furthermore, the formation process of the gate and the gate semi-floating field plate is as follows: After depositing the TiN metal layer, inductively coupled plasma etching is used to etch the metal between the preset gate and the preset field plate, as well as the metal in the non-preset area, to form the gate and the gate semi-floating field plate.

[0019] Thirdly, this application also provides a chip, the chip comprising: an enhanced HEMT device as described in any one of the above descriptions.

[0020] This application provides an enhanced HEMT device with a regenerated structure and dielectric sidewalls, and a method for fabricating the same. The advantages of this method are as follows: 1. This application introduces a multi-regeneration structure with a first regeneration layer and a second regeneration layer. The first regeneration layer mainly functions to increase the two-dimensional electron gas concentration in the channel and reduce the sheet resistance below. The second regeneration layer mainly achieves low-resistance ohmic contact. The synergistic effect of the two significantly reduces the specific on-resistance of the device.

[0021] 2. This application adopts a multiple regeneration structure, which can significantly reduce the specific on-resistance of the device without changing the existing mature process. It also makes it easier to better balance the specific on-resistance and breakdown voltage by adjusting the Si doping concentration of the second regeneration layer, thereby reducing process cost and device structure complexity, and improving the stability and reliability of GaN devices.

[0022] 3. This application introduces a dielectric sidewall process before etching the first regrowth region, which directly defines the spacing between the gate and the first regrowth region by the physical thickness of the dielectric sidewall of the first regrowth mask, significantly reducing the stringent requirements for the overlay accuracy of the photolithography process.

[0023] 4. In addition to introducing a regenerated layer in the source and drain regions, this application also introduces a gate regenerated layer in the gate region. The insertion of this AlGaN layer improves the stability of the threshold voltage and significantly suppresses the gate leakage current. The structure of the gate semi-floating field plate optimizes the electric field distribution at the gate edge, alleviates the electric field concentration effect at the drain end, and significantly improves the off-state breakdown characteristics of the device. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 2 This is one of the detailed schematic diagrams illustrating the fabrication process of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 3 This is a second detailed schematic diagram of the fabrication process of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 4 This is the third detailed schematic diagram of the fabrication process of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 5This is the fourth detailed schematic diagram of the fabrication process of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 6 This is the fifth detailed schematic diagram of the fabrication process of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 7 This is the sixth detailed schematic diagram of the fabrication process of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 8 This is the seventh detailed schematic diagram of the fabrication process of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 9 This is the eighth detailed schematic diagram of the fabrication process of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 10 This is the ninth detailed schematic diagram of the fabrication process of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 11 This is the tenth detailed schematic diagram of the fabrication process of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 12 This is eleventh of the detailed schematic diagrams illustrating the fabrication process of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 13 This is 12th of a detailed schematic diagram illustrating the fabrication process of an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application; Figure 14 This is a schematic flowchart illustrating a method for fabricating an enhanced HEMT device with a regenerated structure and dielectric sidewalls according to an embodiment of this application. Figure label: 1. Substrate layer; 2. Buffer layer; 3. High resistivity layer; 4. Channel layer; 5. Barrier layer; 6. p-GaN cap layer; 7. First regeneration mask dielectric sidewall; 8. First regeneration layer; 9. Gate regeneration layer; 10. Second regeneration mask layer; 11. Second regeneration layer; 12. Isolation structure; 13. First passivation layer; 14. Gate; 15. Gate semi-floating field plate; 16. Second passivation layer; 17. Source; 18. Drain; 60. p-GaN layer; 70. TiN metal layer; 80. First regeneration mask layer; 400. First protective dielectric layer; 100. Photoresist; 200. Gate window. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] Please see Figure 1 This application provides an enhanced HEMT device with a regenerated structure and dielectric sidewalls, comprising: Substrate 1, with buffer layer 2, high-resistivity layer 3, channel layer 4 and barrier layer 5 sequentially stacked on the substrate layer; A first regeneration layer 8, a p-GaN cap layer 6, and a first regeneration mask dielectric sidewall 7 are disposed on the upper surface of the barrier layer 5, wherein the first regeneration mask dielectric sidewall 7 is located on the outer sidewall of the p-GaN cap layer 6, and the first regeneration layer 8 is located on the outer sidewall of the first regeneration mask dielectric sidewall 7. A second regeneration layer 11 is disposed on the first regeneration layer 8, wherein the second regeneration layer covers a portion of the first regeneration layer 8; A gate regeneration layer 9 and a gate 14 are sequentially stacked on the p-GaN cap layer 6. Source 17 is disposed on one side of the p-GaN cap layer 6, wherein the source is located on the upper surface of the second regeneration layer; Drain 18 is disposed on the other side of the p-GaN cap layer 6, wherein the source is located on the upper surface of the second regenerated layer.

[0028] In one embodiment of this application, the enhanced HEMT device further includes: a composite dielectric structure and a gate semi-floating field plate 15; The composite dielectric structure includes: a second regeneration mask layer 10, a first passivation layer 13, and a second passivation layer 16 stacked sequentially; the second regeneration mask layer 10 at least covers a portion of the upper surface of the sidewall 7 of the first regeneration mask dielectric, a portion of the upper surface of the first regeneration layer 8, the sidewall of the gate regeneration layer 9, and a portion of the sidewall of the gate 14; the first passivation layer 13 at least covers the second regeneration mask layer 10, a portion of the second regeneration layer 11, and a portion of the sidewall of the gate 14; a gate semi-floating field plate 15 is disposed on the upper surface of the first passivation layer 13 on the drain side; the second passivation layer 16 is stacked on the first passivation layer 13 and the gate semi-floating field plate 15, and covers the top of the source 17, the drain 18, and the gate 14.

[0029] The following section provides a detailed description of each of the above structures in conjunction with the accompanying drawings.

[0030] Please continue reading. Figure 1 The substrate layer 1 can be any one of sapphire substrate, Si substrate, SiC substrate, diamond substrate, glass substrate, ceramic substrate and polymer substrate, serving as the support structure and carrier structure of the enhancement-mode HEMT device.

[0031] Please continue reading. Figure 1 The buffer layer 2 is located above the substrate layer 1, and the material of the buffer layer 2 is one of AlN, AlGaN, AlN / (Al)GaN superlattice, and GaN. In one embodiment, the material of the buffer layer 2 is AlN / (Al)GaN superlattice, and the thickness of the buffer layer 2 in the longitudinal direction is 300nm~4000nm, so that the buffer layer 2 can grow normally and will not be broken down in the longitudinal direction.

[0032] A high-resistivity layer 3 is located above the buffer layer 2. The material of the high-resistivity layer 3 is GaN; preferably, the high-resistivity layer 3 is C-doped GaN; wherein the C doping concentration is 5 × 10⁻⁶. 17 cm -3 ~2×10 19 cm -3 This doping concentration range allows the high-resistivity layer to achieve high-resistivity insulation, thereby effectively isolating the channel from the underlying buffer layer and preventing leakage.

[0033] The channel layer 4 is located above the high-resistivity layer 3, and is an undoped GaN channel layer. The barrier layer 5 is located above the channel layer 4. Furthermore, the thickness of the channel layer 4 in the longitudinal direction is 50 nm to 500 nm. The material of the barrier layer 5 is Al. x Ga 1-x N, where x represents the aluminum component, and the value of x ranges from 0.1 to 0.5. The thickness of the AlGaN barrier layer 5 in the longitudinal direction is 10 nm to 50 nm to ensure that the channel layer 4 and the barrier layer 5 can work together to generate a two-dimensional electron gas using the polarization effect.

[0034] Please continue reading. Figure 1 A p-GaN cap layer 6 is disposed on the upper surface of the barrier layer 5. Further, the p-GaN cap layer 6 is made of Mg-doped p-GaN, and the Mg doping concentration is 10. 18 cm -3 ~10 20 cm -3 The thickness of the p-GaN cap layer 6 is 50nm~500nm.

[0035] The first regeneration mask dielectric sidewall 7 is located on the outer sidewall of the p-GaN cap layer 6, closely adhering to a portion of the sidewall of the p-GaN cap layer 6 and covering a portion of the upper surface of the barrier layer 5. The material of the first regeneration mask dielectric sidewall 7 is SiN, with a bottom width of 30nm~100nm. This dielectric sidewall is formed using a maskless etching process, utilizing the characteristics of anisotropic etching to retain residual SiN portions at the edge of the p-GaN cap layer 6 structure as dielectric sidewalls. This structural design directly defines the spacing between the gate and the regeneration region using the physical thickness of the dielectric sidewall, significantly reducing the stringent requirements for the overlay accuracy of the photolithography process.

[0036] Please continue reading. Figure 1 The first regenerated layer 8 is located on the outer wall of the first regenerated mask dielectric sidewall 7, covering part of the upper surface of the barrier layer 5. The inner wall of the first regenerated layer 8 is in contact with the outer wall of the first regenerated mask dielectric sidewall 7. The material of the first regenerated layer 8 is Si-doped n-type AlGaN, with a thickness of 3nm~50nm and an Al composition of 10%~30%. The function of the first regenerated layer 8 is to increase the two-dimensional electron gas concentration in the channel and reduce the sheet resistance of the underlying region.

[0037] The second regeneration layer 11 is disposed on the first regeneration layer 8, covering a portion of the first regeneration layer 8. The material of the second regeneration layer 11 is n. + -AlGaN (heavily silicon-doped AlGaN), with a thickness of 3nm~50nm, Al composition of 3%~30%, and Si doping concentration of 10%. 16 cm -3 ~10 21 cm -3 The Al content in the second regenerated layer 11 is lower than that in the first regenerated layer 8, so as to reduce the barrier height between the metal and the semiconductor, which is beneficial to the formation of a low-resistance ohmic contact between the second regenerated layer 11 and the source 17 or the drain 18.

[0038] It should be noted that the first regeneration layer 8 uses a relatively low Si doping concentration; for example, the Si doping concentration in the first regeneration layer 8 is 10. 15 cm -3 ~10 20 cm -3 This design improves the concentration of the two-dimensional electron gas while avoiding lattice quality degradation and carrier mobility reduction caused by excessive doping. The second regenerated layer 11 is doped with a high concentration of Si to ensure good ohmic contact with the source and drain metals. The two regenerated layers are designed with a gradient of doping concentration (low doping in the first regenerated layer and high doping in the second regenerated layer), which ensures both channel carrier concentration and mobility while achieving low-resistance ohmic contact.

[0039] A gate regeneration layer 9 is disposed between the p-GaN cap layer 6 and the gate 14. The gate regeneration layer 9 is made of AlGaN, with a thickness of 3nm to 50nm and an Al content of 10% to 30%. The introduction of the gate regeneration layer 9 can improve the stability of the threshold voltage and significantly suppress the gate leakage current.

[0040] Please continue reading. Figure 1 The gate 14 is disposed on the upper surface of the gate regeneration layer 9. The gate 14 is made of TiN and has a thickness of 20nm~300nm. The gate semi-floating field plate 15 is disposed on the upper surface of the first passivation layer 13 on the drain side. The gate semi-floating field plate 15 is made of the same material as the gate 14, TiN, and has a thickness of 20nm~300nm. The structure of the gate semi-floating field plate 15 can optimize the electric field distribution at the gate edge, alleviate the electric field concentration effect at the drain end, and significantly improve the off-state breakdown characteristics of the device.

[0041] Please continue reading. Figure 1 In some embodiments of this application, the enhanced HEMT device further includes an isolation structure 12. The isolation structure 12 sequentially penetrates the second regenerated layer 11, the first regenerated layer 8, the barrier layer 5, and the channel layer 4, and partially penetrates the high-resistivity layer 3, meaning the lower surface of the isolation structure 12 is located inside the high-resistivity layer 3. The upper surface of the isolation structure 12 is flush with the upper surface of the second regenerated layer 11. The isolation structure 12 includes either a mesa isolation structure or an ion implantation structure. The mesa isolation structure is formed in the mesa region of the device through an etching process to achieve electrical isolation between different device regions; the ion implantation structure uses an ion implanter to accelerate and implant impurity ions into the semiconductor material, precisely changing the electrical properties of the semiconductor material by controlling parameters such as the type, energy, dose, and angle of the implanted ions. In a preferred embodiment of this application, the isolation structure 12 employs an N-ion implantation structure with an implanted N-ion concentration of 10. 15 cm -3 ~10 17 cm -3 .

[0042] In some embodiments of this application, the lower surface of the source electrode 17 is in contact with a portion of the upper surface of the second regenerated layer 11 and at least a portion of the upper surface of the isolation structure 12, and the lower surface of the source electrode 17 is flush with the upper surface of the second regenerated layer 11. The lower surface of the drain electrode 18 is in contact with a portion of the upper surface of the second regenerated layer 11 and at least a portion of the upper surface of the isolation structure 12, and the lower surface of the drain electrode 18 is flush with the upper surface of the second regenerated layer 11. The materials of the source electrode 17 and the drain electrode 18 are ohmic metals selected from any one of Ti / Al / Ni / Au or Ti / Al / Ti / Au.

[0043] The enhanced HEMT device with regenerated structure and dielectric sidewalls provided in this application embodiment has at least the following beneficial effects: 1. This application introduces a multi-regeneration structure with a first regeneration layer and a second regeneration layer. The first regeneration layer mainly functions to increase the two-dimensional electron gas concentration in the channel and reduce the sheet resistance below. The second regeneration layer mainly achieves low-resistance ohmic contact. The synergistic effect of the two significantly reduces the specific on-resistance of the device.

[0044] 2. This application adopts a multiple regeneration structure, which can significantly reduce the specific on-resistance of the device without changing the existing mature process. It also makes it easier to better balance the specific on-resistance and breakdown voltage by adjusting the Si doping concentration of the second regeneration layer, thereby reducing process cost and device structure complexity, and improving the stability and reliability of GaN devices.

[0045] 3. This application introduces a dielectric sidewall process before etching the first regrowth region, which directly defines the spacing between the gate and the first regrowth region by the physical thickness of the dielectric sidewall of the first regrowth mask, significantly reducing the stringent requirements for the overlay accuracy of the photolithography process.

[0046] 4. In addition to introducing a regenerated layer in the source and drain regions, this application also introduces a gate regenerated layer in the gate region. The insertion of this AlGaN layer improves the stability of the threshold voltage and significantly suppresses the gate leakage current. The structure of the gate semi-floating field plate optimizes the electric field distribution at the gate edge, alleviates the electric field concentration effect at the drain end, and significantly improves the off-state breakdown characteristics of the device.

[0047] Please see Figures 2 to 14 This application also provides a method for fabricating an enhanced HEMT device with a regenerated structure and dielectric sidewalls, applicable to the fabrication of the aforementioned enhanced HEMT device with a regenerated structure and dielectric sidewalls, comprising at least the following steps: S10. Provide a substrate layer 1, which can be any one of sapphire substrate, Si substrate, SiC substrate, diamond substrate, glass substrate, ceramic substrate and polymer substrate.

[0048] S20, please refer to Figure 2 The buffer layer 2, the high-resistivity layer 3, the channel layer 4, the barrier layer 5 and the p-GaN layer 60 are grown sequentially from bottom to top on the substrate.

[0049] In a specific embodiment, a metal-organic chemical vapor deposition (MOCVD) process is used to sequentially grow a buffer layer 2, a high-resistivity layer 3, a channel layer 4, a barrier layer 5, and a p-GaN layer 60 on a substrate layer 1. The buffer layer 2 is made of AlGaN and has a thickness of 300 nm to 800 nm. The high-resistivity layer 3 is C-doped GaN with a C doping concentration of 5 × 10⁻⁶. 17cm -3 ~2×10 19 cm -3 The channel layer 4 is made of undoped GaN with a thickness of 50 nm to 500 nm. The barrier layer 5 is made of Al. x Ga 1-x N, where x ranges from 0.1 to 0.5, representing the aluminum composition, and the thickness ranges from 10 nm to 50 nm. The p-GaN layer 60 is made of Mg-doped p-GaN with a Mg doping concentration of 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 The thickness is 50nm~500nm.

[0050] S30, please refer to Figure 3 A TiN metal layer 70 is deposited on the upper surface of the p-GaN layer 60, and a first protective dielectric layer 400 is deposited on the upper surface of the TiN metal layer 70.

[0051] Before subsequent etching and other processes of the p-GaN layer 60, a protective layer is first formed on the surface to prevent contamination. For example, when using ion implantation to generate isolation structures, the surface of enhancement-mode HEMT devices is bombarded by high-energy ions, resulting in roughness. Therefore, a protective layer is needed to absorb the surface bombardment and prevent damage to the semiconductor surface.

[0052] Specifically, TiN is deposited on the upper surface of the p-GaN layer 60 using electron beam evaporation or magnetron sputtering to form a TiN metal layer 70 with a thickness of 10 nm to 300 nm. Subsequently, a first protective dielectric layer 400 is deposited on the upper surface of the TiN metal layer 70 using plasma-enhanced chemical vapor deposition (PECVD). The material of the first protective dielectric layer 400 is SiN. In this embodiment, plasma-enhanced chemical vapor deposition is used to deposit the first protective dielectric layer 400 on the upper surface of the p-GaN layer 60 to form a SiN dielectric layer with a thickness of 100 nm to 300 nm. The TiN metal layer 70 and the first protective dielectric layer 400 together constitute a protective stack, which is used to protect the surface of the p-GaN layer 60 from damage and contamination during subsequent etching processes.

[0053] S40, please refer to Figure 4-5 A gate region is formed on the upper surface of the first protective dielectric layer 400. The first protective dielectric layer 400, the TiN metal layer 70 and the p-GaN layer 60 outside the gate region are etched away, and the etching depth extends to the upper surface of the barrier layer 5 to form a p-GaN cap layer 6.

[0054] Specifically, a first photoresist 100 is spin-coated onto the upper surface of the p-GaN layer 60, and exposure and development are performed in a predetermined gate region to form a patterned first photoresist 100 covering the gate region. Subsequently, plasma etching is used to etch away the first protective dielectric layer 400, the TiN metal layer 70, and the p-GaN layer 60 outside the predetermined gate region. After etching, the entire wafer is cleaned to remove the first photoresist 100 and the first protective dielectric layer 400, and surface oxides are removed by acid washing. In this embodiment, hydrofluoric acid or BOE solution is used to etch away the first protective dielectric layer 400 on the material surface, and SC-1 solution or hydrogen peroxide is used to etch away the TiN metal layer 70, exposing the upper surfaces of the p-GaN cap layer 6 and the barrier layer 5.

[0055] S50, please refer to Figure 6-7 The first regeneration mask layer 80 is grown on the top of the device using low-pressure chemical vapor deposition (LPCVD), and the first regeneration mask layer 80 is etched without a mask using inductively coupled plasma (ICP) to form the first regeneration mask dielectric sidewall 7, as well as the source / drain regeneration region and the gate regeneration region.

[0056] Specifically, a SiN layer is first deposited using PECVD or LPCVD as the first regeneration mask layer 80. The bottom width of the target dielectric sidewall is 50 nm. Since the F-based gas and SiN material will produce isotropic etching in the subsequent etching process, the lateral etching rate is lower than the vertical etching rate. Therefore, the deposition thickness of the SiN material is set to 60 nm to 80 nm to increase the etching process redundancy. After deposition, the SiN layer is etched without a mask using ICP to generate SiN sidewalls as the first regeneration mask dielectric sidewalls 7.

[0057] S60, please refer to Figure 8 Within the preset regrowth region, doped silicon AlGaN is epitaxially grown on both sides of the p-GaN cap layer 6 and the first regrowth mask dielectric sidewall 7 to form the first regrowth layer 8 and the gate regrowth layer 9, respectively.

[0058] Specifically, selective epitaxial growth is performed using molecular beam epitaxy (MBE) or MOCVD. Si doping is performed simultaneously during the growth of the first regenerated layer 8. The difference in the behavior of Ga atoms on different material surfaces determines the growth selectivity: on the barrier layer 5 and p-GaN cap layer 6, Ga atoms have a high adhesion coefficient, allowing AlGaN to grow in high-quality single-crystal form; however, on the SiN layer surface, Ga atoms have a low adhesion coefficient, requiring aggregation and nucleation before regeneration. Therefore, the AlGaN film formed in the non-regenerated region is not only much thinner than the regenerated layer but also has weak adhesion, which can be ignored in subsequent processes. The thickness of the first regenerated layer 8 is 3 nm to 50 nm, with an Al composition of 10% to 30%. The thickness of the gate regenerated layer 9 is 3 nm to 50 nm, with an Al composition of 10% to 30%.

[0059] S70, please refer to Figure 9 The second regeneration mask layer 10 is grown on the top of the device using low-pressure chemical vapor deposition. The second regeneration mask layer 10 above the preset second regeneration layer area is etched away, and then the second regeneration layer 11 is epitaxially grown on the first regeneration layer 8.

[0060] Specifically, the material of the second regeneration mask layer 10 is SiN. Exposure and development are performed on a predetermined area of ​​the second regeneration layer on the second regeneration mask layer 10, and the second regeneration mask layer 10 above the predetermined area is etched away using a dry etching method. Subsequently, n is epitaxially grown on the first regeneration layer 8 using MBE. + -AlGaN layer, Si doping concentration is 1×10⁻⁶ 16 cm -3 ~1×10 21 cm -3 An Al composition of 3%–30% and a thickness of 3 nm–50 nm are used to form a second regenerated layer 11. The second regenerated layer 11 is used to form a good ohmic contact and reduce contact resistance.

[0061] It should be noted that in this embodiment, the first regenerated layer 8 uses a relatively low Si doping concentration to optimize the channel transport characteristics and maintain a high carrier mobility, while the second regenerated layer 11 uses a relatively high Si doping concentration to reduce the metal-semiconductor contact barrier. The two regenerated layers achieve functional decoupling and synergy through a gradient doping design of light doping to heavy doping, and together reduce the total on-resistance of the device.

[0062] In one embodiment of this application, the preparation process of the first regrowth layer and the second regrowth layer includes any one of molecular beam epitaxy and metal-organic chemical vapor deposition.

[0063] S80. Place the device in a high-temperature environment of 700℃-900℃ for 5-15 minutes for activation.

[0064] Specifically, the device is subjected to activation annealing at a high temperature of 700℃-900℃ for 5 to 15 minutes to achieve acceptor activation. The high temperature heat energy causes the Mg-H bonds in the p-GaN cap layer 6 to dissociate, releasing the magnesium acceptor that has been passivated by hydrogen atoms, thus obtaining a low-resistivity p-GaN cap layer 6.

[0065] S90. N ions are implanted downwards into the high-resistivity layer from the second regeneration layer on both sides of the device to form an isolation structure on both sides of the device.

[0066] Specifically, please refer to Figure 10 N ions are implanted downwards into the high-resistivity layer 3 through the second regeneration layer 11 on both sides of the device to form the isolation structure 12 located on both sides of the device.

[0067] In this embodiment, the implanted N ion concentration is 10. 15 cm -3 ~10 17 cm -3 The isolation structure 12 sequentially penetrates the second regeneration layer 11, the first regeneration layer 8, the barrier layer 5, and the channel layer 4, and partially penetrates the high-resistivity layer 3. The lower surface of the isolation structure 12 is located inside the high-resistivity layer 3, and the upper surface of the isolation structure 12 is flush with the upper surface of the second regeneration layer 11.

[0068] S100, please refer to Figure 11-12 A first passivation layer 13 is grown on the top of the device using PECVD (plasma-enhanced chemical vapor deposition) or LPCVD (low-pressure chemical vapor deposition). The first passivation layer 13 is patterned and etched. A gate window 200 is opened in a preset gate region to form a gate 14 and a gate semi-floating field plate 15.

[0069] Specifically, the first passivation layer 13 is made of SiN or SiO2 and has a thickness of 50nm to 200nm. A pattern is formed by photolithography, and the first passivation layer 13 is patterned by etching to open a gate window 200 in a predetermined gate region. Subsequently, a TiN metal layer is deposited using electron beam evaporation or magnetron sputtering, and a pattern is formed by photolithography. ICP etching is then used to remove the metal between the gate and the predetermined field plate, as well as the metal in non-predetermined areas, forming the gate 14 and the gate semi-floating field plate 15. The thickness of the gate 14 and the gate semi-floating field plate 15 is 20nm to 300nm.

[0070] In one embodiment of this application, the formation process of the gate and the gate semi-floating field plate is as follows: after depositing a TiN metal layer, the metal between the preset gate and the preset field plate, as well as the metal in the non-preset area, is etched by ICP etching to form the gate and the gate semi-floating field plate.

[0071] S110, please refer to Figure 13 A second passivation layer 16 is grown on the top of the device using PECVD or LPCVD. The dielectric of the preset source and drain regions is etched away until the upper surface of the second regenerated layer 11 is etched to form the source etch region and the drain etch region. Ohmic metal is deposited to form the source 17 and the drain 18.

[0072] Specifically, the material of the second passivation layer 16 is SiN or SiO2. A dry etching method is used to etch the predetermined source and drain regions above the second regenerated layer 11, exposing the upper surface of the second regenerated layer 11. Then, ohmic metal is deposited in the predetermined source and drain regions using electron beam evaporation or magnetron sputtering. The ohmic metal is selected from any one of Ti / Al / Ni / Au or Ti / Al / Ti / Au. After deposition, an annealing treatment is performed at 500℃~600℃ for 30 seconds~120 seconds to form the source 17 and drain 18.

[0073] This application also provides a chip comprising: an enhanced HEMT device as described in any one of the preceding descriptions.

[0074] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.

[0075] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0076] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. An enhanced HEMT device having a regenerated structure and dielectric sidewalls, characterized in that, include: A substrate layer, wherein a buffer layer, a high-resistivity layer, a channel layer and a barrier layer are sequentially stacked on the substrate layer; A first regeneration layer, a p-GaN cap layer, and a first regeneration mask dielectric sidewall are disposed on the upper surface of the barrier layer, wherein the first regeneration mask dielectric sidewall is located on the outer sidewall of the p-GaN cap layer, and the first regeneration layer is located on the outer sidewall of the first regeneration mask dielectric sidewall. A second regeneration layer is disposed on the first regeneration layer, wherein the second regeneration layer covers a portion of the first regeneration layer; A gate regeneration layer and a gate are sequentially stacked on the p-GaN cap layer; The source electrode is disposed on one side of the p-GaN cap layer, wherein the source electrode is located on the upper surface of the second regenerated layer; The drain is located on the other side of the p-GaN cap layer, while the source is located on the upper surface of the second regenerated layer.

2. The enhanced HEMT device according to claim 1, characterized in that, The enhanced HEMT device further includes: a composite dielectric structure and a gate semi-floating field plate; The composite medium structure includes: a second regeneration mask layer, a first passivation layer and a second passivation layer stacked sequentially; The second regeneration mask layer covers at least a portion of the upper surface of the first regeneration mask dielectric sidewall, a portion of the upper surface of the first regeneration layer, the sidewall of the gate regeneration layer, and a portion of the sidewall of the gate. The first passivation layer at least covers the second regeneration mask layer, a portion of the second regeneration layer, and a portion of the gate sidewall; A gate semi-floating field plate is disposed on the upper surface of the first passivation layer on the drain side; the second passivation layer is stacked on the first passivation layer and the gate semi-floating field plate, and covers the top of the source, drain and gate.

3. The enhanced HEMT device according to claim 2, characterized in that, The enhanced HEMT device further includes: an isolation structure; The isolation structure sequentially penetrates the second regeneration layer, the first regeneration layer, the barrier layer, and the channel layer, and the isolation structure partially penetrates the high-resistivity layer.

4. The enhanced HEMT device according to claim 1, characterized in that, The material of the first regenerated layer is doped AlGaN, and the thickness ranges from 3nm to 50nm. The material of the second regrowth layer is doped AlGaN, and the thickness ranges from 3nm to 50nm. The doping concentration of the second regrowth layer is greater than that of the first regrowth layer.

5. The enhanced HEMT device according to claim 1, characterized in that, The gate regeneration layer is made of doped AlGaN and has a thickness ranging from 3 nm to 50 nm.

6. The enhanced HEMT device according to claim 2, characterized in that, The material of the gate semi-floating field plate is TiN, and the thickness is between 20nm and 300nm.

7. A method for fabricating an enhanced HEMT device with a regenerated structure and dielectric sidewalls, characterized in that, include: S10, Provide a substrate layer; S20. A buffer layer, a high-resistivity layer, a channel layer, a barrier layer, and a p-GaN layer are grown and formed sequentially from bottom to top on the substrate. S30. Deposit a TiN metal layer on the upper surface of the p-GaN layer, and deposit a first protective dielectric layer on the upper surface of the TiN layer; S40. A gate region is formed on the upper surface of the first protective dielectric layer, and the first protective dielectric layer, the TiN metal layer, and the p-GaN layer outside the gate region are etched away, with the etching depth reaching the upper surface of the barrier layer, thereby forming a p-GaN cap layer. S50. A first regeneration mask layer is grown on the top of the device using a low-pressure chemical vapor deposition method, and the first regeneration mask layer is etched without a mask using inductively coupled plasma etching to form the first regeneration mask dielectric sidewall, as well as the source / drain regeneration region and the gate regeneration region. S60. Within the preset regrowth region, doped AlGaN is epitaxially grown on both sides of the p-GaN cap layer and the first regrowth mask dielectric sidewall to form the first regrowth layer and the gate regrowth layer, respectively. S70. A second regeneration mask layer is grown on the top of the device using low-pressure chemical vapor deposition. The second regeneration mask layer above the preset second regeneration layer area is etched away. Finally, a second regeneration layer is epitaxially grown on the first regeneration layer. S80. Place the device in a high-temperature environment of 700℃-900℃ for 5-15 minutes for activation. S90. N ions are implanted downwards into the high-resistivity layer from the second regenerated layer on both sides of the device to form an isolation structure on both sides of the device. S100. A first passivation layer is grown on the top of the device using plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition. The first passivation layer is patterned and etched. A gate window is opened in a preset gate region to form a gate and a gate semi-floating field plate. S110. A second passivation layer is grown on the top of the device using plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition. The dielectric in the preset source and drain regions is etched away until the upper surface of the second regenerated layer is formed, creating source and drain etch regions. Ohmic metal is then deposited to form the source and drain.

8. The preparation method according to claim 7, characterized in that, The fabrication processes of the first and second regenerated layers include: Either molecular beam epitaxy or metal-organic chemical vapor deposition.

9. The preparation method according to claim 7, characterized in that, The formation process of the gate and the gate semi-floating field plate is as follows: After depositing the TiN metal layer, inductively coupled plasma etching is used to etch the metal between the preset gate and the preset field plate, as well as the metal in the non-preset area, to form the gate and the gate semi-floating field plate.

10. A chip, characterized in that, The chip includes: an enhanced HEMT device as described in any one of claims 1-6.

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