A full diamond hetero-gate schottky mosfet

Abstract

The present application relates to the technical field of MOS semiconductor, and discloses a full diamond hetero-gate Schottky MOSFET, comprising a substrate layer, wherein a drain P+ layer and a source P+ layer are deposited on the left and right sides of the upper side of the substrate layer, a source electrode is deposited on the upper side of the source P+ layer, a drain electrode is deposited on the upper side of the drain P+ layer, a gate is arranged between the source electrode and the drain electrode, and an isolation layer is arranged on the surface of the gate; a channel layer is formed in the substrate layer and between the source P+ layer and the drain P+ layer by ion implantation. The present application adopts a full diamond material system to construct a MOSFET core structure, the substrate, the source and the drain are all made of diamond material, the intrinsic advantages of diamond, such as super-wide band gap, high thermal conductivity and high breakdown field strength, are fully utilized, and the synergistic design of the hetero-gate and the multi-layer composite insulation structure significantly reduces the interface state density while improving the voltage grade and high-temperature stability of the device.

Description

Technical Field

[0001] This invention relates to the field of MOS semiconductor technology, and more particularly to an all-diamond heterogate Schottky MOSFET. Background Technology

[0002] Diamond, with its ultra-wide bandgap (approximately 5.5 eV), extremely high critical breakdown field strength (approximately 10 MV / cm), and the highest thermal conductivity found in nature (approximately 22 W / cm·K), is widely recognized as an ideal semiconductor material for next-generation high-frequency, high-power, and high-temperature electronic devices. However, the actual performance of diamond MOSFET devices has long been constrained by several bottlenecks: on the one hand, the poor interface quality between the metal oxide gate dielectric and the diamond semiconductor layer results in a high interface state density, leading to severe carrier scattering and low channel mobility; on the other hand, the two-dimensional hole gas present on the hydrogen-terminated diamond surface causes the device to intrinsically exhibit a depletion-type operating mode, and the threshold voltage instability caused by the interface states further threatens the reliable operation of the device.

[0003] Furthermore, the low barrier height of traditional Schottky gates often leads to large gate leakage currents and poor thermal stability. Although researchers have attempted to improve device performance through interface engineering, gate dielectric optimization, and surface termination modification, effectively reducing interface state density, improving gate control capability, and enhancing high-temperature reliability while fully leveraging the intrinsic advantages of diamond remains a challenging technical problem to be solved. Summary of the Invention

[0004] This invention provides an all-diamond heterogate Schottky MOSFET to solve existing technical problems, thereby addressing the issue of excessively high interface state density while improving the device's voltage withstand level and high-temperature stability.

[0005] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, an all-diamond heterogate Schottky MOSFET, comprising a substrate layer, wherein a drain region P+ layer and a source region P+ layer are deposited on the left and right sides above the substrate layer, respectively, wherein a source electrode is deposited above the source region P+ layer and a drain electrode is deposited above the drain region P+ layer, and a gate electrode and an isolation layer covering the surface of the gate electrode are provided between the source electrode and the drain electrode.

[0006] A channel layer is formed inside the substrate layer and between the source P+ layer and the drain P+ layer by ion implantation. The two ends of the channel layer are in direct contact with the source P+ layer and the drain P+ layer, respectively. A composite structure layer is deposited above the channel layer, wherein the composite structure layer is in direct contact with the gate and the isolation layer. A passivation layer is deposited above the isolation layer and between the source and the drain.

[0007] Furthermore, the surface of the isolation layer is also covered with a transition layer, wherein the cross-sectional profile of the transition layer is in the shape of a "door".

[0008] Furthermore, the source electrode is a four-layer source electrode, and the drain electrode is a four-layer drain electrode.

[0009] Furthermore, the gate includes a composite gate, the composite structure layer includes a composite structure, the isolation layer includes an isolation layer, and the passivation layer includes a passivation layer.

[0010] Furthermore, the composite structure is composed of an intrinsic diamond layer, a silicon nitride layer, and an aluminum oxide layer, wherein the intrinsic diamond layer, silicon nitride layer, and aluminum oxide layer are arranged sequentially from top to bottom.

[0011] Furthermore, the gate includes a second composite gate, the composite structure layer includes a second composite structure, the isolation layer includes a second isolation layer, and the passivation layer includes a second passivation layer.

[0012] Furthermore, the second composite structure is composed of a hafnium oxide layer and an aluminum oxide layer, wherein the hafnium oxide layer and the aluminum oxide layer are arranged sequentially from top to bottom.

[0013] Furthermore, the source electrode is a three-layer source electrode, the drain electrode is a three-layer drain electrode; the gate electrode is a composite gate electrode, the composite structure layer is a composite structure layer, the isolation layer is an isolation layer layer, and the passivation layer is a passivation layer layer.

[0014] Furthermore, the composite structure three consists of a modified silica layer and an intrinsic diamond layer two, wherein the modified silica layer and the intrinsic diamond layer two are arranged sequentially from top to bottom.

[0015] The all-diamond heterogate Schottky MOSFET provided by this invention has the following advantages compared to existing technologies:

[0016] 1. This invention constructs the core structure of a MOSFET using an all-diamond material system. The substrate, source / drain regions, and channel layer are all made of diamond, which fully leverages the intrinsic advantages of diamond, such as its ultra-wide bandgap, high thermal conductivity, and high breakdown field strength. Combined with the synergistic design of a heterogate and a multilayer composite insulation structure, this invention significantly reduces the interface state density while improving the device's withstand voltage rating and high-temperature stability, providing a new solution for the reliable operation of power semiconductor devices under extreme conditions.

[0017] 2. This invention forms a composite insulating layer that combines interface passivation, ion blocking, and electric field buffering functions by gradient matching of intrinsic diamond, silicon nitride, and alumina three-layer materials in terms of dielectric constant and band structure. Combined with the high work function and stable contact of the platinum composite gate, the device can maintain extremely low gate leakage current and excellent switching characteristics under high temperature and high pressure conditions, making it particularly suitable for high power density switching applications.

[0018] 3. This invention utilizes a high dielectric constant double-layer insulation structure composed of hafnium oxide and aluminum oxide to increase the thickness of the physical insulation layer while maintaining a relatively thin equivalent oxide layer thickness. This enhances the gate's control over the channel and reduces gate leakage. Combined with the optimization of the Schottky barrier height by the nickel-platinum-gold triple-layer composite gate, a balanced improvement in gate control capability and reliability is achieved in high-frequency switching applications.

[0019] 4. This invention utilizes the direct contact between the intrinsic diamond layer and the channel layer, which are made of the same material, to fundamentally eliminate interface defects caused by lattice mismatch at heterogeneous interfaces. Combined with the modification of dielectric properties by boron-doped silicon dioxide, the device structure and fabrication process are greatly simplified while ensuring excellent electrical performance, thus reducing manufacturing costs. This invention is suitable for cost-sensitive and high-reliability medium and high voltage power electronic applications. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of the present invention;

[0021] Figure 2 This is a schematic diagram of the structure of Embodiment 1 of the present invention;

[0022] Figure 3 This is a schematic diagram of the composite structure one in Embodiment 1 of the present invention;

[0023] Figure 4 This is a schematic diagram of the structure of Embodiment 2 of the present invention;

[0024] Figure 5 This is a schematic diagram of the composite structure two in Embodiment 2 of the present invention;

[0025] Figure 6 This is a schematic diagram of the structure of Embodiment 3 of the present invention;

[0026] Figure 7 This is a schematic diagram of composite structure three in Embodiment 3 of the present invention.

[0027] In the diagram: 1. Substrate layer; 2. Source P+ layer; 3. Drain P+ layer; 4. Source; 5. Drain; 6. Gate; 7. Channel layer; 8. Composite structure layer; 9. Isolation layer; 10. Passivation layer; 11. Transition layer; 401. Four-layer source; 402. Three-layer source; 501. Four-layer drain; 502. Three-layer drain; 601. Composite gate one; 602. Composite gate two; 603. Composite gate three; 801. Composite structure one; 802, Composite structure two; 803, Composite structure three; 901, Isolation layer one; 902, Isolation layer two; 903, Isolation layer three; 101, Passivation layer one; 102, Passivation layer two; 801a, Intrinsic diamond layer one; 801b, Silicon nitride layer; 801c, Alumina layer one; 802a, Hafnium oxide layer; 802b, Alumina layer two; 803a, Modified silicon dioxide layer; 803b, Intrinsic diamond layer two. Detailed Implementation

[0028] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] Example 1

[0030] like Figure 1 , Figure 2 As shown, according to one aspect of the present invention, an all-diamond heterogate Schottky MOSFET is provided, comprising a substrate layer 1 (the substrate layer 1 is made of intrinsic diamond material with high conductivity), wherein drain region P+ layer 3 and source region P+ layer 2 are deposited on the upper left and right sides of the substrate layer 1 respectively (the source region P+ layer 2 and drain region P+ layer 3 are both P+ regions formed by heavily doped boron diamond), wherein a source electrode 4 is deposited above the source region P+ layer 2 and a drain electrode 5 is deposited above the drain region P+ layer 3, and a gate electrode 6 and an isolation layer 9 covering the surface of the gate electrode 6 are provided between the source electrode 4 and the drain electrode 5;

[0031] A channel layer 7 (formed by lightly doped boron diamond) is formed by ion implantation inside the substrate layer 1 and between the source region P+ layer 2 and the drain region P+ layer 3. The two ends of the channel layer 7 are in direct contact with the source region P+ layer 2 and the drain region P+ layer 3, respectively. A composite structure layer 8 is deposited above the channel layer 7, and the composite structure layer 8 is in direct contact with the gate 6 and the isolation layer 9. A passivation layer 10 is deposited above the isolation layer 9 and between the source 4 and the drain 5.

[0032] In this embodiment, the surface of the isolation layer 9 is further covered with a transition layer 11, wherein the cross-sectional profile of the transition layer 11 is in the shape of a "door". The transition layer 11 is made of aluminum oxide (chemical formula: The thickness of the transition layer 11 is 5nm to 10nm, and in this embodiment, 7nm is preferred to improve the interface adhesion.

[0033] In this embodiment, the source 4 includes a four-layer source 401, and the drain 5 includes a four-layer drain 501 (both the four-layer source 401 and the four-layer drain 501 are four-layer structures made of titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au) arranged from bottom to top, which results in lower contact resistance and stronger high-temperature stability). Gate 6 includes a composite gate 601 (composite gate 601 adopts a composite metal structure of platinum (Pt) and gold (Au); where platinum is in the lower layer with a thickness of 30nm; gold is in the upper layer with a thickness of 60nm; this design significantly improves high temperature resistance and oxidation resistance, and the Schottky barrier height is about 0.88eV), composite structure layer 8 includes composite structure 801, isolation layer 9 includes isolation layer 901 (isolation layer 9 is made of aluminum nitride, chemical formula AlN. The thickness of isolation layer 9 is 550nm~850nm, preferably 650nm; wherein isolation layer 9 is prepared by MOCVD or ALD method, deposition temperature 1050℃; breakdown field strength is not less than 100MV / cm; dielectric loss tangent tanδ≤0.0005; electromagnetic interference shielding effectiveness is not less than 35dB), passivation layer 10 includes passivation layer 101 (passivation layer 101 is made of silicon nitride, chemical formula... ).

[0034] like Figure 3 As shown, composite structure 801 consists of an intrinsic diamond layer 801a, a silicon nitride layer 801b, and an aluminum oxide layer 801c, arranged sequentially from top to bottom. Composite structure 801 serves as an insulating layer, employing intrinsic diamond layer 801a (made of intrinsic diamond) and silicon nitride layer 801b (made of silicon nitride, chemical formula: ...). ), Alumina layer 801c (material is alumina, chemical formula is A three-layer composite structure; the total thickness of the composite structure 801de is 45nm to 65nm, preferably 55nm; wherein the thickness of the alumina layer 801c is 15nm, the thickness of the silicon nitride layer 801b is 15nm, and the thickness of the intrinsic diamond layer 801a is 25nm; this can further suppress the accumulation of interface charge and reduce the interface state density.

[0035] The core innovation of Example 1 lies in the synergistic design of an intrinsic diamond / silicon nitride / alumina three-layer composite insulating structure (composite structure-801) and a platinum / gold composite gate (composite gate-601). In composite structure-801, the alumina layer-801c serves as the bottom interface layer, directly contacting the channel layer 7. The excellent interface passivation capability of alumina effectively suppresses dangling bonds and defect states at the channel / insulator interface. The middle silicon nitride layer-801b acts as a highly dense barrier layer, effectively blocking the diffusion and penetration of metal ions and water molecules. The top intrinsic diamond layer-801a, with its ultra-wide bandgap and ultra-high breakdown field strength, acts as the outermost electric field buffer and withstand voltage barrier. The three layers form a gradient match in dielectric constant, band structure, and coefficient of thermal expansion, significantly reducing the interface state density and resulting in a more uniform electric field distribution. Meanwhile, the composite gate 601 adopts a composite metal structure with a platinum lower layer and a gold upper layer. The high work function of platinum forms a stable Schottky contact with diamond, while the excellent conductivity and oxidation resistance of gold ensure the long-term stability of the gate under high-temperature environments. The isolation layer 901 is made of aluminum nitride and deposited at 1050℃ using the MOCVD / ALD method. Its breakdown field strength is not less than 100MV / cm, and its dielectric loss tangent tanδ ≤ 0.0005, combining high thermal conductivity with excellent electrical insulation properties.

[0036] This embodiment achieves multiple performance breakthroughs through a synergistic architecture of "three-layer composite insulation + double-layer composite gate + AlN isolation layer". In terms of electrical performance, the three-layer gradient matching design of the composite structure 801 effectively suppresses interface charge accumulation and reduces interface state density, thereby reducing gate leakage current and threshold voltage drift. The high barrier of the platinum / gold composite gate ensures that the device maintains low gate leakage current and good switching characteristics at high temperatures. Regarding reliability, the ultra-high breakdown field strength of the intrinsic diamond layer 801a significantly improves the withstand voltage capability of the gate dielectric, the density of the silicon nitride layer 801b blocks the intrusion of impurity ions, and the low dielectric loss and excellent thermal conductivity of the AlN isolation layer 901 effectively reduce the heat accumulation effect of the device during high-frequency, high-power operation. The use of a four-layer source 401 and drain 501 further reduces contact resistance and enhances high-temperature stability. Overall, this embodiment is particularly suitable for power switching applications requiring high withstand voltage, low leakage current, and excellent high-temperature stability.

[0037] Example 2

[0038] like Figure 1 , Figure 4 As shown, according to one aspect of the present invention, an all-diamond heterogate Schottky MOSFET is provided, comprising a substrate layer 1 (the substrate layer 1 is a high-resistivity intrinsic diamond substrate, wherein the thickness is 550 μm to 850 μm, preferably 700 μm; the substrate layer 1 is subjected to vacuum high-temperature annealing at 1450°C for 2.5 h, and the vacuum degree is... Carrier concentration To ensure high-temperature insulation and high thermal conductivity, drain P+ layer 3 and source P+ layer 2 are deposited on the left and right sides above the substrate layer 1, respectively. (Both source P+ layer 2 and drain P+ layer 3 are P+ regions formed by heavily doped boron diamond, and are symmetrically distributed on both sides of the channel layer 7; the thickness is 300nm~400nm, preferably 350nm; the boron doping concentration is...) The source region P+ layer 2 is deposited with a source electrode 4 above it and the drain region P+ layer 3 is deposited with a drain electrode 5 above it. A gate electrode 6 and an isolation layer 9 covering the surface of the gate electrode 6 are provided between the source electrode 4 and the drain electrode 5.

[0039] A channel layer 7 is formed by ion implantation inside substrate layer 1, located between source region P+ layer 2 and drain region P+ layer 3. Channel layer 7 is a region formed from lightly doped boron diamond, situated between source region P+ layer 2 and drain region P+ layer 3; its thickness is 150 nm to 250 nm, preferably 200 nm; wherein the boron doping concentration is... 1; MPCVD in-situ epitaxial growth is adopted, so that the interface of the channel layer 7 is continuous and the defect density is low. The two ends of the channel layer 7 are in direct contact with the source region P+ layer 2 and the drain region P+ layer 3, respectively. A composite structure layer 8 is deposited above the channel layer 7, wherein the composite structure layer 8 is in direct contact with the gate 6 and the isolation layer 9. A passivation layer 10 is deposited above the isolation layer 9 and between the source 4 and the drain 5.

[0040] In this embodiment, the surface of the isolation layer 9 is further covered with a transition layer 11, wherein the cross-sectional profile of the transition layer 11 is in the shape of a "door". The source 4 includes a four-layer source 401, and the drain 5 includes a four-layer drain 501 (both the four-layer source 401 and the four-layer drain 501 are four-layer structures arranged from bottom to top using titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au); wherein the thickness of the titanium layer is 30nm, the thickness of the aluminum layer is 50nm, the thickness of the nickel layer is 20nm, and the thickness of the gold layer is 40nm; the source-drain spacing is 400μm to 700μm, preferably 550μm). Gate 6 comprises a composite gate 602 (composite gate 602 uses a three-layer composite metal of nickel (Ni), platinum (Pt), and gold (Au) from bottom to top; wherein the thickness of the lower nickel (Ni) layer is 30nm, the thickness of the middle platinum (Pt) layer is 20nm, and the thickness of the upper gold (Au) layer is 50nm; this enhances the gate's high-temperature resistance and oxidation resistance, and the Schottky barrier height is approximately 0.86eV), composite structure layer 8 comprises composite structure 802, and isolation layer 9 comprises isolation layer 902 (isolation layer 902 is made of hafnium oxide, chemical formula is...). The thickness of the second isolation layer 902 is 500nm to 800nm, preferably 650nm; it is prepared by the second isolation layer 902 ALD method at a deposition temperature of 350℃. The passivation layer 10 includes a second passivation layer 102 (the second passivation layer 102 is made of alumina located in the lower layer). ) and the silicon nitride located on the upper layer ( () A stacked structure; wherein the total thickness of the second passivation layer 102 is 120nm to 160nm, preferably 140nm; the second passivation layer 102 is prepared by ALD+PECVD process to improve moisture resistance, oxidation resistance and ion migration resistance).

[0041] like Figure 5 As shown, composite structure 802 consists of a hafnium oxide layer 802a and an aluminum oxide layer 802b, which are arranged sequentially from top to bottom. Composite structure 802 utilizes aluminum oxide layer 802b (material: aluminum oxide, chemical formula: ...). ) and hafnium oxide layer 802a (material is hafnium oxide, chemical formula is The composite structure is a double-layer composite structure; the total thickness of the composite structure 802 is 40nm to 60nm, preferably 50nm; the thickness of the alumina layer 802b is 20nm (using ALD process), and the thickness of the hafnium oxide layer 802a is 30nm (using ALD process); this can significantly reduce the interface state density and improve the pressure resistance and stability.

[0042] The innovation of Example 2 lies in the combination of a hafnium oxide / aluminum oxide high-k double-layer composite insulation (composite structure 2 802) and a nickel / platinum / gold three-layer composite gate (composite gate 2 602). In composite structure 2 802, the lower alumina layer 2 802b acts as an interface passivation layer in direct contact with the channel layer 7. The wide bandgap and high dielectric constant of alumina enable it to effectively reduce the interface state density and serve as a reliable electric field buffer layer. The upper hafnium oxide layer 802a has a higher dielectric constant, allowing for a smaller equivalent oxide layer thickness (EOT) with a thicker physical thickness, thereby enhancing the gate's control over the channel while maintaining low gate leakage current. Composite gate 2 602 employs a three-layer composite metal structure with a lower nickel layer, a middle platinum layer, and an upper gold layer. The nickel layer forms a good Ohm-Schottky contact interface with diamond, the high work function of the platinum layer provides a stable Schottky barrier, and the gold layer ensures low resistance and excellent oxidation resistance. The second isolation layer 902 uses hafnium oxide, whose high dielectric constant and low leakage current characteristics further enhance the electrical isolation effect between the gate and the source and drain.

[0043] This embodiment leverages the material advantages of high-k dielectrics to achieve a thicker physical insulating layer while maintaining a smaller EOT, thus achieving a better balance between gate control capability and reliability. The hafnium oxide / aluminum oxide dual-layer structure design fully utilizes the interface passivation capability of alumina and the high dielectric constant of hafnium oxide, significantly reducing the interface state density and improving the breakdown characteristics of the gate dielectric. The nickel / platinum / gold triple-layer composite gate optimizes the Schottky barrier height through the gradient design of the metal work function, enhancing the gate's ability to control the depletion of channel carriers. In terms of reliability, the hafnium oxide-based high-k dielectric exhibits lower high-temperature leakage current and stronger resistance to thermal carrier injection compared to traditional silicon dioxide gate oxide layers. The alumina / silicon carbide stacked structure of passivation layer 102 effectively blocks the intrusion of external moisture and ions, significantly improving the long-term environmental stability of the device. The four-layer structure of source 401 and drain 501 further optimizes the source-drain ohmic contact, reducing the on-resistance. Overall, this embodiment achieves superior gate control characteristics and lower power consumption while maintaining high voltage withstand capability, making it particularly suitable for high-frequency switching and power conversion applications.

[0044] Example 3

[0045] like Figure 1 , Figure 6 As shown, according to one aspect of the present invention, an all-diamond heterogate Schottky MOSFET is provided, comprising a substrate layer 1 (the substrate layer 1 is made of high-resistivity intrinsic diamond material, and its thickness is 550 μm to 850 μm, preferably 700 μm; annealed in vacuum at 1450°C for 2.5 h, with a vacuum degree of...) Carrier concentration Prepared under the following conditions), wherein drain P+ layer 3 and source P+ layer 2 are deposited on the left and right sides above the substrate layer 1, respectively (both source P+ layer 2 and drain P+ layer 3 are P+ regions formed by heavily doped boron diamond, with a thickness of 300nm to 400nm, preferably 350nm; wherein the boron concentration is... (Activated by ion implantation and annealing at +950℃), wherein a source electrode 4 is deposited above the source region P+ layer 2, a drain electrode 5 is deposited above the drain region P+ layer 3, and a gate electrode 6 and an isolation layer 9 covering the surface of the gate electrode 6 are provided between the source electrode 4 and the drain electrode 5.

[0046] A channel layer 7 is formed by ion implantation inside substrate layer 1, located between source region P+ layer 2 and drain region P+ layer 3. (Channel layer 7 is a region formed using lightly boron-doped diamond, with a thickness of 150 nm to 250 nm, preferably 200 nm; wherein the boron concentration is...) (Prepared by in-situ epitaxy using MPCVD) The two ends of the channel layer 7 are in direct contact with the source region P+ layer 2 and the drain region P+ layer 3, respectively. A composite structure layer 8 is deposited above the channel layer 7, wherein the composite structure layer 8 is in direct contact with the gate 6 and the isolation layer 9. A passivation layer 10 is deposited above the isolation layer 9 and between the source 4 and the drain 5.

[0047] In this embodiment, the source 4 includes a three-layer source 402, and the drain 5 includes a three-layer drain 502 (the three-layer source 402 and the three-layer drain 502 adopt a three-layer structure with a bottom layer of titanium (Ti), a middle layer of aluminum (Al), and a top layer of gold (Au); wherein the thickness of the bottom titanium (Ti) layer is 30nm, the thickness of the middle aluminum (Al) layer is 50nm, and the thickness of the top gold (Au) layer is 40nm; and the source-drain spacing is 400μm~700μm, which is preferable). Select 550μm); Gate 6 includes a composite gate 3 603 (composite gate 3 603 adopts a composite structure of lower nickel (Ni) and upper gold (Au); wherein the thickness of the lower nickel (Ni) layer is 40nm and the thickness of the upper gold (Au) layer is 50nm; the barrier height of composite gate 3 603 is about 0.84eV), composite structure layer 8 includes composite structure 3 803, and isolation layer 9 includes isolation layer 3 903 (isolation layer 3 903 adopts silicon dioxide doped with boron element ( The structure consists of a silicon dioxide layer 10 and a passivation layer 10. The passivation layer 10 has a thickness of 600 nm to 900 nm, preferably 700 nm. The boron doping concentration is 2 at.% to 5 at.%. The isolation layer 903 is prepared by PECVD deposition at a temperature of 400℃. The internal stress is ≤150 MPa, and the breakdown field strength is ≥8 MV / cm. The passivation layer 10 includes a passivation layer 103 (the passivation layer 103 is prepared by doping boron into the lower silicon dioxide layer). ) and upper silicon nitride ( The stack of layers; wherein the passivation layer 3103 has a thickness of 120nm to 160nm, preferably 140nm; to improve environmental stability).

[0048] like Figure 7 As shown, composite structure 3 803 consists of a modified silica layer 803a and an intrinsic diamond layer 803b, wherein the modified silica layer 803a and the intrinsic diamond layer 803b are arranged sequentially from top to bottom. Composite structure 3 803 uses modified silica layer 803a (silicon dioxide doped with boron). The composite structure consists of a double-layer structure of 803a and an intrinsic diamond layer 803b; the total thickness of the composite structure 803 is 40nm to 60nm, preferably 50nm; wherein the thickness of the modified silicon dioxide layer 803a is 20nm and the thickness of the intrinsic diamond layer 803b is 30nm; the composite structure 803 is prepared by ALD+MPCVD process to achieve a low interface state density.

[0049] The innovation of Example 3 lies in the simplified and efficient solution of using a "boron-doped silica / intrinsic diamond" double-layer composite insulation (composite structure 3 803) and a nickel / gold double-layer composite gate (composite gate 3 603). In composite structure 3 803, the lower intrinsic diamond layer 2 803b directly contacts the channel layer 7, utilizing the high crystallinity and extremely low defect density of the intrinsic diamond layer to form an atomically flat channel / insulation layer interface with extremely low interface state density; the upper modified silica layer 803a modifies the dielectric properties of traditional silica by introducing boron, improving its dielectric constant and breakdown resistance while maintaining good process compatibility with silica. Composite gate 3 603 adopts a double-layer structure of lower nickel and upper gold. The nickel layer forms a stable Schottky contact with the diamond, and the gold layer provides low resistance and oxidation protection.

[0050] This embodiment achieves significant simplification of structure and process while ensuring high device performance. In the composite structure 803, the intrinsic diamond layer 803b is in contact with the channel layer 7, fundamentally eliminating interface defects caused by lattice mismatch and thermal mismatch at the heterogeneous interface, minimizing the interface state density. The boron-doped silicon dioxide layer 803a maintains good adhesion to diamond while controlling the dielectric constant and band structure through boron doping, resulting in a more uniform electric field distribution in the insulating layer. The isolation layer 903 also uses boron-doped silicon dioxide, forming a material system consistency with the modified silicon dioxide layer 803a in the composite structure 803, simplifying the process integration difficulty. This ensures effective gate control of the channel while controlling leakage current; the three-layer source 402 and drain 502 maintain low contact resistance while simplifying the process. The boron-doped silicon dioxide / intrinsic diamond stacked structure of the passivation layer 103 provides good moisture resistance, oxidation resistance, and ion migration resistance. Overall, this embodiment significantly simplifies the device structure and fabrication process while maintaining excellent electrical performance, reducing manufacturing costs. It is particularly suitable for medium and high voltage power electronics applications that are cost-sensitive and have high reliability requirements.

[0051] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A full diamond heterogate Schottky MOSFET, comprising a substrate layer (1), wherein a drain P+ layer (3) and a source P+ layer (2) are deposited on the left and right sides above the substrate layer (1), respectively, wherein a source electrode (4) is deposited above the source P+ layer (2) and a drain electrode (5) is deposited above the drain P+ layer (3), characterized in that: A gate (6) and an isolation layer (9) covering the surface of the gate (6) are provided between the source (4) and the drain (5). A channel layer (7) is formed inside the substrate layer (1) and between the source region P+ layer (2) and the drain region P+ layer (3) by ion implantation. The two ends of the channel layer (7) are in direct contact with the source region P+ layer (2) and the drain region P+ layer (3), respectively. A composite structure layer (8) is deposited above the channel layer (7), wherein the composite structure layer (8) is in direct contact with the gate (6) and the isolation layer (9). A passivation layer (10) is deposited above the isolation layer (9) and between the source (4) and the drain (5).

2. The all-diamond heterogate Schottky MOSFET according to claim 1, characterized in that: The surface of the isolation layer (9) is also covered with a transition layer (11), wherein the cross-sectional profile of the transition layer (11) is in the shape of a "door".

3. The all-diamond heterogate Schottky MOSFET according to claim 2, characterized in that: The source (4) includes a four-layer source (401), and the drain (5) includes a four-layer drain (501).

4. The all-diamond heterogate Schottky MOSFET according to claim 3, characterized in that: The gate (6) includes a composite gate (601), the composite structure layer (8) includes a composite structure (801), the isolation layer (9) includes an isolation layer (901), and the passivation layer (10) includes a passivation layer (101).

5. The all-diamond heterogate Schottky MOSFET according to claim 4, characterized in that: The composite structure (801) consists of an intrinsic diamond layer (801a), a silicon nitride layer (801b), and an aluminum oxide layer (801c), wherein the intrinsic diamond layer (801a), the silicon nitride layer (801b), and the aluminum oxide layer (801c) are arranged sequentially from top to bottom.

6. The all-diamond heterogate Schottky MOSFET according to claim 3, characterized in that: The gate (6) includes a composite gate two (602), the composite structure layer (8) includes a composite structure two (802), the isolation layer (9) includes an isolation layer two (902), and the passivation layer (10) includes a passivation layer two (102).

7. The all-diamond heterogate Schottky MOSFET according to claim 6, characterized in that: The composite structure two (802) is composed of a hafnium oxide layer (802a) and an aluminum oxide layer two (802b), wherein the hafnium oxide layer (802a) and the aluminum oxide layer two (802b) are arranged sequentially from top to bottom.

8. The all-diamond heterogate Schottky MOSFET according to claim 1, characterized in that: The source (4) includes a three-layer source (402), the drain (5) includes a three-layer drain (502); the gate (6) includes a composite gate three (603), the composite structure layer (8) includes a composite structure three (803), the isolation layer (9) includes an isolation layer three (903), and the passivation layer (10) includes a passivation layer three (103).

9. The all-diamond heterogate Schottky MOSFET according to claim 8, characterized in that: The composite structure three (803) consists of a modified silica layer (803a) and an intrinsic diamond layer two (803b), wherein the modified silica layer (803a) and the intrinsic diamond layer two (803b) are arranged sequentially from top to bottom.

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