A VDMOSFET device with mesa gate oxide and a method of fabrication

Abstract

The application discloses a VDMOSFET device with a mesa gate oxide and a preparation method thereof. The device comprises an N-type epitaxial layer, two deep P-type base regions located inside the N-type epitaxial layer and horizontally at both ends of the N-type epitaxial layer, a shallow P-type base region and a P+ region located on the upper surface of each deep P-type base region in the vertical direction, wherein the side surfaces of the shallow P-type base region and the P+ region located on the same deep P-type base region are in contact, an N+ region located in each shallow P-type base region, a gate oxide layer located on the upper surface of the N-type epitaxial layer in the vertical direction, wherein the lower surface of the gate oxide layer is in contact with part of the upper surface of the shallow P-type base region and part of the upper surface of the N+ region, and the part of the gate oxide layer between the two deep P-type base regions is in a convex structure. The application improves the single particle resistance of the device while ensuring the gate control ability of the gate electrode on the channel.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power devices, specifically relating to a VDMOSFET device with mesa gate oxide and its fabrication method. Background Technology

[0002] In the context of a generally positive outlook for the power electronics industry, power semiconductor devices, which play a decisive role in power electronics, have become a direct factor influencing the cost and efficiency of power electronic devices. Although silicon-based power devices are currently quite mature, as power semiconductors gradually develop towards higher power, higher frequency, and lower power consumption, silicon (Si)-based devices, limited by their inherent physical characteristics, are beginning to struggle in applications requiring high voltage, high temperature, high efficiency, and high power density. With the rise of third-generation semiconductor technology, third-generation wide-bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) have received widespread attention and research. Taking 4H silicon carbide as an example, its bandgap is 3.26 eV, more than three times that of traditional silicon. Therefore, in extreme operating environments where silicon is unsuitable due to its inherent limitations, the application of wide-bandgap semiconductor materials such as silicon carbide is becoming increasingly widespread. In the field of power semiconductor devices, devices need to operate under extreme conditions such as high temperature, high pressure, and even high radiation.

[0003] With the rapid development of aerospace technology, the demand for the functionality and performance of electronic equipment in the aerospace field has increased significantly. For example, power system control and distribution, high-voltage electric propulsion power supplies, and high-voltage solid-state semiconductor switches in satellites, space probes, and space stations all place higher demands on power devices. Furthermore, the harsh high-temperature and high-radiation environments in space also pose severe challenges to power electronic systems. Cosmic radiation mainly comes from cosmic rays and space particles. The most threatening sources of cosmic radiation for aerospace systems and probes are galactic cosmic rays, solar cosmic rays, and the Van Allen radiation belts near the Earth. The effects of cosmic radiation on silicon carbide power devices mainly include displacement effects, total dose effects, and single-event effects. When spacecraft traverse the Van Allen radiation belts surrounding the Earth to operate in outer space, the radiation environment seriously threatens the safety of electronic equipment. When operating in outer space for extended periods, electronic equipment must also withstand cosmic rays and solar flares. Therefore, the aerospace field not only needs high-performance power devices to improve overall performance but also radiation-resistant power devices to enhance safety and reliability in complex space environments.

[0004] Power SiC MOSFETs suffer from single-event burn-out at less than 50% of their rated voltage. Unlike silicon-based devices, they exhibit leakage current degradation (SID) when the leakage voltage exceeds 30% of the rated voltage. Therefore, research on power SiC MOSFETs primarily focuses on SID degradation and burn-out. SIDs can lead to performance degradation in power electronic systems, and in severe cases, threaten the reliability and on-orbit lifespan of satellites and spacecraft. Thus, research on radiation hardening of 4H-SiC power devices to withstand SIDs is crucial for ensuring the reliability and stability of power electronic systems in aerospace applications. However, for conventional VDMOSFETs, high-energy particle impacts on SiC VDMOSFETs easily generate large gate leakage currents, readily leading to device burn-out. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a VDMOSFET device with a mesa gate oxide and its fabrication method. In a first aspect, the present invention provides a VDMOSFET device with mesa gate oxide, comprising: N-type epitaxial layer 3; Located inside the N-type epitaxial layer 3, and situated at both ends of the N-type epitaxial layer 3 in the horizontal direction, are two deep P-type base regions 4. Along the vertical direction, there are shallow P-type base regions 5 and P+ regions 6 located on the upper surface of each deep P-type base region 4, wherein the sides of the shallow P-type base regions 5 and P+ regions 6 located on the same deep P-type base region 4 are in contact. N+ regions 7 are located within each shallow P-type base region 5; Along the vertical direction, a gate oxide layer 8 is located on the upper surface of the N-type epitaxial layer 3, wherein the lower surface of the gate oxide layer 8 is in contact with a portion of the upper surface of the shallow P-type base region 5 and a portion of the upper surface of the N+ region 7, and the portion of the gate oxide layer 8 located between the two deep P-type base regions 4 has a raised structure.

[0006] In one embodiment of the present invention, the portion of the gate oxide layer 8 located between the two deep P-type base regions 4 is a trapezoidal protrusion structure.

[0007] In one embodiment of the present invention, along the horizontal direction, the width of the shallow P-type base region 5 is smaller than the width of the contacted deep P-type base region 4, and the width of the N+ region 7 is smaller than the width of the shallow P-type base region 5 in which it is located.

[0008] In one embodiment of the present invention, the depth of the deep P-type base region 4 in the vertical direction ranges from 0.3 to 0.5 μm.

[0009] In one embodiment of the present invention, the depth of the shallow P-type base region 5 in the vertical direction ranges from 0.8 to 1 μm.

[0010] In one embodiment of the present invention, the doping concentration range of the deep P-type base region 4 is 5E17 cm⁻¹. -3 -5E18cm -3 .

[0011] In one embodiment of the present invention, the VDMOSFET device with mesa gate oxide further includes: A polysilicon gate 9 is located on the upper surface of the gate oxide layer 8 along the vertical direction; A passivation layer 10 covers the side surface of the gate oxide layer 8 and the polysilicon gate 9; The source electrode 11 is located on the upper surface of the P+ region 6 along the vertical direction, and is in contact with a portion of the upper surface of the shallow P-type base region 5 and a portion of the upper surface of the N+ region 7.

[0012] Secondly, the present invention provides a method for fabricating a VDMOSFET device with mesa gate oxide, for fabricating the aforementioned VDMOSFET device with mesa gate oxide, the method comprising: S1. An N-type buffer layer 2 and an N-type epitaxial layer 3 are sequentially grown on the upper surface of a SiC N-type substrate 1. S2. Deep P-type base regions 4 are formed at both ends of the N-type epitaxial layer 3 by P-type ion implantation; S3. Continue to grow an N-type epitaxial layer 3 on the upper surface of the sample obtained in step S2, and form a shallow P-type base region 5 on the grown N-type epitaxial layer 3 by P-type ion implantation. S4. An N+ region 7 is formed on the shallow P-type base region 5 by N-type ion implantation; S5. A P+ region 6 is formed on the shallow P-type base region 5 by P-type ion implantation. S6. A gate oxide layer 8 is formed on the upper surface of the sample obtained in step S5; S7. A polysilicon gate 9 is formed on the upper surface of the gate oxide layer 8; S8. A passivation layer 10, a source electrode 11, and a drain electrode 12 are sequentially formed on the sample obtained in step S7.

[0013] In one embodiment of the present invention, S2 specifically includes: A mask layer is grown on the upper surface of the N-type epitaxial layer 3 by CVD. Then, the mask layer is coated, exposed, developed, etched, and the mask layer is removed in sequence to form a deep P-type base region implantation window. P-type ion implantation is then performed to form a deep P-type base region 4 in the N-type epitaxial layer 3. After the ion implantation is completed, the mask layer is removed and the obtained sample is cleaned into a light film.

[0014] In one embodiment of the present invention, S6 specifically includes: On the upper surface of the sample obtained in step S5, a gate oxide layer is grown by dry oxygen oxidation at 1300℃ for 30 min. Then, it is annealed in a NO atmosphere at 1300℃ for 30 min to form the gate oxide layer 8. After that, the sample is cleaned. Then, a portion of the gate oxide layer 8 is etched to expose a portion of the upper surface of the shallow P-type base region 5, a portion of the upper surface of the N+ region 7, and the upper surface of the P+ region 6, while making the portion of the gate oxide layer 8 between the two deep P-type base regions 4 a raised structure. After etching, the obtained sample is cleaned again.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention utilizes a long mesa gate oxide structure to weaken the high electric field in the gate oxide layer of a conventional SiC VDMOSFET device under low drain-source bias and heavy particle irradiation. This ensures the gate electrode's control capability over the channel while simultaneously increasing the thickness of the gate oxide layer above the JFET, thereby strengthening the area of ​​the gate oxide layer susceptible to damage during single-event leakage degradation of the SiC VDMOSFET. This invention requires no additional processing steps; a simple etching process is used to form the long mesa gate oxide structure, improving the device's single-event immunity while maintaining the gate electrode's control capability over the channel.

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a VDMOSFET device with mesa gate oxide provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a sample prepared in step S1 of the fabrication method of the VDMOSFET device with mesa gate oxide provided in the embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of another sample prepared in step S1 of the fabrication method of the VDMOSFET device with mesa gate oxide provided in the embodiment of the present invention. Figure 4This is a schematic diagram of the sample prepared in step S2 of the fabrication method of the VDMOSFET device with mesa gate oxide provided in the embodiment of the present invention. Figure 5 This is a schematic diagram of the sample prepared in step S3 of the fabrication method of the VDMOSFET device with mesa gate oxide provided in the embodiment of the present invention. Figure 6 This is a schematic diagram of the sample prepared in step S4 of the fabrication method of the VDMOSFET device with mesa gate oxide provided in the embodiment of the present invention. Figure 7 This is a schematic diagram of the sample prepared in step S5 of the fabrication method of the VDMOSFET device with mesa gate oxide provided in the embodiment of the present invention. Figure 8 This is a schematic diagram of the structure of a sample prepared in step S6 of the fabrication method of the VDMOSFET device with mesa gate oxide provided in the embodiment of the present invention. Figure 9 This is a schematic diagram of the structure of another sample prepared in step S6 of the fabrication method of the VDMOSFET device with mesa gate oxide provided in the embodiment of the present invention. Figure 10 This is a schematic diagram of the sample prepared in step S7 of the fabrication method of the VDMOSFET device with mesa gate oxide provided in the embodiment of the present invention. Detailed Implementation

[0018] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0019] This invention proposes a VDMOSFET device with a long mesa gate oxide layer and its fabrication method. Compared to conventional VDMOSFET vertical double-diffused field-effect transistors, the VDMOSFET device structure with a long mesa gate oxide layer has advantages. When a SiC VDMOSFET is bombarded by high-energy particles, the conventional gate oxide structure generates a large gate leakage current, leading to device burn-out. The VDMOSFET with a long mesa gate oxide layer can reduce the electric field inside the gate, thereby reducing the gate leakage current and improving the device's resistance to single-particle irradiation, thus raising the threshold for leakage degradation and burn-out.

[0020] In a first aspect, embodiments of the present invention provide a VDMOSFET device with a mesa gate oxide. The device includes: N-type epitaxial layer 3; Located inside the N-type epitaxial layer 3, and at the two ends of the N-type epitaxial layer 3 in the horizontal direction, are two deep P-type base regions 4. Along the vertical direction, shallow P-type base regions 5 and P+ regions 6 are located on the upper surface of each deep P-type base region 4, wherein the sides of shallow P-type base regions 5 and P+ regions 6 located on the same deep P-type base region 4 are in contact. N+ regions 7 are located within each shallow P-type base region 5; Along the vertical direction, a gate oxide layer 8 is located on the upper surface of the N-type epitaxial layer 3, wherein the lower surface of the gate oxide layer 8 is in contact with a portion of the upper surface of the shallow P-type base region 5 and a portion of the upper surface of the N+ region 7, and the portion of the gate oxide layer 8 located between the two deep P-type base regions 4 is a protruding structure, thereby forming a gate oxide layer structure with a long mesa.

[0021] For example, Figure 1 This is a schematic diagram of a VDMOSFET device with mesa gate oxide provided in an embodiment of the present invention. Figure 1 As shown, the gate oxide layer 8 is disposed on the upper surface of the device and covers at least part of the shallow P-type base region 5, the N-type epitaxial layer 3 and the region above the JFET region. The gate oxide layer 8 located above the JFET region forms a long mesa structure through a trapezoidal protrusion structure to increase the gate oxide thickness or extend the gate oxide mesa length in this region, thereby weakening the high electric field in the gate oxide layer during heavy particle irradiation, reducing the gate leakage current, and improving the device's resistance to single-event leakage degradation and single-event burn-off.

[0022] Continue to refer to Figure 1 The device also includes: Along the vertical direction, the N-type buffer layer 2 is located on the lower surface of the N-type epitaxial layer 3; Along the vertical direction, the N-type substrate 1 is located on the lower surface of the N-type buffer layer 2; Along the vertical direction, a polysilicon gate 9 is located on the upper surface of the gate oxide layer 8; A passivation layer 10 covers the side of the gate oxide layer 8 and the polysilicon gate 9; The source electrode 11 is located on the upper surface of the P+ region 6 along the vertical direction, and is in contact with a portion of the upper surface of the shallow P-type base region 5 and a portion of the upper surface of the N+ region 7. Drain electrode 12 is located on the lower surface of N-type substrate 1 along the vertical direction.

[0023] In this invention, a polysilicon gate 9 is disposed above the gate oxide layer 8 to control the opening and closing of the channel on the surface of the shallow P-type base region 5 under gate bias. The polysilicon gate 9 and the gate oxide layer 8 together constitute a gate-controlled structure. A SiO2 passivation layer 10 is disposed on the device surface to cover and protect the polysilicon gate 9 and the active region surface of the device, reducing the impact of surface contamination, moisture, and the external environment on device reliability. The source electrode 11 is disposed on the front side of the device and forms an ohmic contact with the N+ region 7 and the P+ region 6 to draw out the source current. Simultaneously, the P+ region 6 fixes the potential of the P-type base region, suppressing the turn-on of parasitic transistors. The drain electrode 12 is disposed on the back side of the N-type substrate 1 and forms an ohmic contact with the N-type substrate 1 to draw out the drain current, thus forming a vertical conductive path in the device.

[0024] In this invention, the N-type substrate 1 can be a SiC N-type substrate. The doping concentration of the N-type substrate 1 is 5E18cm⁻¹. -3 The doping ions can be impurity ions such as N (nitrogen) and P (phosphorus) that can form N-type semiconductors.

[0025] In this invention, the doping concentration of the N-type buffer layer 2 is 1E18cm⁻¹. -3 The doping ions can be impurity ions such as N (nitrogen) and P (phosphorus) that can form N-type semiconductors.

[0026] In this invention, the doping concentration range of the N-type epitaxial layer 3 is 5E15 cm⁻¹. -3 -7E15cm -3 The doping ions can be impurity ions such as N (nitrogen) and P (phosphorus) that can form N-type semiconductors.

[0027] In this invention, the doping concentration range of the deep P-type base region 4 is 5E17-5E18 cm⁻¹. -3 The doping ions can be impurity ions such as Al (aluminum) that can form P-type semiconductors.

[0028] In this invention, the doping concentration of the shallow p-type base region 5 ranges from 1E16 to 5E17 cm⁻¹. -3 The doping ions can be impurity ions such as Al (aluminum) that can form P-type semiconductors.

[0029] In this invention, the doping concentration range of P+ region 6 is 5E18cm. -3 -1E20cm -3 The preferred doping concentration range is 6E19 cm⁻¹. - ³-1E20 cm - ³, the doping ions can be impurity ions such as Al (aluminum) that can form P-type semiconductors.

[0030] In this invention, the doping concentration range of N+ region 7 is 1E19cm.-3 -5E20cm -3 The preferred doping concentration range is 1E19 cm⁻¹. - ³~1E20 cm - ³, the doping ions can be impurity ions such as N (nitrogen) and P (phosphorus) that can form N-type semiconductors; and, the N+ region 7 forms an ohmic contact with the source electrode 8.

[0031] In this invention, along the vertical direction, the depth range of the deep P-type base region 4 is 0.3-0.5 μm, the depth range of the shallow P-type base region 5 is 0.8-1 μm, the depth range of the P+ region 6 is 0.5-1 μm, and the depth range of the N+ region 7 is 0.3-0.5 μm.

[0032] In this invention, such as Figure 1 As shown, the width of the shallow P-type base region 5 is smaller than the width of the contacting deep P-type base region 4, and the width of the N+ region 7 is smaller than the width of the shallow P-type base region 5. In this invention, the lateral width range of the deep P-type base region 4 is preferably 2μm-5μm, the lateral width range of the shallow P-type base region 5 is preferably 1μm-3μm, the lateral width range of the P+ region 6 is preferably 0.5μm-2μm, and the lateral width range of the N+ region 7 is preferably 0.5μm-2μm. It should be noted that the lateral widths of the deep P-type base region 4, shallow P-type base region 5, P+ region 6, and N+ region 7 can be adjusted according to the cell size, channel length, JFET region width, and voltage rating of the device, and are not limited to the above preferred ranges. The combined depth and width of each region allows the device to improve the electric field distribution near the gate oxide layer while ensuring channel gate control capability and conduction performance, thereby enhancing the single-event irradiation resistance of the SiC VDMOSFET device.

[0033] For example, the thickness of the N-type substrate 1 is 350 μm, and the thickness of the N-buffer layer 2 is 1 μm.

[0034] This invention utilizes the long mesa gate oxide structure to weaken the high electric field caused by the gate oxide layer in ordinary SiC VDMOSFET devices under low drain-source bias and heavy particle irradiation. While ensuring the gate electrode's gate control capability of the channel, it also increases the thickness of the gate oxide layer above the JFET, thereby strengthening the area of ​​the gate oxide layer that is easily damaged in single-event leakage degradation of SiC VDMOSFET. This ensures the gate electrode's gate control capability of the channel while improving the device's single-event immunity.

[0035] Secondly, embodiments of the present invention provide a method for fabricating a VDMOSFET device with a mesa gate oxide. The method includes: S1. An N-type buffer layer 2 and an N-type epitaxial layer 3 are sequentially grown on the upper surface of a SiC N-type substrate 1.

[0036] Specifically, an N-type buffer layer 2 is epitaxially grown on the upper surface of a SiC N-type substrate 1, wherein the SiC substrate 1 is an N-type substrate with a thickness of 350 μm and a doping concentration of 5E18 cm⁻¹. -3 The thickness of N-buffer layer 2 is 1 μm, and the doping concentration is 1E18 cm⁻¹. -3 The structural diagram of the obtained sample is shown below. Figure 2 As shown, the thickness of the N-type buffer layer 2 is determined by the voltage rating of the device. For a typical 1200V device, the doping concentration and thickness of the N-type drift region are 7E15cm. -3 And 11 μm. Next, an N-type epitaxial layer 3 was epitaxially grown on the upper surface of the N-type buffer layer 2, and the structural schematic diagram of the obtained sample is shown below. Figure 3 As shown, the thickness of the N-type epitaxial layer 3 is 11 μm, and the doping concentration is 7E15cm. -3 The doping ions can be impurity ions such as N (nitrogen) and P (phosphorus) that can form N-type semiconductors.

[0037] S2. Deep P-type base regions 4 are formed at both ends of the N-type epitaxial layer 3 by P-type ion implantation.

[0038] Specifically, a mask layer is grown on the upper surface of the N-type epitaxial layer 3 using a CVD process. Then, processes such as resist coating, exposure, development, mask layer etching, and resist removal are performed sequentially to form a deep P-type base region implantation window. Subsequently, P-type ion implantation is performed to form a deep P-type base region 4 within the N-type epitaxial layer 3. A schematic diagram of the resulting sample structure is shown below. Figure 4 As shown. After ion implantation, the mask layer is removed and the resulting sample is cleaned into a light film.

[0039] S3. Continue to grow an N-type epitaxial layer 3 on the upper surface of the sample obtained in step S2, and form a shallow P-type base region 5 on the grown N-type epitaxial layer 3 by P-type ion implantation.

[0040] Specifically, an N-type epitaxial layer 3 is grown on the upper surface of the sample obtained in step S2. Then, a shallow P-type base region 5 is formed using the same or similar photolithography, etching, and ion implantation processes as in step S2. After ion implantation, the mask layer is removed, and the resulting sample is cleaned into a wafer. The final sample structure is shown in the schematic diagram below. Figure 5 As shown.

[0041] S4. An N+ region 7 is formed on the shallow P-type base region 5 by N-type ion implantation.

[0042] Specifically, a 2 μm thick SiO2 film is deposited on the upper surface of the sample obtained in step S3 using a CVD process as an etching mask. Subsequently, processes such as resist coating, exposure, development, etching the mask layer, and resist removal are performed to form an N+ region implantation window. Then, N-type ion implantation is performed to form an N+ region 7 within the shallow P-type base region 5. A schematic diagram of the resulting sample structure is shown below. Figure 6 As shown, the depth of region 7 in the N+ region ranges from 0.3 to 0.5 μm, and the doping concentration ranges from 1E19 cm⁻¹. -3 -1E20cm -3 After ion implantation, the mask layer is removed and the resulting sample is cleaned into a light film.

[0043] S5. A P+ region 6 is formed on the shallow P-type base region 5 by P-type ion implantation.

[0044] Specifically, a 2μm thick SiO2 film is deposited on the upper surface of the sample obtained in step S4 using a CVD process as an etching mask. Subsequently, processes such as resist coating, exposure, development, etching the mask layer, and resist removal are performed to form a P+ region implantation window. Then, P-type ion implantation is performed to form P+ region 6, where the depth of P+ region 6 ranges from 0.5 to 1μm, and the doping concentration ranges from 6E19 cm⁻¹. -3 -1E20cm -3 After ion implantation, the mask layer was removed and the sample was cleaned to form a light sheet. Subsequently, activation annealing was performed at 1500℃-2000℃ for 30 min to electrically activate the implanted ions. After annealing, the sample was cleaned again to form a light sheet. The structural schematic diagram of the obtained sample is shown below. Figure 7 As shown.

[0045] S6. A gate oxide layer 8 is formed on the upper surface of the sample obtained in step S5.

[0046] Here, after the active region is fabricated, a gate oxide layer can be grown on the upper surface of the sample obtained in step S5 by dry oxygen oxidation at 1300℃ for 30 min. Then, it is annealed in a NO atmosphere at 1300℃ for 30 min to improve the SiC / SiO2 interface quality, reduce the interface state density, and form the gate oxide layer 8. After cleaning the sample, the structural schematic diagram of the obtained sample is shown below. Figure 8 As shown. Next, the gate oxide layer 8 is etched to form a gate oxide layer structure with long mesa in the JFET region or the region where the gate leakage field is concentrated. After etching, the obtained sample is cleaned into a wafer. A schematic diagram of the obtained sample structure is shown below. Figure 9 As shown.

[0047] S7. A polysilicon gate 9 is formed on the upper surface of the gate oxide layer 8.

[0048] Specifically, a 0.5 μm thick polysilicon layer is grown and deposited on the upper surface of the gate oxide layer 8. The polysilicon layer is then subjected to N-type doping and activation annealing to reduce the polysilicon gate resistance. Subsequently, the polysilicon layer is patterned using photolithography and etching processes to form the polysilicon gate 9. A schematic diagram of the resulting sample structure is shown below. Figure 10 As shown.

[0049] S8. A passivation layer 10, a source electrode 11, and a drain electrode 12 are sequentially formed on the sample obtained in step S7.

[0050] Specifically, after fabricating the polysilicon gate 9, conventional SiC VDMOSFET processes are used to fabricate the SiO2 passivation layer 10, source electrode 11, and drain electrode 12. The source electrode 11 forms an ohmic contact with the N+ region 7 and the P+ region 6, and the drain electrode 12 is formed on the back side of the N-type substrate 1 and forms an ohmic contact with it, ultimately resulting in the following... Figure 1 The diagram shows a SiCVD MOSFET device structure with mesa gate oxide.

[0051] The fabrication method proposed in this invention does not require additional processes. It uses a simple etching process to form a long mesa gate oxide structure, which improves the device's single-particle rejection performance while ensuring the gate electrode's gate control capability over the channel.

[0052] In the description of this invention, it should be understood that the terms "lateral", "width", "thickness", "upper", "lower", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0053] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0054] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0055] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A VDMOSFET device with mesa gate oxide, characterized in that, include: N-type epitaxial layer (3); Located inside the N-type epitaxial layer (3), and at the two ends of the N-type epitaxial layer (3) in the horizontal direction respectively; Along the vertical direction, there are shallow P-type base regions (5) and P+ regions (6) located on the upper surface of each deep P-type base region (4), wherein the sides of the shallow P-type base regions (5) and the P+ regions (6) located on the same deep P-type base region (4) are in contact with each other; The N+ region (7) is located within each shallow P-type base region (5); Along the vertical direction, there is a gate oxide layer (8) on the upper surface of the N-type epitaxial layer (3), wherein the lower surface of the gate oxide layer (8) is connected to a portion of the upper surface of the shallow P-type base region (5) and a portion of the upper surface of the N+ region (7), and the portion of the gate oxide layer (8) between the two deep P-type base regions (4) is a protruding structure.

2. The VDMOSFET device with mesa gate oxide according to claim 1, characterized in that, The portion of the gate oxide layer (8) located between the two deep P-type base regions (4) is a trapezoidal protrusion structure.

3. The VDMOSFET device with mesa gate oxide according to claim 1, characterized in that, Along the horizontal direction, the width of the shallow P-type base region (5) is smaller than the width of the deep P-type base region (4) it contacts, and the width of the N+ region (7) is smaller than the width of the shallow P-type base region (5) it is located in.

4. The VDMOSFET device with mesa gate oxide according to claim 1, characterized in that, The depth of the deep P-type base region (4) in the vertical direction ranges from 0.3 to 0.5 μm.

5. The VDMOSFET device with mesa gate oxide according to claim 1, characterized in that, The depth of the shallow P-type base region (5) in the vertical direction ranges from 0.8 to 1 μm.

6. The VDMOSFET device with mesa gate oxide according to claim 1, characterized in that, The doping concentration range of the deep P-type base region (4) is 5E17 cm⁻¹. -3 -5E18cm -3 .

7. The VDMOSFET device with mesa gate oxide according to claim 1, characterized in that, The VDMOSFET device with mesa gate oxide also includes: A polysilicon gate (9) is located on the upper surface of the gate oxide layer (8) along the vertical direction; A passivation layer (10) covering the side of the gate oxide layer (8) and the polysilicon gate (9); The source electrode (11) is located on the upper surface of the P+ region (6) in the vertical direction and is in contact with a portion of the upper surface of the shallow P-type base region (5) and a portion of the upper surface of the N+ region (7).

8. A method for fabricating a VDMOSFET device with mesa gate oxide, characterized in that, The method for fabricating the VDMOSFET device with mesa gate oxide as described in any one of claims 1 to 7 comprises: S1. An N-type buffer layer (2) and an N-type epitaxial layer (3) are sequentially grown on the upper surface of a SiC N-type substrate (1). S2. Deep P-type base regions (4) are formed at both ends of the N-type epitaxial layer (3) by P-type ion implantation; S3. Continue to grow an N-type epitaxial layer (3) on the upper surface of the sample obtained in step S2, and form a shallow P-type base region (5) on the grown N-type epitaxial layer (3) by P-type ion implantation. S4. An N+ region (7) is formed on the shallow P-type base region (5) by N-type ion implantation; S5. A P+ region (6) is formed on the shallow P-type base region (5) by P-type ion implantation; S6. A gate oxide layer (8) is formed on the upper surface of the sample obtained in step S5; S7. A polysilicon gate (9) is formed on the upper surface of the gate oxide layer (8); S8. A passivation layer (10), a source electrode (11), and a drain electrode (12) are sequentially formed on the sample obtained in step S7.

9. The VDMOSFET device with mesa gate oxide according to claim 8, characterized in that, S2 specifically includes: A mask layer is grown on the upper surface of the N-type epitaxial layer (3) by CVD. Then, the mask layer is coated, exposed, developed, etched and removed in sequence to form a deep P-type base region implantation window. P-type ion implantation is then performed to form a deep P-type base region (4) in the N-type epitaxial layer (3). After the ion implantation is completed, the mask layer is removed and the obtained sample is cleaned into a light film.

10. The VDMOSFET device with mesa gate oxide according to claim 8, characterized in that, S6 specifically includes: On the upper surface of the sample obtained in step S5, a gate oxide layer is grown by dry oxygen oxidation at 1300℃ for 30 min. Then, it is annealed in NO atmosphere at 1300℃ for 30 min to form a gate oxide layer (8). After that, the sample is cleaned. Then, a part of the gate oxide layer (8) is etched to expose part of the upper surface of the shallow P-type base region (5), part of the upper surface of the N+ region (7) and the upper surface of the P+ region (6), while making the part of the gate oxide layer (8) between the two deep P-type base regions (4) a raised structure. After the etching is completed, the obtained sample is cleaned.

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