Semiconductor device and method of manufacture, power module, power conversion circuit and vehicle

Abstract

The application discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and belongs to the technical field of semiconductors. The semiconductor device comprises a semiconductor body, a first region, a well region, a second region and a third region, the first region is located on a first surface, the well region is located on a side of the first region away from the first surface, the second region extends from the first surface into the semiconductor body, the third region is arranged close to the bottom of the second region and is connected with the second region, and the doping concentration of the third region is less than that of the second region. The semiconductor body is provided with a gate trench extending from the first surface into the semiconductor body. An insulating layer is located on the surface of the gate trench. A gate structure is filled in the gate trench. A source electrode is located on the first surface. A drain electrode is located on the second surface. The application can reduce the electric field peak value at the bottom of the gate trench, reduce the risk of device breakdown, reduce the parasitic capacitance and improve the high-frequency characteristics of the device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a semiconductor device and its preparation method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] SiC MOSFETs (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors) have evolved from planar to trench types. By improving the gate structure, the current flow direction on the gate changed from planar to vertical. However, SiC MOSFETs in related technologies have large parasitic capacitances, affecting the high-frequency characteristics of the device, and the insulating layer at the bottom of the gate trench has an electric field peak, which is prone to breakdown. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, which can reduce the electric field peak at the bottom of the gate trench, reduce the risk of device breakdown, reduce parasitic capacitance, and improve the high-frequency characteristics of the device.

[0004] In a first aspect, this application provides a semiconductor device, comprising: A semiconductor body includes a first surface and a second surface disposed opposite to each other in the thickness direction. The semiconductor body includes a first region having a first conductivity type and a well region, a second region, and a third region having a second conductivity type. The first conductivity type is opposite to the second conductivity type. The first region is located on the first surface, and the well region is located on the side of the first region away from the first surface. The second region extends from the first surface into the semiconductor body, and the third region is located in the semiconductor body and disposed near the bottom of the second region. The doping concentration of the third region is less than that of the second region. The semiconductor body has gate trenches extending from the first surface into the semiconductor body. The gate trenches extend along a first direction, and the third region is connected to the second region in the first direction. The second region separates two adjacent gate trenches. The first direction is perpendicular to the thickness direction. An insulating layer is located on the surface of the gate trench; A gate structure is filled in the gate trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

[0005] According to the semiconductor device of this application, by setting a third region near the bottom of the second region and connecting the third region to the second region, the doping concentration of the third region is less than that of the second region, the device structure is vertically adaptively grounded, and the depletion region is confined to the vicinity of the third region when reverse biased, thereby reducing the electric field peak at the bottom of the gate trench, reducing the risk of device breakdown, reducing the parasitic capacitance of the device, and improving the high-frequency characteristics of the device.

[0006] According to one embodiment of this application, the third region includes a plurality of sub-regions, which are connected sequentially along the thickness direction, and adjacent sub-regions are partially offset in the thickness direction.

[0007] According to one embodiment of this application, the second region includes a shielding region and a shielding scattering region covering the shielding region, and the third region includes a buried layer region and a buried layer scattering region covering the buried layer region; The shielding area penetrates the buried layer area along the thickness direction; or, the bottom of the shielding area is connected to the buried layer area; or, the shielding area and the buried layer area are spaced apart along the thickness direction, and the shielding scattering area is connected to the buried layer scattering area.

[0008] According to one embodiment of this application, a plurality of second regions located on one side of the gate trench are spaced apart along the first direction.

[0009] According to one embodiment of this application, the third region extends along the first direction and is connected to a plurality of second regions located on one side of the gate trench.

[0010] According to one embodiment of this application, a plurality of third regions located on one side of the gate trench are alternately arranged and connected with a plurality of second regions along the first direction.

[0011] According to one embodiment of this application, the gate trench has a plurality of third regions and a plurality of second regions arranged alternately along the first direction on both sides in the second direction, the second direction being perpendicular to the first direction and the thickness direction; The second regions on both sides of the gate trench are disposed opposite to each other in the second direction, and the third regions on both sides of the gate trench are disposed opposite to each other in the second direction; or, The second regions on both sides of the gate trench are offset in the second direction, and the third regions on both sides of the gate trench are offset in the second direction.

[0012] According to one embodiment of this application, the third region disposed opposite to each other in the second direction further extends along the second direction to the bottom of the gate trench and is connected thereto.

[0013] According to one embodiment of this application, the semiconductor body further includes a third region extension region having a second conductivity type, the third region extension region being connected to the bottom of the third region and extending along the thickness direction; The third region extension area is spaced apart from the second surface, or the third region extension area extends to the second surface along the thickness direction.

[0014] Secondly, this application provides a method for fabricating a semiconductor device, comprising: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other in the thickness direction, the semiconductor body including a first region having a first conductivity type and a well region, a second region and a third region having a second conductivity type, the first conductivity type being opposite to the second conductivity type, the first region being located on the first surface, the well region being located on the side of the first region away from the first surface, the second region extending from the first surface into the semiconductor body, the third region being located in the semiconductor body and disposed near the bottom of the second region, the doping concentration of the third region being less than the doping concentration of the second region; A gate trench is formed extending from the first surface into the semiconductor body; the gate trench extends along a first direction, the third region is connected to the second region in the first direction, the second region separates two adjacent gate trenches, and the first direction is perpendicular to the thickness direction; An insulating layer is formed on the surface of the gate trench; A gate structure is filled in the gate trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

[0015] Thirdly, this application provides a power module including a substrate and a semiconductor device as described in the first aspect above, wherein the substrate is used to support the semiconductor device.

[0016] Fourthly, this application provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and a semiconductor device as described in the first aspect above, the semiconductor device being electrically connected to the circuit board.

[0017] Fifthly, this application provides a vehicle including a load and a power conversion circuit as described in the fourth aspect above, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of the semiconductor device provided in the embodiments of this application; Figure 2 This is one of the top views of the gate trench, the second region, and the third region in the semiconductor device provided in the embodiments of this application; Figure 3 This is one of the cross-sectional schematic diagrams of the semiconductor device provided in the embodiments of this application; Figure 4 This is a second cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 5 This is the third cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 6 This is a second top view of the gate trench, the second region, and the third region in the semiconductor device provided in the embodiments of this application; Figure 7 This is the fourth cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 8 This is the third top view of the gate trench, the second region, and the third region in the semiconductor device provided in the embodiments of this application; Figure 9 This is the fifth cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 10 This is the fourth top view of the gate trench, the second region, and the third region in the semiconductor device provided in the embodiments of this application; Figure 11 This is the sixth cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 12 This is the seventh cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 13 This is the eighth cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 14This is the ninth cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 15 This is the tenth cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 16 This is a schematic flowchart of the method for fabricating a semiconductor device provided in an embodiment of this application; Figure 17 This is one of the structural schematic diagrams in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 18 This is a second schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 19 This is the third schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 20 This is the fourth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 21 This is the fifth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 22 This is the sixth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 23 This is the seventh schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 24 This is the eighth schematic diagram of the structure in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 25 This is the ninth schematic diagram of the structure in the method for fabricating a semiconductor device provided in the embodiments of this application. Detailed Implementation

[0020] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0021] The following description, with reference to the accompanying drawings, describes the semiconductor device and its fabrication method, power module, power conversion circuit, and vehicle provided in embodiments of this application.

[0022] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. Figure 2 This is one of the top views of the gate trench, the second region, and the third region in the semiconductor device provided in the embodiments of this application. Figure 3 for Figure 2A schematic diagram of the cross-section at the dashed line AA'. Figure 4 for Figure 2 A schematic diagram of the cross-section at the dashed line BB'. Figure 5 for Figure 2 A cross-sectional view at the dashed line CC'. The semiconductor device can be a MOSFET.

[0023] like Figure 1 As shown, the semiconductor device provided in this application embodiment includes a semiconductor body 1. The semiconductor body 1 includes a first surface S1 and a second surface S2 disposed opposite to each other along the thickness direction X. The semiconductor body 1 includes a first region 14 having a first conductivity type and a well region 12 having a second conductivity type. The first region 14 is located on the first surface S1, and the well region 12 is located on the side of the first region 14 facing away from the first surface S1. The second conductivity type is opposite to the first conductivity type.

[0024] Combination Figures 2 to 5 As shown, the semiconductor body 1 further includes a second region 15 and a third region 16, both of which are of a second conductivity type. The second region 15 extends from the first surface S1 into the semiconductor body 1. For example, the second region 15 may be disposed on the first surface S1 and extend into the semiconductor body 1. The third region 16 is disposed near the bottom of the second region 15 and connected to it, and the doping concentration of the third region 16 is lower than that of the second region 15. For example, the third region 16 includes a buried layer region 161 and a buried scattering region 162 covering the buried layer region 161. The second region 15 includes a shielding region 151 and a shielding scattering region 152 covering the shielding region 151. The doping concentration of the buried layer region 161 is lower than that of the shielding region 151.

[0025] The semiconductor body 1 is provided with a gate trench 13 extending from the first surface S1 into the semiconductor body 1.

[0026] The semiconductor device also includes an insulating layer 2, a gate structure 3, a source 4, and a drain 5.

[0027] The insulating layer 2 is located on the surface of the gate trench 13, that is, the insulating layer 2 covers the bottom surface and sidewalls of the gate trench 13. The material of the insulating layer 2 may include silicon oxide, etc.

[0028] The gate structure 3 fills the gate trench 13. The insulating layer 2 is located between the gate trench 13 and the gate structure 3, and is used to isolate the gate structure 3 from the semiconductor body 1. The material of the gate structure 3 may include polysilicon, etc.

[0029] The source electrode 4 is located on the first surface S1 of the semiconductor body 1. The source electrode 4 is in contact with the first region 14 and the second region 15. The material of the source electrode 4 may include metals such as aluminum, copper, and nickel.

[0030] The semiconductor body 1 may include a substrate 10 and an epitaxial layer 11, wherein the epitaxial layer 11 is located on one side of the thickness direction X of the substrate 10. The epitaxial layer 11 may include a single film layer, or it may include a stacked structure formed by multiple film layers. The epitaxial layer 11 can be obtained through a single epitaxial operation or through multiple epitaxial operations.

[0031] The material of the substrate 10 and the epitaxial layer 11 can be the same or different. In some embodiments, both the epitaxial layer 11 and the substrate 10 can be made of SiC. SiC has excellent physical and electrical properties. Compared with silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency applications.

[0032] When the semiconductor body 1 includes a substrate 10 and an epitaxial layer 11, the second surface S2 is the surface of the substrate 10 away from the epitaxial layer 11, and the first surface S1 is the surface of the epitaxial layer 11 away from the substrate 10. Figure 1 The second surface S2 shown is the bottom surface of the semiconductor body 1, and the first surface S1 is the top surface of the semiconductor body 1.

[0033] The substrate 10 is doped with a first conductivity type, which can be either N-type or P-type. The substrate 10 can be doped with N-type dopant ions to form an N-type substrate; N-type dopant ions can include P (phosphorus) or N (nitrogen) ions, etc. The substrate 10 can also be doped with P-type dopant ions to form a P-type substrate; P-type dopant ions can include Al (aluminum) ions or B (boron) ions, etc.

[0034] The epitaxial layer 11 is doped with the first conductivity type, meaning that the epitaxial layer 11 has the same doping type as the substrate 10. When the epitaxial layer 11 comprises multiple layers, the doping types of these multiple layers can be the same.

[0035] In the case where the semiconductor body 1 includes a substrate 10 and an epitaxial layer 11, the second region 15 extends from the first surface S1 into the epitaxial layer 11, and the third region 16 is located in the epitaxial layer 11.

[0036] As an example, the semiconductor body 1 is an N-type semiconductor body, that is, the substrate 10 is an N-type substrate and the epitaxial layer 11 is an N-type epitaxial layer. The well region 12 is a P-type well region (PW), the first region 14 is an N-type doped region, the second region 15 is a P-type doped region, and the third region 16 is a P-type doped region.

[0037] In the case where the semiconductor body 1 includes a substrate 10 and an epitaxial layer 11, the gate trench 13 extends from the first surface S1 into the epitaxial layer 11. The height of the second region 15 along the thickness direction X can be greater than the height of the gate trench 13 along the thickness direction X. The third region 16 can be connected to the bottom of the second region 15, and the third region 16 can also extend to the bottom of the gate trench 13.

[0038] In some embodiments, the semiconductor device may further include a dielectric layer 6 located between the source 4 and the gate structure 3, for isolating the source 4 from the gate structure 3. The material of the dielectric layer 6 may include silicon oxide, silicon nitride, etc.

[0039] The drain electrode 5 is located on the second surface S2 of the semiconductor body 1. The drain electrode 5 may cover the second surface S2 of the semiconductor body 1. The material of the drain electrode 5 may include metals such as aluminum, copper, and nickel.

[0040] In this embodiment, the second region 15 can serve as a shielding layer to block electromagnetic or electric field interference, and the third region 16 can serve as a buried layer embedded within the epitaxial layer 11. The third region 16 is located near the bottom of the second region 15, and the third region 16 and the second region 15 are connected by scattering in the first direction Y. By utilizing the vertical structure of the device to adaptively ground longitudinally (i.e., along the thickness direction X), the potential stability of the third region 16 is improved, and the structure is simple. Moreover, the third region 16 has the opposite doping type to the epitaxial layer 11, forming a PN junction. When reverse biased, the depletion region is confined to the vicinity of the third region 16, reducing the electric field peak at the bottom of the gate trench 13, reducing the risk of device breakdown, and reducing the parasitic capacitance (Cgd) of the device, thereby improving the high-frequency characteristics of the device.

[0041] In some embodiments, combined with Figure 2 As shown, the gate trench 13 extends along the first direction Y, and the semiconductor body 1 includes a plurality of second regions 15. One or more second regions 15 are respectively arranged on both sides of the gate trench 13 along the second direction Z. The plurality of second regions 15 located on one side of the gate trench 13 are distributed at intervals along the first direction Y, and the first direction Y is perpendicular to the thickness direction X.

[0042] For example, the plurality of second regions 15 on one side can be evenly spaced, and the distance between any two adjacent second regions 15 along the first direction Y is equal to a preset distance. In some embodiments, the plurality of second regions 15 can also be unevenly spaced, and the distance between any two adjacent second regions 15 along the first direction Y is unequal.

[0043] The second direction Z is perpendicular to both the thickness direction X and the first direction Y. Multiple second regions 15 can be connected to a third region 16. The dimension of the cross-section of the second region 15 parallel to the first direction Y and the second direction Z is approximately 0.8 μm. 0.8um.

[0044] In related technologies, the second region extends along the first direction Y, resulting in a larger cell pitch, which leads to a lower power density and a larger on-resistance.

[0045] In this embodiment, the size of the second region 15 is reduced, and multiple second regions 15 are distributed at intervals along the first direction Y. This reduces the cell spacing, increases the current flow path, and achieves ultra-low on-resistance. Moreover, reducing the cell spacing makes the electric field distribution more uniform, thereby improving the avalanche tolerance of the device.

[0046] In some embodiments, the semiconductor body 1 includes a plurality of third regions 16, which are alternately arranged with and scatter-connected to a plurality of second regions 15 along a first direction Y.

[0047] It should be noted that the second region 15 and the third region 16 are scatteringly connected. For example, the second region 15 extends along the thickness direction X, and the third region 16 extends along the first direction Y. The thickness direction X intersects the first direction Y, and the multiple third regions 16 are scattering about the extension direction of the second region 15 as an axis.

[0048] A plurality of third regions 16 are provided below the gate trench 13 (in the direction close to the substrate 10). These third regions 16 are distributed on both sides of the gate trench 13 along the second direction Z; that is, the third regions 16 may not be located directly below the gate trench 13. Multiple second regions 15 and multiple third regions 16 located on the same side of the gate trench 13 are alternately arranged and connected along the first direction Y. Specifically, on the same side of the gate trench 13, a second region 15 can be provided between any two adjacent third regions 16, and a third region 16 can be provided between any two adjacent second regions 15, with each third region 16 connected to its adjacent second region 15. In some embodiments, two second regions 15 can be provided between four adjacent third regions 16, and some of the four third regions 16 can be grounded.

[0049] In this embodiment, the second region 15 and the third region 16 are alternately arranged and connected along the first direction Y to prevent the third region 16 from floating, thereby improving the grounding of the device and maintaining its stability.

[0050] In some embodiments, the gate trench 13 has a plurality of third regions 16 and a plurality of second regions 15 alternately arranged along the first direction Y on both sides in the second direction Z. Figures 2 to 4As shown, the second regions 15 on both sides of the gate trench 13 in the second direction Z are disposed opposite to each other in the second direction Z, and the third regions 16 on both sides of the gate trench 13 in the second direction Z are disposed opposite to each other in the second direction Z.

[0051] For example, such as Figure 2 As shown, the extending direction of the gate trench 13 can be taken as the central axis. Four second regions 15 (or third regions 16) with a first preset distance between each other are arranged on one side of the gate trench 13, and four second regions 15 (or third regions 16) with a first preset distance between each other are also arranged on the other side of the gate trench 13. The second regions 15 (or third regions 16) on both sides of the gate trench 13 are symmetrically arranged about the central axis, that is, the second regions 15 (or third regions 16) on both sides of the gate trench 13 are arranged opposite each other in the second direction Z. In some embodiments, the gate trench 13 has a plurality of third regions 16 and a plurality of second regions 15 alternately arranged along the first direction Y on both sides in the second direction Z. Figure 6 and Figure 7 ( Figure 6 This is a second top view of the gate trench, the second region, and the third region in the semiconductor device provided in the embodiments of this application. Figure 7 for Figure 6 As shown in the cross-sectional schematic diagram at the dashed line DD', the second regions 15 on both sides of the gate trench 13 in the second direction Z are offset in the second direction Y, and the third regions 16 on both sides of the gate trench 13 in the second direction Z are offset in the second direction Y.

[0052] In this embodiment, the second regions 15 on both sides of the gate trench 13 are staggered in the second direction Y to further increase the current conduction path and reduce the conduction resistance.

[0053] In some embodiments, combined with Figure 8 and Figure 9 ( Figure 8 This is the third top view of the gate trench, the second region, and the third region in the semiconductor device provided in the embodiments of this application. Figure 9 for Figure 8 As shown in the cross-sectional schematic diagram at the dashed line EE', the third region 16, which is disposed opposite to it in the second direction Z, also extends along the second direction Z to the bottom of the gate trench 13 and is connected thereto.

[0054] In this embodiment, the third regions 16 on both sides of the gate trench 13 are connected to each other at the bottom of the gate trench 13, so that the third regions 16 are better grounded and the potential stability of the third regions 16 is further improved.

[0055] In some embodiments, combined with Figure 10 As shown ( Figure 10(This is a top view of the gate trench, second region, and third region in the semiconductor device provided in the embodiments of this application). The third region 16 extends along the first direction Y and is connected to a plurality of second regions 15 respectively.

[0056] The gate trench 13 has a third region 16 extending along the first direction Y on both sides in the second direction Z. The third region 16 and the second region 15 on the same side of the gate trench 13 are connected. The size of the third region 16 along the second direction Z can be larger than the size of the second region 15 along the second direction Z.

[0057] In this embodiment, the third region 16 extends along the first direction Y, further reducing the electric field peak at the bottom of the gate trench and further reducing the parasitic capacitance of the device.

[0058] In some embodiments, such as Figure 1 As shown, the third region 16 includes multiple sub-regions 160, which are connected sequentially along the thickness direction X, and adjacent sub-regions 160 are partially offset in the thickness direction X.

[0059] As an example, such as Figure 3 As shown, the third region 16 includes three sub-regions: a first sub-region 160a, a second sub-region 160b, and a third sub-region 160c. These sub-regions are sequentially distributed along the direction from the first surface S1 to the second surface S2. The first sub-region 160a is connected to the second sub-region 160b, and the first and second sub-regions 160b are partially offset along the thickness direction X. The second sub-region 160b and the third sub-region 160c are sequentially distributed and connected, and are also partially offset along the thickness direction X.

[0060] In this embodiment, the staggered sub-regions 160 form a PN junction with the epitaxial layer 11, which extends the conductive channel of the device, further reduces the electric field peak at the bottom of the gate trench, reduces the risk of device breakdown, and further reduces the parasitic capacitance of the device, thereby improving the high-frequency characteristics of the device.

[0061] In some embodiments, the second region 15 includes a shielding region 151 and a shielding scattering region 152 covering the shielding region 151. The doping concentration of the shielding region 151 is greater than the doping concentration of the shielding scattering region 152. The second region 15 includes at least one shielding scattering region 152, and a plurality of shielding scattering regions 152 are distributed sequentially from the inside to the outside, and the doping concentration of the plurality of shielding scattering regions 152 distributed sequentially from the inside to the outside gradually decreases.

[0062] The third region 16 includes a buried layer region 161 and a buried layer scattering region 162 covering the buried layer region 161. The doping concentration of the buried layer region 161 is greater than the doping concentration of the buried layer scattering region 162. When the third region 16 includes multiple sub-regions 160, each sub-region 160 may include a buried layer region 161 and a buried layer scattering region 162 covering the buried layer region 161, and the buried layer scattering regions 162 of the multiple sub-regions 160 are connected sequentially.

[0063] The connection between the second region 15 and the third region 16 may include: the shielding region 151 is connected to the buried layer region 161; or, the shielding region 151 is connected to the buried layer scattering region 162; or, the shielding scattering region 152 is connected to the buried layer region 161; or, the shielding scattering region 152 is connected to the buried layer scattering region 162.

[0064] In some embodiments, combined with Figure 11 ( Figure 11 for Figure 10 As shown in the schematic diagram of a cross section at the dashed line FF', the shielding area 151 penetrates the buried layer area 161 along the thickness direction X, and the shielding area 151 is connected to the buried layer area 161 to realize the connection between the second region 15 and the third region 16.

[0065] In some embodiments, combined with Figure 12 ( Figure 12 for Figure 10 As shown in the schematic diagram of another cross section at the dashed line FF', the bottom of the shielding area 151 is connected to the buried layer area 161, and the shielding area 151 and the buried layer area 161 are connected to realize the connection between the second area 15 and the third area 16.

[0066] In some embodiments, combined with Figure 13 ( Figure 13 for Figure 10 As shown in the schematic diagram of another cross section at the dashed line FF', the shielding area 151 and the buried layer area 161 are distributed at intervals along the thickness direction X, and the shielding scattering area 152 is connected to the buried layer scattering area 162, thereby realizing the connection between the second region 15 and the third region 16.

[0067] In some embodiments, combined with Figure 14 and Figure 15 As shown, the semiconductor body 1 also includes a third region extension region 17 having a second conductivity type. The third region extension region 17 is connected to the bottom of the third region 16 and extends along the thickness direction X. As an example, the epitaxial layer 11 is an N-type epitaxial layer, and the third region extension region 17 is a P-type third region extension region.

[0068] There can be multiple third region extension areas 17, and the multiple third region extension areas 17 are distributed at intervals along the second direction Z. When the third region 16 includes a buried layer region 161 and a buried layer shielding region 162, the third region extension areas 17 are connected to the bottom of the buried layer region 161.

[0069] In some embodiments, combined with Figure 14 As shown, the third region extension region 17 is spaced apart from the second surface S2, meaning that the side of the third region extension region 17 facing the second surface S2 does not contact the second surface S2. The third region extension region 17 extends from the bottom of the third region 16 along the thickness direction X toward the second surface S2, and the third region extension region 17 does not extend to the second surface S2, so that the third region extension region 17 and the epitaxial layer 11 form a semi-superjunction structure, enabling the semiconductor device to be used in a semi-superjunction device.

[0070] In some embodiments, combined with Figure 15 As shown, the third region extension region 17 extends along the thickness direction X to the second surface S2. The third region extension region 17 extends from the bottom of the third region 16 along the thickness direction X toward the second surface S2, and extends to the substrate 10, maintaining a distance from the second surface S2, so that the third region extension region 17 and the epitaxial layer 11 form a superjunction structure, so that the semiconductor device can be applied in a superjunction device.

[0071] According to the semiconductor device provided in the embodiments of this application, by providing a third region 16 near the bottom of the second region 15 and connecting the third region 16 to the second region 15, and the doping concentration of the third region 16 being less than that of the second region 15, the device structure is vertically adaptively grounded, and the depletion region is confined to the vicinity of the third region 16 when reverse biased, thereby reducing the electric field peak at the bottom of the gate trench 13, reducing the risk of device breakdown, reducing the parasitic capacitance of the device, and improving the high-frequency characteristics of the device.

[0072] Accordingly, this application also provides a method for fabricating a semiconductor device, which can fabricate the semiconductor device described in the above embodiments.

[0073] Figure 16 This is a schematic flowchart illustrating the method for fabricating a semiconductor device provided in an embodiment of this application.

[0074] like Figure 16 As shown, the method for fabricating a semiconductor device provided in this application includes steps S110 to S160.

[0075] Step S110: Provide a semiconductor body. The semiconductor body includes a first surface and a second surface disposed opposite to each other in the thickness direction. The semiconductor body includes a first region having a first conductivity type and a well region, a second region, and a third region having a second conductivity type. The first conductivity type is opposite to the second conductivity type. The first region is located on the first surface, and the well region is located on the side of the first region away from the first surface. The second region extends from the first surface into the semiconductor body. The third region is disposed near the bottom of the second region and is connected to the second region. The doping concentration of the third region is less than that of the second region.

[0076] In some embodiments, combined with Figure 17 As shown, the semiconductor body 1 may include a substrate 10 and an epitaxial layer 11. First, a substrate 10 is provided, and then an epitaxial layer 11 is formed on one side of the substrate 10 in the thickness direction X by means of vapor phase epitaxy, liquid phase epitaxy, or solid phase epitaxy. The material of the substrate 10 and the material of the epitaxial layer 11 may be the same or different. In some embodiments, both the epitaxial layer 11 and the substrate 10 may be made of SiC.

[0077] The semiconductor body 1 includes a first surface S1 and a second surface S2 disposed opposite to each other along the thickness direction X. The second surface S2 is the surface of the substrate 10 away from the epitaxial layer 11, and the first surface S1 is the surface of the epitaxial layer 11 away from the substrate 10. The substrate 10 and the epitaxial layer 11 are both doped with a first conductivity type, such as N-type.

[0078] Combination Figure 18 As shown, a first mask layer 6 is formed on the first surface S1, and the first mask layer 6 has a first mask opening 61. The first mask layer 6 may include silicon oxide, etc. Ion implantation is performed in the epitaxial layer 11 through the first mask opening 61 to form a third region 16. The third region 16 has a second conductivity type, such as P-type. When the third region 16 includes multiple sub-regions 160, multiple sub-regions 160 are sequentially formed by ion implantation using different implantation energies.

[0079] For example, the third region 16 includes three sub-regions: a first sub-region 160a, a second sub-region 160b, and a third sub-region 160c. These sub-regions are sequentially distributed along the direction from the first surface S1 to the second surface S2. During the formation of the third region 16, high-energy ion implantation is used to form the third sub-region 160c, followed by sequential implantation of the second sub-region 160b and the first sub-region 160a using the same method but different implantation energies. The first sub-region 160a, the second sub-region 160b, and the third sub-region 160c can be sequentially connected by scattering; that is, each sub-region can include a buried layer region 161 and a buried scattering region 162, and the buried scattering regions 162 of the first sub-region 160a, the second sub-region 160b, and the third sub-region 160c are sequentially connected.

[0080] After the formation of the third region 16, combined with Figure 19 As shown, the first mask layer 6 is removed using a wet etching process.

[0081] Then, a well region 12 is formed on the first surface S1.

[0082] Combination Figure 20 As shown, a second mask layer 7 is formed on the first surface S1, and the second mask layer 7 has a second mask opening 71. A second region 15 is formed in the semiconductor body 1 by ion implantation through the second mask opening 71, and a third region 16 is disposed near the bottom of the second region 15 and connected to the second region 15. The third region 16 has a second conductivity type, such as P-type.

[0083] In some embodiments, combined with Figure 14 and Figure 15 As shown, the semiconductor body 1 also includes a third region extension region 17 having a second conductivity type. The third region extension region 17 is connected to the bottom of the third region 16 and extends along the thickness direction X. For example, the third region extension region 17 can be formed by etching a trench or tapered hole through the epitaxial layer 11, implanting P-type impurities, and then advancing at high temperature.

[0084] Then, combine Figure 21 As shown, the second mask layer 7 is removed. A third mask layer 8 is formed on the first surface S1, and the third mask layer 8 has a third mask opening 81. Ion implantation is performed through the third mask opening 81 to form a first region 14 on the first surface S1, such that a well region 12 is located on the side of the first region 14 facing away from the first surface S1. Then, the third mask layer 8 is removed. The first region 14 has a first conductivity type, such as N-type. The well region 12 has a second conductivity type, such as P-type.

[0085] Step S120: Form a gate trench extending from the first surface into the semiconductor body.

[0086] Combination Figure 22 As shown, a fourth mask layer 9 is formed on the first surface S1, and the fourth mask layer 9 has a fourth mask opening 91. Through the fourth mask opening 91, an etching process is used to etch the semiconductor body 1 to form a gate trench 13 extending from the first surface S1 into the semiconductor body 1. Then, the fourth mask layer 9 is removed.

[0087] Step S130: An insulating layer is formed on the surface of the gate trench.

[0088] Combination Figure 23 As shown, an insulating layer 2 is formed on the bottom surface and sidewalls of the gate trench 13. The material of the insulating layer 2 may include silicon oxide, etc.

[0089] Step S140: Fill the gate structure in the gate trench.

[0090] Combination Figure 23 As shown, a thin-film deposition process is used to fill the gate trench 13 with the gate structure 3. An insulating layer 2 is located between the gate trench 13 and the gate structure 3, serving to isolate the gate structure 3 from the semiconductor body 1. The material of the gate structure 3 may include polysilicon, etc.

[0091] In some embodiments, after forming the gate structure 3, the combination Figure 24 As shown, a dielectric layer 6 is formed on the side of the gate structure 3 away from the second surface S2 using a thin-film deposition process, and the dielectric layer 6 covers the gate structure 3. The material of the dielectric layer 6 may include silicon oxide, silicon nitride, etc.

[0092] Step S150: Form a source electrode on the first surface.

[0093] Combination Figure 25 As shown, a source electrode 4 is formed on the first surface S1 of the semiconductor body 1 using a thin-film deposition process. The source electrode 4 is in contact with the first region 14 and the second region 15. The source electrode 4 can also be located on the side of the dielectric layer 6 away from the semiconductor body 1, that is, the dielectric layer 6 is located between the source electrode 4 and the gate structure 3, which is used to isolate the source electrode 4 from the gate structure 3. The material of the source electrode 3 can include metals such as aluminum, copper, and nickel.

[0094] Step S160: Form a drain electrode on the second surface.

[0095] Combination Figure 4 As shown, a drain 5 is formed on the second surface S2 of the semiconductor body 1 using a thin-film deposition process. The drain 5 can cover the second surface S2 of the semiconductor body 1. The material of the drain 5 can include metals such as aluminum, copper, and nickel.

[0096] According to the semiconductor device fabrication method provided in the embodiments of this application, by setting a third region 16 near the bottom of the second region 15 and connecting the third region 16 to the second region 15, the doping concentration of the third region 16 is less than that of the second region 15, the device structure is vertically adaptively grounded, and the depletion region is restricted to the vicinity of the third region 16 when reverse biased, thereby reducing the electric field peak at the bottom of the gate trench 13, reducing the risk of device breakdown, reducing the parasitic capacitance of the device, and improving the high-frequency characteristics of the device.

[0097] Accordingly, this application also provides a power module. The power module includes a substrate and the semiconductor device from any of the above embodiments, wherein the substrate is used to support the semiconductor device.

[0098] For example, a power module can be used as one of a power amplifier, power converter, power controller, power management module, or power regulator. A power amplifier amplifies the power of an electrical signal. A power converter converts electrical energy from one form to another; for example, a power converter can be an AC / DC converter or a DC / DC converter. A power controller is a device for controlling the flow of power. A power management module manages the power supply, ensuring that power is stably and efficiently distributed to different parts of an electronic device. A power regulator adjusts the power output to meet the needs of a specific application.

[0099] On the other hand, embodiments of this application also provide a power conversion circuit. The power conversion circuit includes a circuit board and the semiconductor device in any of the above embodiments. The semiconductor device is electrically connected to the circuit board, and the power conversion circuit can be used for current conversion, voltage conversion, or power factor correction.

[0100] For example, the power conversion circuit can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter, or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current to direct current, the AC / AC converter is used to convert alternating current to alternating current, the DC / DC converter is used to convert direct current to direct current, the DC / AC inverter is used to convert direct current to alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce harmonic pollution of the power grid.

[0101] On the other hand, embodiments of this application also provide a vehicle. The vehicle includes a load and the power conversion circuit described in the above embodiments. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load to supply power to the load.

[0102] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0103] In the description of this application, "multiple" means two or more.

[0104] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0105] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other in the thickness direction. The semiconductor body includes a first region having a first conductivity type and a well region, a second region, and a third region having a second conductivity type. The first conductivity type is opposite to the second conductivity type. The first region is located on the first surface, and the well region is located on the side of the first region away from the first surface. The second region extends from the first surface into the semiconductor body, and the third region is located in the semiconductor body and disposed near the bottom of the second region. The doping concentration of the third region is less than that of the second region. The semiconductor body has a gate trench extending from the first surface into the semiconductor body. The gate trench extends along a first direction, the third region is connected to the second region in the first direction, the second region separates two adjacent gate trenches, and the first direction is perpendicular to the thickness direction; An insulating layer is located on the surface of the gate trench; A gate structure is filled in the gate trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, characterized in that, The third region includes multiple sub-regions, which are connected sequentially along the thickness direction, and adjacent sub-regions are partially offset in the thickness direction.

3. The semiconductor device according to claim 2, characterized in that, The second region includes a shielding area and a shielding scattering area that covers the shielding area; the third region includes a buried layer area and a buried layer scattering area that covers the buried layer area. The shielding area penetrates the buried layer area along the thickness direction; or, the bottom of the shielding area is connected to the buried layer area; or, the shielding area and the buried layer area are spaced apart along the thickness direction, and the shielding scattering area is connected to the buried layer scattering area.

4. The semiconductor device according to claim 1, characterized in that, The second regions located on one side of the gate trench are spaced apart along the first direction.

5. The semiconductor device according to claim 4, characterized in that, The third region extends along the first direction and is connected to a plurality of second regions located on one side of the gate trench.

6. The semiconductor device according to claim 4, characterized in that, The plurality of third regions located on one side of the gate trench are alternately arranged and connected with the plurality of second regions along the first direction.

7. The semiconductor device according to claim 6, characterized in that, The gate trench has a plurality of third regions and a plurality of second regions arranged alternately along the first direction on both sides in the second direction, and the second direction is perpendicular to the first direction and the thickness direction. The second regions on both sides of the gate trench are disposed opposite to each other in the second direction, and the third regions on both sides of the gate trench are disposed opposite to each other in the second direction; or, The second regions on both sides of the gate trench are offset in the second direction, and the third regions on both sides of the gate trench are offset in the second direction.

8. The semiconductor device according to claim 7, characterized in that, The third region, which is disposed opposite to the second direction, also extends along the second direction to the bottom of the gate trench and is connected thereto.

9. The semiconductor device according to claim 1, characterized in that, The semiconductor body further includes a third region extension having a second conductivity type, the third region extension being connected to the bottom of the third region and extending along the thickness direction; The third region extension area is spaced apart from the second surface, or the third region extension area extends to the second surface along the thickness direction.

10. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other in the thickness direction, the semiconductor body including a first region having a first conductivity type and a well region, a second region and a third region having a second conductivity type, the first conductivity type being opposite to the second conductivity type, the first region being located on the first surface, the well region being located on the side of the first region away from the first surface, the second region extending from the first surface into the semiconductor body, the third region being located in the semiconductor body and disposed near the bottom of the second region, the doping concentration of the third region being less than the doping concentration of the second region; A gate trench is formed extending from the first surface into the semiconductor body; the gate trench extends along a first direction, the third region is connected to the second region in the first direction, the second region separates two adjacent gate trenches, and the first direction is perpendicular to the thickness direction; An insulating layer is formed on the surface of the gate trench; A gate structure is filled in the gate trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

11. A power module, characterized in that, Including a substrate and as claimed in claim 1 9. The semiconductor device described in any one of the claims, wherein the substrate is used to support the semiconductor device.

12. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and as claimed in claim 1. The semiconductor device according to any one of the following nine claims, wherein the semiconductor device is electrically connected to the circuit board.

13. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 12, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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