Semiconductor device and method of manufacture, power module, power conversion circuit and vehicle

Abstract

The application discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged oppositely; the first surface is further provided with a gate trench; a gate electrode is located in the gate trench; a source electrode is located on the first surface; a drain electrode is located on the second surface; wherein the semiconductor body further comprises a well region, a first region, a second region and a first buried layer; the first buried layer is connected with the second region, and the first buried layer can form a self-adaptive JFET structure; the pinch-off effect of the first buried layer depletion region in the JFET structure can automatically reduce the effective conduction cross section, so as to inhibit the sharp rise of the current, improve the short-circuit resistance of the device and improve the stability of the gate oxide layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Silicon carbide trench devices have advantages such as high current density and small cell pitch, and are widely used. However, existing trench devices still have shortcomings in performance stability and short-circuit withstand capability.

[0003] Application content This application provides a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, which improve the short-circuit withstand capability of the device and enhance the stability of the gate oxide layer.

[0004] In a first aspect, embodiments of this application provide a semiconductor device, including: A semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; The semiconductor body further includes a well region, a first region, a second region, and a first buried layer; the first region is disposed on a first surface of the semiconductor body, and the well region is disposed on the side of the first region away from the first surface; the first surface is also provided with a gate trench; the second region is disposed on the first surface and located on one side of the gate trench; at least a portion of the well region is located between the second region and the gate trench; wherein the depth of the second region in the thickness direction of the semiconductor body is greater than the depth of the gate trench in the thickness direction of the semiconductor body; the first buried layer is disposed on the side of the second region away from the first surface and contacts the second region; wherein at least a portion of the orthographic projection of the first buried layer on the second surface overlaps with the orthographic projection of the well region between the second region and the gate trench on the second surface; the first region is of a first conductivity type, and the well region, the second region, and the first buried layer are of a second conductivity type; the thickness direction is the direction from the first surface to the second surface; The gate is located within the gate trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

[0005] Optionally, the semiconductor body further includes: a second buried layer and a connection layer; In the thickness direction, the second buried layer is disposed on one side of the first buried layer; in the first direction, the second buried layer is located on the side of the first buried layer away from the second region, and the first direction is perpendicular to the thickness direction of the semiconductor body; the orthographic projection of the second buried layer on the second surface overlaps with the orthographic projection of the gate trench on the second surface; the connecting layer is disposed between the first buried layer and the second buried layer; both ends of the connecting layer are in contact with the first buried layer and the second buried layer, respectively; The connecting layer, the first buried layer, and the second buried layer all extend along a second direction, which is perpendicular to the first direction and the thickness direction; the extension length of the connecting layer in the second direction is less than the extension length of the first buried layer and the second buried layer in the second direction.

[0006] Optionally, the orthographic projection of the first embedded layer on the second surface does not overlap with the orthographic projection of the second embedded layer on the second surface.

[0007] Optionally, the connection layer includes a plurality of connection sub-layers arranged at intervals along the second direction; The connecting sublayer is in contact with the first buried layer; the same connecting sublayer is in contact with the second buried layer.

[0008] Secondly, embodiments of this application provide a power module, including a substrate and at least one semiconductor device as described in any embodiment of this application, wherein the substrate is used to support the semiconductor device.

[0009] Thirdly, embodiments of this application provide a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, the semiconductor device being electrically connected to the circuit board.

[0010] Fourthly, embodiments of this application provide a vehicle including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0011] Fifthly, embodiments of this application provide a method for fabricating a semiconductor device, comprising: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; The semiconductor body further includes a well region, a first region, a second region, and a first buried layer; the first region is disposed on a first surface of the semiconductor body, and the well region is disposed on the side of the first region away from the first surface; the first surface is also provided with a gate trench; the second region is disposed on the first surface and located on one side of the gate trench; at least a portion of the well region is located between the second region and the gate trench; wherein the depth of the second region in the thickness direction of the semiconductor body is greater than the depth of the gate trench in the thickness direction of the semiconductor body; the first buried layer is disposed on the side of the second region away from the first surface and contacts the second region; wherein at least a portion of the orthographic projection of the first buried layer on the second surface overlaps with the orthographic projection of the well region between the second region and the gate trench on the second surface; the first region is of a first conductivity type, and the well region, the second region, and the first buried layer are of a second conductivity type; the thickness direction is the direction from the first surface to the second surface; A gate is formed within the gate trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

[0012] Optionally, the semiconductor body further includes: a second buried layer and a connection layer; Provide semiconductor bodies, including: Provide substrate; A first epitaxial layer is formed on one side of the substrate, and a first buried layer, a second buried layer, and a connecting layer are formed in the first epitaxial layer; in the thickness direction, the second buried layer is disposed on one side of the first buried layer; in the first direction, the second buried layer is located on the side of the first buried layer away from the second region, and the first direction is perpendicular to the thickness direction of the semiconductor body; the connecting layer is disposed between the first buried layer and the second buried layer; both ends of the connecting layer are in contact with the first buried layer and the second buried layer, respectively; wherein the connecting layer, the first buried layer, and the second buried layer all extend along a second direction, the second direction being perpendicular to the first direction and perpendicular to the thickness direction; the extension length of the connecting layer in the second direction is less than the extension length of the first buried layer and the second buried layer in the second direction; A second epitaxial layer is formed on the first epitaxial layer; The surface of the second epitaxial layer away from the substrate serves as the first surface of the semiconductor body, and the well region, the first region, and the second region are sequentially formed within the second epitaxial layer; The gate trench is formed on the first surface, and the orthographic projection of the second buried layer on the second surface overlaps with the orthographic projection of the gate trench on the second surface.

[0013] Optionally, the first epitaxial layer includes a first sub-epiaxial layer and a second sub-epiaxial layer stacked together; forming the first buried layer, the second buried layer, and the connecting layer in the first epitaxial layer includes: The first sub-epipolar layer is formed on one side of the substrate; The second buried layer is formed in the first sub-epipolar layer; A second sub-epitaxial layer is formed on the side of the first sub-epitaxial layer away from the substrate, and the first buried layer is formed in the second sub-epitaxial layer; The connecting layer is formed between the first buried layer and the second buried layer; Optionally, forming the first buried layer, the second buried layer, and the connecting layer in the first epitaxial layer includes: The first sub-epipolar layer is formed on one side of the substrate; The first buried layer is formed in the first sub-epipolar layer; A second sub-epitaxial layer is formed on the side of the first sub-epitaxial layer away from the substrate, and a second buried layer is formed in the second sub-epitaxial layer; The connecting layer is formed between the first buried layer and the second buried layer.

[0014] Optionally, the connection layer formed between the first buried layer and the second buried layer includes: A plurality of connecting sub-layers are formed between the first buried layer and the second buried layer, spaced apart along the second direction; the connecting sub-layers are in contact with the first buried layer; the same connecting sub-layer is in contact with the second buried layer.

[0015] The semiconductor device provided in this application embodiment has a first region and a well region formed on a first surface of the semiconductor body. A gate trench is also formed on the first surface. A second region is formed on the first surface and located on the side of the first region away from the gate trench. A first buried layer is located on the side of the second region away from the first surface. The second region and the first buried layer can protect the bottom corner of the gate trench, thereby improving the problem of gate oxide layer breakdown and ensuring the reliability of the device operation. Simultaneously, the first buried layer can form an adaptive JFET structure. Under abnormal operating conditions such as short circuits or overvoltages, the pinch-off effect of the depletion region of the first buried layer in the JFET structure automatically reduces the effective conductive cross-section, thereby suppressing a sharp rise in current and improving the device's short-circuit withstand capability. Attached Figure Description

[0016] Figure 1This is a schematic diagram of a cross-sectional structure of a semiconductor device provided in an embodiment of this application; Figure 2 A schematic cross-sectional structure diagram of another semiconductor device provided in the embodiments of this application. Figure 3 This is a top view of a semiconductor device provided in an embodiment of this application; Figure 4 This is a three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this application; Figure 5 for Figure 3 A schematic diagram of the cross-sectional structure at position AA'; Figure 6 for Figure 3 A schematic diagram of the cross-sectional structure at the BB' position; Figure 7 for Figure 1 A schematic diagram of a cross-sectional structure at position AA'; Figure 8 A top view schematic diagram of another semiconductor device provided in an embodiment of this application; Figure 9 for Figure 3 A schematic diagram of a cross-sectional structure at position AA'; Figure 10 for Figure 3 A schematic diagram of a cross-sectional structure at the BB' position; Figure 11 A flowchart illustrating a method for fabricating a semiconductor device as provided in this application embodiment; Figure 12 This is a flowchart illustrating a method for fabricating a semiconductor body of a semiconductor device according to an embodiment of this application; Figures 13 to 17 This is a schematic diagram of the intermediate structure of the preparation process provided in the embodiments of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of this application. See also... Figure 1 ,include: Semiconductor body 110, the semiconductor body 110 includes a first surface and a second surface disposed opposite to each other; The semiconductor body 110 further includes a well region 111, a first region 112, a second region 113, and a first buried layer 114; the first region 112 is disposed on a first surface of the semiconductor body 110, and the well region 111 is disposed on the side of the first region 112 away from the first surface; a gate trench 117 is also disposed on the first surface; the second region 113 is disposed on the first surface and located on one side of the gate trench 117; at least a portion of the well region 111 is located between the second region 113 and the gate trench 117; wherein, the depth of the second region 113 in the thickness direction of the semiconductor body is... The depth of the gate trench 117 in the thickness direction of the semiconductor body is greater than that of the gate trench 117; the first buried layer 114 is disposed on the side of the second region 113 away from the first surface and contacts the second region 112; wherein, at least a portion of the orthographic projection of the first buried layer 114 on the second surface overlaps with the orthographic projection of the well region 111 between the second region 113 and the gate trench 117 on the second surface; the thickness direction is the direction from the first surface to the second surface; the first region 112 is of the first conductivity type, and the well region 111, the second region 113 and the first buried layer 114 are of the second conductivity type; Gate 120 is located within gate trench 117; Source electrode 130 is located on the first surface; Drain 140 is located on the second surface.

[0019] Specifically, in the embodiments of this application, the semiconductor devices include, but are not limited to, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), JFETs (Junction Field-Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), and HEMTs (High Electron Mobility Transistors). The semiconductor body may include wide-bandgap or ultra-wide-bandgap semiconductor materials such as silicon carbide semiconductor bodies and gallium nitride semiconductor bodies. Exemplarily, the MOSFET includes N-type MOSFETs or P-type MOSFETs. For N-type MOSFETs, the first conductivity type is N-type, and the second conductivity type is P-type. For P-type MOSFETs, the first conductivity type is P-type, and the second conductivity type is N-type. For regions with N-type conductivity, N-type doping can be used, where the dopant ions can be phosphorus (P) ions or nitrogen (N) ions; for regions with P-type conductivity, P-type doping can be used, where the dopant ions can be aluminum (Al) ions or boron (B) ions. Exemplarily, the embodiments below use N-type conductivity as the first conductivity type and P-type conductivity as the second conductivity type for illustration.

[0020] In this embodiment, the semiconductor body 110 may include a substrate 118, an epitaxial layer 119, a well region 111, a first region 112, a second region 113, and a first buried layer 114. The epitaxial layer 119 is located on one side of the substrate 118, and can be formed on the surface of the substrate 118 by epitaxial growth. The surface of the epitaxial layer 119 away from the substrate 118 serves as the first surface of the semiconductor body 110. The first region 112 is disposed on the first surface, and the well region 111 is disposed on the side of the first region 112 away from the first surface. The well region 111 and the first region 112 can be formed by epitaxial growth, ion implantation, or vapor deposition. For example, when the well region 111 and the first region 112 are formed by epitaxial growth or vapor deposition, the first surface of the semiconductor body 110 can be considered as a renewed surface. For instance, if the well region 111 is epitaxially grown on the surface of the epitaxial layer 119 away from the substrate 118, then the surface of the well region 111 away from the substrate 118 is renewed as the first surface of the semiconductor body 110, and the first region 112 is epitaxially grown on the surface of the well region 111 away from the substrate 118. When the well region 111 and the first region 112 are formed by ion implantation, the first surface of the semiconductor body 110 can be considered as a fixed surface. For instance, the well region 111 is formed by ion implantation on the surface of the epitaxial layer 119 away from the substrate 118, i.e., the first surface, and then the first region 112 is formed again by ion implantation on the first surface.

[0021] A gate trench 117 is also provided on the first surface, which can be formed by an etching process. The gate trench 117 extends from the first surface into the epitaxial layer 119, passing through the first region 112 and the well region 111. The well region 111 and the first region 112 on both sides of the gate trench 117 are used to form conductive channels of the semiconductor device, wherein the first region 112 is of a first conductivity type and the well region 111 is of a second conductivity type.

[0022] A second region 113 is further disposed on the first surface of the semiconductor body 110. The second region 113 extends into the epitaxial layer 119, and in the first direction X, the second region 113 is located on the side of the first region 112 away from the gate trench 117. Exemplarily, the second region 113 can be disposed on one or both sides of the gate trench 117. When the second region 113 is disposed on both sides of the gate trench 117, the two second regions 113 can be disposed symmetrically or asymmetrically relative to the gate trench 117. In this embodiment, for example, the second region 113 is disposed on both sides of the gate trench 117. The second region 113 has a second conductivity type and can be formed by ion implantation. The conductivity type of the second region 113 is the same as that of the well region 111. Therefore, when a high voltage is applied to the drain, a depletion region can be formed between the second region 113 and the epitaxial layer 119, which can serve to shield the gate corner electric field.

[0023] A first buried layer 114 is also disposed within the epitaxial layer 119, and the first buried layer 114 is of a second conductivity type. The first buried layer 114 can be formed by ion implantation. In the thickness direction, the first buried layer 114 is located on the side of the second region 113 away from the first surface. The orthographic projections of the first buried layer 114 and the second region 113 on the second surface overlap, meaning that in the thickness direction of the semiconductor device, at least a portion of the first buried layer 114 is disposed below the second region 113. At the corresponding overlapping positions, the first buried layer 114 and the second region 113 are electrically connected. This connection can be a direct contact connection or an indirect connection formed by an electrical connection structure between the first buried layer 114 and the second region 113; no specific limitation is made here. Exemplarily, in this embodiment, the first buried layer 114 and the second region 113 are connected by contact.

[0024] A gate 120 is disposed within the gate trench 117. For example, a first insulating layer 150 is disposed between the gate trench 117 and the gate 120. The first insulating layer 150 can be obtained by oxidizing the inner wall and bottom of the gate trench 117 and can be called a gate oxide layer. The gate oxide layer can be a high dielectric constant (K) material, and the gate can be polysilicon. The well regions 111 on both sides of the gate can form vertical conductive channels. The structure of the gate trench 117 can also reduce the JFET region between the second region 113 and the epitaxial layer 119, further reducing the on-resistance of the semiconductor device.

[0025] A source electrode 130 is disposed on the first surface of the semiconductor body 110. Exemplarily, the source electrode can be formed by sputtering or other methods. The source electrode is a metal conductive layer, which can be titanium (Ti), nickel (Ni), or silver (Ag). A second insulating layer 160 is also included between the source electrode 130 and the gate 120. The second insulating layer 160 can be an interlayer dielectric (ILD). The second insulating layer 160 covers the surface of the gate 120, isolating the gate 120 and the source electrode 130. The source electrode 130 forms an ohmic contact with the first region 112 and the second region 113.

[0026] With the source 130 of the semiconductor device connected to the negative terminal and the drain 140 connected to the positive terminal, the first buried layer 114 and the second region 113 are electrically connected to the source 130. The potential of the first buried layer 114 is close to the low potential of the source 130, which is typically ground or a reference zero potential. Therefore, when the semiconductor device is turned off or subjected to a high drain voltage, the first buried layer 114 is at a low potential relative to the epitaxial layer 119. Consequently, a reverse-biased PN junction is formed at the interface between the epitaxial layer 119 and the first buried layer 114, and a depletion region is formed at the reverse-biased location. When a higher voltage is applied to the drain, the potential of the epitaxial layer 119 increases; the first buried layer 114, being connected to the source, remains at a low potential, increasing the potential difference between the first buried layer 114 and the epitaxial layer 119. The depletion regions on both sides of the first buried layer 114 expand, and as the drain voltage continues to increase, the depletion regions widen, eventually completely cutting off the conductive channels on both sides of the first buried layer 114. Therefore, the first buried layer 114 can form an adaptive JFET structure. Under abnormal operating conditions such as short circuit or overvoltage, the effective conductive cross section can be automatically reduced by utilizing the pinch-off effect of the depletion region of the first buried layer 114 in the JFET structure, thereby suppressing the sharp rise of current and improving the short circuit resistance of the device.

[0027] Furthermore, since the depth of the second region 113 in the thickness direction of the semiconductor body is greater than the depth of the gate trench 117 in the thickness direction of the semiconductor body, when a higher voltage is applied to the drain 140, a depletion region will be formed between the second region 113 and the epitaxial layer 119, which can also effectively shield the influence of the high electric field on the gate oxide layer forming the corner of the gate. By designing the depth of the second region 113 to be greater than the depth of the gate trench 117, the second region 113 can cover the bottom corner region of the trench in the thickness direction, thereby improving the problem of gate oxide layer breakdown.

[0028] The first buried layer 114 is disposed on the side of the second region 113 away from the first surface and contacts the second region 112. A depletion region may also be formed between the first buried layer 114 and the epitaxial layer 117. At least a portion of the orthographic projection of the first buried layer 114 on the second surface overlaps with the orthographic projection of the well region 111 between the second region 113 and the gate trench 117 on the second surface. That is, in the first direction X, the first buried layer 114 may extend toward the gate trench 117, wherein the first buried layer 114 may extend between the second region 113 and the gate trench 117, such as... Figure 1 As shown. Figure 2 A schematic cross-sectional view of another semiconductor device provided in this application embodiment is shown below. Figure 2The first buried layer 114 can also extend below the gate trench 117. That is, when the depth of the third region 114 is greater than the depth of the gate trench 115, the third region 114 extends towards the gate trench 115, thereby further protecting the bottom corner of the gate trench 115, thus improving the problem of gate oxide layer breakdown and ensuring the reliability of device operation.

[0029] The semiconductor device provided in this embodiment has a first region 112 and a well region 111 on the first surface of the semiconductor body 110. A gate trench 117 is also provided on the first surface. A second region 113 is disposed on the first surface and located on the side of the first region 112 away from the gate trench 117. A first buried layer 114 is located on the side of the second region 113 away from the first surface. The second region 113 and the first buried layer 114 can protect the bottom corner of the gate trench 117, thereby improving the problem of gate oxide layer breakdown and ensuring the reliability of the device operation. Simultaneously, the first buried layer 114 can form an adaptive JFET structure. Under abnormal operating conditions such as short circuits or overvoltages, the pinch-off effect of the depletion region of the first buried layer 114 in the JFET structure automatically reduces the effective conductive cross-section, thereby suppressing a sharp rise in current and improving the device's short-circuit withstand capability.

[0030] Figure 3 This is a top view schematic diagram of a semiconductor device provided in an embodiment of this application. Figure 4 This is a three-dimensional structural diagram of a semiconductor device provided in an embodiment of this application. Figure 5 for Figure 3 See the schematic diagram of the cross-sectional structure at position AA'. Figures 3-5 In this embodiment of the application, the semiconductor body further includes a second buried layer 115 and a connection layer 116.

[0031] In the thickness direction, the second buried layer 115 is disposed on the side of the first buried layer 114 away from the first surface, and the orthographic projection of the second buried layer 115 on the second surface overlaps with the orthographic projection of the gate trench 117 on the second surface; in the first direction X, the second buried layer 115 is located on the side of the first buried layer 114 away from the second region 113; the connecting layer 116 is disposed between the first buried layer 114 and the second buried layer 115, and the two ends of the connecting layer 116 are in contact with the first buried layer 114 and the second buried layer 115, respectively.

[0032] Specifically, in combination Figures 3-5 The gate trench 117 can be a continuous trench in the second direction Y. Figure 4In the diagram, the second direction Y is perpendicular to the plane of the paper and is perpendicular to the first direction X and the thickness direction of the semiconductor device. A second buried layer 115 is also disposed within the epitaxial layer 119, and the second buried layer 115 has a second conductivity type. The second buried layer 115 can be formed by ion implantation. The second buried layer 115 is disposed on the side of the first buried layer 114 away from the first surface, and there is a certain gap between the first buried layer 114 and the second buried layer 115 in the thickness direction. Specifically, in the first direction X, the second buried layer 115 is located on the side of the first buried layer 114 away from the second region 113. That is, in the first direction X, the second buried layer 115 has a certain positional offset relative to the first buried layer 114. A connecting layer 116 is provided between the first buried layer 114 and the second buried layer 115. The connecting layer 116 has a first overlapping region 1161 and a second overlapping region 1162 with the first buried layer 114 and the second buried layer 115 respectively in the thickness direction. The first buried layer 114 is connected to the connecting layer 116 in the first overlapping region 1161 and the first buried layer 114 is connected to the connecting layer 116 in the second overlapping region 1162.

[0033] Combination Figure 3 The first embedded layer 114 and the second embedded layer 115 extend along the second direction Y, and the connecting layer 116 extends in the second direction Y for a shorter length than the first embedded layer 114 and the second embedded layer 115. Figure 6 for Figure 3 See the schematic diagram of the cross-sectional structure at the BB' position. Figure 6 There is a region between the first buried layer 114 and the second buried layer 115 where the connecting layer 116 is not provided, thus forming a structural layout with a partially disconnected region. The partially disconnected region can serve as a conductive channel for charge carriers to pass through and flow to the drain.

[0034] In a semiconductor device where the source 130 is connected to the negative electrode and the drain 140 is connected to the positive electrode, the second buried layer 115 is electrically connected to the source 130 through the connection layer 116, the first buried layer 114, and the second region 113. The potential of the second buried layer 115 is close to the low potential of the source 130, typically ground or a reference zero potential. Therefore, when the semiconductor device is turned off or subjected to a high drain voltage, the second buried layer 115 is at a low potential relative to the epitaxial layer 119. Consequently, a reverse-biased PN junction is formed at the interface between the epitaxial layer 119 and the second buried layer 115, and a depletion region is formed at the reverse-biased location. Figure 4In the partially disconnected region, i.e., the region between the first buried layer 114 and the second buried layer 115 where no connecting layer 116 is provided, the second buried layer 115 forms a reverse-biased junction with the surrounding N-type epitaxial layer 119. When a higher voltage is applied to the drain, the potential of the epitaxial layer 119 increases; the second buried layer 115, being connected to the source, remains at a low potential, increasing the potential difference between the second buried layer 115 and the epitaxial layer 119. This causes the depletion region on both sides of the second buried layer 115 to expand. As the drain voltage continues to increase, the depletion region continues to widen, eventually completely pinching off the conductive channels on both sides of the second buried layer 115. Therefore, the first buried layer 114, the second buried layer 115, and the connecting layer 116 can constitute an adaptive JFET structure. Under abnormal operating conditions such as short circuits or overvoltages, the pinch-off effect of the depletion region of the second buried layer 115 in the JFET structure can automatically reduce the effective conductive cross-section, thereby suppressing a sharp rise in current and improving the device's short-circuit withstand capability.

[0035] Furthermore, since the potentials of the second region 113, the first buried layer 114, the second buried layer 115, and the interconnect layer 116 are closer to the low potential of the source, when a high voltage is applied to the drain, the electric field is mainly distributed in the depletion region between the buried layer and the drift region, thereby protecting the gate oxide layer, reducing the electric field strength in the gate dielectric layer, and improving the reliability of the device.

[0036] The semiconductor device provided in this embodiment has a first region 112 and a well region 111 on the first surface of the semiconductor body 110. A gate trench 117 is also provided on the first surface. A second region 113 is provided on the first surface and located on the side of the first region 112 away from the gate trench 117. A first buried layer 114 is located on the side of the second region 113 away from the first surface. A second buried layer 115 is located on the side of the first buried layer 114 away from the first surface. The first buried layer 114 and the second buried layer 115 are connected by a connecting layer 116. In the second direction Y, there is a region between the first buried layer 114 and the second buried layer 115 where the connecting layer 116 is not provided, i.e., a partially disconnected region. The second region 113, the first buried layer 114, the second buried layer 115 and the connecting layer 116 can protect the bottom corner of the gate trench 117, thereby improving the problem of gate oxide layer breakdown and ensuring the reliability of the device operation. Meanwhile, the first buried layer 114, the second buried layer 115, and the interconnect layer 116 can form an adaptive JFET structure. Under abnormal operating conditions such as short circuit or overvoltage, the effective conductive cross-section will be automatically reduced by utilizing the pinch-off effect of the depletion region of the second buried layer 115 in the JFET structure, thereby suppressing the sharp rise in current and improving the short circuit resistance of the device.

[0037] Furthermore, since the JFET structure effectively shields the electric field coupling effect of high drain-source voltage on well region 111, the doping concentration of well region 111 can be appropriately reduced while ensuring short-circuit withstand capability and blocking performance, thereby reducing the threshold voltage of the device and improving its conduction characteristics.

[0038] Optionally, the orthographic projection of the first buried layer 114 on the second surface overlaps with the orthographic projection of the well region 111 between the second region 113 and the gate trench 117 on the second surface.

[0039] Specifically, in the first direction X, the first buried layer 114 can extend toward the gate trench 117, wherein the first buried layer 114 can extend between the second region 113 and the gate trench 117, such as... Figure 5 As shown. It can also extend below the gate trench 117, as... Figure 7 As shown, without specific limitations, the second buried layer 115 can be located deeper than the first buried layer 114 away from the first surface. Optionally, the orthographic projection of the second buried layer 115 on the second surface overlaps with the orthographic projection of the gate trench 117 on the second surface. The second buried layer 115 can also extend between the second region 113 and the gate trench 117, or it can be located only below the gate trench 117; no specific limitations are imposed here. By maintaining a low potential with the first buried layer 114 and the second buried layer 115, an electric field shielding layer is formed, which can effectively reduce the peak electric field borne by the gate oxide layer. By constructing a potential step around the gate trench 117 using the first buried layer 114 and the second buried layer 115, and by rationally designing the depth of the buried layer, the doping concentration, and the positional offset of the second buried layer 115 relative to the first buried layer 114 in the first direction X, the electric field can be more uniformly distributed within the epitaxial layer 119.

[0040] Optionally, the orthographic projection of the first buried layer 114 on the second surface does not overlap with the orthographic projection of the second buried layer 115 on the second surface. Specifically, in conjunction with Figure 5 By preventing the orthographic projections of the first buried layer 114 and the second buried layer 115 from overlapping on the second surface, it can be ensured that there are no intersecting or overlapping areas between the first buried layer 114 and the second buried layer 115 in the thickness direction of the device. This effectively avoids the first buried layer 114 and the second buried layer 115 intersecting and blocking the conductive path between the source and drain, thereby avoiding an increase in on-resistance under normal operating conditions and improving the conduction performance of the device.

[0041] Figure 8 A top view schematic diagram of another semiconductor device provided in the embodiments of this application is shown below. Figure 8The connecting layer 116 includes multiple connecting sub-layers 1163. In the second direction Y, adjacent connecting sub-layers 1163 are spaced apart. The connecting sub-layers 1163 are in contact with the first buried layer 114. The same connecting sub-layer 1163 is in contact with the second buried layer 115.

[0042] Specifically, multiple connecting sub-layers 1163 are spaced apart along the second direction Y, wherein the spacing between adjacent connecting sub-layers 1163 can form a conductive channel between the source and drain. Each connecting sub-layer 1163 has an overlapping region with the first buried layer 114 and the second buried layer 115, namely the first overlapping sub-region 1164 and the second overlapping sub-region 1165, thereby realizing the electrical connection between the first buried layer 114 and the second buried layer 115. By designing the arrangement and spacing of the connecting sub-layers 1163, multiple local interruption regions can be formed in the second buried layer 115. In the local interruption regions, the second buried layer 115 and the surrounding epitaxial layer 119 form a reverse bias junction. This allows for the distribution and control of the depletion regions on both sides of the second buried layer 115, thereby optimizing the electric field distribution inside the device and improving the electric field concentration problem at the corner of the gate trench 117. It also enhances the dynamic pinch-off capability of the depletion region to the current path under abnormal operating conditions such as high drain voltage or short circuit.

[0043] Based on the above embodiments, Figure 9 for Figure 3 Another schematic diagram of a cross-sectional structure at position AA'. Figure 10 for Figure 3 Another schematic diagram of the cross-sectional structure at the BB' position is shown in the image. Figure 9 and Figure 10 Compared to the embodiments in this application Figure 4 The difference lies in that the second buried layer 115 is disposed on the side of the first buried layer 114 near the first surface and extends along the second direction Y; wherein, the functions of the first buried layer 114 and the second buried layer 115 are the same as... Figure 4 The embodiments serve the same purpose: an adaptive JFET structure can be formed by the first buried layer 114, the second buried layer 115, and the interconnect layer 116. Under abnormal operating conditions such as short circuits or overvoltages, the effective conductive cross-section is automatically reduced by the pinch-off effect of the depletion region of the second buried layer 115 in the JFET structure, thereby suppressing a sharp rise in current and improving the device's short-circuit withstand capability. Furthermore, the gate oxide layer is protected by the second region 113, the first buried layer 114, the second buried layer 115, and the interconnect layer 116 to improve the reliability of the device.

[0044] This application provides a power module based on the above embodiments, including a substrate and a semiconductor device according to any embodiment of this application, wherein the substrate is used to support the semiconductor device. The power module provided by this application has the same beneficial effects as the semiconductor device according to any embodiment of this application.

[0045] This application provides a power conversion circuit based on the above embodiments. The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, with the semiconductor device electrically connected to the circuit board. The power conversion circuit provided by this application has the same beneficial effects as the semiconductor device in any embodiment of this application.

[0046] Based on the above embodiments, this application provides a vehicle including a load and a power conversion circuit as described in any embodiment of this application. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0047] Based on the above embodiments, this application also provides a method for fabricating a semiconductor device. Figure 11 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application, combined with... Figures 3-5 The preparation methods include: S110, providing semiconductor body 110; The semiconductor body 110 includes a first surface and a second surface disposed opposite to each other; The semiconductor body 110 further includes a well region 111, a first region 112, a second region 113, and a first buried layer 114; the first region 112 is disposed on a first surface of the semiconductor body 110, and the well region 111 is disposed on the side of the first region 112 away from the first surface; a gate trench 117 is also disposed on the first surface; the second region 113 is disposed on the first surface and located on one side of the gate trench 117; at least a portion of the well region 111 is located between the second region 113 and the gate trench 117; wherein, the depth of the second region 113 in the thickness direction of the semiconductor body is... The depth of the gate trench 117 in the thickness direction of the semiconductor body is greater than that of the gate trench 117; the first buried layer 114 is disposed on the side of the second region 113 away from the first surface and contacts the second region 112; wherein, at least a portion of the orthographic projection of the first buried layer 114 on the second surface overlaps with the orthographic projection of the well region 111 between the second region 113 and the gate trench 117 on the second surface; the thickness direction is the direction from the first surface to the second surface; the first region 112 is of the first conductivity type, and the well region 111, the second region 113 and the first buried layer 114 are of the second conductivity type; The semiconductor devices include, but are not limited to, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), JFETs (Junction Field-Effect Transistors), IGBTs (Insulated-Gate Bipolar Transistors), and HEMTs (High Electron Mobility Transistors). The semiconductor body can include wide-bandgap or ultra-wide-bandgap semiconductor materials such as silicon carbide semiconductor bodies and gallium nitride semiconductor bodies. For example, the MOSFET includes N-type MOSFETs or P-type MOSFETs. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. Regions with N-type conductivity can be formed by N-type doping, where the dopant ions can be phosphorus (P) ions or nitrogen (N) ions; regions with P-type conductivity can be formed by P-type doping, where the dopant ions can be aluminum (Al) ions or boron (B) ions. For example, the embodiments described below use an N-type conductivity type as the first conductivity type and a P-type conductivity type as the second conductivity type.

[0048] Specifically, the semiconductor body 110 may include a substrate 118, an epitaxial layer 119, a well region 111, a first region 112, a second region 113, and a first buried layer 114. The epitaxial layer 119 is located on one side of the substrate 118, and the epitaxial layer 119 can be formed on the surface of the substrate 118 by epitaxial growth.

[0049] The surface of the epitaxial layer 119 away from the substrate 118 serves as the first surface of the semiconductor body 110. A first region 112 is disposed on the first surface, and a well region 111 is disposed on the side of the first region 112 away from the first surface. The well region 111 and the first region 112 can be formed by epitaxial growth, ion implantation, or vapor deposition. For example, when the well region 111 and the first region 112 are formed by epitaxial growth or vapor deposition, the first surface of the semiconductor body 110 can be considered as a renewed surface. For instance, if the well region 111 is epitaxially grown on the surface of the epitaxial layer 119 away from the substrate 118, then the surface of the well region 111 away from the substrate 118 is renewed as the first surface of the semiconductor body 110, and the first region 112 is epitaxially grown on the surface of the well region 111 away from the substrate 118. When the well region 111 and the first region 112 are formed by ion implantation, the first surface of the semiconductor body 110 can be regarded as a fixed surface. For example, the surface of the epitaxial layer 119 away from the substrate 118, i.e., the first surface, is ion implanted to form the well region 111, and then the first region 112 is formed again by ion implantation on the first surface.

[0050] A gate trench 117 is also provided on the first surface, which can be formed by an etching process. The gate trench 117 extends from the first surface into the epitaxial layer 119, passing through the first region 112 and the well region 111. The well region 111 and the first region 112 on both sides of the gate trench 117 are used to form conductive channels of the semiconductor device, wherein the first region 112 is of a first conductivity type and the well region 111 is of a second conductivity type.

[0051] A second region 113 is further disposed on the first surface of the semiconductor body 110. The second region 113 extends into the epitaxial layer 119, and in the first direction X, the second region 113 is located on the side of the first region 112 away from the gate trench 117. Exemplarily, the second region 113 can be disposed on one or both sides of the gate trench 117. When the second region 113 is disposed on both sides of the gate trench 117, the two second regions 113 can be disposed symmetrically or asymmetrically relative to the gate trench 117. In this embodiment, for example, the second region 113 is disposed on both sides of the gate trench 117. The second region 113 has a second conductivity type and can be formed by ion implantation. The conductivity type of the second region 113 is the same as that of the well region 111. Therefore, when a high voltage is applied to the drain, a depletion region can be formed between the second region 113 and the epitaxial layer 119, which can serve to shield the gate corner electric field.

[0052] A first buried layer 114 is also disposed within the epitaxial layer 119, and the first buried layer 114 is of a second conductivity type. The first buried layer 114 can be formed by ion implantation. The first buried layer 114 is located on the side of the second region 113 away from the first surface, and the orthographic projections of the first buried layer 114 and the second region 113 on the second surface overlap. That is, in the thickness direction of the semiconductor device, at least a portion of the first buried layer 114 is disposed below the second region 113, and the first buried layer 114 and the second region 113 are electrically connected at the corresponding overlapping positions. This connection can be a direct contact connection or an indirect connection formed by an electrical connection structure between the first buried layer 114 and the second region 113; no specific limitation is made here. Exemplarily, in this embodiment, the first buried layer 114 and the second region 113 are connected by contact.

[0053] Furthermore, since the depth of the second region 113 in the thickness direction of the semiconductor body is greater than the depth of the gate trench 117 in the thickness direction of the semiconductor body, when a higher voltage is applied to the drain 140, a depletion region will be formed between the second region 113 and the epitaxial layer 119, which can also effectively shield the influence of the high electric field on the gate oxide layer forming the corner of the gate. By designing the depth of the second region 113 to be greater than the depth of the gate trench 117, the second region 113 can cover the bottom corner region of the trench in the thickness direction, thereby improving the problem of gate oxide layer breakdown.

[0054] The first buried layer 114 is disposed on the side of the second region 113 away from the first surface and contacts the second region 112. A depletion region may also be formed between the first buried layer 114 and the epitaxial layer 117. At least a portion of the orthographic projection of the first buried layer 114 on the second surface overlaps with the orthographic projection of the well region 111 between the second region 113 and the gate trench 117 on the second surface. That is, in the first direction X, the first buried layer 114 may extend toward the gate trench 117, wherein the first buried layer 114 may extend between the second region 113 and the gate trench 117, such as... Figure 1 As shown. The first buried layer 114 can also extend below the gate trench 117, as... Figure 2 As shown. In other words, when the depth of the third region 114 is greater than the depth of the gate trench 115, the third region 114 extends towards the gate trench 115, thereby further protecting the bottom corner of the gate trench 115, which can improve the problem of gate oxide layer breakdown and ensure the reliability of device operation.

[0055] S120, A gate 120 is formed in the gate trench 117; Specifically, a gate 120 is disposed within the gate trench 117. For example, a first insulating layer 150 is disposed between the gate trench 117 and the gate 120. The first insulating layer 150 can be obtained by oxidizing the inner wall and bottom of the gate trench 117 and can be called a gate oxide layer. The gate oxide layer can be a high dielectric constant (K) material. The gate 120 can be polysilicon. The well regions 111 on both sides of the gate 120 can form vertical conductive channels. The structure of the gate trench 117 can also reduce the JFET region between the second region 113 and the epitaxial layer 119, further reducing the on-resistance of the semiconductor device.

[0056] S130, a source electrode 130 is formed on the first surface, and a drain electrode 140 is formed on the second surface.

[0057] Specifically, a source electrode is disposed on the first surface of the semiconductor body 110. For example, the source electrode can be formed by sputtering or other methods, and can be titanium (Ti), nickel (Ni), or silver (Ag). The source electrode forms an ohmic contact with the first region 112 and the second region 113. A second insulating layer 160 is also included between the source electrode and the gate electrode. The second insulating layer 160 can be an interlayer dielectric (ILD) layer, covering the surface of the gate electrode and isolating the gate electrode from the source electrode. A drain electrode can also be formed on the second surface by sputtering or other methods. The second surface can be thinned first, and then the drain electrode can be formed by sputtering or other methods. The drain electrode can be titanium (Ti), nickel (Ni), or silver (Ag).

[0058] Figure 12 This is a flowchart illustrating a method for fabricating a semiconductor body for a semiconductor device according to an embodiment of this application. Figures 13 to 17 This is a schematic diagram of the intermediate structure of the preparation process provided in the embodiments of this application. The preparation method includes: S210, providing substrate 118; S220: A first epitaxial layer 210 is formed on one side of the substrate 118, and a first buried layer 114, a second buried layer 115, and a connecting layer 116 are formed in the first epitaxial layer 210; in the thickness direction, the second buried layer 115 is disposed on one side of the first buried layer 114; in the first direction X, the second buried layer 115 is located on the side of the first buried layer 114 away from the second region 112, and the first direction X is perpendicular to the thickness direction of the semiconductor body; the connecting layer 116 is disposed between the first buried layer 114 and the second buried layer 115; both ends of the connecting layer 116 are in contact with the first buried layer 114 and the second buried layer 115, respectively; wherein, the connecting layer 116, the first buried layer 114, and the second buried layer 115 all extend along the second direction Y, the second direction Y is perpendicular to the first direction X and perpendicular to the thickness direction; the extension length of the connecting layer 116 in the second direction Y is less than the extension length of the first buried layer 114 and the second buried layer 115 in the second direction Y. Specifically, the first epitaxial layer 210 includes a first sub-epitaxy layer 211 and a second sub-epitaxy layer 212 stacked together. The first sub-epitaxy layer 211 can be formed on one side of the substrate 118. The first sub-epitaxy layer 211 can be formed on the surface of the substrate 118 by epitaxial growth, and a second buried layer 115 can be formed on the surface of the first sub-epitaxy layer 211 by ion implantation. Its structure is as follows: Figure 13 As shown.

[0059] A second sub-epipolar layer 212 is grown on the first sub-epipolar layer 211, and a first buried layer 114 is formed by implantation in the second sub-epipolar layer 212. In the embodiments of this application, the first buried layer 114 and the second buried layer 115 may not overlap in the orthographic projection direction.

[0060] Ion implantation is performed on the second sub-epilithographic layer 212 to form a connecting layer 116. The connecting layer 116 has a first overlapping region 1161 and a second overlapping region 1162 with the first buried layer 114 and the second buried layer 115 in the thickness direction. The first buried layer 114 is connected to the connecting layer 116 in the first overlapping region 1161 and the second buried layer 115 in the second overlapping region 1162. Its structure is as follows. Figure 14 As shown.

[0061] exist Figure 9 In the embodiment, a first buried layer 114 can be formed on the surface of the first sub-epilithial layer 211 by ion implantation. Its structure is as follows: Figure 15 As shown.

[0062] A second sub-epitaxy layer 212 is grown on the first sub-epitaxy layer 211, and a second buried layer 115 is formed by injection into the second sub-epitaxy layer 212.

[0063] Ion implantation is performed on the second sub-epilithographic layer 212 to form a connecting layer 116. The connecting layer 116 has a first overlapping region 1161 and a second overlapping region 1162 with the first buried layer 114 and the second buried layer 115 in the thickness direction. The first buried layer 114 is connected to the connecting layer 116 in the first overlapping region 1161 and the second buried layer 115 in the second overlapping region 1162. Its structure is as follows. Figure 16 As shown.

[0064] Combination Figure 8 Optionally, a plurality of connecting sub-layers 1163 arranged at intervals along the second direction Y can be formed between the first buried layer 114 and the second buried layer 115; the connecting sub-layers 1163 are in contact with the first buried layer 114; the same connecting sub-layer 1163 is in contact with the second buried layer 115.

[0065] Specifically, multiple connecting sub-layers 1163 are spaced apart along the second direction Y, wherein the spacing between adjacent connecting sub-layers 1163 can form a conductive channel between the source and drain. Each connecting sub-layer 1163 has an overlapping region with the first buried layer 114 and the second buried layer 115, namely the first overlapping sub-region 1164 and the second overlapping sub-region 1165, thereby realizing the electrical connection between the first buried layer 114 and the second buried layer 115. By designing the arrangement and spacing of the connecting sub-layers 1163, multiple local interruption regions can be formed in the second buried layer 115. In the local interruption regions, the second buried layer 115 and the surrounding epitaxial layer 119 form a reverse bias junction. This allows for the distribution and control of the depletion regions on both sides of the second buried layer 115, thereby optimizing the electric field distribution inside the device and improving the electric field concentration problem at the corner of the gate trench 117. It also enhances the dynamic pinch-off capability of the depletion region to the current path under abnormal operating conditions such as high drain voltage or short circuit.

[0066] S230, A second epitaxial layer 220 is formed on the first epitaxial layer 210; S240, the surface of the second epitaxial layer 220 away from the substrate 118 serves as the first surface of the semiconductor body 110, and a well region 111, a first region 112, and a second region 113 are sequentially formed in the second epitaxial layer 220. Specifically, the first surface can be the surface of the second epitaxial layer 220 away from the substrate 118. The well region 111 and the first region 112 can be formed by epitaxial growth, ion implantation, or vapor deposition. For example, when the well region 111 and the first region 112 are formed by epitaxial growth or vapor deposition, the first surface of the semiconductor body 110 can be considered a renewed surface. For instance, if the well region 111 is epitaxially grown on the surface of the epitaxial layer 119 away from the substrate 118, then the surface of the well region 111 away from the substrate 118 is renewed as the first surface of the semiconductor body 110, and the first region 112 is epitaxially grown on the surface of the well region 111 away from the substrate 118. When the well region 111 and the first region 112 are formed by ion implantation, the first surface of the semiconductor body 110 can be considered a fixed surface. For instance, the well region 111 is formed by ion implantation on the surface of the epitaxial layer 119 away from the substrate 118, i.e., the first surface, and then the first region 112 is formed again by ion implantation on the first surface. The second region 113 can be formed by ion implantation, and the second region 113 extends from the first surface into the second epitaxial layer 220 and / or the first epitaxial layer 210.

[0067] S250, A gate trench 117 is formed on the first surface; the orthographic projection of the second buried layer 115 on the second surface overlaps with the orthographic projection of the gate trench 117 on the second surface.

[0068] Specifically, a gate trench 117 is formed on the first surface through an etching process. The gate trench 117 extends from the first surface into the interior of the third epitaxial layer 119, passing through the first region 112 and the well region 111. This is combined with... Figure 3 The gate trench 117 can be a continuous trench in the second direction Y. The second region 113 is located on one side of the gate trench 117. Exemplarily, the second region 113 can be provided on one or both sides of the gate trench 117. When the second region 113 is provided on both sides of the gate trench 117, the two second regions 113 can be arranged symmetrically or asymmetrically relative to the gate trench 117. In this embodiment, for example, the second region 113 is provided on both sides of the gate trench 117. Its structure is as follows... Figure 17 As shown.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; The semiconductor body further includes a well region, a first region, a second region, and a first buried layer; the first region is disposed on a first surface of the semiconductor body, and the well region is disposed on the side of the first region away from the first surface; the first surface is also provided with a gate trench; the second region is disposed on the first surface and located on one side of the gate trench; at least a portion of the well region is located between the second region and the gate trench; wherein the depth of the second region in the thickness direction of the semiconductor body is greater than the depth of the gate trench in the thickness direction of the semiconductor body; the first buried layer is disposed on the side of the second region away from the first surface and contacts the second region; wherein at least a portion of the orthographic projection of the first buried layer on the second surface overlaps with the orthographic projection of the well region between the second region and the gate trench on the second surface; the first region is of a first conductivity type, and the well region and the second region are of a second conductivity type; the thickness direction is the direction from the first surface to the second surface; The gate is located within the gate trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor body further includes: a second buried layer and a connection layer; In the thickness direction, the second buried layer is disposed on one side of the first buried layer; in the first direction, the second buried layer is located on the side of the first buried layer away from the second region, and the first direction is perpendicular to the thickness direction of the semiconductor body; the orthographic projection of the second buried layer on the second surface overlaps with the orthographic projection of the gate trench on the second surface; the connecting layer is disposed between the first buried layer and the second buried layer; both ends of the connecting layer are in contact with the first buried layer and the second buried layer, respectively; The connecting layer, the first buried layer, and the second buried layer all extend along a second direction, which is perpendicular to the first direction and the thickness direction; the extension length of the connecting layer in the second direction is less than the extension length of the first buried layer and the second buried layer in the second direction.

3. The semiconductor device according to claim 2, characterized in that, The orthographic projection of the first embedded layer on the second surface does not overlap with the orthographic projection of the second embedded layer on the second surface.

4. The semiconductor device according to any one of claims 2-3, characterized in that, The connection layer includes a plurality of connection sub-layers arranged at intervals along the second direction; The connecting sublayer is in contact with the first buried layer; the same connecting sublayer is in contact with the second buried layer.

5. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 1-4, wherein the substrate is used to support the semiconductor device.

6. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-4, wherein the semiconductor device is electrically connected to the circuit board.

7. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 6, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

8. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; The semiconductor body further includes a well region, a first region, a second region, and a first buried layer; the first region is disposed on a first surface of the semiconductor body, and the well region is disposed on the side of the first region away from the first surface; the first surface is also provided with a gate trench; the second region is disposed on the first surface and located on one side of the gate trench; at least a portion of the well region is located between the second region and the gate trench; wherein the depth of the second region in the thickness direction of the semiconductor body is greater than the depth of the gate trench in the thickness direction of the semiconductor body; the first buried layer is disposed on the side of the second region away from the first surface and contacts the second region; wherein at least a portion of the orthographic projection of the first buried layer on the second surface overlaps with the orthographic projection of the well region between the second region and the gate trench on the second surface; the first region is of a first conductivity type, and the well region, the second region, and the first buried layer are of a second conductivity type; the thickness direction is the direction from the first surface to the second surface; A gate is formed within the gate trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The semiconductor body further includes: a second buried layer and a connection layer; Provide semiconductor bodies, including: Provide substrate; A first epitaxial layer is formed on one side of the substrate, and a first buried layer, a second buried layer, and a connecting layer are formed in the first epitaxial layer; in the thickness direction, the second buried layer is disposed on one side of the first buried layer; in a first direction, the second buried layer is located on the side of the first buried layer away from the second region, and the first direction is perpendicular to the thickness direction of the semiconductor body; the connecting layer is disposed between the first buried layer and the second buried layer; both ends of the connecting layer are in contact with the first buried layer and the second buried layer, respectively; wherein the connecting layer, the first buried layer, and the second buried layer all extend along a second direction, the second direction being perpendicular to the first direction and perpendicular to the thickness direction; the extension length of the connecting layer in the second direction is less than the extension length of the first buried layer and the second buried layer in the second direction; A second epitaxial layer is formed on the first epitaxial layer; The surface of the second epitaxial layer away from the substrate serves as the first surface of the semiconductor body, and the well region, the first region, and the second region are sequentially formed within the second epitaxial layer; The gate trench is formed on the first surface, and the orthographic projection of the second buried layer on the second surface overlaps with the orthographic projection of the gate trench on the second surface.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The first epitaxial layer includes a first sub-epiaxial layer and a second sub-epiaxial layer stacked together; the first buried layer, the second buried layer, and the connecting layer are formed in the first epitaxial layer, including: The first sub-epipolar layer is formed on one side of the substrate; The second buried layer is formed in the first sub-epipolar layer; A second sub-epitaxial layer is formed on the side of the first sub-epitaxial layer away from the substrate, and the first buried layer is formed in the second sub-epitaxial layer; The connecting layer is formed between the first buried layer and the second buried layer; Alternatively, the first buried layer, the second buried layer, and the connecting layer are formed in the first epitaxial layer, including: The first sub-epipolar layer is formed on one side of the substrate; The first buried layer is formed in the first sub-epipolar layer; A second sub-epitaxial layer is formed on the side of the first sub-epitaxial layer away from the substrate, and a second buried layer is formed in the second sub-epitaxial layer; The connecting layer is formed between the first buried layer and the second buried layer.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The connecting layer formed between the first buried layer and the second buried layer includes: A plurality of connecting sub-layers are formed between the first buried layer and the second buried layer, spaced apart along the second direction; the connecting sub-layers are in contact with the first buried layer; the same connecting sub-layer is in contact with the second buried layer.

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