Trench-type silicon carbide high-voltage n-type mosfet and method of manufacturing the same

Abstract

The application provides a trench type silicon carbide high-voltage N-type MOSFET and a preparation method thereof, which comprises, from bottom to top, an N++ silicon carbide substrate, an N+ buffer layer, a third epitaxial layer, a second epitaxial layer and a first epitaxial layer. A trench gate structure is formed on the surface of the device, the trench penetrates through the first epitaxial layer and the second epitaxial layer in sequence and just extends to the top of the third epitaxial layer. A gate oxide layer is arranged on the sidewall and the bottom of the trench, and the trench is filled with a polysilicon gate. An N-type protection net structure is arranged below the bottom of the trench. An N+ source region and a P+ contact region are formed between adjacent trenches on the surface of the device, and the P+ contact region extends downward from the surface and reaches the second epitaxial layer. The structure can reduce the peak electric field at the bottom of the trench, improve the stability of the device voltage resistance, improve the current spreading of the source region and the short-circuit effect of the body region, and inhibit the parasitic bipolar effect, and is suitable for high-voltage silicon carbide power devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a trench-type silicon carbide high-voltage N-type MOSFET and its fabrication method. Background Technology

[0002] Silicon carbide MOSFETs, especially high-voltage trench SiC MOSFETs, are widely used in high-voltage, high-temperature, and high-efficiency power electronic systems due to their high breakdown field strength, low conduction loss, and high switching frequency. Compared to planar gate structures, trench MOSFETs can reduce the on-resistance per unit area by increasing the channel density, thus having a significant advantage in high-voltage devices.

[0003] However, existing high-voltage trench SiC MOSFETs still have the following problems: 1. Severe electric field concentration at the bottom of the trench Under high voltage blocking conditions, trench structures are prone to forming local electric field peaks at the bottom or corners of the trench, which leads to a decrease in the actual breakdown voltage of the device and reduces long-term reliability. 2. It is difficult to achieve both high voltage and low on-resistance. To achieve high withstand voltage, a thicker, lightly doped drift layer is usually required, but a thicker drift layer will increase the specific on-resistance of the device. 3. Insufficient or excessive short-circuiting effect in the body area can both cause problems. If the P+ contact region below the source metal is too shallow, the bulk contact will be insufficient, which can easily lead to parasitic bipolar transistor effects; if it is too deep, it may worsen the local electric field distribution and increase the cell area loss. 4. Improper matching between trenches and epitaxial layers can lead to decreased reliability. If the trench is too shallow, the advantages of the trench grid structure cannot be fully utilized; if the trench is too deep, a stronger electric field concentration problem is easily introduced at the bottom of the trench. Therefore, it is necessary to design a new high-voltage trench SiC N-type MOSFET structure to achieve a balance between high voltage withstand capability, low electric field peak value, and good conduction performance. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a trench-type silicon carbide high-voltage N-type MOSFET and its fabrication method.

[0005] According to the present invention, a trench-type silicon carbide high-voltage N-type MOSFET includes an N++ silicon carbide substrate, an N+ buffer layer, a third epitaxial layer, a second epitaxial layer and a first epitaxial layer arranged sequentially from bottom to top; The first epitaxial layer is a P-well epitaxial layer, the second epitaxial layer is an N-well epitaxial layer, and the third epitaxial layer is a P-voltage withstand epitaxial layer; A trench structure extends downward from the upper surface of the first epitaxial layer, the trench structure penetrates the first epitaxial layer and the second epitaxial layer, and the bottom of the trench structure is located in the third epitaxial layer; The trench structure includes a trench, a gate oxide layer located on the inner wall of the trench, and a polysilicon gate filled in the trench. An N-type protective mesh structure is provided below the trench structure; An N+ source region and a P+ contact region are provided in the first epitaxial layer between adjacent trench structures.

[0006] Furthermore, the thickness of the first epitaxial layer is 0.5 μm to 2 μm, the thickness of the second epitaxial layer is 1 μm to 5 μm, and the thickness of the third epitaxial layer is 50 μm to 100 μm.

[0007] Furthermore, the N-type protective mesh structure is located on top of the third epitaxial layer.

[0008] Furthermore, the N-type protection network structure is a strip-shaped, island-shaped, grid-shaped, or continuously distributed N-type doped structure.

[0009] Furthermore, the P+ contact area extends downward from the upper surface of the first epitaxial layer to the junction of the first epitaxial layer and the second epitaxial layer, or extends downward to the upper part of the second epitaxial layer.

[0010] Furthermore, the N+ source region is located within the first epitaxial layer, extends downward from the upper surface of the first epitaxial layer, and is located on both sides of the P+ contact region.

[0011] Furthermore, it also includes a first metal layer, which is in ohmic contact with both the N+ source region and the P+ contact region.

[0012] Furthermore, the corners at the bottom of the trench structure are rounded.

[0013] Furthermore, it also includes a second metal layer attached to the bottom surface of the N++ silicon carbide substrate.

[0014] A method for fabricating a trench-type silicon carbide high-voltage N-type MOSFET according to the present invention includes the following steps: S1: Provide an N++ silicon carbide substrate and form an N+ buffer layer on the N++ silicon carbide substrate; S2: A third epitaxial layer is grown on the N+ buffer layer; S3: A second epitaxial layer is epitaxially grown on the third epitaxial layer; S4: Epitaxially grow a first epitaxial layer on the second epitaxial layer; S5: A trench is formed on the upper surface of the first epitaxial layer, so that the trench passes through the first epitaxial layer and the second epitaxial layer in sequence, and extends to the upper part of the third epitaxial layer; S6: An N-type protective mesh structure is formed below the bottom of the trench; S7: A gate oxide layer is formed on the sidewalls and bottom of the trench, and a polysilicon gate is formed inside the trench; S8: Formation of N+ source region and P+ contact region; S9: A first metal layer is formed on the N+ source region and the P+ contact region, and a second metal layer is formed on the back side of the N++ silicon carbide substrate.

[0015] Compared with the prior art, the present invention has the following beneficial effects: (1) Reduce the peak electric field at the bottom of the trench: Since the trench depth just extends to the top of the third epitaxial layer and an N-protection mesh structure is set below the bottom of the trench, the electric field concentration at the bottom tip of the trench can be significantly reduced, thereby improving the breakdown stability of the device.

[0016] (2) Improve high voltage blocking capability: The third epitaxial layer serves as the main voltage-resistant epitaxial layer and undertakes high voltage blocking; at the same time, the N protection grid assists the electric field to spread downward, avoiding premature breakdown of local high fields, thus helping to achieve higher voltage resistance.

[0017] (3) Improve the short circuit of the body region and suppress parasitic bipolar effect: The P+ contact region below the source metal just reaches the second epitaxial layer, which makes the body region contact more sufficient, which is conducive to suppressing the conduction of parasitic NPN bipolar transistors and improving the safe operation capability of the device.

[0018] (4) Balancing low conduction loss and high reliability: Through the coordinated design of three-layer epitaxy, trench depth and P+ region depth, conduction loss can be reduced while avoiding field strength degradation caused by excessively deep trenches and P+ regions.

[0019] (5) Structural optimization suitable for high voltage SiC trench MOSFETs: This invention is particularly suitable for high voltage silicon carbide N-channel MOSFETs, and has good structural rationality and process feasibility in high voltage applications.

[0020] This invention addresses the challenges of handling high voltage and channel control through the coordinated design of the three-layer epitaxial structure, trench depth, trench bottom protection zone, and the depth of the P+ contact region under the source electrode. By extending the trench just to the first epitaxial layer, it avoids the problem of electric field concentration caused by deep trenches. The use of an N-protection mesh structure below the trench provides shielding and buffering of the electric field at the trench bottom. Furthermore, by extending the P+ region below the metal just to the second epitaxial layer, it optimizes cathode short-circuiting, hole extraction, and conduction modulation. These improvements effectively reduce the peak electric field at the trench bottom, enhance high-voltage blocking capability, improve body short-circuiting and hole extraction capabilities, suppress parasitic bipolar effects, and balance lower on-resistance with higher reliability. Attached Figure Description

[0021] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the trench-type silicon carbide high-voltage N-type MOSFET of the present invention; Figure 2 This is a magnified view of the trench depth and the N+ / P+ protective mesh structure. Figure 3 This is a magnified view of the P+ region extending from the metal beneath the second epitaxial layer. Figure 4 This is a schematic diagram of the channel and current path when the device is turned on. Figure 5 A schematic diagram of the download flow carrier extraction path for the device in the off state; Figure 6 This is a schematic diagram of the device doping distribution; Figure 7 This is a schematic diagram of the electric field distribution under the device's blocking state. Detailed Implementation

[0022] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0023] like Figure 1 and Figure 6 As shown, the present invention provides a trench-type silicon carbide high-voltage N-type MOSFET, comprising an N++ silicon carbide substrate, an N+ buffer layer, a third epitaxial layer, a second epitaxial layer and a first epitaxial layer arranged sequentially from bottom to top.

[0024] The first epitaxial layer is a P-well epitaxial layer, used to form the MOS channel region. The second epitaxial layer is an N-well epitaxial layer, serving as an N-type control epitaxial layer or a current-spreading epitaxial layer. The third epitaxial layer is a P-voltage-resistant epitaxial layer, used to bear the main blocking voltage of the device. The thickness of the first epitaxial layer is 0.5 μm to 2 μm, preferably 1 μm. The thickness of the second epitaxial layer is 1 μm to 5 μm, preferably 2 μm. The thickness of the third epitaxial layer is 50 μm to 100 μm, preferably 75 μm.

[0025] like Figure 2 As shown, a trench structure extends downwards from the upper surface of the first epitaxial layer, penetrating both the first and second epitaxial layers. The bottom of the trench structure is located above the third epitaxial layer. Below the trench structure is an N-type protection mesh structure, located above the third epitaxial layer. The N-type protection mesh structure is a strip-shaped, island-shaped, mesh-shaped, or continuously distributed N-type doped structure used to regulate the electric field distribution at the bottom of the trench. The trench structure includes a trench, a gate oxide layer on the inner wall of the trench, and a polysilicon gate filling the trench. The corners at the bottom of the trench structure are rounded to further reduce electric field concentration at the bottom of the trench.

[0026] like Figure 3 As shown, an N+ source region and a P+ contact region are disposed within the first epitaxial layer between adjacent trench structures. The P+ contact region extends downward from the upper surface of the first epitaxial layer to the junction of the first and second epitaxial layers, or downward to the upper part of the second epitaxial layer. The N+ source region is located within the first epitaxial layer, extending downward from the upper surface of the first epitaxial layer, and is located on both sides of the P+ contact region. The P+ contact region just reaches the second epitaxial layer, enhancing the clamping effect on the body potential, thereby more effectively suppressing the turn-on of parasitic bipolar transistors and improving the stability of the device under avalanche and short-circuit conditions.

[0027] The first metal layer makes ohmic contact with both the N+ source region and the P+ contact region, serving as the source of the device. The second metal layer is connected to the bottom surface of the N++ silicon carbide substrate, serving as the drain of the device.

[0028] Working mechanism: 1. Conductive state, like Figure 4 As shown, after the gate is forward biased, an inverted channel is formed near the P-well epitaxial layer and the trench sidewall. Electrons are injected from the N+ source region, enter the second and third epitaxial layers through the channel, and finally flow out from the drain.

[0029] 2. Blocked state: like Figure 5 , Figure 7As shown, when the gate and source are shorted or the gate is zero biased, the device enters the blocking state. At this time, the high voltage is mainly borne by the third epitaxial layer, and the N-type protection network below the bottom of the trench extends the electric field into the third epitaxial layer, thereby reducing the local peak electric field at the bottom of the trench.

[0030] The present invention also provides a method for fabricating the above-mentioned trench-type silicon carbide high-voltage N-type MOSFET, comprising the steps of: S1: Provide an N++ silicon carbide substrate and form an N+ buffer layer on the N++ silicon carbide substrate.

[0031] S2: A third epitaxial layer is grown on the N+ buffer layer.

[0032] S3: A second epitaxial layer is grown on the third epitaxial layer.

[0033] S4: The first epitaxial layer is epitaxially grown on the second epitaxial layer.

[0034] S5: A trench is formed on the upper surface of the first epitaxial layer, so that the trench passes through the first epitaxial layer and the second epitaxial layer in sequence, and extends to the upper part of the third epitaxial layer.

[0035] S6: An N-shaped protective mesh structure is formed below the bottom of the trench.

[0036] S7: A gate oxide layer is formed on the sidewalls and bottom of the trench, and a polysilicon gate is formed inside the trench.

[0037] S8: Forms the N+ source region and the P+ contact region.

[0038] S9: A first metal layer is formed on the N+ source region and the P+ contact region, and a second metal layer is formed on the back side of the N++ silicon carbide substrate.

[0039] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0040] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A trench-type silicon carbide high-voltage N-type MOSFET, characterized in that, It includes, from bottom to top, an N++ silicon carbide substrate, an N+ buffer layer, a third epitaxial layer, a second epitaxial layer, and a first epitaxial layer; The first epitaxial layer is a P-well epitaxial layer, the second epitaxial layer is an N-well epitaxial layer, and the third epitaxial layer is a P-voltage withstand epitaxial layer; A trench structure extends downward from the upper surface of the first epitaxial layer, the trench structure penetrates the first epitaxial layer and the second epitaxial layer, and the bottom of the trench structure is located in the third epitaxial layer; The trench structure includes a trench, a gate oxide layer located on the inner wall of the trench, and a polysilicon gate filled in the trench. An N-type protective mesh structure is provided below the trench structure; An N+ source region and a P+ contact region are provided in the first epitaxial layer between adjacent trench structures.

2. The trench-type silicon carbide high-voltage N-type MOSFET according to claim 1, characterized in that, The thickness of the first epitaxial layer is 0.5 μm to 2 μm, the thickness of the second epitaxial layer is 1 μm to 5 μm, and the thickness of the third epitaxial layer is 50 μm to 100 μm.

3. The trench-type silicon carbide high-voltage N-type MOSFET according to claim 1, characterized in that, The N-type protection mesh structure is located on the upper part of the third epitaxial layer.

4. The trench-type silicon carbide high-voltage N-type MOSFET according to claim 1, characterized in that, The N-type protection network structure is a strip-shaped, island-shaped, grid-shaped, or continuously distributed N-type doped structure.

5. The trench-type silicon carbide high-voltage N-type MOSFET according to claim 1, characterized in that, The P+ contact area extends downward from the upper surface of the first epitaxial layer to the junction of the first epitaxial layer and the second epitaxial layer, or extends downward to the upper part of the second epitaxial layer.

6. The trench-type silicon carbide high-voltage N-type MOSFET according to claim 1, characterized in that, The N+ source region is located within the first epitaxial layer, extends downward from the upper surface of the first epitaxial layer, and is located on both sides of the P+ contact region.

7. The trench-type silicon carbide high-voltage N-type MOSFET according to claim 1, characterized in that, It also includes a first metal layer, which is in ohmic contact with both the N+ source region and the P+ contact region.

8. The trench-type silicon carbide high-voltage N-type MOSFET according to claim 1, characterized in that, The corners at the bottom of the trench structure are rounded.

9. The trench-type silicon carbide high-voltage N-type MOSFET according to claim 1, characterized in that, It also includes a second metal layer attached to the bottom surface of the N++ silicon carbide substrate.

10. A method for fabricating a trench-type silicon carbide high-voltage N-type MOSFET, characterized in that, Including the following steps: S1: Provide an N++ silicon carbide substrate and form an N+ buffer layer on the N++ silicon carbide substrate; S2: A third epitaxial layer is grown on the N+ buffer layer; S3: A second epitaxial layer is epitaxially grown on the third epitaxial layer; S4: Epitaxially grow a first epitaxial layer on the second epitaxial layer; S5: A trench is formed on the upper surface of the first epitaxial layer, so that the trench passes through the first epitaxial layer and the second epitaxial layer in sequence, and extends to the upper part of the third epitaxial layer; S6: An N-type protective mesh structure is formed below the bottom of the trench; S7: A gate oxide layer is formed on the sidewalls and bottom of the trench, and a polysilicon gate is formed inside the trench; S8: Formation of N+ source region and P+ contact region; S9: A first metal layer is formed on the N+ source region and the P+ contact region, and a second metal layer is formed on the back side of the N++ silicon carbide substrate.

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