Semiconductor structure and method of making same, self-aligned silicide block structure

Abstract

The application discloses a semiconductor structure and a preparation method thereof and a self-aligned silicide blocking structure. The method comprises the following steps: forming a dielectric layer stack structure comprising a first dielectric layer and a second dielectric layer on a substrate; after a covering layer is deposited on the surface of the first dielectric layer and the narrow-pitch opening, spin-coating photoresist on the covering layer; performing a patterning process on the photoresist to obtain a photoresist pattern; and after the covering layer is removed, performing etching treatment on the first dielectric layer and the second dielectric layer based on the photoresist pattern. The application solves the technical problem that in the related art, the SAB structure small-pitch area in the BCD process is caused by the fact that SIN is not completely sealed, photoresist is left, etching is insufficient, SIN is left and silicon loss is uneven.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a semiconductor structure and its preparation method, and a self-aligned silicide barrier structure. Background Technology

[0002] BCD (Browser-Coated Diode) technology is a key technology for integrating BJT, CMOS, and DMOS devices onto a single chip. The SAB (Self-Aligned Base) structure process is crucial for improving electric field concentration, enhancing device breakdown voltage, and preventing the reaction of silicon and cobalt to form CoSi. This process typically involves layer-by-layer deposition of silicon oxide (OX) and silicon nitride (SIN), followed by spin-coating of photoresist (PR) for development and etching to form the field plate structure.

[0003] However, in current BCD processes, there exist small spatial regions where the polycrystalline silicon (poly) gap is only 0.22 μm. Due to the weak step coverage of silicon nitride (SIN), incomplete filling or unsealed tops of SIN can easily occur in these extremely narrow gaps. During subsequent spin-coating of photoresist, liquid photoresist can easily seep into these unsealed gaps, making it impossible to completely remove the photoresist within the gaps during the development stage, resulting in stubborn photoresist residue. This residue severely interferes with subsequent etching processes. Traditional SAB etching consists of two steps: the first step is wet or dry etching of SIN and OX (ME step, i.e., Main Etch Step), and the second step is etching of OX (OE step, i.e., Over-Etch Step). If PR residue exists in the small spatial region, the ME step will first etch away the SIN at the gap, then etch away the PR within the gap, and finally etch the underlying SIN and OX. This results in insufficient actual etching time in this area compared to other large spatial areas, ultimately leading to SIN residue. Extending the etching time to eliminate residue, however, causes excessive silicon loss in other large spatial areas, which in turn affects the formation and uniformity of subsequent CoSi windows, i.e., the so-called silicon loss unevenness problem.

[0004] There is currently no effective solution to the above problems. Summary of the Invention

[0005] This invention provides a semiconductor structure and its fabrication method, as well as a self-aligned silicide barrier structure, to at least solve the technical problems in the related art where incomplete sealing of the SIN in the small-pitch region of the SAB structure in the BCD process leads to photoresist residue, resulting in insufficient etching, SIN residue, and uneven silicon loss.

[0006] According to one aspect of the present invention, a method for fabricating a semiconductor structure is provided, comprising: forming a dielectric layer stack structure including a first dielectric layer and a second dielectric layer on a substrate, wherein a narrow-pitch opening exists between the first dielectric layer and the second dielectric layer, the narrow-pitch opening being an opening with a width less than a preset value, and the second dielectric layer being located below the first dielectric layer; depositing a capping layer on the surface of the first dielectric layer and at the narrow-pitch opening, and then spin-coating photoresist on the capping layer; patterning the photoresist to obtain a photoresist pattern; and after removing the capping layer, etching the first dielectric layer and the second dielectric layer based on the photoresist pattern.

[0007] Optionally, forming a dielectric layer stack structure comprising a first dielectric layer and a second dielectric layer on a substrate includes: after forming a second dielectric layer of a first thickness on the substrate, continuing to form a first dielectric layer on the second dielectric layer based on the first thickness until the second thickness of the first dielectric layer is greater than the first thickness, thereby obtaining the dielectric layer stack structure.

[0008] Optionally, depositing a capping layer on the surface of the first dielectric layer and at the narrow-pitch opening includes: depositing a low-temperature oxide on the surface of the first dielectric layer and at the narrow-pitch opening by chemical vapor deposition to completely cover the surface of the first dielectric layer and at the narrow-pitch opening, thereby obtaining the capping layer.

[0009] Optionally, removing the overlay includes: identifying a target region in the dielectric layer stack structure that includes the narrow-pitch opening; and removing the overlay in the target region by wet etching until the first dielectric layer is exposed.

[0010] Optionally, etching the first dielectric layer and the second dielectric layer based on the photoresist pattern includes: partially etching the first dielectric layer based on the photoresist pattern, such that the remaining third thickness of the first dielectric layer is the same as the fourth thickness of the capping layer; removing the remaining first dielectric layer on the dielectric layer stack structure after removing the capping layer on the dielectric layer stack structure until the second dielectric layer is exposed; and etching the second dielectric layer to remove the second dielectric layer on the dielectric layer stack structure.

[0011] Optionally, before removing the remaining cover layer on the dielectric layer stack structure, the process includes: removing the photoresist on the dielectric layer stack structure by a photoresist stripping process.

[0012] Optionally, the preset value is 0.5 micrometers.

[0013] Optionally, the first dielectric layer is a silicon nitride layer, and the second dielectric layer is an oxide layer.

[0014] According to another aspect of the present invention, a self-aligned silicide barrier structure is also provided, which is generated using the semiconductor structure fabrication method described in any one of the above embodiments.

[0015] According to another aspect of the present invention, a semiconductor structure is also provided, wherein the semiconductor structure is manufactured using the semiconductor structure preparation method described in any one of the above embodiments.

[0016] By applying the above-described technical solution of this application, a dielectric layer stack structure comprising a first dielectric layer and a second dielectric layer is formed on a substrate. A narrow-pitch opening exists between the first dielectric layer and the second dielectric layer, the narrow-pitch opening being an opening with a width less than a preset value. The second dielectric layer is located below the first dielectric layer. After depositing a capping layer on the surface of the first dielectric layer and at the narrow-pitch opening, photoresist is spin-coated onto the capping layer. The photoresist is patterned to obtain a photoresist pattern. After removing the capping layer, the first dielectric layer and the second dielectric layer are etched based on the photoresist pattern. This achieves the complete coverage and sealing of the small space gaps in the SIN layer by CVD deposition of an LTO (low-temperature silicon oxide) film after the SIN layer is deposited and before the photoresist is spin-coated, preventing photoresist penetration. Subsequently, the LTO layer and excess SIN are selectively removed by wet etching and dry etching. This solves the technical problem in related technologies where incomplete sealing of the SIN in the small-pitch region of the SAB structure in the BCD process leads to photoresist residue, resulting in insufficient etching, SIN residue, and uneven silicon loss. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0018] Figure 1 This is a flowchart of a method for preparing a semiconductor structure according to an embodiment of the present invention;

[0019] Figure 2 This is a cross-sectional view of the SAB etching process according to an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram illustrating the principle of improving the pressure resistance of the field plate according to an embodiment of the present invention;

[0021] Figure 4 This is a cross-sectional view of a narrow polycrystalline silicon gap silicon nitride thin film and photoresist residual defects according to an embodiment of the present invention;

[0022] Figure 5 This is the original BSL process flow diagram according to an embodiment of the present invention;

[0023] Figure 6 This is a new BSL process flow diagram according to an embodiment of the present invention. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0026] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be used interchangeably where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0029] As described in the background section, in related technologies, in the BCD process, photoresist residue in the small-pitch region of the SAB structure is caused by incomplete sealing of the SiN, leading to defects such as insufficient etching, SiN residue, and uneven silicon loss. The embodiments of this invention provide a method for fabricating a semiconductor structure, a self-aligned silicide barrier structure, and a semiconductor device.

[0030] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0031] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention, such as... Figure 1 As shown, the method includes the following steps:

[0032] Step S102: A dielectric layer stack structure including a first dielectric layer and a second dielectric layer is formed on the substrate, wherein there is a narrow-pitch opening between the first dielectric layer and the second dielectric layer, the narrow-pitch opening being an opening with a width less than a preset value, and the second dielectric layer is located below the first dielectric layer.

[0033] In this embodiment, the above steps are the dielectric deposition process of the SAB structure in the BCD process. Specifically, the first dielectric layer refers to the silicon nitride layer (SIN) deposited on the silicon substrate, and the second dielectric layer refers to the silicon oxide layer (OX) located below the SIN. The narrow-pitch opening specifically refers to the small space area with a small gap between polysilicon in the BCD device. The preset value refers to the process limit size of 0.22μm (of course, it can also be flexibly set according to actual process requirements). At this time, due to the weak step coverage of SIN, the top of this small space area is often not completely sealed, forming a gap, which poses a hidden danger for subsequent photoresist penetration.

[0034] For example, an oxide (OX) layer and a silicon nitride (SIN) layer are grown layer by layer on the substrate surface using chemical vapor deposition to form a multilayer dielectric structure covering the substrate surface. During this process, due to process fluctuations, the silicon nitride layer (SIN) may not be completely unsealed in the small space region between polyethylene terephthalate (PET) layers, forming micro-gaps. In the small space region, "space" refers to the gap or interval between two adjacent patterns, specifically the physical distance between two adjacent photoresist openings, or between a photoresist opening and a hard mask (such as the edge of the SIN / OX layer). "Small space" means that this distance is very narrow, close to or less than the resolution limit of the lithography machine.

[0035] Figure 2 This is a cross-sectional view of the SAB etching process flow according to an embodiment of the present invention, such as... Figure 2 As shown, this diagram illustrates the complete process of depositing three thin films—oxide (OX), silicon nitride (SIN)—in sequence from the silicon substrate (Si), followed by spin coating of photoresist (PR), exposure and development to define the pattern, and finally dry etching to remove the SIN and OX thin films in the areas without photoresist protection. It visually presents the three-step structural evolution of thin film stacking, photolithographic pattern transfer, and dielectric etching removal, and is a schematic diagram of the core process flow for forming the field plate SAB structure.

[0036] Figure 3 This is a schematic diagram illustrating the principle of improving the pressure resistance of the field plate according to an embodiment of the present invention, as follows: Figure 3 As shown in the figure, the cross-section of the PN junction of high-voltage and low-voltage devices with and without the SAB field plate structure is compared. On the left, without the SAB structure, the electric field at the edge of the N-region is concentrated. On the right, the SAB field plate is fabricated and covers the edge of the N-type active region. By extending the dielectric field plate, the peak electric field at the edge of the PN junction is smoothed, and the electric field concentration effect is dispersed, thereby improving the breakdown voltage of the device. At the same time, the SAB dielectric layer can isolate the silicon substrate from the subsequent cobalt metal, avoiding the formation of CoSi which would affect the device performance.

[0037] Figure 4 This is a cross-sectional view of the narrow polysilicon gap silicon nitride thin film and photoresist residual defects according to an embodiment of the present invention, such as... Figure 4 The image shows a cross-section of the thin film stack in the narrow polysilicon gap region, with the silicon substrate, multilayer sidewall dielectric, polysilicon gate, SAB silicon oxide / silicon nitride, and structures such as photoresist residue and voids in the gaps marked. When depositing silicon nitride, the film layer at the gaps is thin and the film layer above the polysilicon is thick, so the silicon nitride cannot be completely sealed. After spin-coating the photoresist, the photoresist seeps into the gaps and cannot be completely developed. The residual photoresist will interfere with the subsequent main etching steps. Insufficient etching will produce silicon nitride residue. Extending the etching time will cause excessive loss of the silicon substrate and damage the cobalt silicide process window.

[0038] This process forms a stack by sequentially depositing a first dielectric layer (such as silicon oxide) and a second dielectric layer (such as silicon nitride), and etching narrow-pitch openings with extremely small widths in the first dielectric layer to define subsequent structural regions. Due to the limited film filling capacity within the narrow gaps, the second dielectric layer cannot completely fill the top of the gap, thus leaving incompletely sealed voids or micropores inside the gap.

[0039] This process allows subsequent steps to selectively deposit a low-temperature silicon oxide layer with weak step coverage. Utilizing its characteristic of covering only the surface without penetrating into the gaps, an effective anti-permeation barrier is formed. This pre-designed structure ensures that subsequent wet processes can completely remove the barrier layer, thereby preventing photoresist from entering the gaps to a certain extent and ultimately significantly improving the unevenness of oxide layer etching loss.

[0040] Step S104: After depositing a capping layer on the surface of the first dielectric layer and at the narrow-pitch opening, photoresist is spin-coated onto the capping layer.

[0041] In this embodiment, the capping layer refers to the low-temperature silicon oxide layer formed by chemical vapor deposition (CVD). Since CVD deposition has poor step coverage, the LTO layer is mainly deposited on the protrusions on the SIN surface to completely cover and seal the small space gaps of the underlying SIN, without being deposited deep into the small space to form internal filling. This physically blocks the path of photoresist (PR) flowing into the gaps. Spin-coating photoresist is a conventional photolithography process performed under this closed and protected state.

[0042] This process utilizes a capping layer (such as low-temperature silicon oxide) to physically seal the surface of the underlying first dielectric layer and the narrow-pitch openings. By depositing this capping layer on the surface of the first dielectric layer and at the existing narrow-pitch openings, the top voids left by insufficient filling of the second dielectric layer are filled, forming a continuous and dense surface layer. Subsequently, photoresist is spin-coated onto the capping layer surface. Since the capping layer has sealed the original gap entrances, the photoresist can only adhere to the outer surface of the capping layer and cannot penetrate into the interior of the underlying narrow-pitch openings. This physically blocks the path for the photoresist to enter the gaps, creating clean interface conditions for subsequent development and etching processes.

[0043] This process solves the technical problem of photoresist seepage and difficulty in removal caused by unsealed gaps in traditional processes. Since the photoresist cannot enter the narrow-pitch opening, the subsequent development step can easily and thoroughly remove the photoresist outside the opening area, avoiding the occurrence of residual photoresist (i.e., photoresist residue) inside the gap.

[0044] Step S106: The photoresist is patterned to obtain a photoresist pattern.

[0045] In this embodiment, the patterning process includes the exposure and development of photoresist. Since the LTO layer has prevented the photoresist from seeping into the gaps in the small space area, the development step can smoothly and thoroughly remove the photoresist at the opening of the small space area, forming a clear and residue-free photoresist pattern.

[0046] This process utilizes photolithography to transfer the designed circuit pattern onto a photoresist layer covering the surface of a dielectric stack. Through exposure and development, the photoresist in unexposed or exposed areas is selectively removed, creating openings on the capping layer surface corresponding to the target pattern. These openings precisely expose the portions of the underlying capping layer that need to be removed, while preserving other areas. This allows subsequent processes to selectively etch the underlying dielectric layer based on these openings, ensuring that only specific areas of the structure are processed, while the rest remain protected.

[0047] This process ensures the geometric precision and positional accuracy of the device structure. By forming a clear and complete photoresist pattern, not only are the areas in the SAB structure where the capping layer needs to be removed defined, but the remaining photoresist and the unremoved capping layer also protect areas that do not require processing.

[0048] Step S108: After removing the cover layer, the first dielectric layer and the second dielectric layer are etched based on the photoresist pattern.

[0049] In this embodiment, removing the capping layer refers to first removing the LTO (low-temperature silicon oxide) layer exposed in the opening area by wet etching (WET), then performing local etching of the SIN by dry etching (ET) to adjust the thickness until the remaining SIN thickness is consistent with the LTO thickness. Subsequently, the LTO in other parts is further removed, and finally the SIN and OX are etched. Etching based on the photoresist pattern refers to using the formed photoresist pattern as a mask to sequentially perform the steps of partial etching of SIN, removal of the remaining LTO, full etching of SIN, and etching of OX.

[0050] This process first uses a wet process to selectively remove the capping layer (such as low-temperature silicon oxide) that is not protected by the photoresist pattern, exposing the surfaces of the first and second dielectric layers to be etched. Then, using the retained photoresist pattern as a mask, dry etching is performed sequentially on the first and second dielectric layers. Because the capping layer has sealed the top of the narrow-pitch opening in the previous process, and the photoresist has not penetrated into the gaps, the etching process can proceed smoothly downwards, directly acting on the dielectric layer material. This avoids the situation where residual photoresist in the gaps hinders the entry of etching gas or ions, ensuring that the etching uniformly removes the dielectric layer until the predetermined depth is reached.

[0051] The sequence of removing the capping layer before etching the dielectric layer, combined with the effective sealing of narrow-pitch openings in the pre-processing steps, completely eliminates etching dead zones or insufficient etching caused by photoresist residue. This not only ensures the consistency of etching depth for the oxide and silicon nitride layers within the narrow-pitch area and significantly improves the non-uniformity of oxide layer etching loss, but also avoids electric field concentration caused by uneven etching, thereby effectively improving the breakdown voltage and overall reliability of the BCD device.

[0052] As described above, in this embodiment, a dielectric layer stack structure including a first dielectric layer and a second dielectric layer is formed on the substrate. A narrow-pitch opening exists between the first and second dielectric layers, with the narrow-pitch opening having a width less than a preset value. The second dielectric layer is located below the first dielectric layer. After depositing a capping layer on the surface of the first dielectric layer and at the narrow-pitch opening, photoresist is spin-coated onto the capping layer. The photoresist is patterned to obtain a photoresist pattern. After removing the capping layer, the first and second dielectric layers are etched based on the photoresist pattern. This achieves the goal of completely covering and sealing the small space gaps of the SIN layer by CVD deposition of an LTO thin film after depositing the SIN layer and before spin-coating the photoresist, preventing photoresist penetration. Subsequently, the LTO layer and excess SIN are selectively removed by wet etching and dry etching. This effectively prevents photoresist from penetrating into the small SIN space area and forming residues, avoiding SIN residues caused by insufficient etching and silicon loss unevenness caused by over-etching, significantly improving the technical effect of addressing the silicon loss unevenness problem in the small space area.

[0053] Therefore, the technical solutions provided by the embodiments of the present invention solve the technical problems in the related art of insufficient etching, residual SIN and uneven silicon loss caused by photoresist residue in the small-pitch area of ​​SAB structure due to incomplete sealing of SIN in BCD process.

[0054] According to the above embodiments of the present invention, forming a dielectric layer stack structure comprising a first dielectric layer and a second dielectric layer on a substrate includes: after forming a second dielectric layer of a first thickness on the substrate, continuing to form a first dielectric layer on the second dielectric layer based on the first thickness, until the second thickness of the first dielectric layer is greater than the first thickness, thereby obtaining a dielectric layer stack structure.

[0055] Figure 5 This is the original BSL process flow diagram according to an embodiment of the present invention, such as... Figure 5As shown, silicon oxide and silicon nitride are deposited first. However, due to the weak SiN filling ability of silicon nitride, SiN is not fully filled in small space areas, and the top fails to bond together. That is, the filling ability of silicon nitride trenches is insufficient, the film inside the narrow gap cannot be filled, and the top cannot be closed. Next, photoresist is spin-coated, and the photoresist seeps into the unsealed gaps. The subsequent development process cannot completely remove the photoresist residue in the gaps, forming photoresist residue. In the dry etching stage, the photoresist residue in the gaps blocks the etching reaction, and the silicon oxide layer in the corresponding area cannot be removed normally. That is, the presence of photoresist residue in the small space area prevents the removal of silicon oxide. Finally, after dry resist removal and wet cleaning processes, the process results in uneven silicon oxide loss in the oxide layer, which fully reproduces the entire process of chain defects caused by poor step coverage in narrow-pitch structures.

[0056] In this embodiment, Figure 6 This is a new BSL process flow diagram according to an embodiment of the present invention, such as... Figure 6 As shown, silicon oxide and silicon nitride are deposited first. It should be noted that the silicon nitride needs to be thicker, that is, the silicon nitride (SIN) needs to be thickened so that the SIN at the top of the narrow gap is basically closed.

[0057] This process constructs stacked structures with specific geometries by controlling the order and thickness of dielectric layer deposition. First, a second dielectric layer (such as silicon nitride) of a certain thickness is deposited, followed by a first dielectric layer (such as silicon oxide) deposited on top, with the thickness of the first dielectric layer being greater than that of the second. This thickness difference design aims to ensure that in subsequent etching processes, when etching reaches the second dielectric layer, the first dielectric layer still has sufficient remaining thickness to maintain structural integrity or serve as a protective layer for subsequent processes. Simultaneously, by utilizing the difference in etching rates between the two layers, the morphology and depth of the final narrow-pitch openings are precisely controlled, providing a suitable foundation structure for the subsequent introduction of capping layers.

[0058] The above process effectively prevents structural collapse or over-etching risks caused by an excessively thin second dielectric layer during etching, thus ensuring the sidewall steepness and dimensional accuracy of narrow-pitch openings. Furthermore, this structure facilitates the uniform deposition and effective coverage of subsequent capping layers (such as low-temperature silicon oxide), reducing stress concentration or cracking of the capping layer due to uneven underlying structure, thereby improving the overall process yield.

[0059] According to the above embodiments of the present invention, depositing a capping layer on the surface of the first dielectric layer and at the narrow-pitch opening includes: depositing a low-temperature oxide on the surface of the first dielectric layer and at the narrow-pitch opening by chemical vapor deposition to completely cover the surface of the first dielectric layer and at the narrow-pitch opening, thereby obtaining a capping layer.

[0060] In this embodiment, such as Figure 6 As shown, after depositing silicon oxide and silicon nitride, low-temperature silicon oxide deposition is performed (completely covering the silicon nitride; chemical vapor deposition is chosen for low-temperature silicon oxide because its step coverage is weaker and therefore it will not deposit into the small space area). That is, this low-temperature silicon oxide layer must completely cover the underlying silicon nitride; the low-temperature silicon oxide is prepared using chemical vapor deposition because its step coverage is weaker, so it only deposits on the surface of the silicon nitride and does not penetrate into the small space area.

[0061] This process utilizes chemical vapor deposition (CVD) to deposit a low-temperature oxide layer as a temporary capping layer on the already formed first dielectric layer and the narrow-spacing opening region. Due to the specific step-covering characteristics of this low-temperature oxide deposition process, its deposition rate is faster on planar surfaces, but slower or almost non-existent inside narrow and deep gaps, thus forming a thin film covering the top of the opening on a macroscopic scale, effectively sealing any gaps or voids that may exist below.

[0062] In the above process, the physical barrier effect of the thin film is used to block all channels that may allow photoresist to penetrate, while avoiding excessive filling of the gaps with material, thus creating a residue-free interface condition for the smooth removal and development of the photoresist.

[0063] According to the above embodiments of the present invention, removing the overlay includes: identifying a target region in the dielectric layer stack structure that includes narrow-pitch openings; and removing the overlay in the target region by wet etching until the first dielectric layer is exposed.

[0064] In this embodiment, such as Figure 6 As shown, after depositing low-temperature silicon oxide, photoresist is spin-coated and development is completed. The low-temperature silicon oxide in the exposed window area is removed by wet etching.

[0065] This process leverages the selective dissolution properties of wet etching to locally process target areas within a dielectric layer stack structure where specific patterns (such as SAB structure field plates) need to be formed. By configuring a specific wet etching solution, it can efficiently remove the low-temperature oxide capping layer covering the surface without significantly eroding the underlying first dielectric layer (silicon oxide) and second dielectric layer.

[0066] This process aims to precisely strip the cover layer within the area defined by the photoresist pattern, thereby re-exposing the surface of the underlying first dielectric layer. This prepares the ground for subsequent dry etching of dielectric layers stacked from the first dielectric layer, ensuring that the etching process can directly act on the target dielectric layer.

[0067] According to the above embodiments of the present invention, etching the first dielectric layer and the second dielectric layer based on a photoresist pattern includes: partially etching the first dielectric layer based on the photoresist pattern, such that the third thickness of the remaining first dielectric layer is the same as the fourth thickness of the capping layer; after removing the remaining capping layer on the dielectric layer stack structure, removing the remaining first dielectric layer on the dielectric layer stack structure until the second dielectric layer is exposed; and etching the second dielectric layer to remove the second dielectric layer on the dielectric layer stack structure.

[0068] In this embodiment, such as Figure 6 As shown, after wet etching, partial etching of silicon nitride is performed to match the thickness of the remaining silicon nitride with that of low-temperature silicon oxide. That is, part of the silicon nitride is etched away, and the remaining silicon nitride thickness is consistent with the thickness of low-temperature silicon oxide. Then, the photoresist is stripped off, all the remaining low-temperature silicon oxide is removed by wet etching, and then the remaining silicon nitride and a small amount of oxide layer in the narrow gap are etched away. Finally, the oxide layer is etched as a whole, that is, the remaining silicon nitride and part of the silicon oxide in the small space area are etched. Since the silicon nitride in the small space area is thin, part of the silicon oxide is etched. Here, the pre-process is mainly used to block the gap and isolate the photoresist penetration path, thereby eliminating the problem of photoresist residue in the gap from the root, greatly reducing the process defects of uneven oxide layer etching loss in the small gap area (uneven oxide layer loss), and also reducing the unevenness of silicon oxide loss in the small space area.

[0069] This process employs a staged, thickness-differentiated etching strategy. First, using a photoresist pattern as a mask, a shallow etching of the first dielectric layer is performed, precisely controlling its remaining thickness to match the thickness of the capping layer (low-temperature oxide), thus establishing a thickness reference in the vertical direction. Subsequently, a wet etching process removes the capping layer. Since the first dielectric layer and capping layer are at the same thickness, the wet etching can simultaneously remove the remaining first dielectric layer until the surface of the underlying second dielectric layer is fully exposed. Finally, using the second dielectric layer as the new etching target, dry etching continues until the second dielectric layer is completely removed, forming the final SAB structure window.

[0070] This process solves the problem of uniformity in dielectric layer removal in narrow-pitch areas and significantly improves the non-uniformity of oxide layer etching loss. By pre-setting the remaining thickness of the first dielectric layer to be consistent with that of the capping layer, it ensures that the remaining first dielectric layer can be removed uniformly and synchronously during the wet removal step of the capping layer, avoiding deviations in etching endpoint judgment or local residues caused by thickness differences.

[0071] According to the above embodiments of the present invention, before removing the remaining cover layer on the dielectric layer stack structure, the process includes: removing the photoresist on the dielectric layer stack structure by a photoresist removal process.

[0072] In this embodiment, such as Figure 6As shown, a photoresist stripping process must be performed before silicon nitride etching (which aims to etch the remaining silicon nitride and some silicon oxide in the small space area; since the silicon nitride in the small space area is thin, this step will also etch away some silicon oxide).

[0073] This process introduces a photoresist stripping step before removing the capping layer. This step utilizes methods such as plasma or wet stripping to thoroughly remove the photoresist pattern remaining in non-target areas on the dielectric layer surface. Because the capping layer previously sealed the narrow-pitch openings, the stripping process only affects the photoresist on the capping layer surface and does not reach the interior of the gaps.

[0074] This process eliminates the obstruction of photoresist to the subsequent wet etching capping layer process, ensuring that the wet etching solution can directly and uniformly contact and dissolve the capping layer, avoiding incomplete removal or residue of the capping layer caused by photoresist obstruction, and creating clean surface conditions for the simultaneous removal of the first dielectric layer.

[0075] Optionally, the preset value can be 0.5 micrometers, or it can be flexibly set according to the actual process requirements, without specific limitations here.

[0076] Optionally, the first dielectric layer is a silicon nitride layer, and the second dielectric layer is an oxide layer.

[0077] As can be seen from the above, through the technical solution provided by the above embodiments of the present invention, after depositing the SIN layer and before spin-coating the photoresist, an additional low-temperature silicon oxide (LTO) film is deposited on the SIN surface by CVD process. The good step coverage ability of LTO is used to completely seal the small-pitch area of ​​SIN, thereby preventing PR liquid from seeping in and forming residues. Subsequently, the LTO layer covering the opening area and small gap is selectively removed by wet etching (WET) and dry etching (ET) processes, which ultimately reduces the uneven silicon loss caused by PR residue in the small-pitch area and balances the overall etching uniformity.

[0078] In summary, in this embodiment of the invention, before forming the SAB structure in the BCD process, after depositing the SIN layer, a layer of LTO (low-temperature oxide) is deposited on the SIN surface using CVD technology to cover and seal the small space region between the poly atoms, preventing PR from flowing into the gaps and forming residues during spin-coating. Subsequently, the LTO layer is removed using wet etching and dry etching processes. Finally, the SAB etching process is performed. This technical solution blocks PR from entering the unsealed SIN gaps through the LTO layer, avoiding ME etching abnormalities and SIN residue problems caused by PR residue. This significantly reduces Siloss loading in the small space region while ensuring clean SIN removal, optimizing the quality and yield of the subsequent CoSi window (cobalt silicide contact window).

[0079] The aforementioned silicon loss occurs because the etchant, when etching dielectric layers (such as SIN and OX) to form contact windows, not only etches the dielectric layer but also inevitably slightly etches the underlying silicon substrate (Si), causing silicon loss. Si loss loading is a phenomenon where different pattern sizes result in inconsistent etching depths of the silicon substrate in different areas. The aforementioned CoSi window (cobalt silicide contact window) is the etched-away portion of the SAB structure, i.e., the exposed silicon region in the source / drain region after the removal of the SAB barrier layer (SIN / OX).

[0080] According to another aspect of the present invention, a self-aligned silicide barrier structure is also provided, which is generated using the semiconductor structure fabrication method described in any of the above embodiments.

[0081] The self-aligned silicide barrier structure refers to a field plate structure formed by patterned etching of a silicon nitride (SIN) layer and an oxide (OX) layer. Specifically, it includes: a first dielectric layer: a silicon nitride (SIN) layer, which is the main barrier material and field plate material; and a second dielectric layer: an oxide (OX) layer, which covers or lies under the SIN layer as a protective layer and dielectric layer.

[0082] This structure is formed by etching the SIN and OX regions (ME step) using photoresist (PR) as a mask. It retains a specific pattern, covering the semiconductor regions that need protection (such as the field oxide region, around the gate, etc.), while removing the areas where metal contacts need to be formed (CoSi window), exposing the underlying silicon substrate. It utilizes the retained SIN / OX structure as a field plate to improve the electric field concentration of the BCD device, enhance its breakdown voltage, and prevent subsequently deposited metals (such as cobalt (Co) from reacting with silicon (Si) in non-contact areas to form high-resistivity CoSi, while simultaneously protecting the Si surface. Especially in the small-space region, the SAB structure ensures that SIN and OX are completely and uniformly removed (in the window region) or retained (in the blocking region), preventing SIN residue (leading to poor contact) or over-etching (leading to excessive Si loss).

[0083] According to another aspect of the present invention, a semiconductor structure is also provided, wherein the semiconductor structure is fabricated using any of the above-described methods for semiconductor structure fabrication.

[0084] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A dielectric layer stack structure comprising a first dielectric layer and a second dielectric layer is formed on a substrate, wherein a narrow-pitch opening exists between the first dielectric layer and the second dielectric layer, the narrow-pitch opening being an opening with a width less than a preset value, and the second dielectric layer is located below the first dielectric layer. After depositing a capping layer on the surface of the first dielectric layer and at the narrow-pitch opening, photoresist is spin-coated onto the capping layer, wherein the capping layer is obtained by chemical vapor deposition of a low-temperature oxide on the surface of the first dielectric layer and at the narrow-pitch opening to completely cover the surface of the first dielectric layer and at the narrow-pitch opening; The photoresist is patterned to obtain a photoresist pattern; After removing the cover layer, the first dielectric layer and the second dielectric layer are etched based on the photoresist pattern.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming a dielectric layer stack structure comprising a first dielectric layer and a second dielectric layer on a substrate includes: After forming a second dielectric layer of a first thickness on the substrate, the first dielectric layer is formed on the second dielectric layer based on the first thickness until the second thickness of the first dielectric layer is greater than the first thickness, thus obtaining the dielectric layer stack structure.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, Removing the overlay includes: Determine the target region in the dielectric layer stack structure that includes the narrow-pitch opening; The cover layer in the target area is removed by wet etching until the first dielectric layer is exposed.

4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that, Etching of the first dielectric layer and the second dielectric layer based on the photoresist pattern includes: The first dielectric layer is partially etched based on the photoresist pattern, so that the third thickness of the remaining first dielectric layer is the same as the fourth thickness of the cover layer. After removing the remaining cover layer on the dielectric layer stack structure, remove the remaining first dielectric layer on the dielectric layer stack structure until the second dielectric layer is exposed; The second dielectric layer is etched to remove the second dielectric layer from the dielectric layer stack structure.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, Before removing the remaining cover layer on the dielectric layer stack structure, the process includes: The photoresist on the dielectric layer stack structure is removed by a photoresist removal process.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that, The preset value is 0.5 micrometers.

7. The method for preparing a semiconductor structure according to claim 4, characterized in that, The first dielectric layer is a silicon nitride layer, and the second dielectric layer is an oxide layer.

8. A self-aligned silicide barrier structure, characterized in that, The self-aligned silicide barrier structure is generated using the method for fabricating a semiconductor structure according to any one of claims 1 to 7.

9. A semiconductor structure, characterized in that, The semiconductor structure is manufactured using the semiconductor structure preparation method described in any one of claims 1 to 7.

Images